Apple MacBook Unibody A1342 (K84, 820-2567)
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1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
1
REV
ECN
DESCRIPTION OF REVISION
C
0000813234
CK APPD DATE
PRODUCTION RELEASED
2009-11-01
K84 MLB SCHEMATIC PROD OK2FAB 11/01/2009
D
D (.csa)
Date
Page TABLE_TABLEOFCONTENTS_HEAD
Contents 1
Table of Contents System Block Diagram
3
37 01/19/2009
4 TABLE_TABLEOFCONTENTS_ITEM
BOM Configuration
01/19/2009
5
Revision History Revision History
02/04/2009
7
FUNC TEST
02/04/2009
8 TABLE_TABLEOFCONTENTS_ITEM
Power Aliases
K24_MLB
SIGNAL ALIAS
K24_MLB
9
10
CPU FSB
04/06/2009
11
CPU Power & Ground CPU Decoupling
WELLSPRING 2
K24_MLB
SMS
K24_MLB
47
DEBUG SENSORS AND ADC
K19_IMLB
SPI ROM
K24_MLB
AUDIO: CODEC/REGULATOR
AUDIO
AUDIO: LINE INPUT FILTER
AUDIO
AUDIO: HEADPHONE FILTER
AUDIO
AUDI0: SPEAKER AMP
AUDIO
AUDIO: JACK
AUDIO
AUDIO: JACK TRANSLATORS
AUDIO
DC-In & Battery Connectors
K24_MLB
PBUS Supply/Battery Charger
K24_MLB
K24_MLB
SMC Constraints
K24_MLB
K84 SPECIAL CONSTRAINTS
K24_MLB
K84 RULE DEFINITIONS
K24_MLB
04/06/2009
04/06/2009
01/19/2009
01/19/2009
TABLE_TABLEOFCONTENTS_ITEM
03/04/2009
02/25/2009
03/04/2009
60
02/25/2009
13
eXtended Debug Port(MiniXDP)
02/25/2009
61
48
K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
02/15/2009
TABLE_TABLEOFCONTENTS_ITEM
14
04/06/2009
14
MCP CPU Interface
62
49
K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
06/09/2009
C
TABLE_TABLEOFCONTENTS_ITEM
15
04/06/2009
15 TABLE_TABLEOFCONTENTS_ITEM
MCP Memory Interface
K24_MLB
MCP Memory Misc
K24_MLB
MCP PCIe Interfaces
K24_MLB
16
TABLE_TABLEOFCONTENTS_ITEM
17
18
MCP Ethernet & Graphics MCP PCI & LPC
20 TABLE_TABLEOFCONTENTS_ITEM
MCP SATA & USB MCP HDA & MISC MCP Power & Ground
K24_MLB
MCP Standard Decoupling
K24_MLB
25
26
TABLE_TABLEOFCONTENTS_ITEM
MCP Graphics Support 28
SB Misc FSB/DDR3 Vref Margining DDR3 SO-DIMM Connector A DDR3 SO-DIMM Connector B DDR3 Support
K24_MLB
X16 WIRELESS CONNECTOR
K24_MLB
34
TABLE_TABLEOFCONTENTS_ITEM
37
Ethernet PHY (RTL8211CL) Ethernet & AirPort Support ETHERNET CONNECTOR 45
SATA Connectors
K24_MLB
External USB Connectors
K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
POWER SEQUENCING
K24_MLB
POWER FETS
K24_MLB
LVDS CONNECTOR
K24_MLB
DISPLAYPORT SUPPORT
K24_MLB
DisplayPort Connector
K24_MLB
LCD Backlight Driver (MC34845)
VEMURI_K19I
LCD Backlight Support
K24_MLB
CPU/FSB Constraints
K24_MLB
03/24/2009
02/15/2009
02/15/2009
02/15/2009
04/06/2009
TABLE_TABLEOFCONTENTS_ITEM
B
04/06/2009
97
02/09/2009
98
69
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
94
68 01/19/2009
34
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
MISC POWER SUPPLIES
02/04/2009
93
67 04/06/2009
33 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
39
K24_MLB
90
66 04/06/2009
32 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
38
CPU VTT(1.05V) SUPPLY
02/15/2009
79
65 04/06/2009
31 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
64 01/27/2009
30
K24_MLB
78
63 04/06/2009
29 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
33
MCP CORE REGULATOR
77
62 02/05/2009
28 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
32
K24_MLB
76
61 02/05/2009
27 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
31
03/03/2009
IMVP6 CPU VCore Regulator 75
60 04/06/2009
26 TABLE_TABLEOFCONTENTS_ITEM
1.5V/0.75V DDR3 SUPPLY 74
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
29
5V/3.3V SUPPLY 73
TABLE_TABLEOFCONTENTS_ITEM
59 02/15/2009
25 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
02/05/2009
72
58 04/06/2009
24
TABLE_TABLEOFCONTENTS_ITEM
57 04/06/2009
23 TABLE_TABLEOFCONTENTS_ITEM
02/05/2009
70
56 04/06/2009
22 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
22
06/09/2009
69
55 03/24/2009
21 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
21
06/09/2009
68
54 04/06/2009
06/09/2009
67
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
20
06/09/2009
66
TABLE_TABLEOFCONTENTS_ITEM
53 04/06/2009
19 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
19
06/09/2009
65
52 04/06/2009
18 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
51 04/06/2009
17 TABLE_TABLEOFCONTENTS_ITEM
63
50 04/06/2009
16
B
K24_MLB
Ethernet Constraints
04/06/2009
TABLE_TABLEOFCONTENTS_ITEM
13
C
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
WELLSPRING 1
59
46 03/30/2009
12
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
12
Fan
K24_MLB
109
77 04/06/2009
58
45
K24_MLB
11
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
57
44 04/06/2009
10 TABLE_TABLEOFCONTENTS_ITEM
Thermal Sensors
MCP Constraints 2
03/30/2009
107
76 02/04/2009
56
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
K24_MLB
106
75 01/27/2009
Current Sensing
43 02/04/2009
9 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
55
42
K24_MLB
8
VOLTAGE SENSING
MCP Constraints 1
104
74 04/06/2009
54
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
K24_MLB
103
73 01/19/2009
K84 SMBUS CONNECTIONS
41
K24_MLB
7
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
53
40 01/19/2009
6
LPC+SPI Debug Connector
04/06/2009
Memory Constraints 102
72 02/15/2009
Sync
101
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
52
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
6
TABLE_TABLEOFCONTENTS_ITEM
SMC Support
39
K24_MLB
5
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
Contents
71 02/04/2009
Date
Page
K24_MLB
51
38
Power Block Diagram 4
04/02/2009
SMC 50
TABLE_TABLEOFCONTENTS_ITEM
(.csa)
Sync
49
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
3
TABLE_TABLEOFCONTENTS_ITEM
Contents
36 01/19/2009
2 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
K24_MLB
2
Date
Page
01/19/2009
1 TABLE_TABLEOFCONTENTS_ITEM
(.csa)
Sync
04/06/2009
TABLE_TABLEOFCONTENTS_ITEM
46
02/05/2009
35
100
70
TABLE_TABLEOFCONTENTS_ITEM
04/06/2009
TABLE_TABLEOFCONTENTS_ITEM
A
A DRAWING TITLE
SCHEM,MLB,K84 DRAWING NUMBER
Schematic / PCB #’s
Apple Inc.
051-7982 REVISION
R
PART NUMBER
DESCRIPTION
REFERENCE DES
051-7982
1
SCHEM,MLB,K84
SCH
CRITICAL
820-2567
1
PCBF,MLB,K84
PCB
CRITICAL
8
QTY
7
CRITICAL
BOM OPTION
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6
5
4
3
2
C.0.0 BRANCH
PAGE
1 OF 109 SHEET
1 OF 77
1
SIZE
D
8
7
6
5
4
3
2
1
U1000
U1300
J6950,J6900
INTEL CPU CORE 2 DUO
XDP CONN
2.26 GHZ
DC/BATT CONN
PG 13
DC-DC POWER SUPPLIES
PENRYN PG 55
PG 56-64
PG 10
FSB
D
J5800
D
TRACKPAD
64-Bit
PG 45
1067 MHZ
PG 14 U5515,U5535 J3100,J3200
2 SODIMMS MAIN
CPU & MCP THERMAL SENSORS
FSB INTERFACE
GPIOs
MEMORY
DDR3 1067MHZ
DIMM PG 42
PG 15,16
PG 27,28
U5920
SUDDEN MOTION SENSOR PG 46
Misc
U6100
CLK
SPI
PG 21
SYNTH
CURRENT & VOLTAGE SENSORS
Boot ROM
PG 53,54,60
PG 48
J5601
J4501
FAN CONN AND CONTROL
SPI
SATA
PG 43
Conn
PG 21 PG 34
HD
NVIDIA
J4500
U4900
A
SATA
B,0
ADC
BSA
Fan
Ser J5100
PG 34
C
MCP79 B03
SATA
Conn
PG 20
Prt
SMC
LPC Conn
H8S/2117
LPC
ODD
Port80,serial
PG 36,37
C
PG 38
PG 19
U1400
J9000
PWR
LVDS CONN
LVDS OUT
PG 65
CTRL
RGB OUT J3401
J5800
DP OUT
Bluetooth
J9400
J9000
J4600,4610
TRACKPAD/
EXTERNAL CAMERA
KEYBOARD MINI DISPLAY PORT
USB 2.0
HDMI OUT
Connectors PG 30
PG 45
PG 65 PG 35
CONN
PG 17
8 7 6 5
PCI-E
UP TO 20 LANES3
B
0
1
2
3
4
USB
PG 18
PG 20
TMDS OUT
(UP TO 12 DEVICES)
PG 67
9
DVI OUT
B SMB PG 21
RGMII
HDA
PCI
DIMMS
(UP TO FOUR PORTS)
MIKEY
SMC
PG 18 PG 19
PG 21
U6201
Audio Codec CIRRUS LOGIC CS4206 PG 49
U6500
HEADPHONE/LINE OUT Amp U6610,U6620,U6630 PG 51
U3700
LINE-IN
A
GIGABIT
Speaker
MIC
10/100/1000M E-NET
U6700
RTL8211CL
SYNC_MASTER=K24_MLB
DRAWING NUMBER
PG 53
Apple Inc. J3401
J3900
J6700,J6701,J6702,J6703,J6704
NOTICE OF PROPRIETARY PROPERTY:
E-NET
SIZE
051-7982
D
REVISION
C.0.0
R
MINI PCI-E
A
System Block Diagram
PG 52
MUX
PG 31
SYNC_DATE=01/19/2009
PAGE TITLE
Amps
LINE-IN/LINE OUT
BRANCH
Audio
AirPort
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
Conn Conns
PG 30 PG 33
PG 53
PAGE
2 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
K84 POWER SYSTEM ARCHITECTURE PP18V5_DCIN_CONN
D6905 02 ENABLE
PPVIN_G3H_P3V42G3H
D6905
3.425V G3HOT LT3470
PBUS_VSENSE
03
PP3V42_G3H_REG
04
SMC RESET "BUTTON" NCP303LSN
VOUT
V
7A FUSE
D
PPVBAT_G3H_CHGR_REG
U6990
PPBUS_G3H
01
U5000
Q5315
23
PPCPUVCORE_VTT_ISNS
PPCPUVCORE_VTT_ISNS_R
02
F7000
D
0.01 OHM
R5492
PPVIN_S0_CPUVTTS0 VIN
6A FUSE
AC ADAPTER IN
PPCPUVTT_S0_REG
CPUVTTS0_EN (S0)
CHGR_EN (S5)
F6905
EN_PSV
VOUT
CPUVTT
ENABLES
(7.2A MAX CURRENT)
(1.05V)
DCIN(16.5V)
MCP79
TPS51117 U7600
VIN VOUT
PBUS SUPPLY/
06-1
PWRBTN*
31
PGOOD
CPUVTTS0_PGOOD
BATTERY CHARGER
PLTRST*
PPVIN_S5_CPU_IMVP
LPC_RESET_L
RSMRST*
ISL6258AHRTZ
V
01
U7000
CPU VCORE
02
MCP_PS_PWRGD
SMC_CPU_VSENSE
CPU_PWRGD
VIN
CPUPWRGD(GPIO49)
29
PPVCORE_S0_CPU_REG
26
VOUT
30
(44A MAX CURRENT)
U2850
CPU_RESET#
FSB_CPURST_L
J6950
PS_PWRGD
ISL9504BCRZ U1400 IMVP_VR_ON
C
VR_ON
Q7050
3S2P BATT_POS_F
(9 TO 12.6V)
28
25
PPVBAT_G3H_CHGR_OUT
VR_PWRGOOD_DELAY
PGOOD
U7400
06
P1V05ENET_EN
1.05V SO
22
EN
1.05V (S5)
MCP79
11
11-1
P3V3S3_EN
VIN ISL8009B
U7750
P1V05_S5_EN
RC DELAY
PM_SLP_S4_L
PP4V5_AUDIO_ANALOG
U6200 RESET*
VOUT
EN
06
PWRGOOD
4.5V AUDIO TPS71745 VIN
(Q3841,Q3840)
PPVIN_S3_5VS3/PPVIN_S5_3V3S5
U1000
PP1V05_S5_REG
32
VOUT
08
Q7940
PP5V_S3_REG
02
SMC
C
CPU
PP1V05_ENET_FET
FETS
CHGR_BGATE
PP5VRT_S0_FET
P16
15 SLP_S3#
11-3
RC DELAY
U1400
P5VS3_EN_L
04
U4900
DDRREG_EN
VIN
5V
EN1
VOUT1
(RT)
SMC_PM_G2_EN P60
Q7800
(S5)
PP3V3_S5_REG (4A MAX
3.3V
EN2
PPBUS_S0_LCDBKLT_PWR
07
PP5VLT_S0_FET
Q7910 PP3V3_S3_FET
02 EN0
SMC_PM_G2_EN
P5VS3_EN_L
RC DELAY
P5VS0_EN Q7948
CURRENT)
TPS51125 11-2
17
PP3V3_S5
VOUT2
P3V3S5_EN_L
PP3V42_G3H_REG PCI_RESET0#
15-1
PP5V_S3
PP5V_S3_REG (10A MAX CURRENT)
05
U7200
PGOOD1,2
13
P5VS0_EN
VREG3
VIN
P3V3S3_EN
MC34845 U9700
P5V3V3_PGOOD
PPVOUT_S0_LCDBKLT VOUT
B
SMC
24
NAND GATE 04-1
SMC_ADAPTER_EN Q3801,Q3805
PWRGD(P12)
18
PM_RSMRST_L
99ms DLY
IMVP_VR_ON IMVP_VR_ON(P16)
PP3V3_S0_FET
09
PM_WLAN_EN_L
RSMRST_PWRGD
25
RSMRST_IN(P13) PLT_RST*
OR GATE
PM_SLP_S3_L
ALL_SYS_PWRGD
Q7930
16
Q3801,Q3805
B
10
RSMRST_OUT(P15)
AP_PWR_EN
SMC_ONOFF_L PWR_BUTTON(P90)
P3V3S0_EN
15
P17(BTN_OUT)
05
Q3810
RST*
P3V3_ENET_FET
PM_PWRBTN_L SMC_RESET_L
P1V05S0_LDO_PGOOD P5V3V3_PGOOD
SLP_S5_L SLP_S5_L(P95)
P3V3ENET_EN_L
MCPCORESO_PGOOD
SLP_S4_L SLP_S4_L(P94)
CPUVTTS0_PGOOD
SLP_S3_L SLP_S3_L(P93)
PP3V3_S0_PWRCTL
PPVIN_S5_1V5S30V75S0
S3 TO S0 PP1V5_S0_FET
PP1V5_S0
FETS
02
21 1.8V LDO
(Q7901 & Q7971)
TPS62202
VIN
=DDRREG_EN
=DDTVTT_EN
PM_SLP_S3_L
S3
RC
P1V8S0_EN
U7760
PP1V5_S3_REG (13A MAX CURRENT)
VOUT1
RST*
14
0.75V
PP3V3_S0 VOUT2
A
PP0V75_S0_REG (1A MAX CURRENT)
V1
PP1V5_S0
TPS51116 U7300
16-4
DELAY
PP1V8_S0_REG 19-1
1.5V S5
V2
PP1V05_S0
V3
20 RC
MCPDDR_EN 16-2
DELAY
RC
MCP_CORE
P3V3S0_EN
16-3
U4900
S0PGOOD_PWROK
MCPCORES0_EN
DELAY
PPMCPCORE_S0_R VOUT
LTC2909
A PAGE TITLE
Power Block Diagram
U7870
R7525 PPMCPCORE_S0_REG
DRAWING NUMBER
Apple Inc.
(13A MAX CURRENT)
EN
RC
CPUVTTS0_EN
C.0.0
ISL6263D
16-1 16-6
NOTICE OF PROPRIETARY PROPERTY:
PBUSVSENS_EN U7500 (S0)
RC
MCPCORES0_EN 16-5
DELAY
VIN
16-1
P5VS0_EN
02
(S0)
8
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
PPVIN_S0_MCPCORE
D
REVISION
R
DELAY
SIZE
051-7982 BRANCH
PAGE
3 OF 109 SHEET
OF
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
BOM Variants TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
639-0035
PCBA,MLB,FOX DDR CONN,K84
K84_COMMON,CPU_2_0GHZ,FOX_DDR_CONN,EEE_8CG
Bar Code Labels / EEE #’s TABLE_BOMGROUP_ITEM
PART NUMBER
DESCRIPTION
REFERENCE DES
826-4393
QTY 1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:8CG]
CRITICAL CRITICAL
BOM OPTION EEE_8CG
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:A36]
CRITICAL
EEE_A36
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:CXR]
CRITICAL
EEE_CXR
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:CY1]
CRITICAL
EEE_CY1
TABLE_BOMGROUP_ITEM
639-0254
PCBA,MLB,MLX DDR CONN,K84
K84_COMMON,CPU_2_0GHZ,MLX_DDR_CONN,EEE_A36 TABLE_BOMGROUP_ITEM
085-0748
K84 MLB DEVELOPMENT BOM
K84_DEVEL_ENG TABLE_BOMGROUP_ITEM
639-0554
PCBA,MLB,FOX DDR CONN,PVT K84
K84_COMMON_PVT,CPU_2_0GHZ,FOX_DDR_CONN,EEE_CXR TABLE_BOMGROUP_ITEM
639-0555
PCBA,MLB,MLX DDR CONN,PVT K84
K84_COMMON_PVT,CPU_2_0GHZ,MLX_DDR_CONN,EEE_CY1 TABLE_BOMGROUP_ITEM
085-1076
D
K84 MLB DEVELOPMENT PVT
K84_DEVEL_PVT
D
BOM Groups TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
K84_COMMON
COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_ENG,K84_PROGPARTS
K84_COMMON_PVT
COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_PROD,K84_PROGPARTS
K84_MCP
MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC
K84_MISC
ONEWIRE_PU,DP_ESD,MIKEY,LDO_NO,MEM_SENSE,1P05_HIGH_SIDE_SENSE,MCP_T_DIODE_SENSOR,MCPSMC_DIGITEMP_YES
K84_PROGPARTS
BOOTROM_PROG,SMC_PROG,WELLSPRING_PROG
K84_DEBUG_ENG
DEVEL_BOM,SMC_DEBUG_YES,XDP
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
K84_DEBUG_PVT
DEVEL_BOM_PVT,SMC_DEBUG_YES,XDP,NO_VREFMRGN
K84_DEBUG_PROD
SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN
K84_DEVEL_ENG
DEBUG_ADC,XDP_CONN,LPCPLUS,VREFMRGN
K84_DEVEL_PVT
XDP_CONN,LPCPLUS
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Module Parts
PART NUMBER
C
DESCRIPTION
REFERENCE DES
337S3769
1
PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7550
U1000
CRITICAL
338S0710
1
IC,GMCP,MCP79,35X35MM,BGA1437,B03
U1400
CRITICAL
MCP_B03
516S0706
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA
J3200
CRITICAL
FOX_DDR_CONN
516-0201
1
CONN,204P,SODIMM,P=0.6MM
J3100
CRITICAL
FOX_DDR_CONN
516S0790
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,NON/SC
J3200
CRITICAL
MLX_DDR_CONN
516-0213
1
CONN,204P,SODIMM,P=0.6MM,HF
J3100
CRITICAL
MLX_DDR_CONN
452-1708
4
SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97
SCREW1,SCREW2,SCREW3,SCREW4
CRITICAL
514-0704
1
CONN,RCPT,RJ45,PLASTIC,HF,K83/K84
J3900
CRITICAL
514-0705
2
CONN,RCPT,USB,4P,PLASTIC,HF,K83/K84
J4600,J4610
CRITICAL
514-0706
1
CONN,RCPT,MDP,20P,PLASTIC,HF,K83/K84
J9400
CRITICAL
514-0718
1
CONN,RCPT,S/PDIF,TX,HF,CFR,K83/K84
J6700
CRITICAL
353S2718
1
IC,ISL88042,4X V MONTR,2.78/2.86V,TDFN8
U7870
CRITICAL
870-1885
4
POGO PIN,MED,NOISE-IMPROVED,K84
ZS0900,ZS0901,ZS0902,ZS0903
CRITICAL
CRITICAL
870-1885
3
POGO PIN,MED,NOISE-IMPROVED,K84
ZS0908,ZS0909,ZS0911
CRITICAL
870-1886
5
POGO PIN,TALL,NOISE-IMPROVED,K84
ZS0904,ZS0905,ZS0906,ZS0907,ZS0910
CRITICAL
870-1886
5
POGO PIN,TALL,NOISE-IMPROVED,K84
ZS0912,ZS0913,ZS0914,ZS0915,ZS0919
CRITICAL
870-1887
3
POGO PIN,THIN,NOISE-IMPROVED,K84
ZS0917,ZS0918,ZS0916
CRITICAL
104S0033
4
RES,MF,1/4W,6.8OHM,5%,0805,SMD
R6612,R6617,R6630,R6633
CRITICAL
1
CONN,RCPT,60P,P=0.4,STK HT 1.0
J1300
CRITICAL
518S0774
B
QTY
353S2718 514-0704 514-0705 514-0706 514-0718
IS IS IS IS IS
NEW INTERSIL PART FOR FIXING B4 CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI
DONGLE ISSUE PLATING VERSION PLATING VERSION PLATING VERSION PLATING VERSION
OF OF OF OF
514-0692 514-0689 514-0691 514-0694
PART PART PART PART
FOR FOR FOR FOR
BOM OPTION CPU_2_0GHZ
C
K84 BOARD STACK-UP
XDP_CONN
RJ45 CONNECTOR USB CONNECTORS MINI DP CONNECTOR AUDIO CONNECTOR
DEVELOPMENT BOM
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
085-0748
1
K84 MLB DEVELOPMENT BOM
DEVEL
CRITICAL
DEVEL_BOM
085-1076
1
K84 MLB DEVELOPMENT PVT
DEVEL_PVT
CRITICAL
DEVEL_BOM_PVT
Top
SIGNAL
2
GROUND
3
SIGNAL(High Speed)
4
SIGNAL(High Speed)
5
GROUND
6
POWER
7
POWER
8
GROUND
B
9
SIGNAL(High Speed)
10
SIGNAL(High Speed)
Programmable Parts 338S0563
1
IC,SMC,HS8/2117,9X9MM,TLP,HF
U4900
CRITICAL
SMC_BLANK
341S2485
1
IC,SMC,K84
U4900
CRITICAL
SMC_PROG
335S0610
1
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
U6100
CRITICAL
BOOTROM_BLANK
341S2487
1
IC,PRGRM,EFI BOOTROM,UNLOCK,K84
U6100
CRITICAL
BOOTROM_PROG
337S2983
1
IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794
U5701
CRITICAL
WELLSPRING_BLANK
341S2491
1
IC,WELLSPRING CONTROLLER,K84
U5701
CRITICAL
WELLSPRING_PROG
11
GROUND
BOTTOM
SIGNAL
LOCKED BOOTROM APN IS 341S2488
Alternate Parts TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
152S0693
152S0778
ALL
DALE/VISHAY, MAGLAYERS AS ALTERNATE
152S0796
152S0685
ALL
CYNTEC AS ALTERNATE
TABLE_ALT_ITEM
A
SYNC_MASTER=K24_MLB
TABLE_ALT_ITEM
157S0058
157S0055
ALL
DELTA AS ALTERNATE
138S0603
138S0602
ALL
MURATA AS ALTERNATE
SYNC_DATE=01/19/2009
BOM Configuration DRAWING NUMBER
TABLE_ALT_ITEM
Apple Inc.
TABLE_ALT_ITEM
128S0093
128S0218
ALL
KEMET AS ALTERNATE
152S0516
ALL
MAGLAYERS AS ALTERNATE
152S0586
ALL
MAGLAYERS AS ALTERNATE
NOTICE OF PROPRIETARY PROPERTY:
D
REVISION
C.0.0
R
152S0847
SIZE
051-7982
TABLE_ALT_ITEM
152S0874
A
PAGE TITLE TABLE_ALT_ITEM
BRANCH
TABLE_ALT_ITEM
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
TABLE_ALT_ITEM
104S0018
104S0023
ALL
DALE/VISHAY AS ALTERNATE
PAGE
4 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8 Revision History
D
C
B
A
7 NOTE: All page numbers are .csa, not PDF.
6
5
4
3
2
1
See page 1 for .csa -> PDF mapping.
1/19/2009:INITIAL RELEASE 0.0.1- ALL PAGES SYNC’ED FROM K24 - REPLACED K24 REFERENCES WITH K84 3/20/2009: RELEASE 7.1.0 (MAJOR)3/25/2009: RELEASE 7.3.0 (MAJOR)- UPDATED SCHEMATIC AND PCB PART NUMBER INFO - PAGE 31 & 32: PIN SWAPS ON THE DDR3 CONNECTOR PAGES FOR ROUTING PURPOSES (REFER TO RON’S EMAIL) - DELETED PAGE 71 (5V S3 LT POWER SUPPLY) AS THERE IS NO NEED OF A SEPARATE 5V S3/S0 SUPPLY 1/21/2009: RELEASE 0.0.2- PAGE 7: DELETED PP5VLT_S3 NETS - DELETED PAGES 41,42,43,48,97,98,105 [FIREWIRE, IR CONTROLLER, BACKLIGHT CKT] ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.0.0*** - PAGE 7: RENAMED PP5VRT_S3 TO PP5V_S3 ["LT" & "RT" NOMENCLATURE CLEAN-UP] - UPDATED BOM CONFIGURATIONS - PAGE 8: COMBINED 5V S3 LT AND RT ALIASES INTO ONE =PP5V_S3_REG AND RENAMED NETS - DELETED IR SPECIFIC NETS ON SATA CONNECTOR -PG. 67, DELETED R6726 (LT & RT NOMENCLATURE CLEAN-UP) -PG. 66, CHANGED C6610/11/30/31 TO 0.015UF - PAGE 8: DELETED =PPVIN_S3_5VLTS3, =PP5VLT_S3_V5IN NETS 1/21/2009: RELEASE 0.0.3-PG. 68, ADDED MIKEY MIC LOAD COMPARATOR CKT - PAGE 9: ADDED ALIAS MCP_GPIO_4 FOR MIKEY MIC LOAD DETECT CIRCUIT - CORRECTD BOM CONFIG TABLES -PG. 68, ADDED R6873 - PAGE 21: UNSTUFFED R2143 PU ON MCP_GPIO_4 AS THERE IS ALREADY A 100K PU ON AUDIO PAGE -PG. 68, CORRECTED CODEC OUTPUT SIGNALS TABLE COMMENTS - PAGE 45: ADDED APN TEXT NOTE FOR SIL CONNECTOR 1/21/2009: RELEASE 0.0.4- PAGE 55: ADDED BC846BM NPN TRANSISTOR (APN 372S0129) TO MCP T-DIODE SENSOR CIRCUIT SIMILAR TO - CORRECTED BOM CONFIG TABLE (ADDED BACK BKLT_ENG) THAT IN CPU T-DIODE SENSOR AND STUFFED C5540 - ADDED BACK PAGES 97-98 (LCD BACKLIGHT DRIVER AND SUPPORT CKT) 3/24/2009: RELEASE 7.2.0 (MAJOR)- PAGE 72: RENAMED NETS AND NOTES TO REMOVE REFERENCES TO RT POWER SUPPLY - DELETED KB BACKLIGHT DRIVER/DETECTION CKT - PAGE 72: REPLACED L7260 WITH APN 152S0959 AS PER DAYU - PAGE 4: CHANGE THE CPU TO NEW APNB 337S3704 - PAGE 72: ADDED C7282 APN 128S0218 IN PARALLEL WITH C7280 AS PER DAYU 1/23/2009: RELEASE 0.0.5- PAGE 7: DELETED PPBUS_R_G3H AS NO NEED OF TWO PPBUS BRANCHES - PAGE 73: REPLACED Q7320 AND Q7321 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU - UPDATED PAGES 72-73 : 5V/3.3V & DDR3 POWER SUPPLIES AS PER FLO’S RECOMMENDATIONS - PAGE 8: COMBINED TWO SEPARATE PPBUSA/B BRANCHES INTO ONE =PPBUS_G3H - PAGE 74: REPLACED C7433 AND C7431 WITH 0.001UF CAPS APN 132S1035 - SET SOURCE SYNC OF AUDIO PAGES (62-63, 65-68) FROM LENG’S AUDIO PAGES - PAGE 9: ADDED LVDS HOLE APN 998-1521 - PAGE 75: REPLACED C7576 WITH 0.022UF APN 132S0102 CAP TO INCREASE THE SLEW RATE - PAGE 75: ADDED A NOTE OCP=14.5A TO R7575 - PAGE 34: CHANGED J3401 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA 1/27/2009: TMLB FIRST RELEASE 0.0.1- PAGE 45: MIRROR’ED J4500 AND RECONNECTED PINS AS PER NEW PIN OUT DESCRIPTION FROM DIANA - PAGE 75: REPLACED Q7560 AND Q7565 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU - NAME CHANGED TO TMLB. SO CALLING IT RELEASE 0.0.1 - PAGE 45: CHANGED J4501 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA - PAGE 76: CORRECTED MAX OUTPUT NOTE TO REFLECT 7.2A INSTEAD OF 8A - UPDATED SCHEM AND PCBF PART NUMBER INFO - PAGE 50: DELETED SMC_PPBUSA_ISENSE ALIAS AND STUFFED R5055 - PAGE 76: REPLACED Q7620 WITH 2 CSD58858 APN 376S0790 MOSFETS AS PER DAYU - UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_PROD AND BLANK PROGRAMMED PARTS. ALSO, DELETED BMON_ENG BOM OPTION - PAGE 54: DELETED U5470 INA210 CIRCUIT AS THERE IS NO NEED - PAGE 77: ADDED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL VIA A 0 OHM RESISTOR TO PIN 3 (PG) OF THE LDO - PAGE 54: REMOVED BMON CURRENT SENSE CIRCUIT - PAGE 70: REMOVED R7080 SENSE RESISTOR AND RENAMED =PPBUSB_G3H TO =PPBUS_G3H AS NO NEED - PAGE 78: DELETED P5V_LTS3_PGOOD AS THERE IS NO 5V LT POWER SUPPLY ANYMORE - REMOVED ALS SPECIFIC NETS (PAGE 34 & 52) TO HAVE TWO PPBUS BRANCHES - PAGE 78: RENAMED =P5VRTS3_EN_L TO =P5VS3_EN_L - PAGE 70: DELETED R7050 CONNECTION BETWEEN CHGR_AGATE AND CHGR_LOWCURRENT_GATE - PAGE 78: ROUTED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL TO THE WIRED AND CIRCUIT 2/5/2009: RELEASE 0.0.2 AS PER DAYU - COPIED TMLB OVER TO MLB AS K84 WILL BE PENRYN SKU WHILE K83 WILL BE ATOM SKU - PAGE 70: ADDED R7050 (6259_YES) CONNECTION FROM PIN 4 (VREF) TO PM_SLP_S3_L AS PER DAYU - UPDATED THE SCHEMATICS, PCBF AND PCBA PART NUMBER INFO - PAGE 70: AS PER DAYU, ADDED: 3/26/2009: RELEASE 7.4.0 (MAJOR)- REPLACED TEXT TMLB WITH MLB THROUGH OUT THE SCHEMATICS R7051 (6259_YES) CONNECTION BETWEEN CHGR_PIN26 AND CHGR_LOWCURRENT_GATE; - PAGE 4: UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_ENG FOR K84_COMMON BOM GROUP R7052 (6259_NO) CONNECTION BETWEEN CHGR_PIN26 AND GND_CHGR_SGND; - PAGE 4: UPDATED EEE NUMBER - 8CG - PAGE 60: REPLACED DUAL PACKAGE OPA330 OPAMPS WITH SINGLE PACKAGE ONES - APN 353S2179 R7053 (6259_YES) CONNECTION BETWEEN CHGR_PIN6 AND PIN 12 (VHST); - PAGE 4: ADDED 085 DEVELOPMENT BOM VARIANT & K84_DEVEL_ENG, K84_DEVEL_PVT BOM GROUPS R7054 (6259_NO) CONNECTION BETWEEN CHGR_PIN6 AND GND_CHGR_SGND [U6030, U6031, U6040, U6041]. ALSO, ADDED C6031 & C6041 - PAGE 7: DELETED IR_RX_OUT, PP5V_S3_IR_R, KBDLED_ANODE, SMC_KBDLED_PRESENT_L - PAGE 73: RENAMED TEXT NOTE FOR =PP1V5_S3_REG NET TO VOLTAGE=1.5V - PAGE 9: DELETED EXTRA MEDIUM POGO PIN ZS0912 AND SCREW HOLES Z0908, Z0909 - PAGE 8: DELETED FIREWIRE, IR AND BMON SPECIFIC NETS - PAGE 97: STUFF R9716 AS PER KIRAN’S FEEDBACK - PAGE 9: DELETED R0950 PCIE_FW_PRSNT_L ’S PD RESISTOR 3/26/2009: RELEASE 7.5.0 (MAJOR)- PAGE 9: ADDED UNUSED FIREWIRE LANE NETS AS TEST POINTS - PAGE 9: CHANGED ALIAS OF FW_PME_L TO TP_FW_PME_L - PAGE 73: ADDED SHORT XW7304 FROM PIN 1 OF C7300 TO POWER GND (PIN 18) - PAGE 9: ADDED SMC_SYS_KBDLED TP ALIAS - PAGE 72: REPLACED C7282 WITH OSCON APN 128S0248 IN PARALLEL WITH C7280 AS PER DAYU - PAGE 55: REPLACED CPU/MCP THERMAL SENSORS U5515 ANDB U5535 WITH THE CHEAPER VERSION APNB 353S2573 - PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 & C7240 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS 3/26/2009: RELEASE 7.6.0 (MAJOR)- PAGE 72: REPLACE Q7220 WITH SIZ700DT - PAGE 73: REPLACE 16V INPUT SIDE CAPS C7331 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS - PAGE 76: REPLACE Q7620 WITH SIZ700DT - ADDED PLACEMENT NOTES TO XW SHORTS AS PER DAYU - ADDED OMIT BOM OPTION TO ALL THE XW SHORTS 2/6/2009: MAJOR RELEASE 0.1.0 - ADDED DIDT=TRUE ATTRIBUTE TO BOOT/VBST SIGNALS OF ALL THE SWITCHING SUPPLIES - NO CHANGES SINCE LAST MINOR RELEASE 0.0.2 - PAGE 8: DELETED =PP3V42_G3H_BATT AS THERE IS NO BIL CONNECTOR - PAGE 8: ADDED =PP3V42_G3H_HALL FOR THE HALL EFFECT CONNECTOR 2/6/2009: WEEKLY RFA BOM RELEASE 1.0.0- PAGE 8: ADDED =PP3V3_S3_AUDIO ALIAS NET FOR CASEY’S NEW CHANGES BELOW - NO CHANGES SINCE LAST MAJOR RELEASE 0.1.0 - PAGE 8: DELETED =PP3V42_G3H_PPBUSAISNS AS PPBUS SENSE CIRCUIT HAS BEEN REMOVED - PAGE 8: RENAMED ALIAS =PP5V_S3_P5VS0FET TO =PP5V_S3_P5VLTS0FET AS THIS GOES TO 5V LT S0 FET CIRCUIT 2/15/2009: RELEASE 2.0.0 (WEEKLY RFA)- PAGE 8: ADDED =PP5V_S3_P5VRTS0FET ALIAS, GOING TO 5V RT S0 FET CIRCUIT 1. PAGE 3: POWER BLOCK DIAGRAM - ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR. ALSO, ADDED SENSE RESISTOR ON PPBUS - PAGE 8: ADDED PLACEMENT NOTE TO Q5502 2.CKT E PAGE 8: ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR, WHILE PPBUSB FEEDS 5V/3.3 V SUPPLY, LCD BKLT & PPBUS VOLTAGE SENS - PAGE 9: ADDED OMIT ATTRIBUTE TO THE LVDS HOLE 3. PAGES 31, 32: REPLACED 0.1UF 0204 TYPE DDR3 DECOUPLING CAPS WITH 0402 TYPE CAPS ( APPLE P/N : 132S1059) - PAGE 69: ADDED HALL EFFECT CONNECTOR CIRCUIT J6955 APN 516S0787 4. PAGE 34: REPLACED AIRPORT CONNECTOR WITH PN 516S0580 AND UPDATED CONNECTIONS ACCORDINGLY - PAGE 79: RENAMED INPUT VOLTAGE NETS OF 5V S0 FET CIRCUITS TO REFLECT RT AND LT 5. PAGE 34: REPLACED SCHMITT’S TRIGGER WITH PN 311S0449 (MATCHES UPDATED ALIASES ON PAGE 8) 6. PAGE 45: REPLACED SATA HDD CONNECTOR WITH APPLE PN 516S0350 AND UPDATED CONNECTIONS ACCORDINGLY 7. PAGE 45: ADDED 2 PIN CONNECTOR (APPLE PN 518S0519) FOR SIL 8. PAGE 46: REPLACED ESD DIODES WITH CHEAPER PN 377S0066 ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.5.0*** 9. PAGE 54: ADDED BOM OPTION- DEBUG_SENSE- TO CPU 1.05V/CPU VCORE HIGH SIDE CURRENT SENSE AND MCP MEM VDD CURRENT SENSE CIRCUITS FOR DEVELOPMENT BOM -PG. 67, ADDED R6725 10. PAGE 4: ADDED DEBUG_SENSE BOM OPTION TO THE K84_DEVEL_ENG BOM GROUP -PG. 67 ADDED =PP3V3_S3_AUDIO NET 11. UPDATED PAGE THESE 58: DELETED NET NAMES IPD ON FLEX PAGE CONNECTOR 7 ALSO J5800. RENAMED PP18V5_S3, PP3V3_S3_LDO_R, PP3V3_S3_LDO TO PP18V5_S3_LDO, PP3V3_S3_IPD_R AND PP3V3_S3_IPD RESPECTIVELY TO MATCH WITH NEW ADDED PAGE 60 NET NAMES. -PG. 67, DELETED L6706 12. ADDED PAGE 60 AND COPIED OVER ZEPHYR2 SCHEMATICS PAGE FROM M97 IPD_FLEX_WELLSPRING. DELETED THE IPD BOARD CONNECTOR. CALLING IT WELLSPRING 3 -PG. 67, ADDED XW6702 13. PAGE 69: REPLACED BATTERY CONNECTER WITH PN 518S0540 AND BIL CONNECTOR WITH PN 518S0588. UPDATED CONNECTIONS ACCORDINGLY -PG. 66, UPDATED 5V S3 ALIAS NOTES 14. PAGE POWER) ALIAS 70: ON DIVIDED PAGE 8 PPBUS INTO TWO BRANCHES - PPBUSA & PPBUSB. ADDED SENSE RESISTOR R7080 (2 MOHMS) ON PPBUSA. ALSO ADDED INA210 AMPLIFIER CKT ACROSS SENSE LINES. ADDED PP3V42_G3H_PPBUSAISNS (IN210 -PG. 67, NO STUFFED R6724 15: PAGE 97: REPLACED BKLT DRIVER CKT WITH THAT OF FREESCALE PART, SIMILAR TO K19I 16. PAGE 69: MOVED THE DECAP C6908 TO CORRECT PART U6901.5 ( SIMILAR TO K24) 17. PAGE 4: REMOVED BKLT_ENG BOM OPTION 3/29/2009: RELEASE 8.0.0 (RFA)***PAGES SYNC’ED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 1.0.0*** 1. REPLACED MIKEY CD3272 WITH CD3282 - PAGE 7: SCRUBBED THROUGH THE FUNCTIONAL TEST POINTS AGAINST TOM’S SPREADSHEET 2. ADAPT JACK INSERT DETECT CIRCUIT TO CD3282 JACK INSERT DETECT FUNCTION. 3/6/2009: RELEASE 6.0.0 (RFA:)- PAGE 7: RENAMED RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR 3. REMOVED JACK EXTRACT CIRCUITRY, FUNCTION IS TAKEN OVER BY CD3282 - PAGE 7: DELETED BATT SIGNAL CONN AND ADDED HALL EFFECT CONNECTOR TEST POINTS 4. REMOVE FM ANTENNA NET. - PAGE 4: ADDED 152S0693 AS ALT FOR 152S0778 FOR SUPPLY REDUNDANCY - PAGE 7: DELETED THERMAL FUNC_TEST SECTION - PAGE 4: ADDED 138S0603 AS ALT FOR 138S0602B FOR SUPPLY REDUNDANCY - PAGE 9: ADDED TP_ ALIASES FOR - CARDREADER_RESET, USB_CARDREADER_N/P, AND ***PAGES SYNC’ED FROM K24 SINCE LAST RELEASE 1.0.0*** - PAGE 4: ADDED CYNTEC ALTERNATES FOR 107S0074 --> 107S0138 [R7020] AND 107S0075 USB_IR_N/P 1. PAGE 75: MCP VCORE INDUCTOR CHECK FOR PD: CHANGED L7560 TO 152S0966 AND THEN TO 152S0867. BUT NOW IT IS BACK TO 13A PART FOR NOW [R7008] --> 107S0139 - PAGE 9: FIXED BAD_TP_NC NETS - TP_RTL8211_CLK125, TP_PP3V3_ENET_PHY_VDDREG 2. ADDED DIDT TO ALL THE GATE AND PHASE NETS - PAGE 4: ADDED DALE/VISHAY ALTERNATES FOR 104S0023 --> 104S0018 - PAGE 9: DELETED Z0912 MLB MOUNTING HOLE AS NO LONGER NEEDED - PAGE 4: ADDED BOM OPTION 6259_NO TO THE TABLE UNDER K84_MISC BOM GROUP - PAGE 34: RENAMED TITLE: RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR - PAGE 7: DELETED SMC_BIL_BUTTON_L NET FROM BATT SIGNAL CONN GROUP AS BIL IS NO LONGER A POR - PAGE 50: REPLACED R5030 WITH APN: 114S0114,(IT’S A 1% TOL, 1/16W, 0402, 84.5OHM RESISTOR) 2/25/09: WEEKLY RFA RELEASE (3.0.0) - PAGE 8: DELETED =PP3V42_G3H_AUDIO AS IT IS NO LONGER USED - PAGE 66: FIXED UNNAMED NETS CONNECTED TO - R6632 - ADDED DIDT ATTRIBUTE - PAGE 8: DELETED =PP3V3_S0_TPAD AS THERE IS NO KEYBOARD BACKLIGHT DRIVER - PAGE 74: FIXED UNNAMED NETS CONNECTED TO - XW7401, XW7402, XW7403 AND XW7404 - PAGE 4: REMOVED SUPERCAP_NO BOM OPTION. ADDED DEBUG_ADC BOM OPTION UNDER K84_DEVEL_ENG - PAGE 8: DELETED =PP3V42_G3H_5V3V3_EN AS IT IS NO LONGER USED - PAGE 78: FIXED BAD_TP_NC NETS - TP_DDRREG_PGOOD (THIS IS FOR NEW SENSOR PAGE 60) - PAGE 9; ADDED 3 ADDITIONAL TALL POGO PINS AS PER NEW MCO AND DELETED ZS0909 SHORT POGO AS IT WAS EXTRA - PAGE 76: REPLACED L7620 WITH ITS REPLACEMENT - APN 152S0518 - PAGE 4: CORRECTED APN FOR PROGRAMMED PARTS - SMC, BOOT ROM, WELLSPRING - PAGE 9: ADDED TP ALIASES TO IMVP6_VR_TT AND IMVP6_NTC - PAGE 69: CHANGE PIN OUTS OF J6955 AS PER CHINMAY - PAGE 4: REMOVED LDO_YES BOM OPTION - PAGE 34: ADDED LC FILTER (L3406 AND C3432) ON PP3V3_S3_BT POWER RAIL AS PER JOHN SCHEN’S FEEDBACK - PAGE 34: REPLACED THE AIRPORT CONNECTOR WITH 1.8 MM HEIGHT CONNECTOR APN 516S0582 - PAGE 8: DIVIDED PP5V_S0_FET INTO TWO BRANCHES - PP5VRT_S0_FET & PP5VLT_S0_FET (FOR ROUTING PURPOSE, - PAGE 39: REPLACED ETHERNET CONNECTOR WITH THAT OF M97A/K24 PART APN 514-0636 (SYNC’ED WITH K24) 3/31/2009: RELEASE 9.0.0 (RFA)5V S3 IS DIVIDED INTO RT AND LT POWER SUPPLY AND WILL HAVE CORRESPONDING S0 FETS) - PAGE 8: DIVIDED PP5V_S3_REG INTO TWO BRANCHES - PP5VRT_S3_REG & PP5VLT_S3_REG - PAGE 45: RENAMED =PP5V_S0_HDD_R TO PP5V_S0_HDD_R (AS PER UNALIASED.LST REPORT) - PAGE 8: ADDED PP5V_S3_DEBUG_ADC_AVDD/DVDD & PP5V_S3_DEBUG_ISNS ALIASES FOR NEW SENSOR PAGE 60 - PAGE 50: ADDED UNUSED NET ALIAS FOR SMC_BIL_BUTTON_L (NC_SMC_BIL_BUTTON_L) - PAGE 4: DELETED DEBUG_SENSE BOM OPTION AND ADDED MEM_SENSE AND - PAGE 8: ADDED PP3V3_S3_BT ALIAS FOR BLUETOOTH ON RIGHT CLUTCH CONNECTOR PAGE - PAGE 52: DELETED TERM BIL FROM SMC BATTERY & BIL CONNECTIONS 1P05_HIGH_SIDE_SENSE OPTIONS UNDER K84_COMMON BOM GROUP - PAGE 8: ADDED ALIAS PPVIN_S3_5VLTS3 UNDER PPBUSB - PAGE 57: ADDED PLACEMENT NOTES TO C5702 AND C5704 AS PER JOHN SCHEN’S FEEDBACK - PAGE 4: ADDED MCP_T_DIODE_SENSOR, MCPSMC_DIGITEMP_NO BOM OPTIONS UNDER - PAGE 8: ADDED ALIAS PP5VLT_S3_V5IN UNDER PP5VRT_S3_REG - PAGE 59: REPLACED SMS PART WITH THE NEW BOSCH BMA141 ANALOG PART. ADDED R5923 10K PU RESISTOR ON K84_COMMON BOM GROUP - PAGE 4: ADDED SHORT POGO PIN 870-1699 AS ALTERNATE FOR THE MEDIUM ONES - PAGE 28: REMOVED RTC POWER SOURCES CIRCUIT AND SUPERCAP_NO BOM OPTION FROM R2820 SEL1 SIGNAL AND REMOVED 10K PD ON ST PIN. REPLACED C5926 WITH 0.01UF CAP AS PER DATA SHEET. AND, - PAGE 34: SINCE X16 AIRPORT CARD SOLUTION IS BEING USED, PP5V_S3_WLAN IS REPLACED BY PP3V3_S3_WLAN REPLACED C5923-C5925 CAPS WITH 0.033 UF VALUES FOR CUT-OFF FREQUENCY OF ~146HZ - PAGE 4: UPDATED DESCRIPTION FOR THE CPU (GOING TO Q3450). ALSO, REPLACED PP5V_WLAN WITH PP3V3_WLAN ON PAGE 6 (FUNCTIONAL TEST POINTS) - PAGE 60: CORRECTED PLACEMENT NOTE ASSOCIATED TO XW6080 TO REFLECT D9710 INSTEAD OF D9701 - PAGE 7: UPDATED TPS AS PER NEW UPDATE FROM TOM (SPREADSHEET ATTACHED TO THE RADAR) - PAGE 34: R3453 IS MODIFIED TO 110K RESISTOR, R3454 IS NOSTUFF AND R3453 IS PULLED UP TO PP3V3_WLAN_F. - PAGE 69: CHANGED L6995 TOB APN 152S1017 FOR COT SAVING AND EFFICIENCY - PAGE 12: REPLACED C1260 WITH APN 128S0267 AS PER DAYU THIS IS TO ENSURE 3.3V LEVEL AT THE INPUT OF U3402 AND MAINTAIN 100MS DELAY SPEC BETWEEN 3.3V POWER - PAGE 69: REMOVED BIL CIRCUIT AS IT NO LONGER A POR [R6960, C6954, D6951, C6953, C6952, J6955, C6951] - PAGE 34: DELETED TEXT NOTE ASSOCIATED WITH J3401 TO THE CARD GETTING STABLE AND AIRPORT GETTING OUT OF RESET - PAGE 70: MOVED C7028 TO PPVBAT_G3H_CHGR_REG AS PER JOHN SCHEN’S FEEDBACK - PAGE 45: ADDED VOLTAGE, MIN LINE AND NECK WIDTH FOR PP5V_S0_HDD_FLT - PAGE 34: DISCONNECTED PP5V_S3_BTCAMERA_F POWER RAIL FROM THE CONNECTOR AND REPLACED IT WITH PP3V3_S3_BT - PAGE 70: ADDED PLACEMENT NOTE TO C7027 AS PER JOHN SCHEN’S FEEDBACK - PAGE 52: ADDED 0 OHMS STUFFING OPTION TO CONNECT MIKEY SMBUS CONNECTIONS TO MCP SMBUS 0. (SIMILAR TO M96). CAMERA SIGNALS ARE ROUTED VIA LVDS CONNECTOR. MOVED PP5V_S3_BTCAMERA POWER CIRCUIT - PAGE 70: REPLACED R7080 WITH APN 107S0142 WHICH IS TRUE 4-TERMINAL SENSE RESISTOR WITH SMALLER PACKAGE ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0 OHMS ALONG WITH THE USB CAMERA SIGNALS TO LVDS PAGE. ALSO, RENAMED THIS POWER RAIL TO PP5V_S3_CAMERA ON LVDS (DAYU’S RECOMMENDATION) - PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN MIKEY AND MCP SMBUS 1 CONNECTIONS. PAGE - PAGE 70: ADDED BOM OPTION 6259_YES TO R7050 AND 6259_NO TO U7060 AND AMON PULLDOWN LOGIC AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_NO WITH THESE 0 OHMS - PAGE 34: ADDED SENSE RESISTOR R3452 ON PP3V3_WLAN SIGNAL CIRCUIT COMPONENTS. TURNED ON 6259_NO, FOR NOW, ON PAGE 4 TABLE - PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN SMC B SMBUS AND MCP SMBUS 1 - PAGE 34: ADDED CHOKES ON PCIE TX/RX SIGNALS. UPDATED PAGE 6 (FUNCTIONAL TEST POINTS) ACCORDINGLY - PAGE 72: CONNECTED SMC_PM_G2_EN SIGNAL TO EN0 PIN 13 OF U7200 VIA A 100K RESISTOR FOR KEEPING THE POWER SUPPLY CONNECTIONS. AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0 - PAGE 34: REPLACED L3404 WLAN INDUCTOR WITH LOW DCR 0603 PART - APN 155S0367 OFF IN CASE IF SMC TURNS OFF OHMS - PAGE 39: REPLACED ETHERNET CONNECTOR WITH APN 514-0668 (SIMILAR TO K36B) - PAGE 72: ADDED PLACEMENT NOTE TO C7230 AS PER JOHN SCHEN’S FEEDBACK - PAGE 52: ADDED BOM OPTION MCPSMC_DIGITEMP_NO TO R5230 AND R5231 - PAGE 72: REMOVED NOSTUFF’ED C7251 AS PER DAYU - PAGE 54: REPLACED DEBUG_SENSE BOM OPTION WITH MEM_SENSE FOR MCP MEMORY VDD - PAGE 45: CHANGED SATA HDD CONNECTOR TO APN 516S0616 - PAGE 73: REPLACED C7307,C7308 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY) CURRENT SENSE CIRCUIT AND WITH 1P05_HIGH_SIDE_SENSE FOR CPU 1.05V AND - PAGE 73: ADDED PLACEMENT NOTE TO C7333 AS PER JOHN SCHEN’S FEEDBACK - PAGE 45: ADDED SENSE RESISTORS R4598 AND R4599 ON 5V ODD AND 5V HDD RAILS RESPECTIVELY CPU VCORE HIGH SIDE CURRENT SENSE CIRCUIT - PAGE 50: UNSTUFFED R5055 AND USED SMC_NB_MISC_ISENSE SIGNAL PORT (SMC) FOR CONNECTING PPBUSA ISENSE SIGNAL. - PAGE 73: DELETED NOTES AT THE BOTTOM RIGHT AFTER CONSULTING WITH DAYU - PAGE 55: ADDED MCP_T_DIODE_SENSOR BOM OPTION TO THE MCP T-DIODE THERMAL ADDED ALIAS ON THIS PAGE - PAGE 73: MOVED C7344 NEXT TO R7350 AND ADDED PLACEMENT NOTE (JOHN SCHEN WANTED IT TO BE NEXT TO L7320 SENSOR CIRCUIT DAYU PERFERRED IT TO BE AFTER THE SENSE RESISTOR - PAGE 51: REPLACED TWO DEMUX SOLUTION WITH A SINGLE DEMUX 1X2 SOLUTION. APN USED - 353S2220 - PAGE 59: DELETED R5923 FROM THE TEXT NOTE [ONLY CHIP SELECT IS BEING DEMUXED] - PAGE 74: ADDED PLACEMENT NOTES TO C7419,C7422 AND C7423 AS PER JOHN SCHEN’S FEEDBACK - PAGE 60: MANUALLY UPDATED RESISTORS VALUES (VOLTAGE DIVIDERS,AMPLIFIER GAINS, RC) TO MATCH WITH - PAGE 51: R5156, R5157 AND R5158 ARE NOW 0 OHM ISOLATION RESISTORS PLACED ON SPI BUS NEXT TO THE LOCATION WHERE - PAGE 74: STUFFED C7432 AS PER DAYU K19I UPDATES, EXCEPT VOLTAGE DIVIDER FOR PP3V3_WLAN [K19I USES 5V RAIL]. FOR IT BRANCHES INTO TWO - ONE GOING TO MLB SPI ROM AND THE OTHER GOING TO LPC CONNECTOR. THESE RESISTORS ARE - PAGE 74: REMOVED C7400, C7402, R7451 AND R7452 AS PER DAYU PP3V3_WLAN, R6010 HAS BEEN CHANGED TO 634K TO GET VDIVIDER = ~2V PLACED ON THE LPC CONNECTOR BRANCH. THIS IS TO AVOID STUBS IN PRODUCTION - PAGE 75: ADDED PLACEMENT NOTE TO C7563 AS PER JOHN SCHEN’S FEEDBACK - PAGE 75: ADDED C7590 (2.2UF) APN 138S0579 IN PARALLEL WITH C7563 AS PER DAYU - PAGE 52: ADDED SENSOR ADC CONNECTION BLOCK UNDER ’SMC 0 SMBUS CONNECTIONS’ SECTION - PAGE 74: CHANGE L7400 AND L7401 TO 152S1019 AS PER DAYU FOR COST SAVING. ALSO, UPDATED ASSOCIATED TEXTS - PAGE 102: ADDED CONN_PCIE_MINI_R2D_P/N AND CONN_PCIE_MINI_D2R_P/N NETS IN THE - PAGE 75: MOVED C7569 TO PPMCPCORE_S0_R AS PER JOHN SCHEN’S FEEDBACK - PAGE 54: MOVED PBUS INA210 CIRCUIT TO THIS CURRENT SENSOR PAGE. RENAMED REF DES AS PER THIS PAGE 54 CONSTRAINT SET - PAGE 55: DELETED J5590 CONNECTOR (CONNECTED TO HEAT-PIPE TEMPERATURE DETECTION RAILS) - PAGE 90: ADDED EMI CAPS (C9017-C9025) ON I2C, LED_RETURNS AND LCD_BKLT POWER RAILS GOING TO LVDS. - PAGE 70: ADDED TP TO PIN 13 - PAGE 55: REPLACED U5515 & U5535 WITH CHEAPER APN 353S2571 ADDED PLACEMENT NOTES TOO - PAGE 4: ADDED MIKEY_LOAD_DET BOM OPTION UNDER K84_MISC BOM GROUP - PAGE 60: REMOVED WELLSPRING 3 PAGE (GOING BACK TO K24 SOLUTION) AND REPLACED IT WITH K19I DEBUG SENSOR PAGE (SCHUTIL SYNC) - PAGE 94: REPLACED C9486 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY) - PAGE 61: RENAMED SPI SIGNALS TO MATCH WITH CHANGES ON PAGE 51 ***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 8.0.0*** - PAGE 69: ADDED BOM OPTION NOSTUFF TO D6950 FOR NOW - CHANGED R6211 & R6212 FROM 39 OHMS TO 22 OHMS ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 5.0.0*** - PAGE 69: ADDED D6951 ESD DIODE ON BIL SMBUS SIGNALS (NOSTUFF FOR NOW) -PG. 67, CHANGED U6700 CB INPUT TO BE CONTROLLED BY CS4206 GPIO0. - DELETED NOTE ABOVE U6500 - PAGE 69: REPLACED BATTERY CONNECTOR J6950 WITH APN 518S0540 (M96) CONNECTOR -PG. 62, CHANGED TP_AUD_GPIO_0 TO AUD_GPIO_0. - ADDED BOMOPTION = MIKEY_LOAD_DET ATTRIBUTE TO R6870, R6871, C6870, - PAGE 70: ADDED BYPASS 0 OHM RESISTOR R7050 (NOSTUFF FOR NOW) OPTION FOR NEW CHIP WHICH WON’T REQUIRE U7060 SOLUTION -PG.66, REPLACED THE LM48310’S (U6610/20/30) WITH LM48311’S - UPDATED SIGNAL PATH CHART TO INCLUDE MCP79 GPIO ASSIGNMENTS - PAGE 71: ADDED NEW PAGE FOR PP5V_LT_REG POWER SUPPLY. UPDATED ALL THE REF DES AS PER THE PAGE NUMBER -PG. 67, CONNECTED HP OUTPUTS TO NC OF U6700 AND LINE INPUTS TO NO OF U6700. - ADDED BOMOPTION = MIKEY ATTRIBUTE TO R6860, C6860, Q6802, R6864, R6865, & R6861 - PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 WITH 68UF OSCON CAP (APN 128S0275) & C7240 WITH 39UF (APN 128S0248) -PG. 68, CHANGED AUD_PORTB_DET_L TO AUD_PORTA_DET_L. C6871, U6870, C6872, R6872, & R6873 - PAGE 71: CHANGED C7160 TO 39UF OSCON CAP (APN 128S0248) - REMOVED NOTE RE: ROUTING TO MCP79 GPIO ABOVE U6870 -PG. 68, CHANGED AUD_PORTG_DET_L TO AUD_PORTB_DET_L. - PAGE 72: REPLACE Q7220 WITH SIZ700DT AND L7260 WITH SMALLER 10A PART (APN 152S0778) -PG. 67, SET MIN. LINE AND NECK WIDTHS FOR AUD_CONN_L AND AUD_CONN_R - REMOVED BOMOPTION = NOSTUFF ATTRIBUTE FROM R6724 - PAGE 73: ADDED SENSE RESISTOR R7350 ON 1.5V DDR3 SUPPLY RAIL - ADDED BOMOPTION = NOSTUFF ATTRIBUTE TO R6725 - PAGE 77: REMOVED 1.05V S0 PLL LDO CIRCUIT. AND, REMOVED LDO_NO BOM OPTION FROM R7745 ***PAGES SYNCED FROM K24 SINCE LAST RELEASE 5.0.0*** - PAGE 75: CHANGED C7571 & C7560 TO 68UF OSCON CAPS (APN 128S0275) - PAGE 25: CHANGED C2500,C2501,C2502,C2503,C2515,C2520,C2528,C2540,C2580,C2582,C2584,C2586,C2588, - PAGE 78: RENAMED P5VS3_EN_L TO P5VRTS3_EN_L (RT POWER SUPPLY ENABLE) AND ADDED R7814, C7814 S3 ENABLE CIRCUIT C2595 TO 138S0653 4/1/2009: RELEASE 9.1.0 (MAJOR)FOR GENERATING P5VLTS3_EN ENABLE SIGNAL FOR LT POWER SUPPLY - PAGE 26: CHANGED C2615,C6210 TO 138S0653 - PAGE 78: ADDED P5V_LTS3_PGOOD POWER GOOD SIGNAL (WIRED AND WITH OTHER S0 RAILS PGOOD) CORRESPONDING TO 5V LT - PAGE 77: CHANGED U7740 TO 500MA 1.05V LDO - PAGE 4: CHANGED MCP P/N TO 338S0702 AS PER CHALLEE POWER SUPPLY - PAGE 52: FIXED SENSOR ADC SMBUS CONNECTIONS (BOTH SCL AND SDA WERE WRONGLY CONNECTED - PAGE 78: ADDED 0 OHM ISOLATION RESISTORS ON POWER GOOD SIGNALS (BEFORE WIRED AND) TO SMB_0_S0_DATA NETS - PAGE 79: ADDED 5V LT S0 FET AND UPDATED NET NAMES FOR BOTH RT AND LT S0 FET CIRCUITS ACCORDINGLY 3/17/2009: RELEASE 7.0.0 (RFA)- PAGE 69: REFRESHED HALL EFFECT SENSOR WITH THE NEW SYMBOL - PAGE 90: UPDATED LVDS CONNECTOR CONNECTIONS AS PER STEVE’S RECOMMENDATION. ADDED CAMERA SIGNALS - ADDED PLACEMENT NOTES (ATTRIBUTE) TO ALL XW SHORTS - PAGE 90:RE-ROUTED LED_RETURN SIGNALS FOR LAYOUT FEASIBILITY(CHIP WAS MOVED TO TOP SIDE) - PAGE 97: ADDED BOM OPTION - NOSTUFF- TO R9702 AS PER K19I - PAGE 4: DELETING ENTRIES FOR 107S0138 AND 107S0139 FROM ALTERNATES PARTS TABLE AS THEY WOULD BE REPLACING - PAGE 90: ADDED C9017 (1000PF) CAP AS PER JOHN SCHEN - PAGE 8: DELETED PP5V_S0_BKL, RENAMED PP1V05_S0_MCP_PLL_UF_R TO PP1V05_S0_MCP_PLL_UF THE 107S0074/75 PARTS - PAGE 97: FIXED THE LCDBKLT_VIN SIGNAL NAME ASSOCIATION TO THE CORRECT NET INSTEAD OF - PAGE 8: DELETED PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_BKL_VDDIO, PP3V3_S0_MCP_PLL_VLDO - PAGE 7: RENAMED PP5V_S3_BTCAMERA_F WITH PP3V3_S3_BT_F R9730 PIN - PAGE 8: RENAMED PPVIN_S5_1V5S3_0V75S0 TO PPVIN_S5_1V5S30V75S0 - PAGE 7: DELETED PP5V_S0, PP5V_S3 AND ADDED PP5VRT_S0,PP5VLT_S0, PP5VRT_S3, PP5VLT_S3 DEBUG - PAGE 97: DISCONNECTED PGND (OF CAPS) FROM XW9700 AND ADDED A SEPARATE XW9701 - PAGE 28: DELETED FW_RESET_L SIGNAL VOLTAGE TEST POINTS SHORT TO ISOLATE NOISY PGND FROM THE SYSTEM GND. NAMED IT - PAGE 58: DELETED KB BKLT CIRCUIT - PAGE 7: ADDED PPBUS_R_G3H DEBUG VOLTAGE TEST POINT GND_LCDBKLT_PGND AND ASSIGNED MIN_LINE/NECK_WIDTH ATTRIBUTES - PAGE 60: UPDATED WLAN DIVIDER CIRCUIT WITH 3V3 POWER RAIL INSTEAD OF 5V - PAGE 8: DELETED ALIAS =PP1V05_S0_SMC_LS AS IT IS NO LONGER NEEDED - PAGE 97: RENAMED GND_LCDBKLT TO GND_LCDBKLT_SGND - PAGE 73: UPDATED 1.5V/0.75V POWER SUPPLY WITH CORRECT NET NAMES REFLECTING 1.5V/0.75V INSTEAD OF 1.8V/0.9V AND - PAGE 9: REMOVING 2 EXTRA TALL POGO PINS (ZS0911, ZS0912) AS PER NEW MCO - PAGE 97:DISCONNECTED PINS 2 AND 5 FROM GND PINS(13,19,21)AND CONNECTED SEPARATELY TO IN SYNC WITH PAGE 8 ALIASES - PAGE 9: REPLACED 5 SHORT POGO PINS WITH MEDIUM ONES AND ADDED THREE EXTRA MEDIUM ONES (TOTAL MEDIUM SYSTEM GND - PAGE 4: REMOVED 152S0778 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE SINCE L7260 AS HAS BEEN REPLACED WITH THIS PART POGO PINS = 8) AS PER NEW MCO - PAGE 97: REPLACED D9710 WITH 40V PART- APN 371S0580 AS PER DEREK - PAGE 97: STUFFED R9726 AND SWAPPED C9705 AND R9705 AS PER FREESCALE FOR COMPENSATION. - PAGE 4: REMOVED 104S0018 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE - PAGE 34: REPLACE Q3450 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 - PAGE 45: REPLACE Q4590 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 ALSO, CHANGED R9705 TO 10K 1% VALUE - APN 114S0315 - PAGE 52: DELETE J6955 REFERENCE AS THERE IS NO BIL CONNECTOR ***PAGES SYNCED FROM K24 SINCE LAST RELEASE 2.0.0*** - PAGE 52: REMOVED REFERENCES TO THE LED BACKLIGHT AS FREESCALE PART DOESN’T HAVE I2C BUS ACCESS 4/2/2009: RELEASE 9.2.0 (MAJOR): - PAGE 54: REPLACING R5492 WITH APN 107S0139 PART FOR COST SAVING - PAGE 7: SCRUBBED TPS AS PER UPDATE FROM TOM - PG 50: SWAPPED THE PART NUMBER AND THE ALTERNATE PART NUMBER FOR VR5020. MADE ISL60002 THE ALTERNATE PART - PAGE 59: REMOVING R5923 AND ONLY 1 PU ON SEL LINES IS ENOUGH - PAGE 49: FIXED PLACEMENT NOTE ASSOCIATED WITH C4907 (SHOULD BE: PLACE NEAR PIN E1) - PAGE 70: REPLACING R7020 WITH APN 107S0138 PART FOR COST SAVING - PAGE 49:FIXED PLACEMENT NOTES ASSOCIATED WITH R4999,C4920(SHOULD BE:PLACE NEAR PIN M12) - PAGE 70: REPLACING R7008 WITH APN 107S0139 PART FOR COST SAVING ***PAGES SYNCED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 2.0.0*** - PAGE 51: FIXED PLACEMENT NOTE ASSOCIATED WITH R5146 - PLACE NEAR U5110 INSTEAD OF SMC - CHANGED SPEAKER AMPS TO LM48310, PLACEHOLDERS FOR LM48311. LM48311 IS THE CSP VERSION OF THE LM48310. - PAGE 70: R7080 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER - PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH SMBUS_SMC_B_S0_SCL/SDA - CHANGED LDO TO B LP5900. - PAGE 97: RENAMED SINGLE PIN NET GND_LCDBKLT TO GND_LCDBKLT_PGND - PAGE 73: R7350 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER - REMOVED OPTIONAL STUFFING RESISTORS AROUND THE RE-TASKING JACK ANALOG SWITCH. - PAGE 79: REPLACE Q7940 AND Q7948 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 - PAGE 90: REMOVED EMI CAPS [C9017-C9025] ON LED_RETURN, I2C AND LCD_BKLT POWER NETS 2/26/2009: RELEASE 4.0.0 (RFA RELEASE): - PAGE 90: UPDATED LVDS CONNECTOR PINOUT CONNECTIONS AS PER STEVE’S NEW SPREADSHEET - PAGE 4: ADDED LDO_NO BOM OPTION - PAGE 97: ADDED DIDIT=TRUE ATTRIBUTE TO THE SWITCHING NODE PINS 3 & 4 - PAGE 8: RENAMED PP1V05_S0_MCP_PLL_UF BACK TO PP1V05_S0_MCP_PLL_UF_R - PAGE 97: CHANGED C9711 FROM 0.1UF TO 1.0UF 0603 TYPE CAP AS PER FREESCALE FEEDBACK - PAGE 8: ADDED BACK - PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_MCP_PLL_VLDO - PAGE 97: CHANGED C9715 AND C9716 TO 50V CAPS FOR COST SAVING AND AS PER FREESCALE FEEDBACK - PAGE 13: REPLACED XDP CONNECTOR WITH MINI XDP CONNECTOR APN 516S0625 - PAGE 97: CHANGED R9717 - R9722 FROM 0.1% TO 1% PARTS FOR COST SAVINGS AND AS PER FREESCALE FEEDBACK - PAGE 34: ADDED NOTE WITH REGARD TO SMBUS CONNECTIONS TO THE AIRPORT CONNECTOR - PAGE 97: NO STUFF’ED C9721 - C9726 AS PER FREESCALE FEEDBACK - PAGE 34: ADDED NOTE WITH REGARD TO 100 MS DELAY REQUIREMENT BETWEEN 3.3 WLAN - PAGE 97: FOR 25KHZ OPERATION, CHANGE R9726 TO NO STUFF, INTERCHANGE R9705(6.8K) WITH C9705 POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET AS IN K19I - PAGE 54: REMOVED NOTE ON AMON AND BMON - PAGE 97: CHANGED R9710 TO 6.65K APN 114S0298 AND R9716 TO 226K APN 114S0445 PARTS AS PER - PAGE 57: REPLACED KEYBOARD CONNECTOR WITH APN 518S0738 FREESCALE FEEDBACK - PAGE 77: ADDED BACK - 1.05 PLL LDO CIRCUIT - PAGE 107: ADDED CONSTRAINTS FOR FOLLOWING SENSOR NETS: ISNS_HDD_P/ISNS_HDD_N; ISNS_ODD_P/ISNS_ODD_N; - PAGE 90: REFRESHED THE SYMBOL OF U9000, PART NUMBER CHANGED TO 353S2603 ISNS_AIRPORT_P/ISNS_AIRPORT_N; ISNS_1V5_S3_P/ISNS_1V5_S3_N; ISNS_LCDBKLT_P/ ISNS_LCDBKLT_N 3/4/2009: RELEASE 5.0.0 (RFA)- PAGE 107: REMOVED FOLLOWING SENSOR NETS CONSTRAINTS: ISNS_P1V5S0MCP_P/ISNS_P1V5S0MCP_N; - PAGE 34: ADDED A TEXT NOTE THAT J3401 (AIRPORT CONNECTOR) COULD CHANGE TO 1.8MM HEIGHT APN 516S0582 ISNS_PVCORES0MCP_P/ISNS_PVCORES0MCP_N SYNC_MASTER=K24_MLB SYNC_DATE=01/19/2009 - PAGE 57: REPLACED KEYBOARD CONNECTOR WITH THAT OF K24 (APN 518S0637) - SYNC’ED FROM K24 - PAGE 74: ADDED XW7401-XW7404 SHORTS ACROSS L7400 AND L7401 PAGE TITLE - PAGE 69: REPLACED BATTERY CONNECTOR WITH THAT OF K24 (APN 518-0359) - PAGE 69: DELETED NOTE REGARDING INDUCTOR FILTER REQUIREMENT ON BATT_POS_F (AS PER JOHN SCHEN) ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 6.0.0*** - PAGE 70: CHANGED Q7050 TO 376S0761 AS PER DAYU & K24 DESIGN -PG. 67, DELETED R6725 AND NET =PP3V42G3H_AUDIO -PG. 66, ADDED R6613/14/15/16/17 - PAGE 70: CHANGED Q7000 AND Q7001 CHEAPER TO 376S0667 (HAT1128) AS PER DAYU’S RECOMMENDATION - PAGE 71: DISCONNECTING EN_PSV (PIN 34) FROM P5VLTS3_EN SIGNAL AND CONNECTING IT TO -PG. 66, ADDED C6612/13 DRAWING NUMBER SIZE PP5VLT_S3_V5IN (5VRT PS) -PG. 66, ADDED R6631/2/3/4/5 -PG. 66, ADDED C6634/5 - PAGE 72: L7220 CHANGED TO 152S0778 FOR COST SAVING AS PER DAYU - PAGE 73: ADDED ONE MORE OSCON 39UF CAP ON INPUT SIDE -PG. 66, CHANGED C6610/11 TO 0.022UF - PAGE 73: MOVED THE SENSE RESISTOR NEXT TO INDUCTOR -PG. 66, CHANGED C6630/31 TO 0.022UF REVISION - PAGE 74: REMOVED UNUSED NETWORK ON U7400 PIN 5 AND PIN 6 AS PER DAYU [R7406, C7410, R7427, R7426] -PG. 65, DELETED R6521 R - PAGE 74: STUFF R7413 AS PER DAYU -PG. 65, ADDED R6523/4 - PAGE 74: CHANGED Q7400 AND Q7402 TO 376S0772 AS PER DAYU -PG. 62, ADDED PLACEMENT COMMENT ATTR. TO XW6200/1 - PAGE 74: CHANGED Q7401 AND Q7403 TO 376S0771 AS PER DAYU -PG. 67, ADDED PLACEMENT COMMENT ATTR. TO XW6700/1/10/11 NOTICE OF PROPRIETARY PROPERTY: BRANCH - PAGE 75: CHANGED R7525 TO 107S0132 FOR COST SAVING AS PER DAYU -PG. 68, ADDED PLACEMENT COMMENT ATTR. TO XW6851/80 - PAGE 78: DELETING P5VLTS3_EN RC CIRCUIT AS IT IS NO LONGER NEEDED (SEE ABOVE). ALSO UPDATED ASSOCIATED TEXT NOTE -PG. 66, REPLACED U6610/30 WITH LM48556 CKTS THE INFORMATION CONTAINED HEREIN IS THE - PAGE 97: FIXED CONNECTION POINT (DOT) FOR LCDBKLT_VIN -PG. 67, DELETED C6760/1/2/3. PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. - PAGE 97: ADDED 0 OHMS SERIES RESISTOR ON LCD_BKLT_PWM FOR DEBUGGING PURPOSES -PG. 67, CHANGEED J6703 TO TWO PIN CONN. THE POSESSOR AGREES TO THE FOLLOWING: PAGE - PAGE 97: RENAMED LCD_BKLT_PWM TO LVDS_IG_BKL_PWM -PG. 67, ADDED J6704 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE - PAGE 97: CHANGED VOVP VALUE TO 6.9V AS PER FREESCALE FEEDBACK -PG. 62, REPLACED C6225 WITH APN: 128S0216 - PAGE 97: ADDED R9726 (22K) AND SWAPPED C9705 AND R9705 LOCATIONS FOR NOISE REDUCTION AS PER FREESCALE RECOMMENDATION II NOT TO REPRODUCE OR COPY IT - PAGE 97: DELETED C9712 AS IT IS REDUNDANT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET - PAGE 97: ADDED PLACEMENT NOTE ATTRIBUTE TO C9713 AND C9710 FOR PLACING THOSE NEAR L9710
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Revision History Apple Inc.
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IV ALL RIGHTS RESERVED
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8 Revision History
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4/2/2009: RELEASE 9.3.0 (MAJOR): - PAGE 4:B ADDED 5.95MM SANYO PART 128S0288 AS ALTERNATE TO 128S0271 - PAGE 4:B ADDED 5.95MM SANYO PART 128S0286 AS ALTERNATE TO 128S0248 - PAGE 4: DELETED 152S0694 ALTERNATE ENTRY FOR 152S0138 AS IT IS NOT USED - PAGE 50: REPLACED DUAL Q5032 FET WITH TWO SINGLE Q5032 & Q5033 (APN 376S0612) N-CH FETS FOR ROUTING PURPOSES (SIL ANODE SIGNAL) - PAGE 54:B CHANGED R5412 TO 118OHM (114S0127) - PAGE 72: ADDED MIN_LINE/NECK_WIDTH ATTRIBUTES TO 5V_S3_DRVL, 3V3S5_VBST, 3V3S5_DRVL (FIXED THE NET NAME- ADDED UNDERSCORE) - PAGE 75: CHANGED L7560 TO APN 152S0526 - 0.68UH, 3.5MOHM,16A - AS PER DAYU - PAGE 75: CHANGED R7569 TO 11.3K APN 114S0319 FOR SETTING THE CORRECT OCSET AS PER DAYU - PAGE 97: CHANGED MIN_NECK_WIDTH ASSOCIATED WITH PPVOUT_S0_LCDBKLT TO 0.24MM AS THAT’S THE PIN WIDTH - PAGE 97: CHANGED MIN_LINE/NECK_WIDTH ASSOCIATED WITH GND_LCDBKLT_SGND TO 0.6/0.24MM ***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 9.2.0*** - REMOVED R6725 AND =PP3V3_S3_AUDIO CONNECTION TO MAX14504 ANALOG SWITCH 4/2/2009: RELEASE: 9.4.0 (MAJOR): - PAGE 97: ADDED A 1000PF CAP (C9727) ON LCDBKLT_VIN NEAR PIN 1 - PAGE 97: REPLACED C9717 WITH 1000PF CAP APN 132S0147 AND ADDED PLACEMENT NOTE AS PER JOHN SCHEN 4/2/2009: RELEASE: 9.5.0 (MAJOR): - PAGE 9: REPLACED Z0906,Z0907,Z0910 AND Z0911 MLB MOUNTING HOLES WITH 2.7 MM DIAMETER PLATED HOLES - APN 998-1584 4/3/2009: RELEASE: 9.6.0 (MAJOR): - PAGE 4: UNDER K84_PROGPARTS BOM GROUP, REPLACED BLANK P/N WITH PROGRAMMED P/N - PAGE 8: ADDED GLOBAL DIGITAL GROUND NET WITH MIN_LINE/NECK_WIDTH AND VOLTAGE ATTRIBUTES - PAGE 9: REPLACED Z0905 AND Z0913 MLB MOUNTING HOLES WITH 2.7 MM DIAMETER PLATED HOLES - APN 998-1584 - PAGE 9: DELETED GND MIN_LINE/NECK_WIDTH AND VOLTAGE ATTRIBUTES FROM FAN STANDOFF **PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.5.0*** - REMOVED OPTIONAL STUFF-AROUND RESISTORS FOR ANALOG SWITCH - CONNECT AUDIO JACK SHIELD TO DIGITAL GROUND. 4/3/2009: RELEASE: 10.0.0 (RFA): - PAGE 9: ADDED 7 EXTRA TALL POGO PINS FOR EMI - 4 STUFFED AT THE BOTTOM, 3 UNSTUFFED ON THE TOP - PAGE 28: DELETED MAKE_BASE=TRUE ASSOCIATED WITH PCIE_RESET_L - PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH I2C_MIKEY_SCL/SDA_R - PAGE 69: REFRESHED J6955 SYMBOL - APN 516S0787 - PAGE 78: DELETED MAKE_BASE=TRUE ASSOCIATED WITH ALL_SYS_PWRGD - PAGE 78: DELETED SYNONYMS AS THEY ARE NOT NEEDED ANYMORE (DUE TO 0 OHMS) **PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.6.0*** - ADDED 100PF EMC CAP ON THREE SPEAKER CONNECTORS. - CHANGED MIN_WIDTH OF CODEC HP OUT NETS.
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4/5/2009: RELEASE 10.1.0 (MAJOR): - PAGE 4: ADDED CHGR_6258 BOM OPTION UNDER MODULE PARTS TABLE AND TO K84 MISC BOM GROUP. THIS IS TO STUFF ISL6258 PART - PAGE 9: ADDED ONE MORE TALL POGO PIN ON BOTTOM SIDE - PAGE 13: FIXED THE NOTE ON THE XDP PAGE- REPLACING 920-0620 ADAPTER BOARD WITH 920-0782 ADAPTER FLEX - PAGE 34: RENAMED P5VWLAN_SS NET TO P3V3WLAN_SS - PAGE 46: DELETED TEXT NOTE RELATED TO R4691 & R4690 AS IT IS NA TO K84 - PAGE 52: MOVED THE R5251 CONNECTION TO SENSOR ADC TO THE RIGHT SIDE TO SHOW A SEPARATE CONNECTION FOR CLARITY - PAGE 52: DELETED TEXT NOTE ON BATTERY LED DRIVER AS IT IS NA TO K84 - PAGE 69: PUT R6961 BEFORE C6955 TO GET RC FILTER. ALSO, FOR NOW, REPLACED R6961 WITH A 0 OHM RESISTOR AND NOSTUFF’ED C6955 - PAGE 70: ADDED OMIT BOM OPTION TO U7000 AS THIS PART WILL GET STUFFED WITH EITHER ISL6258 OR ISL6259 DEPENDING UPON PAGE 4 BOM TABLE - PAGE 70: FIXED Q7001 DRAIN-SOURCE ORIENTATION 4/6/2009 - RELEASE 10.1.1 (MINOR): **SCHEMATIC AND BOM CLEAN-UP** - PAGE 4: DELETED CHGR_6258 AND RENAMED 6259_NO TO CHGR_6259_NO. REPLACED CHGR_6258 WITH CHGR_6259_NO IN MODULE PARTS TABLE - PAGE 4: DELETED ENTRIES IN THE ALTERNATE BOM TABLE FOR THE FOLLOWING APN: 516-0213 AND 516S0709 - PAGE 8: DELETED =PP3V3_S3_AUDIO ALIAS AS IT IS NO LONGER APPLICABLE - PAGE 57: DELETED NO_TEST = TRUE ATTRIBUTE FROM Z2_SCLK AND Z2_MOSI AS THEY CONFLICT WITH FUNC_TEST ATTRIBUTE ON PAGE 7 - PAGE 69: RENAMED 6259_NO/YES TO CHGR_6259_NO/YES 4/6/2009 - RELEASE 11.0.0 (OK2FAB): - NO CHANGE SINCE LAST MINOR RELEASE 10.1.1
4/23/2009 - RELEASE 12.1.0 (MAJOR): - PAGE 4: ADDED METAL PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO ADDED CORRESPONDING NOTES514-0691 ALTERNATE FOR 514-0690; 514-0689 ALTERNATE FOR 514-0688 - PAGE 13: REPLACED J1300 XDP CONNECTOR WITH MORE ROBUST CONNECTOR APN 998-2515 - PAGE 39: REPLACED J3900 ETHERNET CONNECTOR WITH POR PLASTIC CONNECTOR APN 514-0692 - PAGE 46: REPLACED J4600 & J4610 USB CONNECTORS WITH POR PLASTIC CONNECTOR APN 514-0688 - PAGE 75: CHANGE Q7560 AND Q7565 TO SIS426 APN 376S0749 PER RDAR://6812904 - PAGE 75: CHANGE R7565 TO 1OHM APN 113S0023 PER RDAR://6812904 - PAGE 76: CHANGED THE CPU VTT OVER CURRENT TRIP POINT PER RDAR://6792329 BY CHANGING R7604 FROM 8.87KN) TO 6.04KN) - PAGE 94: REPLACED J9400 DP CONNECTOR WITH POR PLASTIC CONNECTOR APN 514-0690 - PAGE 75: CHANGED C7565 AND C7568 TO CASE_B4_SM PACKAGE FROM CASE_B2_SM DUE TO PACKAGING ERROR (SAME APN) 4/24/2009 - RELEASE 12.2.0 (MAJOR): **PAGES SYNCED FROM CASEY’S AUDIO_MLB SINCE LAST RELEASE 12.1.0*** - REPLACED J6700 WITH APN: 514-0694 - ADDED DZ 6702 AND L6706 - CONNECTED R6860 TO AUD_IP_PERPH_DET 4/27/2009 - RELEASE 12.3.0 (MAJOR & WEEKLY ECO): - PAGE 4: ADDED NEW BOM ENTRY 639-0254 FOR MOLEX DDR3 CONNECTOR CONFIG. ALSO, EDITED 639-0035 BOM NAME TO REFLECT FOXCONN DDR3 CONNECTOR. ADDED TWO ENTRIES (J3200 AND J3100) FOR FOXCONN AND TWO FOR MOLEX UNDER MODULE PARTS TABLE . - PAGE 74: CHANGED C7432 TO 0.001UF AS PER RDAR://6792327 - PAGE 74: UNSTUFFED C7434 AS PER RDAR://6792327 - PAGE 74: CHANGED C7428 TO 0.47UF AS PER RDAR://6792327 - PAGE 74: CHANGED R7415 TO 10.5K AS PER RDAR://6792327 - PAGE 97: CHANGED R9716 FROM 226K TO 243K TO CHANGE THE OVP POINT TO 35.3V AS PER KIRAN 4/28/2009: RELEASE 12.4.0 (MAJOR): - PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS FOR EMI PURPOSES - L6707 & L6708
APN 155S0367 ON RIGHT PIEZO SPEAKER
4/28/2009: RELEASE 12.5.0 (MAJOR): - PAGE 67: MOVED L6707 & L6708 TO J6703 (FULL RANGE SPEAKER CONNECTOR) BETWEEN CAPS AND CONNECTOR 4/29/2009: RELEASE 12.6.0 (MAJOR & WEEKLY ECO): - PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER J6704 FOR EMI PURPOSES - L6709 & L6710 - PAGE 97: CHANGED L9710 TO A BIGGER 2525 PACKAGE (LOW DCR) APN 152S0585 FOR BETTER EFFICIENCY 4/29/2009: RELEASE 12.7.0 (MAJOR & WEEKLY ECO): - PAGE 97: CHANGED L9710 BACK TO THE ORIGINAL APN 152S0826 AS 2525 PACKAGE CAN’T FIT IN
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5/01/2009: RELEASE 12.8.0 (MAJOR): - PAGE 4: ADDED A36 EEE NUMBER FOR NEW BOM CONFIGURATION 639-0254 - PAGE 60: ADDED 0 OHMS SERIES RESISTORS R6003 AND R6004 ON AVDD AND DVDD SUPPLY RAILS TO ADC CHIP - PAGE 60: CHANGED R6001 & R6002 TO 33 OHMS RESISTORS TO FIX UNDERSHOOT ON I2C BUS 05/01/2009: RELEASE 12.9.0 (MAJOR): - PAGE 4: UPDATED PLASTIC PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO ADDED CORRESPONDING NOTES514-0690 PLASTIC ALTERNATE FOR 514-0691 METAL; 514-0688 PLASTIC ALTERNATE FOR 514-0689 METAL - PAGE 46: REPLACED PLASTIC USB CONNECTORS WITH METAL APN 514-0689 PARTS - PAGE 94: REPLACED PLASTIC MINI DP CONNECTOR WITH METAL APN 514-0691 PART
05/08/2009: RELEASE 12.12.0 (MAJOR & WEEKLY ECO): - PAGE 4: DELETED SANYO 6.00MM OSCON CAPS 128S0248 & 128S0271 FROM THE ALTERNATE TABLE (MAKING ALTERNATES AS PRIMARY) - PAGE 4: TURNING ON BOM OPTION MCPSMC_DIGITEMP_YES AS POR IS TO CONNECT MIKEY TO MCP79 SMBUS 0 INSTEAD OF SMBUS 1 AND TO CONNECT SMC B SMBUS TO MCP79 SMBUS 1 - PAGE 4: ADDED A TEXT NOTE STATING THAT ADC CAN ONLY WORK IN S0 STATE AS IT HAS I2C BUS PU TO S0 POWER RAIL - PAGE 37: CHANGED C3714 AND C3715 TO 2.2UF APN 138S0642 TO FIX ETHERNET JITTER ISSUE - PAGE 50: CHANGED R5030 TO 63.4 OHMS APN 114S0102 TO INCREASE THE SIL CURRENT PER RDAR://PROBLEM/6752822 - PAGE 50: CHANGED R5714 TO 0 OHM APN 116S0004 PER RDAR://PROBLEM/6752822 - PAGE 52: CHANGED R5200, R5201, R5260 & R5261 TO 2K APN 116S0073 - PAGE 72: REPLACED C7252, C7291 & C7292 WITH 5.95MM SANYO APN 128S0288 - PAGE 72: REPLACED C7240 & C7282 WITH 5.95MM SANYO APN 128S0286 - PAGE 73: REPLACED C7331 & C7345 WITH 5.95MM SANYO APN 128S0286 - PAGE 77: CHANGED C7771 TO 47UF APN 138S0659 TO FIX ETHERNET JITTER ISSUE
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05/10/2009: RELEASE 12.13.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL): - PAGE 60: CHANGED R6003 AND R6004 TO 10 OHMS 5% RESISTOR VALUES RDAR://PROBLEM/6834630 05/11/2009: RELEASE 12.14.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL): - PAGE 57 : CHANGED R5714 TO 165 OHMS APN 114S0141 AS PER RDAR://PROBLEM/6875543 - PAGE 72 : CHANGED C7252, C7291 & C7292 BACK TO ORIGINAL APN 128S0271 05/20/2009: AGILE RELEASE PROTO 2 - FINAL PROTO 2 OK2FAB RELEASE - UPDATED PAGE BORDERS TO NEW E4 05/22/2009: AGILE RELEASE PROTO 2 ***RETRY*** - FINAL PROTO 2 OK2FAB RELEASE - UPDATED PAGE BORDERS TO NEW E4
OK2FAB 13.0.0 (FAB): DSIZE STANDARDS OK2FAB 14.0.0 (FAB)DSIZE STANDARDS
06/09/2009: RELEASE 14.1.0 (MAJOR)- PAGE 4: REMOVING CHGR_6259_NO BOM OPTION AS ISL 6259 IS NOT POR - PAGE 4: ADDED NEW ISL PART APN 353S2718 AS AN ALTERNATE TO FIX B4 DONGLE ISSUE - PAGE 9: REPLACED ALL MEDIUM POGO PINS WITH APN 870-1794 (2 MM) AND ZS0916-ZS0918 WITH THINBC APN 870-1820 (2 MM) ONES - PAGE 59: ADDED R5922 10 OHMS SERIES R ON VDD SUPPLY TO FIX SMS NOISE ISSUE - PAGE 67: CHANGED J6704 TO A THREE PIN CONNECTOR 518S0520 - PAGE 69: REFRESHED J6955 SYMBOL (HALL EFFECT CONNECTOR) - PAGE 70: REMOVED CHGR_6259_YES/NO BOM ATTRIBUTES AS ISL 6259 IS NOT POR - PAGE 70: DELETED R7051 & R7053 CHGR_6259_YES BOM OPTIONS COMPONENTS - PAGE 70: REPLACING R7052 & R7054 CHGR_6259_NO BOM OPTION COMPONENTS WITH XW SHORTS- XW7052 & XW7054 - PAGE 70: REMOVED R7050 CHGR_6259_YES COMPONENT AS IT IS NOT NEEDED WITH ISL 6258 (PM_SLP_S3_L DIRECTLY CONNECTS TO ISL 6258 PIN) - PAGE 94: STUFFED C9485 AND CHANGED IT TO 22UF (APN 138S0654),CHANGED C9400 & C9481 TO 4.7UF (APN 138S0618) & CHANGED C9480 TO 22UF (APN 138S0654): TO FIX B4 DONGLE ISSUE ***PAGES SYNCED FROM CASEY HARDY?S AUDIO_MLB SINCE LAST RELEASE 14.0.0*** - ADDED R6862 PULL-UP RESISTOR TO PERPH. DETECT CKT.
08/31/2009: RELEASE 16.1.0 (MAJOR)- PAGE 4: REMOVED 138S0606 FROM THE ALTERNATES TABLE AS IT DOESN’T PERTAIN TO K84 - PAGE 4: REPLACED CPU APN 337S3704 WITH 337S3769 IN MODULE PARTS TABLE AND REMOVED 337S3704 FROM THE ALTERNATE PART TABLE AS POR IS 337S3769 (P7550) - PAGE 4: REMOVE 870-1794, 870-1698 & 870-1820 FROM THE ALTERNATES TABLE AS POR IS LOW NOISE POGO PINS - PAGE 4: ADDED LOW NOISE POGO APNS 870-1885 (IN PLACE OF 870-1794), 870-1886 (IN PLACE OF 870-1698) & 870-1887 (IN PLACE OF 870-1820) IN MODULE PARTS TABLE - PAGE 4: ADDED NEW INTERSIL ISL6258A (WITH IMPROVED CHARGE CURRENT ACCURACY LIMITS) APN 353S2811 AS AN ALTERNATE FOR APN 353S1832 - PAGE 4: REMOVED 998S APN FROM THE ALTERNATES TABLE PERTAINING TO I/O CONNECTORS AS THEY ARE NO LONGER POR FOR DVT - PAGE 4: REMOVED 514-0706, 514-0705 AND 514-0718 FROM THE ALTERNATES TABLE AND ADDED TO MODULE PARTS TABLE AS THEY ARE NOW POR I/O CONNECTORS - PAGE 9: ADDED OMIT BOM OPTION ON ALL THE POGO PINS - PAGE 46: ADDED OMIT BOM OPTIONS TO J4600 & J4610 USB CONNECTORS - PAGE 67: ADDED OMIT BOM OPTION TO J6700 AUDIO CONNECTOR - PAGE 94: ADDED OMIT BOM OPTION TO J9400 MINI DP CONNECTOR - PAGE 97: UPDATED SCHEMATIC NOTE RELATED TO TARGET AND ACTUAL ISET & OVP NUMBERS AS PER KIRAN’S EMAIL
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09/16/2009: RELEASE 17.0.0 (FAB)- FINAL DVT OK2FAB RELEASE 09/21/2009: RELEASE A.0.0 (FAB)- FINAL PVT OK2FAB RELEASE - PAGE 4: ADDED APN 104S0033 (6.8 OHMS, 1/4W) RESISTORS IN MODULE PARTS TABLE FOR R6612, R6617, R6630 & R6633 ADDED APN 518S0774 FOR XDP CONNECTOR J1300 (TO REPLACE 998-2515) - PAGE 13: ADDED OMIT TO J1300 - PAGE 50: CHANGED R5030 SIL RESISTOR TO 80.6 OHMS APN 114S0112 AS PER ID - PAGE 53: REPLACED APN 376S0545 WITH 376S0820 @ Q5315 - PER ECO#0000737172 - PAGE 66: ADDED BOMOPTION OMIT TO RESISTORS R6612, R6617, R6630 & R6633 10/12/2009: RELEASE B.0.0 (FAB)- PROD_DEBUG (POST FIRST 5K UNTIL 1 MONTH INTO PRODUCTION) OK2FAB RELEASE - PAGE 4: ADDED 1 NEW POR BOMS 639-0554, 639-0555 AND 1 NEW DEVELOPEMENT BOM 085-1076 FOR INITIAL RAMP - PAGE 4: UPDATED BOM GROUPS TABLE TO REFLECT AFOREMENTIONED CHANGES. NEW DEVELOPMENT BOM ONLY HAS XDP CONNECTOR AND LPCPLUS COMPONENTS - PAGE 4: ADDED 2 NEW EEES TO ATTACH WITH AFOREMENTIONED NEW 639 BOMS - PAGE 4: DELETED 353S2811 ENTRY FROM THE ALTERNATES TABLE - PAGE 70: REPLACED U7000 WITH THE NEW INTERSIL SCREENED PARTS APN 353S2811 11/01/2009: RELEASE C.0.0 (FAB)- PROD (POST 1ST MONTH OF PRODUCTION) OK2FAB RELEASE - PAGE 2: UPDATED SYSTEM BLOCK DIAGRAM - PAGE 3: UPDATED POWER SYSTEM BLOCK DIAGRAM - PAGE 4: UPDATED BOM TABLES TO NOT INCLUDE ANY 085 DEVELOPMENT BOMS. AND, K84_DEBUG_PROD BOM GROUP IS TURNED ON
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06/10/2009: RELEASE 14.2.0 (MAJOR)- PAGE 4: ADDED APN 138S0661 LOW NOISE MURATA CAPS AS ALTERNATE FOR C9715 & C9716 TO FIX LCD BKLT AUDIBLE NOISE ISSUE - PAGE 49: ADDED 0.1UF CAPS ON SMS_X_AXIS, SMS_Y_AXIS & SMS_Z_AXIS NETS TO FIX NOISE ISSUE - PAGE 77: CHANGED R7780 TO 25.5K APN 114S0354 & R7781 TO 80.6K APN 114S0402 AS PER DAYU 06/11/2009: RELEASE 14.3.0 (MAJOR)- PAGE 77: ADDED 0 OHMS BOM OPTIONS R7782 BETWEEN PIN 4 OF U7750 (SKIP PIN) AND POWER RAIL AND R7783 BETWEEN PIN 4 AND GND. R7782 WILL BE NOSTUFF FOR NOW. THIS IS AS PER DAYU TO FIX ETHERNET JITTER ISSUE 06/11/2009: RELEASE 14.4.0 (MAJOR)- PAGE 49: REPLACED C4950-C4952 WITH 1UF APN 138S0640 CAPS - PAGE 78: DISCONNECTED P1V05_S5_PGOOD FROM PIN 3 OF U7840 AND CONNECTED IT TO PIN 1 (RSMRST_PWRGD) TO FIX LEAKAGE ISSUE
06/22/2009: RELEASE 14.6.0 (MAJOR)- PAGE 4: ADDED CPU APN 337S3769 AS ALTERNATE TO 337S3704 - PAGE 9: ADDED NOSTUFF BOM OPTION TO ZS0920 - PAGE 50: CHANGED R5030 TO 48.7 OHMS APN 114S0091 (SIL CURRENT TO 12MA) - PAGE 57: CHANGED R5714 TO 113 OHMS APN 114S0125 (KB LED CURRENT TO 8.5MA) - PAGE 97: ADDED CRITICAL ATTRIBUTE TO C9715 & C9716 - PAGE 97: CHANGED R9710 TO 7.68K APN 114S0304 (LCD BKLT CURRENT TO 20MA) 06/25/2009: RELEASE 14.7.0 (MAJOR)- PAGE 70: DELETED OMIT BOM OPTION FROM U7000 AS ISL6259 HAVE BEEN REMOVED 07/17/2009: AGILE EVT OK2FAB RELEASE 15.0.0 (FAB)- NO CHANGES SINCE LAST MAJOR 14.7.0. THIS IS FINAL EVT FAB RELEASE 07/21/2009: RELEASE 15.1.0 (MAJOR)- PAGE 4: DELETED MIKEY_LOAD_DET BOM OPTION FROM THE TABLE UNDER K84_MISC CATEGORY AS PER CASEY - PAGE 4: UPDATED ALTERNATES FOR MINI DP AND USB CONNECTORS WITH PG2 PLASTIC CONNECTORS- APN 514-0706 (MDP) & 514-0705 (USB). AND, UPDATED NOTE BELOW THE ALTERNATES PARTS TABLE ACCORDINGLY - PAGE 4: ADDED PG2 CONNECTOR APN 514-0704 IN THE MODULE PARTS TABLE FOR RJ45 J3900 CONNECTOR - PAGE 4: DELETED 353S2310 PART FROM THE ALTERNATES BOM TABLE AS ALL PRODUCTION HAS NOW MOVED TO ITS ALTERNATE PART 353S2718 - PAGE 4: ADDED NEW INTERSIL PART APN 353S2718 IN THE MODULE PARTS TABLE FOR U7870 TO FIX B4 DONGLE ISSUE - PAGE 21: DELETED NOSTUFF BOM ATTRIBUTE FROM R2143 AS MIKEY_LOAD_DET CIRCUIT HAS BEEN REMOVED. SO R2143 NEEDS TO BE STUFFED NOW - PAGE 39: ADDED BOMOPTION ATTRIBUTE OMIT TO J3900 AS NEW PG2 CONNECTOR PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE - PAGE 78: ADDED BOMOPTION ATTRIBUTE OMIT TO U7870 AS NEW INTERSIL PART PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE
B
07/27/2009: RELEASE 15.2.0 (MAJOR)- PAGE 4: DELETED LOW NOISE MURRATA CAP ENTRY FROM THE ALTERNATES TABLE - PAGE 49: CHANGED SMS NOISE FILTERING CAPS C4950-C4952 TO 0.47UF APN 132S0178 TO FIX THE SMART TEST FAILURE - PAGE 70: DISCONNECTED PM_SLP_S3_L FROM PIN 4 (VREF) AS IT WAS INCORRECTLY CONNECTED, THEREBY CAUSING HIGHER SLEEP/SHUTDOWN POWER - PAGE 97: NOSTUFFED C9716 AND CHANGED C9715 TO APN 138S0661 AS POR IS TO HAVE SINGLE CAP LOW NOISE MURRATA CAP SOLUTION AS PER ACOUSTICS ENGINEER 08/05/2009: RELEASE 15.3.0 (MAJOR)- PAGE 4: ADDED APN 138S0606 (TAIYO-YUDEN) AS AN ALTERNATE FOR APN 138S0602 - PAGE 4: ADDED PDNI PLATED AUDIO CONNECTOR W/ CHAMFER APN 514-0718 AS AN ALTERNATE FOR J6700 APN 514-0694 - PAGE 4: ADDED GOLD PLATED AUDIO CONNECTOR W/O CHAMFER APN 998-2622 AS AN ALTERNATE FOR J6700 APN 514-0694 - PAGE 4: ADDED GOLD PLATED RJ45 CONNECTOR APN 998-2621 AS AN ALTERNATE FOR J3900 APN 514-0704 - PAGE 4: ADDED GOLD PLATED MINI DP CONNECTOR APN 998-2626 AS AN ALTERNATE FOR J9400 APN 514-0691 - PAGE 4: ADDED GOLD PLATED USB CONNECTOR APN 998-2624 AS AN ALTERNATE FOR J4600/J4610 APN 514-0689 - PAGE 4: ADDED LOW NOISE POGO PINS 870-1885 (MEDIUM), 870-1886 (TALL), AND 870-1887 (THIN) AS ALTERNATES - PAGE 49: CHANGED C4950, C4951, C4952 TO APN:132S0131 (CAP,0402,0.033UF, 16V,10%) AS THESE WOULD BE USED TO ACHIEVE CUT-OFF FREQUENCY OF ~146HZ FOR SMS (AS PER THE VENDOR) AND FILTER THE NOISE TOO AS SEEN BY SMC CHIP. CAPS ON SMS PAGE WOULD BE UNSTUFFED - PAGE 59: ADDED NOSTUFF BOM OPTION ATTRIBUTE TO C5923-C5925 AS STATED ABOVE. ALSO, EDITED THE NOTE ACCORDINGLY - PAGE 70: CHANGED R7031 FROM 10 OHM TO 2.2 OHM, 5%, APN:116S0010 TO FIX SLOW CHARGING ISSUE, PER DAYU - PAGE 70: CHANGED R7047 FROM 10 OHM TO 0 OHM, 5%, APN:116S0004 TO FIX SLOW CHARGING ISSUE, PER DAYU - PAGE 70: CHANGED C7043 FROM 0.1UF TO 1UF, 10%, APN:138S0640 TO FIX SLOW CHARGING ISSUE, PER DAYU
SYNC_MASTER=K24_MLB
A
Revision History
08/27/2009: AGILE PDFC OK2FAB RELEASE 16.0.0 (FAB)- FINAL PDFC (PRE DVT) RELEASE! - PAGE 97: REFRESHED THE SYMBOL OF C9715 4.7UF APN 138S0661
DRAWING NUMBER
Apple Inc. NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
051-7982
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REVISION
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05/05/2009: RELEASE 12.11.0 (MAJOR & WEEKLY ECO): - PAGE 4: ADDED 4 QUANTITIES OF DIMM CONNECTOR SCREWS APN 452-1708 - PAGE 46: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS THOUGH POR IS PLASTIC USB CONNECTOR PART - PAGE 94: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS THOUGH POR IS PLASTIC MINI DP CONNECTOR PART
7
SYNC_DATE=01/19/2009
PAGE TITLE
05/04/2009: RELEASE 12.10.0 (MAJOR): - PAGE 4: REMOVED SHORT POGO PIN ALTERNATE - PAGE 4: REVERTING MCP TO EARLIER USE APN 338S0710 - PAGE 60: CHANGED U6050 INA 211 PART TO 200X GAIN INA 210 APN 353S2073
8
2
06/12/2009: RELEASE 14.5.0 (MAJOR)- PAGE 9: ADDED ONE MORE EXTRA TALL POGO PIN AS PER EMC RECOMMENDATION : ZS0920 - PAGE 78: ADDED 0 OHM BOM OPTION R7895 BETWEEN 1V05_S5_PGOOD AND RSMRST_PWRGD FOR DEBUG PURPOSES
4/7/2009 - RELEASE 12.0.0 OK2FAB (RFA): - NO CHANGE SINCE LAST RFA RELEASE 11.0.0. ***THIS IS A RESUBMIT AS PREVIOUS RFA DIDNT GO THROUGH***
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Functional Test Points
X16 WIRELESS CONN
FAN CONNECTORS FUNC_TEST
D
I12 I15 I16
TRUE TRUE TRUE
PP5VRT_S0 FAN_RT_PWM FAN_RT_TACH
7 8
I303
43
I301
43
I302
(NEED TO ADD 1 GND TP)
I300 I299
MIC FUNC_TEST I238 I237 I239
TRUE TRUE TRUE
I298 I293
BI_MIC_LO BI_MIC_HI BI_MIC_SHIELD
53 54 I288
53 54 I292
53 54 I295
I227 I226 I228 I230 I229 I231
I290
SPEAKER FUNC_TEST SPKRAMP_L_N_OUT TRUE SPKRAMP_L_P_OUT TRUE SPKRAMP_R_N_OUT TRUE SPKRAMP_R_P_OUT TRUE SPKRAMP_SUB_N_OUT TRUE SPKRAMP_SUB_P_OUT TRUE
I271
52 53
I289
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
POWER NETS
FUNC_TEST
PP3V3_S3_BT_F 30 CONN_PCIE_MINI_D2R_P 30 72 CONN_PCIE_MINI_D2R_N 30 72 CONN_PCIE_MINI_R2D_P 30 72 CONN_PCIE_MINI_R2D_N 30 72 PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N PP3V3_WLAN 7 30 (NEED PCIE_WAKE_L 17 30 CONN_USB2_BT_P 30 73 CONN_USB2_BT_N 30 73 MINI_CLKREQ_Q_L 30 MINI_RESET_CONN_L 30
I287 I285 I284 I280 I281
30 72 I282
30 72 I376
2 TP) I396 I283 I279 I278 I270
(NEED TO ADD 2 GND TP)
I379
52 53 I273
52 53 I274
52 53 I275
52 53 I276
52 53 I272 I393
IPD_FLEX_CONN I375 I374
I259 I258
C
I260 I245 I262 I261 I256 I257 I255 I252 I253 I254 I250 I251 I313 I246 I247 I248 I249 I395
I297 I294
LVDS FUNC_TEST PP3V3_LCDVDD_SW_F PP3V3_S0_LCD_F PPVOUT_S0_LCDBKLT LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 PP5V_S3_CAMERA_F USB_CAMERA_CONN_P USB_CAMERA_CONN_N
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
I372 I370
(NEED 2 TP)
7 65 65
I371 I369
7 47 65 68
(NEED 2 TP)
I368
18 65
I361
18 65
I366
18 65 72
I365
18 65 72
I363
18 65 72
I364
18 65 72
I362
18 65 72
I360
18 65 72
I359
65 72
I357
65 72
I358
65 68
I377
65 68
I378
B
I268 I269 I267 I265 I266
KEYBOARD CONN
7 65 I354
65 73
I355
65 73
I344
I349
(NEED 2 TP)
I348
7 34 47 I350
34 36 34 72 34 72
I352 I351 I353
34 72 I327
34 72 I328
I343
FUNC_TEST
I342
I314 I315 I318 I317 I307
TRUE TRUE TRUE TRUE TRUE TRUE
I388 I387
44 45
I386
44 45 I385
44 45 I383
45
I382
44 45
I381
44 45 I380
44 45
I397
44 45 44 45
D
8 8 8 8 8 8 8 7 8 8 8 7 8 8 8 8 7 8 8 8 8 21 22 25 7 30 7 34 47 7 34 36 37 7 45 7 45 7 65 7 47 65 68
C
49 36 57 63 21 36 37 63 21 32 36 63 67 7 65
(NEED TO ADD 1 GND TP)
44 45 44 45 39 75 39 75 44 45
DC POWER CONN
FUNC_TEST
44 45
TRUE TRUE
PP18V5_DCIN_FUSE ADAPTER_SENSE
(NEED 2 TP) 55 55
FUNC_TEST
65 68
I329
I319
44 45 44 45
PPVCORE_S0_CPU PPVCORE_S0_MCP PP0V75_S0 PP1V05_S0 PP1V5_S0 PP1V8_S0 PP5VLT_S0 PP5VRT_S0 PP3V3_S0 PP1V5_S3 PP3V3_S3 PP5V_S3 PP1V1R1V05_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET_PHY PP1V2R1V05_ENET PP3V3_G3_RTC PP3V3_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP3V3_S5_AVREF_SMC PP18V5_S3 PP3V3_S3_LDO PP3V3_LCDVDD_SW_F PPVOUT_S0_LCDBKLT PP4V5_AUDIO_ANALOG SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L PP5V_S3_CAMERA_F
(NEED TO ADD 2 GND TP) 65 68
FUNC_TEST
PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SYS_LED_ANODE_R
I389
I304
(NEED TO ADD 2 GND TP)
SATA HDD/SIL
I390
7 45
65 68
I345
PP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N
I391
7 45
I312
I347
TRUE TRUE TRUE TRUE TRUE TRUE
PP3V3_S3_LDO PP18V5_S3 Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL PSOC_F_CS_L PICKB_L
(NEED TO ADD 2 GND TP)
I346
I264
I392
65 68
(NEED TO ADD 5 GND TP)
SATA ODD CONN
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
FUNC_TEST
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
FUNC_TEST
(NEED 2 TP) I341
7 34 34 72 34 72
I339 I340 I338
34 72 I336
34 72 34
I337 I333
(NEED TO ADD 3 GND TP) I335 I334 I332 I330 I331
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD
7 8 7 8 44 44 44 44 44 44 44
B
44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44
(NEED TO ADD 1 GND TP)
BATT POWER CONN I322 I321 I320
A
I305
TRUE TRUE TRUE TRUE
FUNC_TEST
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SYS_DETECT_L BATT_POS_F
39 75 39 75 55 55 56
SYNC_MASTER=K24_MLB
(NEED 2 TP) (NEED TO ADD 2 GND TP)
SYNC_DATE=02/04/2009
A
PAGE TITLE
FUNC TEST HALL EFFECT CONNECTOR I326 I308
TRUE TRUE
PP3V42_G3H SMC_LID_R
DRAWING NUMBER
FUNC_TEST
Apple Inc.
7 8
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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"S0,S0M" RAILS =PPVCORE_S0_CPU_REG
64
PPVCORE_S0_CPU
=PP5VRT_S0_FET
PP5VRT_S0
=PPVCORE_S0_CPU =PPVCORE_S0_CPU_VSENSE
11 12 40
D
=PP5V_S0_CPUVTTS0
61
=PP5V_S0_LPCPLUS
38
=PP5V_S0_FAN_RT
43
=PP5V_S0_CPU_IMVP
61
=PPCPUVTT_S0_REG
64
PP1V05_S0
=PP5VLT_S0_FET
=PP1V05_S0_CPU
10 11 12 13
=PP1V05_S0_MCP_FSB
14 22 23
23
=PP1V05_S0_MCP_SATA_DVDD
8 23
=PP1V05_S0_MCP_HDMI_VDD
18 24
=PP1V05_S0_MCP_PLL_UF_R
60
=PPMCPCORE_S0_REG
7
=PP3V3_S0_FET
62
7
22 23
7
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE
64
=PP1V5_S0_FET
=PP3V42_G3H_SMBUS_SMC_BSA
=PP1V5_S3_MEM_B
28
=PP3V42_G3H_PWRCTL
=PP1V5_S3_MEMRESET
29
PP3V3_S3
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V42_G3H_RTC_D
25
58
=PP3V42_G3H_ONEWIRE
55
=PP3V42_G3H_HALL
55
26
=PP3V3_S3_WLAN
30 21
=PP3V3_S3_TPAD
44
=PP3V3_S3_SMS
46
=PP3V3_S3_BT
30
PP5V_S3
7
55
=PP18V5_DCIN_CONN
PP18V5_G3H MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V MAKE_BASE=TRUE
13 21 22 23 24 24
57
=PP3V3_S0_ODD
34
=PP3V3_S0_SMBUS_SMC_0_S0
39
=PP3V3_S0_SMBUS_SMC_B_S0
39
=PP3V3_S0_SMBUS_MCP_0
39
=PP3V3_S0_FAN_RT
43
=PP3V3_S0_AUDIO
49 53 54
=PP3V3_S0_IMVP
59
=PP5V_S3_REG
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE
65
56
=PP5V_S3_EXTUSB
35
=PP5V_S3_CAMERA
65
=PP5V_S3_AUDIO_AMP
52
=PP5V_S3_MCPDDRFET
64
=PP5V_S3_1V5S30V75S0
58
=PP5V_S3_AUDIO
49 51 53
=PP5V_S3_P5VLTS0FET
64
=PP5V_S3_VTTCLAMP
64
=PP5V_S3_DEBUG_ISNS
47
=PP5V_S3_SYSLED
37
=PP5V_S3_TPAD
45
=PP5V_S3_ODD
34
=PP5V_S3_DEBUG_ADC_AVDD
47
=PP5V_S3_DEBUG_ADC_DVDD
47
=PP5V_S3_P5VRTS0FET
64
=PPBUS_G3H
=PP18V5_G3H_CHGR
56
PPBUS_G3H
7
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE
=PPVIN_S0_MCPCORE
=PP3V3_S0_MCP_PLL_UF
23
=PP3V3R1V5_S0_MCP_HDA
21 23 37
=PP3V3_S0_MCPTHMSNS
42
=PP3V3_S0_CPUTHMSNS
42
=PP0V75_S0_MEM_VTT_A
27
=PP3V3_S0_DPCONN
67
=PPSPD_S0_MEM_A
27
=PPSPD_S0_MEM_B
28
=PP3V3_S0_PWRCTL
63
=PP3V3_S0_VMON
63
=PP3V3_S0_CPUVTTISNS
41
=PP3V3_S0_SMBUS_MCP_1
39
=PP1V5_S0_CPU
11 12
=PP1V5_S0_VMON
63
=PP3V3_S0_P1V8S0
62
=PP3V3_S0_MCP_PLL_VLDO
62
=PP3V3_S0_MCPDDRISNS
=PP1V8R1V5_S0_MCP_MEM
16 23
=PP1V5_S0_MEM_MCP
28
41
=PP1V5_S0_MCP_PLL_VLDO
62
58 26
=PPVTT_S3_DDR_BUF
C
PP1V8_S0
=PP1V05_S0_MCP_PLL_UF
57
=PPVIN_S3_5VS3 =PPBUS_G3HRS5
41
=PPCPUVCORE_VTT_ISNS
57 40
PPBUS_G3H_CPU_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE
& CPU VTT SENSING RES.)
7
"S5" RAILS
=PP3V3R1V8_S0_MCP_IFP_VDD
18 24
=PP1V8_S0_AUDIO
49
"ENET" RAILS 32
62 23
69
PPVTT_S3_DDR_BUF MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=1.8V MAKE_BASE=TRUE
B
41
=PPBUS_S0_LCDBKLT =PPVIN_S5_3V3S5
(AFTER HIGH SIDE CPU VCORE =PP1V8_S0_REG
58
(BEFORE HIGH SIDE SENSING RES.)
7
MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V MAKE_BASE=TRUE
62
60
=PPVIN_S5_1V5S30V75S0 =PPCPUVCORE_VTT_ISNS_R
18 19 21
=PP3V3_S0_SMC
28
39
39
=PP3V3_S0_MCP_VPLL_UF
44
38
=PP3V3_S3_VREFMRGN
D
35
=PP3V42_G3H_TPAD
36 37
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S0_MCP_DAC_UF
63
=PP3V3_S5_LPCPLUS
63
=PP3V3_S0_MCP
39
56
=PP3V3_S5_SMC
60
=PP3V3_S3_PDCISENS
37
=PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX
7
=PP5V_S0_VMON
64
PP1V5_S0
=PPVIN_S5_SMCVREF
27
=PP5V_S0_MCPREG
=PPVTT_S0_VTTCLAMP =PP0V75_S0_MEM_VTT_B
64
34
7
7
=PP1V5_S3_MEM_A
66
=PP3V3_S0_MCP_GPIO
C
PP3V42_G3H
=PP1V5_S3_P1V5S0FET
=PP5V_S0_HDD
=PP3V3_S0_LCD
40
=PP3V42_G3H_REG
55
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE
=PP5V_S0_DP_AUX_MUX
=PP3V3_S0_XDP
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
PP0V75_S0
7
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_S0
63
=PPVCORE_S0_MCP_VSENSE
=PP0V75_S0_REG
=PP3V3_S3_FET
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE
=PPVCORE_S0_MCP
58
PP1V5_S3
=PP3V3_S3_MCP_GPIO 64
PPVCORE_S0_MCP
(MCP VCORE AFTER SENSE RES)
64
8 23
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_VMON
"G3H" RAILS
MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE
7
1
59
PP5VLT_S0
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
=PP1V05_S0_MCP_PEX_DVDD
=PP1V5_S3_REG
7
MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE
7
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=1.25V MAKE_BASE=TRUE
(CPU VCORE PWR)
2
"S3" RAILS 58
59
3
=PP3V3_ENET_FET
62
PP3V3_ENET_PHY
=PP1V05_S5_REG
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
=PP3V3_ENET_MCP_RMGT
18 23
=PP3V3_ENET_PHY
31
61
=PPVIN_S5_CPU_IMVP
59
B
7
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
7
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE
PP1V05_S0_MCP_PLL_UF
PP1V1R1V05_S5
=PPVIN_S0_CPUVTTS0
=PP1V05_S5_MCP_VDD_AUXC
22 23
=PP1V05_ENET_P1V05ENETFET
32
DIGITAL GROUND GND 32
=PP1V05_ENET_FET
PP1V2R1V05_ENET
7
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
57
=PP1V05_ENET_MCP_PLL_MAC
=PP3V3_S5_REG
PP3V3_S5
7
23
=PP3V3_S5_MCP_GPIO =PP1V05_ENET_MCP_RMGT =PP1V05_ENET_PHY
18 23
18 20
=PP3V3_S5_ROM
38 48
=PP3V3_S5_LCD
65
=PP3V3_S5_MCP
22 23
31
=PP3V3_S5_MCPPWRGD
PEX & SATA AVDD/DVDD aliases 23
PP1V05_S0_MCP_PEX_AVDD
=PP1V05_S0_MCP_PEX_AVDD0
17
=PP1V05_S0_MCP_PEX_AVDD1
17
=PP1V05_S0_MCP_PEX_DVDD0
17
=PP1V05_S0_MCP_PEX_DVDD1
17
=PP1V05_S0_MCP_SATA_AVDD0
20
206 mA (A01)
MAKE_BASE=TRUE
206 mA (A01)
A
23 8
=PP1V05_S0_MCP_PEX_DVDD
57 mA (A01)
25
=PP3V3_S5_PWRCTL
63
=PP3V3_S5_P1V05ENETFET
32
=PP3V3_S5_P3V3S3FET
64
=PP3V3_S5_P3V3S0FET
64
=PP3V3_S5_P1V05S5
62
=PP3V3_S5_MEMRESET
29
=PP3V3_S5_P3V3ENETFET
32
=PP3V3_S5_DP_PORT_PWR
67
206 mA (A01) 23
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=0V
MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE
SYNC_MASTER=K24_MLB
PP1V05_S0_MCP_SATA_AVDD
=PP1V05_S0_MCP_SATA_AVDD1
20
=PP1V05_S0_MCP_SATA_DVDD0
20
SYNC_DATE=02/04/2009
Power Aliases
127 mA (A01)
DRAWING NUMBER 23 8
=PP1V05_S0_MCP_SATA_DVDD 127 mA (A01)
Apple Inc.
43 mA (A01)
=PP1V05_S0_MCP_SATA_DVDD1
A
PAGE TITLE 127 mA (A01)
MAKE_BASE=TRUE
20
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
051-7982 BRANCH
PAGE
8 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
PCI-E ALIASES
DACS ALIASES
UNUSED GPU LANES
HEATSINK STANDOFFS
17
NC_PEG_D2R_N
Z0901
STDOFF-4.5OD.98H-1.1-3.48-TH
=PEG_D2R_P
NC_PEG_D2R_P
17
=PEG_R2D_C_N
NC_PEG_R2D_C_N
NO_TEST=TRUE
1
1
NO_TEST=TRUE
ABOVE CPU
NC_PEG_R2D_C_P
17
PEG_PRSNT_L
TP_PEG_PRSNT_L
17
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
18
MCP_CLK27M_XTALIN
18
MCP_CLK27M_XTALOUT
NC_MCP_CLK27M_XTALOUT
18
CRT_IG_R_C_PR
NC_CRT_IG_R_C_PR
NO_TEST=TRUE
NO_TEST=TRUE
CRT_IG_G_Y_Y
TP_PEG_CLK100M_N MAKE_BASE=TRUE
18
CRT_IG_B_COMP_PB
NC_CRT_IG_B_COMP_PB
18
CRT_IG_HSYNC
NC_CRT_IG_HSYNC
NO_TEST=TRUE
UNUSED EXPRESS CARD LANE
NO_TEST=TRUE
17
PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_D2R_P
17
PCIE_EXCARD_D2R_N
TP_PCIE_EXCARD_D2R_N
18
CRT_IG_VSYNC
TP_MEM_A_A15
28
MEM_B_A
TP_MEM_B_A15
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ETHERNET ALIASES MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
32
=P3V3ENET_EN
32
=P1V05ENET_EN
PM_SLP_RMGT_L
31
=PP3V3_ENET_PHY_VDDREG
RTL8211_VDDREG
MAKE_BASE=TRUE
31
=RTL8211_REGOUT
NC_RTL8211_REGOUT
31
=RTL8211_ENSWREG
D
21
MAKE_BASE=TRUE
NC_CRT_IG_VSYNC
MAKE_BASE=TRUE
BELOW CPU
BELOW MCP
MEM_A_A
NC_CRT_IG_G_Y_Y NO_TEST=TRUE
1 1
27
NC_MCP_CLK27M_XTALIN
MAKE_BASE=TRUE
18
MAKE_BASE=TRUE
NC_MCP_TV_DAC_VREF
MAKE_BASE=TRUE
TP_PEG_CLK100M_P
PEG_CLK100M_N
MCP_TV_DAC_VREF
NO_TEST=TRUE
MAKE_BASE=TRUE
Z0904
Z0903
D
PEG_CLK100M_P
UNUSED ADDRESS PINS
NC_MCP_TV_DAC_RSET
NO_TEST=TRUE
MAKE_BASE=TRUE
=PEG_R2D_C_P
17
18
MAKE_BASE=TRUE
17
NO_TEST=TRUE
LEFT OF CPU
MCP_TV_DAC_RSET
NO_TEST=TRUE
17
STDOFF-4.5OD.98H-1.1-3.48-TH
18
MAKE_BASE=TRUE
1
SO-DIMM ALIASES
UNUSED CRT & TV-OUT INTERFACE
=PEG_D2R_N
NO_TEST=TRUE
Z0902
2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FAN STANDOFF
17
PCIE_EXCARD_R2D_C_P
TP_PCIE_EXCARD_R2D_C_P
17
PCIE_EXCARD_R2D_C_N
TP_PCIE_EXCARD_R2D_C_N
17
PCIE_EXCARD_PRSNT_L
TP_PCIE_EXCARD_PRSNT_L
31
1
18
18
17
TP_EXCARD_CLKREQ_L
17
PCIE_CLK100M_EXCARD_P
TP_PCIE_CLK100M_EXCARD_P
17
PCIE_CLK100M_EXCARD_N
TP_PCIE_CLK100M_EXCARD_N
LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N
NC_LVDS_IG_A_DATA_N3
18
LVDS_IG_B_CLK_P
NC_LVDS_IG_B_CLK_P
18
LVDS_IG_B_CLK_N
NC_LVDS_IG_B_CLK_N
OMIT
OMIT
72 17
Z0907
Z0906
3P2R2P7
3P2R2P7
72 17
PCIE_FW_D2R_P
LVDS_IG_B_DATA_P
NC_LVDS_IG_B_DATA_P
18
LVDS_IG_B_DATA_N
NC_LVDS_IG_B_DATA_N
NO_TEST=TRUE
TP_PCIE_FW_D2R_P
NO_TEST=TRUE
MAKE_BASE=TRUE
CPU FSB FREQUENCY STRAPS MAKE_BASE=TRUE
MAKE_BASE=TRUE
BSEL
MAKE_BASE=TRUE
0 0 0 0 1 1 1 1
PCIE_FW_R2D_C_P
TP_PCIE_FW_R2D_C_P
70 10
MISC MCP79 ALIASES
MAKE_BASE=TRUE
72 17
PCIE_FW_R2D_C_N
TP_PCIE_FW_R2D_C_N
17
PCIE_FW_PRSNT_L
TP_PCIE_FW_PRSNT_L
IN
CPU_BSEL MAKE_BASE=TRUE
=MCP_BSEL
OUT
14
MAKE_BASE=TRUE
17
FW_CLKREQ_L
TP_FW_CLKREQ_L
17
PCIE_CLK100M_FW_P
TP_PCIE_CLK100M_FW_P
17
PCIE_CLK100M_FW_N
TP_PCIE_CLK100M_FW_N
14
CPU_PECI_MCP
TP_CPU_PECI_MCP
19
FW_PME_L
TP_FW_PME_L
17
GMUX_JTAG_TCK_L
TP_GMUX_JTAG_TCK_L
17
GMUX_JTAG_TDO
TP_GMUX_JTAG_TDO
19
GMUX_JTAG_TDI
TP_GMUX_JTAG_TDI
19
GMUX_JTAG_TMS
TP_GMUX_JTAG_TMS
21
MCP_GPIO_4
MIKEY_MIC_LOAD_DET
17
CARDREADER_RESET
TP_CARDREADER_RESET
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
266 133 200 (166) 333 100 (400) (RSVD)
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
C
FSB MHZ
TP_PCIE_FW_D2R_N
PCIE_FW_D2R_N
1
1
5% 1/16W MF-LF 402
MAKE_BASE=TRUE
18
UNUSED FIREWIRE LANE
2
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
72 17
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MLB MOUNTING (TO C. BRACKET) SCREW HOLES
MAKE_BASE=TRUE
NO_TEST=TRUE MAKE_BASE=TRUE
R0931 22
NC_LVDS_IG_A_DATA_P3 NO_TEST=TRUE
MAKE_BASE=TRUE
EXCARD_CLKREQ_L
MAKE_BASE=TRUE
1
MAKE_BASE=TRUE
3P2R2P7
RTL8211_CLK125
LVDS ALIASES
MAKE_BASE=TRUE
OMIT
Z0905
TP_RTL8211_CLK125
C
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
LVDS CONNECTOR HOLE
20
USB_EXTD_P
TP_USB_EXTD_P
20
USB_EXTD_N
TP_USB_EXTD_N
20
USB_EXCARD_P
20
TP_USB_EXCARD_P
USB_EXCARD_N
TP_USB_EXCARD_N
MAKE_BASE=TRUE MAKE_BASE=TRUE
18
=MCP_MII_RXER
18
=MCP_MII_COL
18
=MCP_MII_CRS
MCP_MII_PD MAKE_BASE=TRUE
1
USB_MINI_P
TP_USB_MINI_P
2
MAKE_BASE=TRUE
20
OMIT
USB_MINI_N
20
USB_EXTC_P
TP_USB_EXTC_P
20
USB_EXTC_N
TP_USB_EXTC_N
73 20
USB_CARDREADER_P
TP_USB_CARDREADER_P
73 20
USB_CARDREADER_N
TP_USB_CARDREADER_N
73 20
USB_IR_N
TP_USB_IR_N
73 20
USB_IR_P
TP_USB_IR_P
3P2R2P7 1
59
SM
TP_IMVP6_NTC MAKE_BASE=TRUE
18
MAKE_BASE=TRUE
=DVI_HPD_GMUX_INT
HPLUG_DET2 MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
MAKE_BASE=TRUE
R0940 20K
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
OMIT
ZS0902 2.0DIA-MED-EMI-MLB-K84
ZS0903 2.0DIA-MED-EMI-MLB-K84
SM
1
IMVP6_NTC
MAKE_BASE=TRUE
2
SM
1
TP_IMVP6_VR_TT MAKE_BASE=TRUE
59
EMI IO MEDIUM POGO PINS (870-1794 ) OMIT
IMVP6_VR_TT
DP HOTPLUG PULL-DOWN
MAKE_BASE=TRUE
OMIT
CPU VCORE ALIASES
5% 1/16W MF-LF 402
TP_USB_MINI_N MAKE_BASE=TRUE
Z0913
R0930 47K
MAKE_BASE=TRUE MAKE_BASE=TRUE
20
ZS0901 2.0DIA-MED-EMI-MLB-K84
TP_SMC_SYS_KBDLED MAKE_BASE=TRUE
1
OMIT
SMC_SYS_KBDLED
LAN ALIASES
UNUSED USB PORTS
1
ZS0900 2.0DIA-MED-EMI-MLB-K84
36
USB ALIASES
Z0910 3P2R2P7
3P2R2P7
54 MAKE_BASE=TRUE
OMIT
OMIT
Z0911
SMC ALIASES
MAKE_BASE=TRUE
MLB MOUNTING (TO TOPCASE) SCREW HOLES
SM
1
1
B
B OMIT
OMIT
ZS0908 2.0DIA-MED-EMI-MLB-K84
ZS0909 2.0DIA-MED-EMI-MLB-K84
SM
OMIT
ZS0911 2.0DIA-MED-EMI-MLB-K84
SM
1
SM
1
1
EMI TALL POGO PINS (870-1698 ) OMIT ZS0904
OMIT ZS0905
OMIT ZS0906
OMIT ZS0907
OMIT ZS0910
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
SM
SM
1
SM
1
SM
1
SM
1
1
OMIT ZS0912
OMIT ZS0913
OMIT ZS0914
OMIT ZS0915
OMIT ZS0919
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
SM
SM
1
SM
1
SM
1
SM
1
1
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/04/2009
A
PAGE TITLE
SIGNAL ALIAS
EMI THINBC POGO PINS (870-1820 ) OMIT ZS0917 2.0DIA-MLB-THIN-BC-K84 SM
DRAWING NUMBER
Apple Inc. OMIT ZS0918
OMIT ZS0916
2.0DIA-MLB-THIN-BC-K84
2.0DIA-MLB-THIN-BC-K84
SM
SM
NOSTUFF
NOTICE OF PROPRIETARY PROPERTY:
SM
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
1 1
C.0.0
ZS0920
1 1
D
REVISION
R
2.0DIA-MLB-THIN-BC-K84
SIZE
051-7982 BRANCH
PAGE
9 OF 109 SHEET
OF
8
7
6
5
4
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1
8
7
6
5
4
3
2
1
OMIT
K5
70 14
BI
FSB_A_L
M3
70 14
BI
FSB_A_L
N2
70 14
BI
FSB_A_L
J1
70 14
BI
FSB_A_L
N3
70 14
BI
70 14
FSB_A_L
P5
BI
FSB_A_L
P2
70 14
BI
FSB_A_L
L2
70 14
BI
FSB_A_L
P4
70 14
BI
FSB_A_L
P1
70 14
BI
FSB_A_L
R1
70 14
BI
FSB_ADSTB_L
M1
70 14
BI
FSB_REQ_L
K3
BI
FSB_REQ_L
H2
70 14
BI
FSB_REQ_L
K2
70 14
BI
FSB_REQ_L
J3
70 14
BI
FSB_REQ_L
L1
70 14
BI
FSB_A_L
Y2
70 14
BI
FSB_A_L
U5
70 14
BI
FSB_A_L
R3 W6
BI
FSB_A_L
70 14
BI
FSB_A_L
U4
70 14
BI
FSB_A_L
Y5
70 14
BI
FSB_A_L
U1
70 14
BI
FSB_A_L
R4
70 14
BI
FSB_A_L
T5
70 14
BI
FSB_A_L
T3
70 14
BI
FSB_A_L
W2
70 14
BI
FSB_A_L
W5
70 14
BI
FSB_A_L
Y4
70 14
BI
FSB_A_L
U2 V4
70 14
BI
FSB_A_L
70 14
BI
FSB_A_L
W3
70 14
BI
FSB_A_L
AA4
70 14
BI
FSB_A_L
AB2
70 14
BI
FSB_A_L
AA3
70 14
BI
FSB_ADSTB_L
70 14
V1
70 14
IN
CPU_A20M_L
A6
70 14
OUT
CPU_FERR_L
A5
70 14
IN
CPU_IGNNE_L
C4
70 14
IN
CPU_STPCLK_L
70 14
IN
CPU_INTR
C6
70 14
IN
CPU_NMI
B4
IN
CPU_SMI_L
A3
70 14
D5
TP_CPU_RSVD_M4
M4
TP_CPU_RSVD_N5
N5
TP_CPU_RSVD_T2
T2
TP_CPU_RSVD_V3
V3
TP_CPU_RSVD_B2
B2
TP_CPU_RSVD_F6
F6
TP_CPU_RSVD_D2
D2
TP_CPU_RSVD_D22 TP_CPU_RSVD_D3
D22 D3
1 OF 4
DEFER* DRDY* DBSY* BR0*
REQ0* REQ1* REQ2* REQ3* REQ4*
A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1*
BI
14 70
FSB_BNR_L
BI
14 70
FSB_BPRI_L
BI
14 70
H5
FSB_DEFER_L
BI
14 70
F21
FSB_DRDY_L
BI
14 70
E1
FSB_DBSY_L
BI
14 70
FSB_BREQ0_L
F1
BI
=PP1V05_S0_CPU
R1000 1% 1/16W MF-LF 402
14 70
1
2
D
IERR* INIT*
B3
CPU_INIT_L
IN
LOCK*
H4
FSB_LOCK_L
BI
RESET* RS0* RS1* RS2* TRDY*
C1
FSB_CPURST_L
IN
13 14 70
F3
FSB_RS_L
IN
14 70
F4
FSB_RS_L
IN
14 70
G3
FSB_RS_L
IN
14 70
G2
FSB_TRDY_L
IN
14 70
G6
FSB_HIT_L
BI
14 70
E4
FSB_HITM_L
BI
14 70
BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR*
8 11 12 13
54.9
D20
HIT* HITM*
70 CPU_IERR_L 14 70
14 70
OMIT
AD4
XDP_BPM_L
AD3
XDP_BPM_L
BI
13 70
AD1
XDP_BPM_L
BI
13 70
AC4
XDP_BPM_L
BI
13 70
AC2
XDP_BPM_L
AC1
XDP_BPM_L
AC5
XDP_TCK
AA6
BI
BI
13 70
1
R1001
70 14
BI
FSB_D_L
E22
70 14
BI
FSB_D_L
F24 E26
BI
FSB_D_L
70 14
BI
FSB_D_L
G22
70 14
BI
FSB_D_L
F23
70 14
BI
FSB_D_L
G25
70 14
BI
FSB_D_L
E25
BI
FSB_D_L
E23 K24 G24
70 14
54.9 1% 1/16W MF-LF 402
13 70
2
BI
13 70
IN
10 13 70
70 14
XDP_TDI
IN
10 13 70
70 14
BI
FSB_D_L
AB3
XDP_TDO
OUT
10 13 70
70 14
BI
FSB_D_L
AB5
XDP_TMS
AB6
XDP_TRST_L
C20
XDP_DBRESET_L
IN
10 13 70
70 14
BI
FSB_D_L
J24
IN
10 13 70
70 14
BI
FSB_D_L
J23
70 14
BI
FSB_D_L
H22 F26
OUT
13 25
R1002
1
BI
FSB_D_L
70 14
BI
FSB_D_L
K22
70 14
BI
FSB_D_L
H23
70 14
BI
FSB_DSTB_L_N
J26
70 14
BI
FSB_DSTB_L_P
H26
70 14
BI
FSB_DINV_L
H25
70 14
BI
FSB_D_L
N22
70 14
BI
FSB_D_L
K25
70 14
BI
FSB_D_L
P26
70 14
BI
FSB_D_L
R23
70 14
BI
FSB_D_L
L23
70 14
BI
FSB_D_L
M24
70 14
BI
FSB_D_L
L22
70 14
BI
FSB_D_L
M23
70 14
BI
FSB_D_L
P25
70 14
BI
FSB_D_L
P23
70 14
BI
FSB_D_L
P22 T24
70 14
68 5% 1/16W MF-LF 402
THERMAL PROCHOT* THERMDA THERMDC
A20M* FERR* IGNNE* STPCLK* LINT0 LINT1 SMI*
FSB_ADS_L
G5
THERMTRIP*
CPU_PROCHOT_L
A24
CPU_THERMD_P
B25
C7
2
OUT OUT
42 76
CPU_THERMD_N
OUT
42 76
PM_THRMTRIP_L
OUT
14 37 70
14 37 70
H CLK
BCLK0 BCLK1
RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8
D21
A22
FSB_CLK_CPU_P
A21
FSB_CLK_CPU_N
IN IN
14 70 14 70
BI
FSB_D_L
70 14
BI
FSB_D_L
R24
70 14
BI
FSB_D_L
L25
70 14
BI
FSB_D_L
T25
70 14
BI
FSB_D_L
N25
70 14
BI
FSB_DSTB_L_N
L26
70 14
BI
FSB_DSTB_L_P
M26
70 14
BI
FSB_DINV_L
N24
70 14
1
R1005 1K
CPU JTAG Support
B
R1090
2
1% 1/16W MF-LF 402
D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0*
D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1*
U1000 PENRYN FCBGA
2 OF 4
DATA GRP 2
FSB_A_L
H1 E2
DATA GRP 3
BI
FCBGA
DATA GRP 0
70 14
ADS* BNR* BPRI*
PENRYN
DATA GRP 1
BI
L4
CONTROL
L5
U1000
XDP/ITP SIGNALS
FSB_A_L FSB_A_L
A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0*
ADDR GROUP0
BI
70 14
70 14
C
J4
ADDR GROUP1
70 14
FSB_A_L
ICH
BI
RESERVED
D
70 14
D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2*
D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3*
Y22
FSB_D_L
BI
14 70
AB24
FSB_D_L
BI
14 70
V24
FSB_D_L
BI
14 70
V26
FSB_D_L
BI
14 70
V23
FSB_D_L
BI
14 70
T22
FSB_D_L
BI
14 70
U25
FSB_D_L
BI
14 70
U23
FSB_D_L
BI
14 70
Y25
FSB_D_L
BI
14 70
W22
FSB_D_L
BI
14 70
Y23
FSB_D_L
BI
14 70
W24
FSB_D_L
BI
14 70
W25
FSB_D_L
BI
14 70
AA23
FSB_D_L
BI
14 70
AA24
FSB_D_L
BI
14 70
AB25
FSB_D_L
BI
14 70
Y26
FSB_DSTB_L_N
BI
14 70
AA26
FSB_DSTB_L_P
BI
14 70
U22
FSB_DINV_L
BI
14 70
AE24
FSB_D_L
BI
14 70
AD24
FSB_D_L
BI
14 70
AA21
FSB_D_L
BI
14 70
AB22
FSB_D_L
BI
14 70
AB21
FSB_D_L
BI
14 70
AC26
FSB_D_L
BI
14 70
AD20
FSB_D_L
BI
14 70
AE22
FSB_D_L
BI
14 70
AF23
FSB_D_L
BI
14 70
AC25
FSB_D_L
BI
14 70
AE21
FSB_D_L
BI
14 70
AD21
FSB_D_L
BI
14 70
AC22
FSB_D_L
BI
14 70
AD23
FSB_D_L
BI
14 70
AF22
FSB_D_L
BI
14 70
AC23
FSB_D_L
BI
14 70
AE25
FSB_DSTB_L_N
BI
14 70
AF24
FSB_DSTB_L_P
BI
14 70
AC20
FSB_DINV_L
BI
14 70
C
B
54.9 70 13 10
XDP_TMS
70 13 10
XDP_TDI
1
70 26 CPU_GTLREF
2
CPU_TEST1
C23
R1006
CPU_TEST2
D25
2.0K
TP_CPU_TEST3
1% 1/16W
R1091
1
MF-LF 402
54.9 1
2 1% 1/16W MF-LF
R1092 2
54.9
402
70 13 10
XDP_TDO
1
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)
1% 1/16W MF-LF 402
CPU_TEST4 NO STUFF
C1014
2 1% 1/16W
NO STUFF
MF-LF
R1010
402 1
NO STUFF
R1011
R1093
10% 16V X5R 402
1
2 1% 1/16W
R1094
MF-LF 402
649 70 13 10
XDP_TRST_L
1
NO STUFF 1
402
1K
54.9
XDP_TCK
1/16W MF-LF
5% 1/16W MF-LF 402
2
AF26 AF1
TP_CPU_TEST6
A26 C3
70 9
OUT CPU_BSEL
B22
70 9
OUT CPU_BSEL
B23
70 9
OUT CPU_BSEL
C21
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2
COMP0 COMP1 COMP2 COMP3
MISC
DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*
R26
70 CPU_COMP
U26
70 CPU_COMP
AA1
70 CPU_COMP
Y1
70 CPU_COMP
1
E5
CPU_DPRSTP_L
IN
14 59 70
B5
CPU_DPSLP_L
IN
14 70
54.9
54.9
1% 1/16W
1% 1/16W
D24
FSB_DPWR_L
IN
14 70
D6
CPU_PWRGD
IN
13 14 70
D7
FSB_CPUSLP_L
IN
14 70
AE6
CPU_PSI_L
R1023
MF-LF
OUT
402
59
5% 1/16W MF-LF 402
1
R1021
MF-LF 402
2
1
2
1
R1022 27.4
R1012 1K
2
C24
TP_CPU_TEST5
TP_CPU_TEST7 2
2 5%
1
1
0.1uF
0
70 13 10
AD26
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.
1% 1/16W
PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.
MF-LF 402
2
R1020 27.4 1% 1/16W
2
MF-LF 402
PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
2
PLACEMENT_NOTE (all 4 resistors):
1%
Place within 12.7mm of CPU
1/16W MF-LF 402
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
CPU FSB DRAWING NUMBER
SYNC FROM T18
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
CHANGE CPU FROM SOCKET TO BGA SYMBOL
SIZE
BRANCH
PAGE
10 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
A4
P6
A8
(CPU CORE POWER)
1
P21
OMIT A11
=PPVCORE_S0_CPU
P24
U1000
8 11 12 A14
R2
PENRYN
44 A (SV Design Target)
A16
41 A (SV HFM)
A19
30.4 A (SV LFM)
A23
R25
AF2
T1
B6
T4
R5
FCBGA
D
AB20
A7 A9
AB7
OMIT
A10
23 A (LV Design Target)
AC7
U1000
AC9
A12
R22
4 OF 4
B8
T23
AC12
B11
T26
AC13
B13
U3
PENRYN A13
FCBGA
A15
3 OF 4
A17
AC15
B16
U6
A18
AC17
B19
U21
A20
AC18
B21
U24
B7
AD7
B24
V2
B9
AD9
C5
V5
B10
AD10
C8
V22
B12
AD12
C11
V25
B14
AD14
C14
W1
B15
AD15
C16
W4
B17
AD17
C19
W23
B18
AD18
C2
W26
B20
VCC
C22
Y3 Y6
C9
AE10
C25
C10
AE12
D1
Y21
C12
AE13
D4
Y24
C13
AE15
D8
AA2
C15
AE17
D11
AA5
C17
AE18
D13
AA8
C18
AE20
D16
AA11
AF9
D19
AA14
D10
AF10
D23
AA16
D12
AF12
D26
AA19
D14
AF14
E3
AA22
D9
C
AE9
D15
VCC
AF15
E6
AA25
D17
AF17
E8
AB1
D18
AF18
E11
E7
AF20
(CPU IO POWER 1.05V) E14
=PP1V05_S0_CPU
E9
8 10 12 13
D
C
AB4
VSS
VSS
AB8
E16
AB11
E19
AB13
E21
AB16
E10
G21
E12
V6
E13
J6
E24
AB19
E15
K6
F5
AB23
E17
M6
F8
AB26
E18
J21
F11
AC3
E20
K21
F13
AC6
F7
M21
F16
AC8
N21
F19
AC11
F2
AC14
4500 mA (before VCC stable) 2500 mA (after VCC stable)
VCCP
F9 F10
N6
F12
R21
F22
AC16
F14
R6
F25
AC19
F15
T21
G4
AC21
F17
T6
G1
AC24
F18
V21
F20
W21
G23
AD2
G26
AD5
H3
AD8
H6
AD11
H21
AD13
H24
AD16 AD19
(CPU INTERNAL PLL POWER 1.5V) AA7
=PP1V5_S0_CPU
(BR1#)
AA9
B26
VCCA
AA10
B
8 12
130 mA C26
AA12
VID0 VID1 VID2 VID3 VID4 VID5 VID6
AA13 AA15 AA17 AA18 AA20 AB9 AC10
AD6
CPU_VID
OUT
59 70
J2
AF5
CPU_VID
OUT
59 70
J5
AD22
AE5
CPU_VID
OUT
59 70
J22
AD25
AF4
CPU_VID
OUT
59 70
J25
AE1
AE3
CPU_VID
OUT
59 70
K1
AE4
K4
AE8
AF3
CPU_VID
AE2
CPU_VID
=PPVCORE_S0_CPU
OUT
59 70
OUT
59 70
1
2
VCCSENSE
AB14
AF7
8 11 12
R1100 100
AB10 AB12
CPU_VCCSENSE_P
1% 1/16W MF-LF 402
OUT
59 70
AB15 PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs. PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.
AB17
VSSSENSE
AB18
AE7
B
CPU_VCCSENSE_N
OUT 1
2
59 70
K23
AE11
K26
AE14
L3
AE16
L6
AE19
L21
AE23
L24
AE26
M2
A2
M5
AF6
R1101
M22
AF8
100
M25
AF11
N1
AF13
N4
AF16
N23
AF19
N26
AF21
1% 1/16W MF-LF 402
P3 B1
A25
(Socket-P KEY)
A
AF25
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
CPU Power & Ground DRAWING NUMBER
SYNC FROM T18 Apple Inc.
CHANGE CPU FROM SOCKET TO BGA SYMBOL
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
PAGE
11 OF 109 SHEET
OF
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
8
051-7982
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
CPU VCore HF and Bulk Decoupling 4X 330UF. 20X 22UF 0805 PLACEMENT_NOTE (C1200-C1219): 11 8 =PPVCORE_S0_CPU
Place inside socket cavity on secondary side.
D
CRITICAL 1
CRITICAL 1
C1200 22UF
2
22UF
20% 6.3V CERM-X5R 805
2
CRITICAL 1
2
CRITICAL 1
C1201
C1203
22UF
20% 6.3V CERM-X5R 805
2
CRITICAL 1
C1210
CRITICAL 1
C1202
22UF
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
2
CRITICAL 1
C1211
CRITICAL 1
22UF 2
CRITICAL 1
C1212
C1213
CRITICAL 1
C1204
22UF
20% 6.3V CERM-X5R 805
2
CRITICAL 1
CRITICAL 1
C1205
CRITICAL 1
22UF
20% 6.3V CERM-X5R 805
2
CRITICAL 1
C1214
C1206
C1216
CRITICAL 1
22UF 2
CRITICAL 1
C1215
20% 6.3V CERM-X5R 805
C1207 20% 6.3V CERM-X5R 805
22UF 2
CRITICAL 1
C1217
22UF
22UF
22UF
22UF
22UF
22UF
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
2
2
2
2
2
2
2
20% 6.3V CERM-X5R 805
CRITICAL 1
C1218
22UF
20% 6.3V CERM-X5R 805
2
2
CRITICAL 1
22UF
20% 6.3V CERM-X5R 805
C1209 22UF
20% 6.3V CERM-X5R 805
22UF
D
CRITICAL 1
C1208
C1219 22UF
2
20% 6.3V CERM-X5R 805
C
C PLACEMENT_NOTE (C1240-C1243): Place on secondary side. CRITICAL
NOSTUFF
1
1
C1240 470UF-4MOHM
2
CRITICAL 1
C1241 470UF-4MOHM
20% 3
Place on secondary side.
CRITICAL
470UF-4MOHM
20%
2.0V POLY-TANT
3
D2T-SM
2
C1243 470UF-4MOHM 20%
20%
2.0V POLY-TANT
3
D2T-SM
Place on secondary side.
CRITICAL 1
C1242
2
2.0V POLY-TANT
3
2.0V POLY-TANT
2
D2T-SM
D2T-SM
Place on secondary side.
VCCA (CPU AVdd) DECOUPLING 1x 10uF, 1x 0.01uF 11 8 =PP1V5_S0_CPU
PLACEMENT_NOTE=Place C1281 near CPU pin B26.
C1250
1
1
2
2
C1251
10uF 20% 6.3V X5R 603
0.01UF 10% 16V CERM 402
B
B VCCP (CPU I/O) DECOUPLING 1x 330uF, 6x 0.1uF 0402 13 11 10 8 =PP1V05_S0_CPU
1 CRITICAL
C1260
1
330UF 2
20% 2.5V TANT CASE-B2-SM
2
C1261
1
C1262
1
C1263
1
C1264
1
C1265
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
2
2
2
2
1
C1266 0.1UF
2
20% 10V CERM 402
A
SYNC_MASTER=K24_MLB
SYNC_DATE=03/30/2009
A
PAGE TITLE
CPU Decoupling DRAWING NUMBER
Apple Inc.
SYNC FROM T18 REMOVE NO STUFF CAPS C1220 TO C1231 REMOVE C1244 & C1245 CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
12 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
Mini-XDP Connector NOTE: This is not the standard XDP pinout.
D
USE WITH 920-0782 ADAPTER FLEX TO SUPPORT CPU, MCP DEBUGGING.
D
MCP79-specific pinout
8 12 11 10 8
=PP3V3_S0_XDP =PP1V05_S0_CPU
XDP
R1315
OMIT CRITICAL
1
J1300
54.9 1% 1/16W MF-LF 402
70 10 70 10
70 10 70 10
DF40C-60DS-0.4V F-ST-SM 2
XDP_BPM_L
OBSFN_A0
4
OBSFN_C0
JTAG_MCP_TDO
BI
XDP_BPM_L
OBSFN_A1
5
6
OBSFN_C1
JTAG_MCP_TRST_L
7
8 10
OBSDATA_C0
MCP_DEBUG
BI
19 73
OBSDATA_C1
MCP_DEBUG
BI
19 73
BI
19 73
BI
BI IN
XDP_BPM_L
OBSDATA_A0
9
XDP_BPM_L
OBSDATA_A1
11
12
13
14 16
OBSDATA_C2
MCP_DEBUG
OBSDATA_C3
MCP_DEBUG
70 10
IN
XDP_BPM_L
70 10
IN
XDP_BPM_L
XDP
OBSDATA_A2
15
OBSDATA_A3
17
18
19
20
1
21
19 73
21
22
OBSFN_D0
JTAG_MCP_TDI
OUT
21
TP_XDP_OBSFN_B1
OBSFN_B1
23
24
OBSFN_D1
JTAG_MCP_TMS
OUT
21
25
26
TP_XDP_OBSDATA_B0
OBSDATA_B0
27
28
OBSDATA_D0
MCP_DEBUG
BI
19 73
TP_XDP_OBSDATA_B1
OBSDATA_B1
29
30
OBSDATA_D1
MCP_DEBUG
BI
19 73
31
32 19 73
TP_XDP_OBSDATA_B2
OBSDATA_B2
33
34
OBSDATA_D2
MCP_DEBUG
BI
TP_XDP_OBSDATA_B3
OBSDATA_B3
35
36
OBSDATA_D3
MCP_DEBUG
BI
37
38
PWRGD/HOOK0
39
40
ITPCLK/HOOK4
FSB_CLK_ITP_P
IN
14 70
FSB_CLK_ITP_N
IN
14 70
XDP_PWRGD
2
21
OBSFN_B0
1K
CPU_PWRGD
IN OUT
TP_XDP_OBSFN_B0
R1399 IN
2
BI
3
C
70 14 10
1
HOOK1
41
42
ITPCLK#/HOOK5
VCC_OBS_AB
43
44
VCC_OBS_CD
XDP_OBS20
5% 1/16W MF-LF 402
19 73
XDP
R1303 1K
19
IN
PM_LATRIGGER_L
HOOK2
45
46
RESET#/HOOK6
21
OUT
JTAG_MCP_TCK
HOOK3
47
48
DBR#/HOOK7
70 XDP_CPURST_L
XDP_DBRESET_L
49
50
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
1
OUT
10 25
SMBUS_MCP_0_DATA
SDA
51
52
TDO
XDP_TDO
IN
10 70
BI
SMBUS_MCP_0_CLK
SCL
53
54
TRSTn
XDP_TRST_L
OUT
10 70
55
56
TDI
XDP_TDI
OUT
10 70
OUT
XDP_TCK
57
58
TMS
XDP_TMS
OUT
10 70
59
60
XDP_PRESENT#
NC
TCK0
1
1
2
2
0.1uF
B
10 14 70
C1301 0.1uF
10% 16V X5R 402
IN
XDP
XDP
C1300
FSB_CPURST_L
PLACEMENT_NOTE=Place close to CPU to minimize stub.
402
BI
73 39 21
TCK1
2 5% 1/16W MF-LF
73 39 21
70 10
C
10% 16V X5R 402
B
(998-2515) 518S0774
Direction of XDP module Please avoid any obstructions ON ODD-NUMBERED SIDE OF J1300
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/25/2009
A
PAGE TITLE
eXtended Debug Port(MiniXDP) DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
13 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400 MCP79-TOPO-B BGA (1 OF 11)
BI
FSB_DSTB_L_P
70 10
BI
FSB_DSTB_L_N
U40
BI
FSB_DINV_L
V41
70 10
70 10 70 10 70 10
D
L36
70 10
BI
FSB_DINV_L
N35
70 10
BI
FSB_DSTB_L_P
M39
70 10
BI
FSB_DSTB_L_N
M41
70 10
BI
FSB_DINV_L
BI
FSB_A_L
BI
FSB_A_L
70 10 70 10 70 10 70 10 70 10 70 10 70 10
FSB_A_L
AE37
BI
FSB_A_L
AE35
BI
FSB_A_L
AB35
BI
FSB_A_L
AF35
BI
FSB_A_L
BI
FSB_A_L
BI
FSB_A_L
AE33
BI
FSB_A_L
AG37
BI
FSB_A_L
AG35 AG39
AG38
FSB_A_L
70 10
BI
FSB_A_L
70 10
BI
FSB_A_L
BI
FSB_A_L
AL39 AG33 AL33 AJ33
BI
FSB_A_L
BI
FSB_A_L
BI
FSB_A_L
AJ37
70 10
BI
FSB_A_L
AJ36
70 10
BI
FSB_A_L
AJ38
70 10
BI
FSB_A_L
AL37
BI
FSB_A_L
BI
FSB_A_L
70 10
BI
FSB_A_L
70 10
BI
FSB_A_L
BI
FSB_A_L
70 10 70 10
BI
FSB_A_L
BI
FSB_A_L
70 10
BI
70 10
BI
FSB_ADSTB_L
70 10 70 10
AN36 AJ35
AL34 AN37 AJ34 AL38 AL35 AN34 AR39
FSB_A_L
BI
FSB_ADSTB_L
AN35
AE36 AK35
BI
FSB_REQ_L
AC38
BI
FSB_REQ_L
AA33 AC39
BI
FSB_REQ_L
70 10
BI
FSB_REQ_L
AC33
70 10
BI
FSB_REQ_L
AC35
70 10
5% 1/16W
70 10
BI
FSB_ADS_L
AD42
MF-LF
MF-LF
MF-LF
70 10
BI
FSB_BNR_L
AD43
BI
FSB_BREQ0_L
AE40
70 FSB_BREQ1_L
AL32
402
2
2
402
70 10
IN
PM_THRMTRIP_L
70 10
BI
FSB_DBSY_L
AD39
IN
CPU_FERR_L
70 10
BI
FSB_DRDY_L
AD41
70 10
BI
70 10
NO STUFF
R1420
NO STUFF 1
R1421
1K
402
1
1
1K
2
402
AB42
FSB_HITM_L
AD40
IN
FSB_LOCK_L
AC43
70 10
OUT
FSB_TRDY_L
AE41
9
OUT
CPU_PECI_MCP
R1422
70 37 10
OUT
CPU_PROCHOT_L
1K
E41 AJ41 AG43
5% 1/16W
MF-LF
MF-LF
FSB_HIT_L
BI
70 10
NO STUFF
5% 1/16W
5% 1/16W
CPU_DSTBP1# CPU_DSTBN1# CPU_DBI1# CPU_DSTBP2# CPU_DSTBN2# CPU_DBI2# CPU_DSTBP3# CPU_DSTBN3# CPU_DBI3# CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32# CPU_A33# CPU_A34# CPU_A35# CPU_ADSTB0# CPU_ADSTB1# CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4#
62
5% 1/16W
2
CPU_DSTBP0# CPU_DSTBN0# CPU_DBI0#
R1416
1% 1/16W 402
9
BI
BI
70 10
9
BI
AC37
70 10
70 10
9
AE34
FSB_A_L
BI
70 10
70 10
FSB_A_L
70 10
70 10
70 37 10
BI
AN38
70 10
B
AE38
AG34
70 10
62
AC34
FSB_A_L
70 10
54.9
J41
FSB_A_L
70 10
R1415
N37
BI
70 10
R1410
V35
FSB_DSTB_L_N
70 10
1
FSB_DINV_L
BI
70 10
1
BI
W37
BI
70 10
1
FSB_DSTB_L_N
70 10
70 10
=PP1V05_S0_MCP_FSB
BI
W39
70 10
70 10
23 22 14 8
FSB_DSTB_L_P
FSB_DSTB_L_P
70 10
C
BI
T40
FSB
70 10
AH40
MF-LF 2
2
CPU_ADS# CPU_BNR# CPU_BR0# CPU_BR1# CPU_DBSY# CPU_DRDY# CPU_HIT# CPU_HITM# CPU_LOCK# CPU_TRDY# CPU_PECI CPU_PROCHOT# CPU_THERMTRIP# CPU_FERR#
402
IN
=MCP_BSEL
(MCP_BSEL)
F42
IN
=MCP_BSEL
(MCP_BSEL)
D42
IN
=MCP_BSEL
(MCP_BSEL)
F41
CPU_BSEL2 CPU_BSEL1 CPU_BSEL0
CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63#
Y43
FSB_D_L
BI
10 70
W42
FSB_D_L
BI
10 70
Y40
FSB_D_L
BI
10 70
W41
FSB_D_L
BI
10 70
Y39
FSB_D_L
BI
10 70
V42
FSB_D_L
BI
10 70
Y41
FSB_D_L
BI
10 70
Y42
FSB_D_L
BI
10 70
P42
FSB_D_L
BI
10 70
U41
FSB_D_L
BI
10 70
R42
FSB_D_L
BI
10 70
T39
FSB_D_L
BI
10 70
T42
FSB_D_L
BI
10 70
T41
FSB_D_L
BI
10 70
R41
FSB_D_L
BI
10 70
T43
FSB_D_L
BI
10 70
W35
FSB_D_L
BI
10 70
AA37
FSB_D_L
BI
10 70
W33
FSB_D_L
BI
10 70
W34
FSB_D_L
BI
10 70
AA36
FSB_D_L
BI
10 70
AA34
FSB_D_L
BI
10 70
AA38
FSB_D_L
BI
10 70
AA35
FSB_D_L
BI
10 70
U38
FSB_D_L
BI
10 70
U36
FSB_D_L
BI
10 70
U35
FSB_D_L
BI
10 70
U33
FSB_D_L
BI
10 70
U34
FSB_D_L
BI
10 70
W38
FSB_D_L
BI
10 70
R33
FSB_D_L
BI
10 70
U37
FSB_D_L
BI
10 70
N34
FSB_D_L
BI
10 70
N33
FSB_D_L
BI
10 70
R34
FSB_D_L
BI
10 70
R35
FSB_D_L
BI
10 70
P35
FSB_D_L
BI
10 70
R39
FSB_D_L
BI
10 70
R37
FSB_D_L
BI
10 70
R38
FSB_D_L
BI
10 70
L37
FSB_D_L
BI
10 70
L39
FSB_D_L
BI
10 70
L38
FSB_D_L
BI
10 70
N36
FSB_D_L
BI
10 70
N38
FSB_D_L
BI
10 70
J39
FSB_D_L
BI
10 70
J38
FSB_D_L
BI
10 70
J37
FSB_D_L
BI
10 70
L42
FSB_D_L
BI
10 70
M42
FSB_D_L
BI
10 70
P41
FSB_D_L
BI
10 70
N41
FSB_D_L
BI
10 70
N40
FSB_D_L
BI
10 70
M40
FSB_D_L
BI
10 70
H40
FSB_D_L
BI
10 70
K42
FSB_D_L
BI
10 70
H41
FSB_D_L
BI
10 70
L41
FSB_D_L
BI
10 70
H43
FSB_D_L
BI
10 70
H42
FSB_D_L
BI
10 70
K41
FSB_D_L
BI
10 70
J40
FSB_D_L
BI
10 70
H39
FSB_D_L
BI
10 70
M43
FSB_D_L
BI
AA41
FSB_BPRI_L
OUT
10 70
AA40
FSB_DEFER_L
OUT
10 70
BCLK_OUT_CPU_P BCLK_OUT_CPU_N
G42
FSB_CLK_CPU_P
OUT
10 70
G41
FSB_CLK_CPU_N
OUT
10 70
BCLK_OUT_ITP_P BCLK_OUT_ITP_N
AL43
FSB_CLK_ITP_P
OUT
13 70
AL42
FSB_CLK_ITP_N
OUT
13 70
BCLK_OUT_NB_P BCLK_OUT_NB_N
AL41
70 FSB_CLK_MCP_P
AK42
70 FSB_CLK_MCP_N
BCLK_IN_N BCLK_IN_P
AK41
CPU_A20M# CPU_IGNNE# CPU_INIT# CPU_INTR CPU_NMI CPU_SMI#
AF41
CPU_A20M_L
OUT
10 70
AH39
CPU_IGNNE_L
OUT
10 70
CPU_BPRI# CPU_DEFER#
D
C
B
10 70
Loop-back clock for delay matching.
OUT
FSB_RS_L
AC41
70 10
OUT
FSB_RS_L
AB41
70 10
OUT
FSB_RS_L
AC42
70 10
R1430
1
1
49.9
49.9
1%
270 mA (A01)
2
2
1
1
49.9
AG27
20 mA
AH27
MF-LF 402
29 mA
AG28
15 mA
AH28
70 MCP_BCLK_VML_COMP_VDD
AM39
70 MCP_BCLK_VML_COMP_GND
AM40
70 MCP_CPU_COMP_VCC
AM43
70 MCP_CPU_COMP_GND
AM42
R1436 49.9
1%
1%
1/16W MF-LF 402
206 mA
1/16W
A R1431
PP1V05_S0_MCP_PLL_FSB
1%
1/16W MF-LF 402
23
R1435
1/16W
2
2
CPU_RS0# CPU_RS1# CPU_RS2#
MF-LF 402
+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU BCLK_VML_COMP_VDD BCLK_VML_COMP_GND CPU_COMP_VCC CPU_COMP_GND
CPU_PWRGD CPU_RESET# CPU_SLP# CPU_DPSLP# CPU_DPWR# CPU_STPCLK# CPU_DPRSTP#
AJ40
AH42
CPU_INIT_L
OUT
10 70
AF42
CPU_INTR
OUT
10 70
AG41
CPU_NMI
OUT
10 70
AH41
CPU_SMI_L
OUT
10 70
=PP1V05_S0_MCP_FSB
R1440 150 5% 1/16W MF-LF 2
7
402
SYNC_MASTER=K24_MLB
AH43
CPU_PWRGD
H38
FSB_CPURST_L
OUT
10 13 70
AM33
FSB_CPUSLP_L
OUT
10 70
AN33
CPU_DPSLP_L
OUT
10 70
AM32
FSB_DPWR_L
OUT
10 70
AG42
CPU_STPCLK_L
OUT
10 70
AN32
CPU_DPRSTP_L
OUT
10 59 70
OUT
10 13 70
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP CPU Interface DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
REVISION
C.0.0
R
BRANCH
PAGE
14 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
8 14 22 23
NO STUFF 1
6
5
4
3
2
1
7
6
5
4
3
2
OMIT
U1400
MCP79-TOPO-B
MCP79-TOPO-B
BGA
BGA
(2 OF 11)
BI
MEM_A_DQ
AL8
71 27
BI
MEM_A_DQ
AL9
71 27
BI
MEM_A_DQ
AP9
71 27
BI
MEM_A_DQ
AN9
71 27
BI
MEM_A_DQ
AL6
71 27
BI
MEM_A_DQ
AL7
71 27
BI
MEM_A_DQ
AN6
71 27
BI
MEM_A_DQ
AN7
71 27
BI
MEM_A_DQ
AR6 AR7
BI
MEM_A_DQ
71 27
BI
MEM_A_DQ
AV6
71 27
BI
MEM_A_DQ
AW5
71 27
BI
MEM_A_DQ
AN10
71 27
BI
MEM_A_DQ
AR5
71 27
BI
MEM_A_DQ
AU6
71 27
BI
MEM_A_DQ
AV5
71 27
BI
MEM_A_DQ
AU7
71 27
BI
MEM_A_DQ
AU8
71 27
BI
MEM_A_DQ
AW9
71 27
BI
MEM_A_DQ
AP11 AW6
71 27
BI
MEM_A_DQ
71 27
BI
MEM_A_DQ
AY5
71 27
BI
MEM_A_DQ
AU9
71 27
BI
MEM_A_DQ
AV9
71 27
BI
MEM_A_DQ
AU11
71 27
BI
MEM_A_DQ
AV11
71 27
BI
MEM_A_DQ
AV13
71 27
BI
MEM_A_DQ
AW13
71 27
BI
MEM_A_DQ
AR11
71 27
BI
MEM_A_DQ
AT11
71 27
BI
MEM_A_DQ
AR14 AU13
71 27
C
BI
MEM_A_DQ
71 27
BI
MEM_A_DQ
AR26
71 27
BI
MEM_A_DQ
AU25
71 27
BI
MEM_A_DQ
AT27
71 27
BI
MEM_A_DQ
AU27
71 27
71 27
BI
MEM_A_DQ
AP25
71 27
BI
MEM_A_DQ
AR25
71 27
BI
MEM_A_DQ
AP27
BI
MEM_A_DQ
AR27
BI
MEM_A_DQ
71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27
BI
MEM_A_DQ
AR29
BI
MEM_A_DQ
AP31
BI
MEM_A_DQ
BI
MEM_A_DQ
BI
MEM_A_DQ
BI
MEM_A_DQ
BI
MEM_A_DQ
BI
MEM_A_DQ
AR31 AV27 AN29 AV29 AN31 AU31
BI
MEM_A_DQ
AR33
BI
MEM_A_DQ
AV37
71 27
BI
MEM_A_DQ
AW37
71 27
BI
MEM_A_DQ
AT31
71 27
BI
MEM_A_DQ
AV31
71 27
BI
MEM_A_DQ
AT37
71 27
BI
MEM_A_DQ
AU37
71 27
BI
MEM_A_DQ
AW39
71 27
BI
MEM_A_DQ
AV39
71 27
BI
MEM_A_DQ
AR37
71 27
BI
MEM_A_DQ
AR38
71 27
BI
71 27
71 27 71 27
B
AP29
MEM_A_DQ
AV38
BI
MEM_A_DQ
AW38
71 27
BI
MEM_A_DQ
AR35
71 27
BI
MEM_A_DQ
AP35
71 27
OUT
MEM_A_DM
AN5
71 27
OUT
MEM_A_DM
AU5
71 27
OUT
MEM_A_DM
AR10
71 27
OUT
MEM_A_DM
AN13
71 27
OUT
MEM_A_DM
AN27
71 27
OUT
MEM_A_DM
AW29
71 27
OUT
MEM_A_DM
AV35
71 27
OUT
MEM_A_DM
AR34
MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0 MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0
(3 OF 11)
MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N
MEMORY PARTITION 0
D
71 27
1
OMIT
U1400
AL10
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AT4
AL11
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AT3
AR8
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AV2
AR9
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AV3
AW7
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AR4
AW8
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AR3
AP13
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AU2
AR13
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AU3
AV25
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AY4
AW25
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AY3
AU30
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
BB3
AU29
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
BC3
AT35
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AW4
AU35
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AW3
AU39
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
BA3
AT39
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
BB2
71 28
BI
MEM_B_DQ
BB5
71 28
BI
MEM_B_DQ
BA5
71 28
BI
MEM_B_DQ
BA8
71 28
BI
MEM_B_DQ
BC8 BB4
BI
MEM_B_DQ
OUT
27 71
71 28
BI
MEM_B_DQ
BC4
OUT
27 71
71 28
BI
MEM_B_DQ
BA7
71 28
BI
MEM_B_DQ
AY8
71 28
BI
MEM_B_DQ
BA9
71 28
BI
MEM_B_DQ
BB10
71 28
BI
MEM_B_DQ
BB12
71 28
BI
MEM_B_DQ
AW12
71 28
71 28
MRAS0# MCAS0# MWE0#
MBA0_2 MBA0_1 MBA0_0
MA0_14 MA0_13 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0
AV17
MEM_A_RAS_L
AP17
MEM_A_CAS_L
AR17
MEM_A_WE_L
AP23
MEM_A_BA
AP19
MEM_A_BA
AW17
MEM_A_BA
MEM_A_A
AR23
MEM_A_A
AU15
MEM_A_A
AN23
OUT
27 71
BI
MEM_B_DQ
OUT
27 71
71 28
BI
MEM_B_DQ
BB9
OUT
27 71
71 28
BI
MEM_B_DQ
AY12 BA12
OUT
27 71
OUT
27 71
OUT
27 71
OUT OUT
27 71
AN19
MEM_A_A
OUT
27 71
AV21
MEM_A_A
OUT
27 71
OUT
27 71
AU21
MEM_A_A
OUT
27 71
AP21
MEM_A_A
OUT
27 71
AR21
MEM_A_A
OUT
27 71
AN21
MEM_A_A
OUT
27 71
AV19
MEM_A_A
OUT
27 71
AU19
MEM_A_A
OUT
27 71
AT19
MEM_A_A
OUT
27 71
OUT
27 71
TP_MEM_A_CLK2P
AV33
TP_MEM_A_CLK2N
71 28
BI
MEM_B_DQ
AW32
71 28
BI
MEM_B_DQ
BA35
71 28
BI
MEM_B_DQ
AY36
71 28
BI
MEM_B_DQ
BA32
71 28
BI
MEM_B_DQ
BB32
71 28
BI
MEM_B_DQ
BA34
BI
MEM_B_DQ
AY35
BI
MEM_B_DQ
71 28
MEM_A_A
AW33
BC32
71 28
71 28 71 28 71 28 71 28 71 28 71 28
BC36
BI
MEM_B_DQ
AW36
BI
MEM_B_DQ
BA39
BI
MEM_B_DQ
BI
MEM_B_DQ
BI
MEM_B_DQ
BI
MEM_B_DQ
BI
MEM_B_DQ
BI
MEM_B_DQ
AY40 BA36 BB36 BA38 AY39 BB40
BI
MEM_B_DQ
AW40
BI
MEM_B_DQ
AV42
71 28
BI
MEM_B_DQ
AV41
71 28
BI
MEM_B_DQ
BA40
71 28
BI
MEM_B_DQ
BC40
71 28
BI
MEM_B_DQ
AW42
71 28
BI
MEM_B_DQ
AW41
71 28
BI
MEM_B_DQ
AT40
71 28
BI
MEM_B_DQ
AT41
71 28
BI
MEM_B_DQ
AP41
71 28 71 28
MEMORY CONTROL 0A MCLK0A_2_P MCLK0A_2_N
BI
MEM_B_DQ
71 28
AR22
MEM_A_A
71 28
71 28
71 28
MEM_A_A
AR19
BI
MEM_B_DQ
27 71
AW21
BB8
MCLK0A_1_P MCLK0A_1_N
BA24
MEM_A_CLK_P
OUT
27 71
71 28
BI
MEM_B_DQ
AN40
AY24
MEM_A_CLK_N
OUT
27 71
71 28
BI
71 28
MCLK0A_0_P MCLK0A_0_N
BB20
MEM_A_CLK_P
OUT
27 71
OUT
27 71
MCS0A_1# MCS0A_0# MODT0A_1 MODT0A_0 MCKE0A_1 MCKE0A_0
MEM_A_CLK_N
BC20
AT15
MEM_A_CS_L
AR18
MEM_A_CS_L
MEM_B_DQ
AU40
BI
MEM_B_DQ
AU41
71 28
BI
MEM_B_DQ
AR41
71 28
BI
MEM_B_DQ
AP42
AT5
OUT
27 71
71 28
OUT
MEM_B_DM
OUT
27 71
71 28
OUT
MEM_B_DM
BA2 AY7
71 28
OUT
MEM_B_DM
AP15
MEM_A_ODT
OUT
27 71
71 28
OUT
MEM_B_DM
BA11
AV15
MEM_A_ODT
OUT
27 71
71 28
OUT
MEM_B_DM
BB34 BB38
71 28
OUT
MEM_B_DM
AU23
MEM_A_CKE
OUT
27 71
71 28
OUT
MEM_B_DM
AY43
AT23
MEM_A_CKE
OUT
27 71
71 28
OUT
MEM_B_DM
AR42
A
MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0 MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0
MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N
AT2
MEM_B_DQS_P
BI
28 71
AT1
MEM_B_DQS_N
BI
28 71
AY2
MEM_B_DQS_P
BI
28 71
AY1
MEM_B_DQS_N
BI
28 71
BB6
MEM_B_DQS_P
BI
28 71
BA6
MEM_B_DQS_N
BI
28 71
BA10
MEM_B_DQS_P
BI
28 71
AY11
MEM_B_DQS_N
BI
28 71
BB33
MEM_B_DQS_P
BI
28 71
BA33
MEM_B_DQS_N
BI
28 71
BB37
MEM_B_DQS_P
BI
28 71
BA37
MEM_B_DQS_N
BI
28 71
BA43
MEM_B_DQS_P
BI
28 71
AY42
MEM_B_DQS_N
BI
28 71
AT42
MEM_B_DQS_P
BI
28 71
AT43
MEM_B_DQS_N
BI
28 71
MRAS1# MCAS1# MWE1#
AW16
MEM_B_RAS_L
OUT
28 71
BA15
MEM_B_CAS_L
OUT
28 71
BA16
MEM_B_WE_L
OUT
28 71
MBA1_2 MBA1_1 MBA1_0
BB29
MEM_B_BA
OUT
28 71
BB18
MEM_B_BA
OUT
28 71
BB17
MEM_B_BA
OUT
28 71
MA1_14 MA1_13 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0
BA29
MEM_B_A
OUT
28 71
BA14
MEM_B_A
OUT
28 71
AW28
MEM_B_A
OUT
28 71
BC28
MEM_B_A
OUT
28 71
BA17
MEM_B_A
OUT
28 71
BB28
MEM_B_A
OUT
28 71
AY28
MEM_B_A
OUT
28 71
BA28
MEM_B_A
OUT
28 71
AY27
MEM_B_A
OUT
28 71
BA27
MEM_B_A
OUT
28 71
BA26
MEM_B_A
OUT
28 71
BB26
MEM_B_A
OUT
28 71
BA25
MEM_B_A
OUT
28 71
BB25
MEM_B_A
OUT
28 71
BA18
MEM_B_A
OUT
28 71
MCLK1A_2_P MCLK1A_2_N
BA42
TP_MEM_B_CLK2P
BB42
TP_MEM_B_CLK2N
MCLK1A_1_P MCLK1A_1_N
BB22
MEM_B_CLK_P
OUT
28 71
BA22
MEM_B_CLK_N
OUT
28 71
MCLK1A_0_P MCLK1A_0_N
BA19
MEM_B_CLK_P
OUT
28 71
AY19
MEM_B_CLK_N
OUT
28 71
MCS1A_1# MCS1A_0#
BB14
MEM_B_CS_L
OUT
28 71
BB16
MEM_B_CS_L
OUT
28 71
MODT1A_1 MODT1A_0
BB13
MEM_B_ODT
OUT
28 71
AY15
MEM_B_ODT
OUT
28 71
MCKE1A_1 MCKE1A_0
AY31
MEM_B_CKE
OUT
28 71
BB30
MEM_B_CKE
OUT
28 71
MEMORY PARTITION 1
8
D
C
MEMORY CONTROL 1A
B
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP Memory Interface DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
15 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400 MCP79-TOPO-B BGA
23 23 16 8
TP_MEM_A_CLK5N
AU34
TP_MEM_A_CLK4P
BB24
TP_MEM_A_CLK4N
BC24
TP_MEM_A_CLK3P
BA21
TP_MEM_A_CLK3N
BB21
TP_MEM_A_CS_L
AU17
TP_MEM_A_CS_L
AR15
TP_MEM_A_ODT
AN17
TP_MEM_A_ODT
AN15
TP_MEM_A_CKE
AV23
TP_MEM_A_CKE
AN25
MCLK0B_2_P MCLK0B_2_N MCLK0B_1_P MCLK0B_1_N MCLK0B_0_P MCLK0B_0_N MCS0B_0# MCS0B_1# MODT0B_0 MODT0B_1 MCKE0B_0 MCKE0B_1
MEMORY CONTROL 1B
D
AU33
MEMORY CONTROL 0B
(4 OF 11)
TP_MEM_A_CLK5P
MCLK1B_2_P MCLK1B_2_N
BA41
TP_MEM_B_CLK5P
BB41
TP_MEM_B_CLK5N
MCLK1B_1_P MCLK1B_1_N
AY23
TP_MEM_B_CLK4P
BA23
TP_MEM_B_CLK4N
MCLK1B_0_P MCLK1B_0_N
BA20
TP_MEM_B_CLK3P
AY20
TP_MEM_B_CLK3N
MCS1B_0# MCS1B_1#
BC16
TP_MEM_B_CS_L
BA13
TP_MEM_B_CS_L
MODT1B_0 MODT1B_1
AY16
TP_MEM_B_ODT
BC13
TP_MEM_B_ODT
MCKE1B_0 MCKE1B_1
BA30
TP_MEM_B_CKE
BA31
TP_MEM_B_CKE
MRESET0#
AY32
D
PP1V05_S0_MCP_PLL_CORE
=PP1V8R1V5_S0_MCP_MEM 87 mA (A01)
R1610
1
17 mA
T27
12 mA
U28
19 mA
U27
39 mA
T28
40.2 1% 1/16W
+V_PLL_XREF_XS +V_PLL_DP +V_PLL_CORE +V_VPLL
MCP_MEM_RESET_L
OUT
29
TP or NC for DDR2.
MF-LF 402
R1611
C
2
71 MCP_MEM_COMP_VDD
AN41
71 MCP_MEM_COMP_GND
AM41
MEM_COMP_VDD MEM_COMP_GND
1
40.2 AA22
1% 1/16W MF-LF 402
AP12 2
G30 P10 T10 T6 V10 V34 W5 AA39 AB22 AB7 AD22 AE20 AF24 AG24 AH35 AK7 AM28 AT25 AP30 AR36 AU10 F28 BC21 AY9
B
BC9 D34 F24 G32 H31 K7 M38 M5 M6 M7 M9 N39 N8 P33 P34 P37 P4 P40 P7 R36 R40 R43 R5 T18 T20 AK11
A
T24 T26
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54
=PP1V8R1V5_S0_MCP_MEM
+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8 +VDD_MEM9 +VDD_MEM10 +VDD_MEM11 +VDD_MEM12 +VDD_MEM13 +VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20 +VDD_MEM21 +VDD_MEM22 +VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26 +VDD_MEM27 +VDD_MEM28 +VDD_MEM29 +VDD_MEM30 +VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34 +VDD_MEM35 +VDD_MEM36 +VDD_MEM37 +VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41 +VDD_MEM42 +VDD_MEM43 +VDD_MEM44 +VDD_MEM45 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64
AM17
8 16 23
4771 mA (A01, DDR3)
AM19
C
AM21 AM23 AM25 AM27 AM29 AN16 BC29 AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29
B
AV24 AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AY26 AW19 AW24 BC25 AL30 AM31
T33 T34 T35 T37 T38 T7 T9 U18 U20
SYNC_MASTER=K24_MLB U22
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP Memory Misc DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
C.0.0
7
BRANCH
PAGE
16 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400 MCP79-TOPO-B BGA (5 OF 11)
IN
=PEG_D2R_P
F7
9
IN
=PEG_D2R_N
E7
9
IN
=PEG_D2R_P
D7
9
IN
=PEG_D2R_N
C7
9
IN
=PEG_D2R_P
E6
9
IN
=PEG_D2R_N
F6
IN
=PEG_D2R_P
E5
9
IN
=PEG_D2R_N
F5
9
IN
=PEG_D2R_P
E4
9
IN
=PEG_D2R_N
E3
9
IN
=PEG_D2R_P
C3
9
IN
=PEG_D2R_N
D3
9
IN
=PEG_D2R_P
G5
9
IN
=PEG_D2R_N
H5
9
IN
=PEG_D2R_P
J7
9
IN
=PEG_D2R_N
J6
9
IN
=PEG_D2R_P
J5 J4
9
D
IN
=PEG_D2R_N
9
IN
=PEG_D2R_P
L11
9
IN
=PEG_D2R_N
L10
9
IN
=PEG_D2R_P
L9
9
IN
=PEG_D2R_N
L8
9
IN
=PEG_D2R_P
L7
9
IN
=PEG_D2R_N
L6
9
IN
=PEG_D2R_P
N11
9
9
IN
=PEG_D2R_N
N10
9
IN
=PEG_D2R_P
N9
9
IN
=PEG_D2R_N
P9 N7
IN
=PEG_D2R_P
9
IN
=PEG_D2R_N
N6
9
IN
=PEG_D2R_P
N5
IN
=PEG_D2R_N
N4
9
9
C
PE0_RX0_P PE0_RX0_N PE0_RX1_P PE0_RX1_N PE0_RX2_P PE0_RX2_N PE0_RX3_P PE0_RX3_N PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE0_RX6_P PE0_RX6_N PE0_RX7_P PE0_RX7_N PE0_RX8_P PE0_RX8_N PE0_RX9_P PE0_RX9_N PE0_RX10_P PE0_RX10_N PE0_RX11_P PE0_RX11_N PE0_RX12_P PE0_RX12_N PE0_RX13_P PE0_RX13_N PE0_RX14_P PE0_RX14_N PE0_RX15_P PE0_RX15_N
=PEG_R2D_C_P
OUT
9
D4
=PEG_R2D_C_N
OUT
9
C4
=PEG_R2D_C_P
OUT
9
B4
=PEG_R2D_C_N
OUT
9
A4
=PEG_R2D_C_P
OUT
9
A3
=PEG_R2D_C_N
OUT
9
B3
=PEG_R2D_C_P
OUT
9
B2
=PEG_R2D_C_N
OUT
9
C1
=PEG_R2D_C_P
OUT
9
D1
=PEG_R2D_C_N
OUT
9
D2
=PEG_R2D_C_P
OUT
9
E1
=PEG_R2D_C_N
OUT
9
E2
=PEG_R2D_C_P
OUT
9
F2
=PEG_R2D_C_N
OUT
9
F3
=PEG_R2D_C_P
OUT
9
F4
=PEG_R2D_C_N
OUT
9
G3
=PEG_R2D_C_P
OUT
9
H4
=PEG_R2D_C_N
OUT
9
H3
=PEG_R2D_C_P
OUT
9
H2
=PEG_R2D_C_N
OUT
9
H1
=PEG_R2D_C_P
OUT
9
J1
=PEG_R2D_C_N
OUT
9
J2
=PEG_R2D_C_P
OUT
9
J3
=PEG_R2D_C_N
OUT
9
K2
=PEG_R2D_C_P
OUT
9
K3
=PEG_R2D_C_N
OUT
9
L4
=PEG_R2D_C_P
OUT
9
L3
=PEG_R2D_C_N
OUT
9
M4
=PEG_R2D_C_P
OUT
9
M3
=PEG_R2D_C_N
OUT
9
M2
=PEG_R2D_C_P
OUT
9
M1
=PEG_R2D_C_N
OUT
9
PE0_REFCLK_P PE0_REFCLK_N
E11
PEG_CLK100M_P
OUT
9
D11
PEG_CLK100M_N
OUT
9
PE1_REFCLK_P PE1_REFCLK_N
G11
PCIE_CLK100M_MINI_P
OUT
30 72
F11
PCIE_CLK100M_MINI_N
OUT
30 72
PE2_REFCLK_P PE2_REFCLK_N
J11
PCIE_CLK100M_FW_P
OUT
9
J10
PCIE_CLK100M_FW_N
OUT
9
PE3_REFCLK_P PE3_REFCLK_N
G13
PCIE_CLK100M_EXCARD_P
OUT
9
F13
PCIE_CLK100M_EXCARD_N
OUT
9
PE4_REFCLK_P PE4_REFCLK_N
J13
TP_PCIE_CLK100M_PE4P
H13
TP_PCIE_CLK100M_PE4N
PE5_REFCLK_P PE5_REFCLK_N
L14
TP_PCIE_CLK100M_PE5P
K14
TP_PCIE_CLK100M_PE5N
PE6_REFCLK_P PE6_REFCLK_N
N14
TP_PCIE_CLK100M_PE6P
M14
TP_PCIE_CLK100M_PE6N
PEX_RST0#
K11
PCIE_RESET_L
OUT
25
PE1_RX0_P PE1_RX0_N
PE1_TX0_P PE1_TX0_N
D8
PCIE_MINI_R2D_C_P
OUT
30 72
C8
PCIE_MINI_R2D_C_N
OUT
30 72
PE1_RX1_P PE1_RX1_N
PE1_TX1_P PE1_TX1_N
B8
PCIE_FW_R2D_C_P
OUT
9 72
A8
PCIE_FW_R2D_C_N
OUT
9 72
PE1_RX2_P PE1_RX2_N
PE1_TX2_P PE1_TX2_N
A7
PCIE_EXCARD_R2D_C_P
OUT
9
B7
PCIE_EXCARD_R2D_C_N
OUT
9
PE1_RX3_P PE1_RX3_N
PE1_TX3_P PE1_TX3_N
B6
TP_PCIE_PE4_R2D_CP
Int PU
PE0_PRSNT_16#
IN
PEG_PRSNT_L
C9
30
IN
MINI_CLKREQ_L
D5
PEB_CLKREQ#/GPIO_49
30
IN
PCIE_MINI_PRSNT_L
D9
PEB_PRSNT#
9
IN
FW_CLKREQ_L
E8
9
IN
PCIE_FW_PRSNT_L
C10
9
IN
EXCARD_CLKREQ_L
M15
PED_CLKREQ#/GPIO_51
9
IN
PCIE_EXCARD_PRSNT_L
B10
PED_PRSNT#
TP_PE4_CLKREQ_L
L16
PEE_CLKREQ#/GPIO_16
TP_PE4_PRSNT_L
L18
PEE_PRSNT#/GPIO_46
AUD_IP_PERIPHERAL_DET
M16
PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47
9
PE0_TX0_P PE0_TX0_N PE0_TX1_P PE0_TX1_N PE0_TX2_P PE0_TX2_N PE0_TX3_P PE0_TX3_N PE0_TX4_P PE0_TX4_N PE0_TX5_P PE0_TX5_N PE0_TX6_P PE0_TX6_N PE0_TX7_P PE0_TX7_N PE0_TX8_P PE0_TX8_N PE0_TX9_P PE0_TX9_N PE0_TX10_P PE0_TX10_N PE0_TX11_P PE0_TX11_N PE0_TX12_P PE0_TX12_N PE0_TX13_P PE0_TX13_N PE0_TX14_P PE0_TX14_N PE0_TX15_P PE0_TX15_N
C5
PCI EXPRESS
9
Int PU
Int PU
Int PU
PEC_CLKREQ#/GPIO_50
PEC_PRSNT#
Int PU
Int PU Int PU
Int PU
D
C
Int PU 54
Int PU
9
OUT
GMUX_JTAG_TCK_L
M18
9
OUT
CARDREADER_RESET
M17
9
IN
GMUX_JTAG_TDO
M19
Int PU Int PU
PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48 Int PU
IN
PCIE_WAKE_L
72 30
IN
PCIE_MINI_D2R_P
K9
72 30
30 7
B
F17
IN
PCIE_MINI_D2R_N
J9
72 9
IN
PCIE_FW_D2R_P
H9
72 9
IN
PCIE_FW_D2R_N
G9
9
IN
PCIE_EXCARD_D2R_P
F9
9
IN
PCIE_EXCARD_D2R_N
E9
TP_PCIE_PE4_D2RP
H7
TP_PCIE_PE4_D2RN
G7
PE_WAKE# Int
PU (S5)
TP_PCIE_PE4_R2D_CN
C6
=PP1V05_S0_MCP_PEX_DVDD0
8
=PP1V05_S0_MCP_PEX_AVDD0 T17
57 mA (A01, DVDD0 & 1)
W19 U17 V19 W16 W17 W18 U16
+DVDD0_PEX1 +DVDD0_PEX2 +DVDD0_PEX3 +DVDD0_PEX4 +DVDD0_PEX5 +DVDD0_PEX6 +DVDD0_PEX7 +DVDD0_PEX8
=PP1V05_S0_MCP_PEX_DVDD1
8
T19 U19
PP1V05_S0_MCP_PLL_PEX
23
T16
+DVDD1_PEX1 +DVDD1_PEX2
A11
Y12
+AVDD1_PEX1 +AVDD1_PEX2 +AVDD1_PEX3
M13
PEX_CLK_COMP
8
206 mA (A01, AVDD0 & 1)
AA12 AB12 M12 P12 R12 N12 T12 U12 AC12 AD12 V12 W12
+V_PLL_PEX
84 mA (A01)
72 MCP_PEX_CLK_COMP
+AVDD0_PEX1 +AVDD0_PEX2 +AVDD0_PEX3 +AVDD0_PEX4 +AVDD0_PEX5 +AVDD0_PEX6 +AVDD0_PEX7 +AVDD0_PEX8 +AVDD0_PEX9 +AVDD0_PEX10 +AVDD0_PEX11 +AVDD0_PEX12 +AVDD0_PEX13
B
=PP1V05_S0_MCP_PEX_AVDD1
8
N13 P13
NO STUFF
A
1
R1710
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
SYNC_MASTER=K24_MLB
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
PAGE TITLE
2.37K 1%
2
SYNC_DATE=04/06/2009
402
DRAWING NUMBER PLACEMENT_NOTE=Place within 12.7mm of U1400
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
C.0.0 BRANCH
PAGE
17 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
7
SIZE
REVISION
R
8
A
MCP PCIe Interfaces
1/16W MF-LF
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400 MCP79-TOPO-B BGA (6 OF 11)
IN
ENET_RXD
C23
74 31
IN
ENET_RXD
B23
74 31
IN
ENET_RXD
E24
74 31
IN
ENET_RXD
A24
74 31
IN
ENET_CLK125M_RXCLK
A23
RGMII_RXC/MII_RXCLK
74 31
IN
ENET_RX_CTRL
C22
RGMII_RXCTL/MII_RXDV
IN
=MCP_MII_RXER
F23
9
IN
=MCP_MII_COL
B26
9
IN
=MCP_MII_CRS
B22
TP_ENET_INTR_L
J22
9
23 18 8
RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3
74 31
=PP3V3_ENET_MCP_RMGT
1
R1810
8 18 23
J24
+3.3V_DUAL_RMGT2
K24
+V_DUAL_RMGT1 +V_DUAL_RMGT2
U23
MII_VREF
E28
MCP_MII_VREF
RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3
B24
ENET_TXD
OUT
31 74
C24
ENET_TXD
OUT
31 74
C25
ENET_TXD
OUT
31 74
D25
ENET_TXD
OUT
31 74
RGMII_TXC/MII_TXCLK RGMII_TXCTL/MII_TXEN
D24
ENET_CLK125M_TXCLK
OUT
31 74
C26
ENET_TX_CTRL
OUT
31 74
RGMII_MDC RGMII_MDIO
D21
ENET_MDC
OUT
31 74
C21
ENET_MDIO
LAN
D
=PP3V3_ENET_MCP_RMGT
+3.3V_DUAL_RMGT1
83 mA (A01)
=PP1V05_ENET_MCP_RMGT
D
8 23
131 mA (A01)
V23
Network Interface Select
MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK RGMII_INTR/GPIO_35
IN
23
Interface
ENET_TXD
RGMII
1
MII
0
NOTE: All Apple products set strap to MII, RGMII products will enable
BI
feature via software.
This
31 74
avoids a leakage issue since
49.9 1/16W MF-LF 402
PP1V05_ENET_MCP_PLL_MAC
23
1%
T23
+V_DUAL_MACPLL
74 MCP_MII_COMP_VDD
C27
74 MCP_MII_COMP_GND
B27
MII_COMP_VDD MII_COMP_GND
5 mA (A01)
RGMII_PWRDWN/GPIO_37
G23
TP_ENET_PWRDWN_L
2
BUF_25MHZ
E23
MCP_CLK25M_BUF0_R
MII_RESET#
J23
ENET_RESET_L
+V_RGB_DAC +V_TV_DAC
J32
103 mA
PP3V3_S0_MCP_DAC
R1811
1
1% MF-LF 402
TP_MCP_RGB_DAC_VREF
C39 B38
2
RGB_DAC_RSET RGB_DAC_VREF
C 9
OUT
MCP_TV_DAC_RSET
E36
9
OUT
MCP_TV_DAC_VREF
A35
TV_DAC_RSET TV_DAC_VREF
=PP3V3_S5_MCP_GPIO
1
9 9
47K
IN
MCP_CLK27M_XTALIN
C38
OUT
MCP_CLK27M_XTALOUT
D38
B
IN
LPCPLUS_GPIO
E16
DP_IG_CA_DET
B15
(See below)
69 68
OUT
LVDS_IG_BKL_PWM
69
OUT
LVDS_IG_BKL_ON
E37
G39
65
TMDS/HDMI
DisplayPort
OUT
LVDS_IG_PANEL_PWR
MCP Signal =MCP_HDMI_TXC_P/N
TMDS_IG_TXC_P/N
DP_IG_ML_P/N
66
OUT
=MCP_HDMI_TXC_P
D35
=MCP_HDMI_TXD_P/N
TMDS_IG_TXD_P/N
DP_IG_ML_P/N
66
OUT
=MCP_HDMI_TXC_N
E35
=MCP_HDMI_TXD_P/N
TMDS_IG_TXD_P/N
DP_IG_ML_P/N 66
OUT
=MCP_HDMI_TXD_P
G35
66
OUT
=MCP_HDMI_TXD_N
F35
66
OUT
=MCP_HDMI_TXD_P
F33
66
OUT
=MCP_HDMI_TXD_N
G33
66
OUT
=MCP_HDMI_TXD_P
J33
66
OUT
=MCP_HDMI_TXD_N
H33
NOTE: 20K pull-down required on DP_HPD_DET.
72 66
OUT
DP_IG_AUX_CH_P
D43
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
72 66
OUT
DP_IG_AUX_CH_N
C43
TMDS_IG_TXD_P/N
DP_IG_ML_P/N
=MCP_HDMI_DDC_CLK
TMDS_IG_DDC_CLK
DP_IG_DDC_CLK
=MCP_HDMI_DDC_DATA
TMDS_IG_DDC_DATA
DP_IG_DDC_DATA
=MCP_HDMI_HPD
TMDS_IG_HPD
DP_IG_HPD
DP_IG_AUX_CH_P/N
TP_DP_IG_AUX_CHP/N
DP_IG_AUX_CH_P/N
XTALIN_TV XTALOUT_TV
IFP interface can 9
IN
=DVI_HPD_GMUX_INT
66
IN
=MCP_HDMI_HPD
be used to provide HDMI or dual-channel TMDS without level-shifters. LVDS:
1
K32
103 mA
2
2
R1861 100K 5% 1/16W MF-LF 402
A31
MCP_DDC_DATA0
RGB_DAC_RED RGB_DAC_GREEN RGB_DAC_BLUE
B39
TP_MCP_RGB_RED
A39
TP_MCP_RGB_GREEN
Okay to float all RGB_DAC signals.
B40
TP_MCP_RGB_BLUE
DDC_CLK0/DDC_DATA0 pull-ups still required.
RGB_DAC_HSYNC RGB_DAC_VSYNC
A40
TP_MCP_RGB_HSYNC
A41
TP_MCP_RGB_VSYNC
TV_DAC_RED TV_DAC_GREEN TV_DAC_BLUE
A36
CRT_IG_R_C_PR
OUT
9
B36
CRT_IG_G_Y_Y
OUT
9
Okay to float all TV_DAC signals.
C36
CRT_IG_B_COMP_PB
OUT
9
Okay to float XTALIN_TV and XTALOUT_TV.
TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45
D36
CRT_IG_HSYNC
OUT
9
C37
CRT_IG_VSYNC
OUT
9
IFPA_TXC_P IFPA_TXC_N
B35
LVDS_IG_A_CLK_P
OUT
65 72
C35
LVDS_IG_A_CLK_N
OUT
65 72
IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N
B32
LVDS_IG_A_DATA_P
OUT
A32
LVDS_IG_A_DATA_N
OUT
7 65 72
D32
LVDS_IG_A_DATA_P
OUT
7 65 72
C32
LVDS_IG_A_DATA_N
OUT
7 65 72
D33
LVDS_IG_A_DATA_P
OUT
7 65 72
C33
LVDS_IG_A_DATA_N
OUT
7 65 72
B34
LVDS_IG_A_DATA_P
OUT
9
C34
LVDS_IG_A_DATA_N
OUT
9
IFPB_TXC_P IFPB_TXC_N
L31
LVDS_IG_B_CLK_P
OUT
9
K31
LVDS_IG_B_CLK_N
OUT
9
IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N
J29
LVDS_IG_B_DATA_P
OUT
9
H29
LVDS_IG_B_DATA_N
OUT
9
L29
LVDS_IG_B_DATA_P
OUT
9
K29
LVDS_IG_B_DATA_N
OUT
9
L30
LVDS_IG_B_DATA_P
OUT
9
K30
LVDS_IG_B_DATA_N
OUT
9
N30
LVDS_IG_B_DATA_P
OUT
9
M30
LVDS_IG_B_DATA_N
OUT
9
DDC_CLK2/GPIO_23 DDC_DATA2/GPIO_24
C30
LVDS_IG_DDC_CLK
OUT
7 65
B30
LVDS_IG_DDC_DATA
DDC_CLK3 DDC_DATA3
D31
=MCP_HDMI_DDC_CLK
E31
=MCP_HDMI_DDC_DATA
IFPAB_RSET IFPAB_VPROBE
E32
MCP_IFPAB_RSET
OUT
24 72
G31
MCP_IFPAB_VPROBE
OUT
24 72
/ Component / Pr
Y
/ Y
Comp / Pb
GPIO_6/FERR*/IGPU_GPIO_6 GPIO_7/NFERR*/IGPU_GPIO_7
LCD_BKL_CTL/GPIO_57 LCD_BKL_ON/GPIO_59 LCD_PANEL_PWR/GPIO_58 HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
NOTE: HDMI port requires level-shifting.
1
5% 1/16W MF-LF
MCP_DDC_CLK0
Power +VDD_IFPx at 1.8V
C31 F31
HPLUG_DET2/GPIO_22 HPLUG_DET3
=PP3V3R1V8_S0_MCP_IFP_VDD
24 8
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
(See below)
DP_AUX_CH0_P DP_AUX_CH0_N
M27
190 mA (A01, 1.8V)
M26
PP3V3_S0_MCP_VPLL
24
16 mA (A01)
8 mA
M28
8 mA
M29
=PP1V05_S0_MCP_HDMI_VDD
24 8
+VDD_IFPA +VDD_IFPB +V_PLL_IFPAB +V_PLL_HDMI
T25
+VDD_HDMI
J31 J30
HDMI_RSET HDMI_VPROBE
FLAT PANEL
BI
F40
=MCP_HDMI_TXD_P/N
R1860
24
206 mA (A01)
8 19 21
C
RGB DAC Disable:
TV DAC Disable:
DDC_CLK0/DDC_DATA0 pull-ups still required.
2
66
Interface Mode
=PP3V3_S0_MCP_GPIO
B31
C
MF-LF
38
OUT
31 74
DDC_CLK0 DDC_DATA0
TV
5% 1/16W 402
32 74
402
RGB ONLY
TP_MCP_RGB_DAC_RSET
DACS
1/16W
R1820
OUT
100K
49.9
20 8
MCP79 requires a S5 pull-up.
7 65 72
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
BI
OUT BI
B
7 65
66 66
95 mA (A01) 72 24
OUT
MCP_HDMI_RSET
72 24
OUT
MCP_HDMI_VPROBE
1
R1850 10K
GPIOs 57-59 (if LCD panel is used):
5% 1/16W MF-LF
In MCP79 these pins have undocumented internal pull-ups (~10K to 3.3V S0).
A
2
402
To ensure pins are low
by default, pull-downs (1K or stronger) must be used.
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP Ethernet & Graphics
=DVI_HPD_GMUX_INT:
DRAWING NUMBER Alias to DVI_HPD for systems using IFP for DVI.
Apple Inc.
Alias to GMUX_INT for systems with GMUX.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
C.0.0
7
BRANCH
PAGE
18 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
D
REVISION
R
Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.
SIZE
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400
21 18 8
=PP3V3_S0_MCP_GPIO
MCP79-TOPO-B BGA
19
(7 OF 11)
73 19
PCI_REQ1_L
V9
OUT
FW_PWR_EN
T3
OUT
AUD_IPHS_SWITCH_EN
U9
19
IN
MCP_RS232_SIN_L
T4
73 13
BI
MCP_DEBUG
AC3
73 13
BI
MCP_DEBUG
AE10
73 13
BI
MCP_DEBUG
AC4
73 13
BI
MCP_DEBUG
AE11 AB3
BI
MCP_DEBUG
73 13
BI
MCP_DEBUG
AC6
73 13
BI
MCP_DEBUG
AB2
BI
MCP_DEBUG
AC7
TP_PCI_AD
AC8
TP_PCI_AD
AA2
TP_PCI_AD
AC9
TP_PCI_AD
AC10
TP_PCI_AD
AC11
TP_PCI_AD
AA1
TP_PCI_AD
AA5
TP_PCI_AD
Y5
TP_PCI_AD
W3
TP_PCI_AD
W6
TP_PCI_AD
W4
TP_PCI_AD
W7
TP_PCI_AD
V3
TP_PCI_AD
W8
TP_PCI_AD
V2
TP_PCI_AD
W9
73 13
73 13
C
TP_PCI_AD
U3
TP_PCI_AD
W11
TP_PCI_AD
U2
TP_PCI_AD
U5
TP_PCI_AD
U1
TP_PCI_AD
U6
TP_PCI_AD
T5
TP_PCI_AD
U7
TP_PCI_INTW_L
P2
TP_PCI_INTX_L
N3
TP_PCI_INTY_L
N2
TP_PCI_INTZ_L
N1
TP_PCI_TRDY_L
38 36
9
38 36
IN
IN
BI
Y3
PM_CLKRUN_L
AD11
FW_PME_L
AE2
TP_LPC_DRQ0_L
AE1
LPC_SERIRQ
AE6
PCI_REQ0# PCI_REQ1#/FANRPM2 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
PCI_GNT0# PCI_GNT1#/FANCTL2 PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS# PCI_GNT4#/GPIO_53/RS232_SOUT# PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_PAR PCI_PERR#/GPIO_43/RS232_DCD# PCI_SERR# PCI_STOP#
PCI
T2
54
19
D
PCI_REQ0_L
73 19 R4
GMUX_JTAG_TMS
OUT
9
U11
GMUX_JTAG_TDI
OUT
9
P3
MCP_RS232_SOUT_L
OUT
19
AA3
TP_PCI_C_BE_L
AA6
TP_PCI_C_BE_L
U39 U4 U8 V16
B
V17 V18 V20 V22 V24 V26 V27 V28 V33 V37 V4 V40 V7 W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22
A
Y24 Y25
8.2K
1
2
R1990
8.2K
1
2
PCI_REQ1_L
R1991 R1992
8.2K
AA11
TP_PCI_C_BE_L
W10
TP_PCI_C_BE_L
AA9
TP_PCI_DEVSEL_L
Y4
TP_PCI_FRAME_L
AA10
TP_PCI_IRDY_L
Y1
TP_PCI_PAR
AB9
TP_PCI_PERR_L
AA7
TP_PCI_SERR_L
Y2
TP_PCI_STOP_L
T1
PM_LATRIGGER_L
OUT
13
R10
MEM_VTT_EN_R
OUT
25
R11
TP_PCI_RESET1_L
R6
TP_PCI_CLK0
19
1
2
8.2K
1
2
19
FW_PWR_EN
R1994
MCP_RS232_SIN_L
8.2K
1
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 402
5%
1/16W
MF-LF
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
Int PU (S5)
PCI_RESET0# PCI_RESET1#
TP_PCI_CLK1
R7
73 PCI_CLK33M_MCP_R
R8
R1910
C
22 5% 1/16W MF-LF 402
PLACEMENT_NOTE=Place close to pin R8
PCI_CLKIN
LPC_FRAME# LPC_PWRDWN#/GPIO_54/EXT_NMI#
PCI_TRDY# PCI_CLKRUN#/GPIO_42
GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 GND81 GND82 GND83 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97
R1989
PCI_REQ0_L
D
2
Int PU
GND
U26
73 19
TP_PCI_GNT1_L
U10
73 PCI_CLK33M_MCP
R9
R1960
22
AD4
LPC_FRAME_R_L
OUT
36 38 73
AE12
LPC_PWRDWN_L
OUT
36 38
LPC_RESET0#
AE5
LPC_RESET_L
OUT
25 73
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
AD3
LPC_AD_R
AD2
LPC_AD_R
AD1
LPC_AD_R
AD5
LPC_AD_R
1
LPC_FRAME_L
2 5%
LPC_CLK0
AE9
GND98 GND99 GND100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND111 GND112 GND113 GND114 GND115 GND116 GND117 GND118 GND119 GND120 GND121 GND122 GND123 GND124 GND125 GND126 GND127 GND128 GND129 GND130
Y26
R1950 R1951
22
1
2
22
1
2
R1952 R1953
22
1
2
22
1
2
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
LPC_AD
BI
LPC_AD
BI
36 38 73
LPC_AD
BI
36 38 73
LPC_AD
BI
LPC_CLK33M_SMC_R
1
U24
MCP_RS232_SOUT_L
TP_PCI_GNT0_L
R3
1
PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#
LPC_DRQ1#/GPIO_19 LPC_DRQ0# Int PU LPC_SERIRQ Int PU
PCI_PME#/GPIO_30
PCI_CLK0 PCI_CLK1 PCI_CLK2
LPC
73 19
OUT
36 38 73
36 38 73
25 73
R1961 10K
Y27
5% 1/16W
AB18
MF-LF 2
H34 AB20
402
Strap for Boot ROM Selection (See HDA_SDOUT)
AB21
B
AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4 AB40 AC22 AC36 AC40 AB33 AC5 AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27 AD28 AD33
SYNC_MASTER=K24_MLB
AD34
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP PCI & LPC DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
19 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400 MCP79-TOPO-B BGA (8 OF 11)
OUT
SATA_HDD_R2D_C_P
AJ7
OUT
SATA_HDD_R2D_C_N
AJ6
72 34
IN
SATA_HDD_D2R_N
AJ5
72 34
IN
SATA_HDD_D2R_P
AJ4
72 34 72 34
External A
SATA_A0_TX_P SATA_A0_TX_N
USB0_P USB0_N
C29
USB_EXTA_P
BI
35 73
D29
USB_EXTA_N
BI
35 73
SATA_A0_RX_N SATA_A0_RX_P
USB1_P USB1_N
C28
USB_MINI_P
BI
9
D28
USB_MINI_N
BI
9
USB2_P USB2_N
A28
USB_EXTD_P
BI
9
B28
USB_EXTD_N
BI
9
USB3_P USB3_N
F29
USB_CAMERA_P
BI
65 73
G29
USB_CAMERA_N
BI
65 73
USB4_P USB4_N
K27
USB_IR_P
BI
9 73
USB_IR_N
BI
9 73
USB_TPAD_P
BI
44 73
USB_TPAD_N
BI
44 73
USB_BT_P
BI
30 73
USB_BT_N
BI
30 73
USB_EXTB_P
BI
35 73
USB_EXTB_N
BI
35 73
USB_EXCARD_P
BI
9
USB_EXCARD_N
BI
9
H25
USB_EXTC_P
BI
9
J25
USB_EXTC_N
BI
9
AirPort (PCIe Mini-Card)
External D
D 72 34
OUT
SATA_ODD_R2D_C_P
72 34
OUT
SATA_ODD_R2D_C_N
72 34 72 34
AJ11 AJ10
IN
SATA_ODD_D2R_N
AJ9
IN
SATA_ODD_D2R_P
AK9
SATA_A1_TX_P SATA_A1_TX_N
D
Camera
SATA_A1_RX_N SATA_A1_RX_P
IR
L27
Geyser Trackpad/Keyboard
AK2
TP_SATA_C_R2D_CN
AJ3
TP_SATA_C_D2RN
AJ2
TP_SATA_C_D2RP
AJ1
TP_SATA_D_R2D_CP
AM4
TP_SATA_D_R2D_CN
AL3
TP_SATA_D_D2RN
AL4
TP_SATA_D_D2RP
AK3
SATA_B0_TX_P SATA_B0_TX_N SATA_B0_RX_N SATA_B0_RX_P
SATA_B1_TX_P SATA_B1_TX_N
J26 J27
Bluetooth
USB6_P USB6_N
SATA USB
TP_SATA_C_R2D_CP
USB5_P USB5_N
SATA_B1_RX_N SATA_B1_RX_P
F27 G27
External B
USB7_P USB7_N
D27 E27
ExpressCard
USB8_P USB8_N
K25 L25
=PP3V3_S5_MCP_GPIO
USB9_P USB9_N
1
1
R2051 8.2K
5%
1/16W
TP_SATA_E_R2D_CP
AN1
TP_SATA_E_R2D_CN
AM1
TP_SATA_E_D2RN
AM2
TP_SATA_E_D2RP
AM3
TP_SATA_F_R2D_CP
AP3
TP_SATA_F_R2D_CN
AP2
TP_SATA_F_D2RN
AN3
TP_SATA_F_D2RP
AN2
SATA_C0_TX_P SATA_C0_TX_N
USB10_P USB10_N
F25 G25
TP_USB_10N
USB11_P USB11_N
K23
USB_CARDREADER_P
BI
9 73
L23
USB_CARDREADER_N
BI
9 73
TP_USB_10P 2
SATA_C1_RX_N SATA_C1_RX_P
1
8.2K
SATA_C0_RX_N SATA_C0_RX_P
SATA_C1_TX_P SATA_C1_TX_N
R2050
1/16W
MF-LF 402
2
R2052
MF-LF 402
C
1
8.2K
5%
5%
1/16W MF-LF
1/16W MF-LF
402
R2053 8.2K
5%
C
8 18
External C
2
402
2
USB_OC0#/GPIO_25 USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO
L21
USB_EXTA_OC_L
IN
35
K21
USB_EXTB_OC_L
IN
35
J21
USB_EXTC_OC_L
IN
H21
EXCARD_OC_L
IN
+V_PLL_USB
L28
PP3V3_S0_MCP_PLL_USB
37
23
19 mA (A01)
USB_RBIAS_GND
A27
73 MCP_USB_RBIAS_GND
1
R2060 TP_MCP_SATALED_L
E12
PP1V05_S0_MCP_PLL_SATA
23
AE16
SATA_LED#
+V_PLL_SATA
84 mA (A01) =PP1V05_S0_MCP_SATA_DVDD0
8
43 mA (A01, DVDD0 & 1)
AF19 AG16 AG17 AG19
+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4
=PP1V05_S0_MCP_SATA_DVDD1
8
B
AH17 AH19
+DVDD1_SATA1 +DVDD1_SATA2
=PP1V05_S0_MCP_SATA_AVDD0
8
127 mA (A01, AVDD0 & 1)
AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13
+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9
=PP1V05_S0_MCP_SATA_AVDD1
8
AN14 AL14 AM13 AM14
72 MCP_SATA_TERMP
1
AE3
+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4 SATA_TERMP
GND131 GND132 GND133 GND134 GND135 GND136 GND137 GND138 GND139 GND140 GND141 GND142 GND143 GND144 GND145 GND146 GND147 GND148 GND149 GND150 GND151 GND152 GND153 GND154 GND155 GND156 GND157 GND158 GND159 GND160
AD35
806 1%
AD37 AD38
1/16W MF-LF 402
2
AE22 AE24 AE39 AE4 AD6 AF16 AF17 AF18
B
AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24
R2010 2.49K 1%
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
1/16W
2
MF-LF 402
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP SATA & USB DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
C.0.0
7
BRANCH
PAGE
20 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400
=PP3V3R1V5_S0_MCP_HDA
MCP79-TOPO-B
8 21 23
7 mA (A01)
BGA (9 OF 11)
+V_DUAL_HDA1 +V_DUAL_HDA2
73 49
HDA_SDIN0
IN
G15
HDA_SDATA_IN0 Int PD
1
K16
R2160 8.2K 5% 1/16W
HDA
D
J16
D
MF-LF 2
402
R2170 22
HDA_SDATA_OUT
73 21 HDA_SDOUT_R
F15
1
2
HDA_SDOUT
OUT
49 73
5%
BIOS Boot Select
1/16W MF-LF
R2171
402
22
TP_MLB_RAM_SIZE
J14
HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK
HDA_BITCLK
73 21 HDA_BIT_CLK_R
E15
1
Int PD
HDA_BIT_CLK
2
OUT
49 73
I/F
HDA_SDOUT
LPC_FRAME#
LPC
0
0
PCI
0
1
SPI0
1
0
SPI1
1
1
5% 1/16W MF-LF 402
R2172 22
TP_MLB_RAM_VENDOR
J15
=PP3V3R1V5_S0_MCP_HDA
23 21 8
HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA
(MXM_OK for MXM systems)
HDA_RESET*
73 21 HDA_RST_R_L
K15
1
2
Int PD
HDA_RST_L
OUT
49 73
5% 1/16W MF-LF
R2173
1
R2110
402
22
HDA_SYNC
49.9
73 21 HDA_SYNC_R
L15
1
HDA_SYNC
2
OUT
49 73
1% 5%
1/16W MF-LF 2
1/16W MF-LF
402
402
73 MCP_HDA_PULLDN_COMP
A15
HDA_PULLDN_COMP
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA
K17
MCP_GPIO_4
L17
AUD_I2C_INT_L
SLP_S3* SLP_RMGT* SLP_S5*
G17
PM_SLP_S3_L
OUT
7 32 36 63 67
J17
PM_SLP_RMGT_L
OUT
9
H17
PM_SLP_S4_L
OUT
7 36 37 63
THERM_DIODE_P THERM_DIODE_N
B11
MCP_THMDIODE_P
OUT
42 76
C11
MCP_THMDIODE_N
OUT
42 76
9 21
IN
R1961 and R2160 selects SPI0 ROM by
21 54
PP1V05_S0_MCP_PLL_NV
23
default, LPC+ debug card pulls
37 mA (A01)
20 mA
AE18
17 mA
AE17
+V_PLL_NV_H +V_PLL_SP_SPREF
LPC_FRAME# high for SPI1 ROM override. NOTE: MCP79 does not support FWH, only LPC ROMs.
PP3V3_G3_RTC
25 22 7
38 37 36 32
R2120
C
1
1
49.9K
IN
R2121
=SPI_CS1_R_L_USE_MLB
L24
1%
1%
L26
GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L
TP_SB_A20GATE
K13
TP_MCP_KBDRSTIN_L
L13
Int PU A20GATE KBRDRSTIN* Int PU SIO_PME* Int PU (S5) EXT_SMI/GPIO_32* Int
1/16W
2
2
MF-LF 402
36
IN
SMC_WAKE_SCI_L
C19
36
IN
SMC_RUNTIME_SCI_L
C18
SM_INTRUDER_L
B20
NOTE: MCP79 rev A01 does not support =PP3V3_S0_MCP
MCP_VID0/GPIO_13 MCP_VID1/GPIO_14 MCP_VID2/GPIO_15
L20
MCP_VID
OUT
21 60
M20
MCP_VID
OUT
21 60
M21
MCP_VID
OUT
21 60
SPKR
C13
MCP_SPKR
SMB_CLK0 SMB_DATA0 SMB_CLK1/MSMB_CLK SMB_DATA1/MSMB_DATA SMB_ALERT*/GPIO_64
L19
SMBUS_MCP_0_CLK
K19
SMBUS_MCP_0_DATA
G21
SMBUS_MCP_1_CLK
F21
SMBUS_MCP_1_DATA
M23
AP_PWR_EN
PU (S5)
1
M25
PM_BATLOW_L
M24
70 59
IN
PM_DPRSLPVR
M22
CPU_DPRSLPVR
36
IN
PM_PWRBTN_L
C16
25
IN
PM_SYSRST_DEBOUNCE_L
D16
PWRBTN* RSTBTN*
Int PU (S5) Int PU
RTC_RST*
1/16W MF-LF
(MGPIO2)
(MGPIO3)
D20
IN
MCP_PS_PWRGD
E20
25
IN
MCP_CPU_VLD
C17
CPU_VLD
13
IN
JTAG_MCP_TDI
E19
13
OUT
JTAG_MCP_TDO
F19
13
IN
JTAG_MCP_TMS
J19
13
IN
JTAG_MCP_TRST_L
J18
13
IN
JTAG_MCP_TCK
G19
JTAG_TDI Int JTAG_TDO JTAG_TMS Int JTAG_TRST* JTAG_TCK
25
IN
MCP_CLK25M_XTALIN
A16
25
OUT
MCP_CLK25M_XTALOUT
B16
25
IN
RTC_CLK32K_XTALIN
A19
25
OUT
RTC_CLK32K_XTALOUT
B19
PU
PU
XTALIN XTALOUT XTALIN_RTC XTALOUT_RTC
FANRPM0/GPIO_60 FANCTL0/GPIO_61 FANRPM1/GPIO_63 FANCTL1/GPIO_62
B12
MEM_EVENT_L
A12
ODD_PWR_EN_L
CPUVDD_EN
D17
D12
SMC_IG_THROTTLE_L
C12
ARB_DETECT
1
1
10K 5% 1/16W MF-LF 402
2
13 39 73
OUT
37
R2181
HDA_SYNC 24 MHz
1
14.31818 MHz
0
10K 13 39 73
BI
39 73
OUT
2
39 73
BI
5%
USER mode: Normal
1/16W MF-LF
SAFE mode: For ROMSIP
402
recovery
SPI Frequency Select
21 30 32
OUT
Connects to SMC for
IN
Frequency
SPI_DO
SPI_CLK
31 MHz
0
0
42 MHz
0
1
25 MHz
1
0
1 MHz
1
1
21 27 28 36 34
OUT
21 37
IN 21
25
OUT
SPI_CS0/GPIO_10 SPI_CLK/GPIO_11 SPI_DI/GPIO_8 SPI_DO/GPIO_9
C14
SPI_CS0_R_L
OUT
38 73
D13
SPI_CLK_R
OUT
38 48 73
NOTE: Straps not provided on this page.
C15
SPI_MISO
IN
38 48 73
B14
SPI_MOSI_R
OUT
38 48 73
SUS_CLK/GPIO_34 BUF_SIO_CLK
B18
PM_CLK32K_SUSCLK_R
OUT
25 73
AE7
TP_MCP_BUF_SIO_CLK
TEST_MODE_EN PKG_TEST
K22
B
MCP_TEST_MODE_EN
L22 1
R2163 10K
R2151
5% 1/16W
5% 1/16W
MF-LF 402
2
R2190 1K
100K
MF-LF 2
OUT
MCP_CPUVDD_EN
1
R2150
Frequency
402
automatic recovery.
PWRGD_SB PS_PWRGD
PM_RSMRST_L
25
BUF_SIO_CLK Frequency
5%
1
Int PU (S5)
IN
36
C
R2180 10K
Int PU (S5)
MISC
C20
Rev B01 will.
BOOT_MODE_USER
TP_MCP_LID_L
IN
RTC_RST_L
B
INTRUDER* LID* LLB*
SPI1 option.
8 22 23
BOOT_MODE_SAFE
2
36
So Apple designs will
not use LPC for BootROM override.
GPIO_1/PWRDN_OK/SPI_CS1
SMC_ADAPTER_EN
49.9K
1/16W MF-LF 402
OUT
1% 1/16W
2
MF-LF 402
402
=PP3V3_S0_MCP_GPIO
8 18 19
=PP3V3_S3_MCP_GPIO
8
HDA Output Caps 1
For EMI Reduction on HDA interface
R2140
1
10K
HDA_SDOUT_R HDA_BIT_CLK_R
A
C2170
1
C2172
10PF 5% 50V CERM
21 73
2
R2141
1
10K
1
R2142 10K
10K
5% 1/16W
5% 1/16W
5% 1/16W
MF-LF
MF-LF
MF-LF
MF-LF
2
402
2
402
2
5% 50V CERM
402
2
C2171
5% 1/16W MF-LF
402
2
MCP_GPIO_4
9 21
21 73
AUD_I2C_INT_L
21 54
HDA_SYNC_R
21 73
MEM_EVENT_L
21 27 28 36
402
SMC_IG_THROTTLE_L
21 37
ARB_DETECT
21
AP_PWR_EN
1
21 30 32
MCP_VID
21 60
MCP_VID
21 60
MCP_VID
21 60
1
1
C2173 10PF
5% 50V CERM
5% 50V CERM
2
2
1
1
R2156
R2157
22K
22K
22K
5%
5%
5%
5%
1/16W MF-LF
1/16W MF-LF
1/16W MF-LF
1/16W MF-LF
2
402
2
402
2
DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
REVISION
C.0.0
R
402
402
7
A
MCP HDA & MISC
R2155
100K
402
SYNC_DATE=03/24/2009
PAGE TITLE
1
R2147
BRANCH
PAGE
21 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
SYNC_MASTER=K24_MLB
2
10PF
402
100K
HDA_RST_R_L
402
1
R2154
21 73
10PF 2
R2143
5% 1/16W 402
1
6
5
4
3
2
1
8
7
6
5
4
OMIT
MCP79-TOPO-B
BGA
BGA
AH37 AH38 AJ39
D
AJ8 AK10 AK33 AK34 AK37 AK4 AK40 AL36 AL40 AL5 AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38 AM5 AM6 AM7 AM9
C
AP26 AN28 AN30 AN39 AN4 Y7 AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37 AP4 AP40 AP7 AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29 AT33
B
AT6 AT7 AT9 AY21 AY22 L12 AU12 AU28 AP33 AU32 AR30 AU36 AU38 AU4 G28 F20 AV28 AV32 AV36 AV4 AV7 AW11 G20 AR43 AW43
A
AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41
23 8
GND253 GND254 GND255 GND256 GND257 GND258 GND259 GND260 GND261 GND262 GND263 GND264 GND265 GND266 GND267 GND268 GND269 GND270 GND271 GND272 GND273 GND274 GND275 GND276 GND277 GND278 GND279 GND280 GND281 GND282 GND283 GND284 GND285 GND286 GND287 GND288 GND289 GND290 GND291 GND292 GND293 GND294 GND295 GND296 GND297 GND298 GND299 GND300 GND301 GND302 GND303 GND304 GND305 GND306 GND307 GND308 GND309 GND310 GND311 GND312 GND313 GND314 GND315 GND316 GND317 GND318 GND319 GND320 GND321 GND322 GND323 GND324 GND325 GND326 GND327 GND328 GND329 GND330 GND331 GND332 GND333 GND334 GND335 GND336 GND337 GND338 GND339 GND340 GND341 GND342 GND343
(10 OF 11)
=PPVCORE_S0_MCP
AV40
23065 mA (A01, 1.2V)
AA25
BA1
16996 mA (A01, 1.0V)
AC23 U25
BA4 AW31
AH12
AY6
AG10
L35
AG5
BC33
Y21
BC37
Y23
BC41
AA16
AY14
AA26
BC5
AA27
C2
AA28
D10
AC16
D14
AC17
D15
AC18
D18
AC19
D19
AC20
D22
AC21
D23
AA17
D26
AC24
D30
AC25
D37
AC26
D6
AC27
E13
AC28
E17
AD21
E21
AD23
E25
W27
E29
V25
E33
AA18
F12
AE19
F16
AE21
F32
AE23
F8
AE25
G10
AE26
G12
AE27
G14
AE28
G16
AF10
BC12
AF11
G22
AA19
G24
AF2
AW20
AF21
G34
AF23
G4
AF25
G43
AF3
G6
AF4
G8
AF7
H11
AH23
H15
AF9
AW35
AA20
H23
AG11
AN8
AG12
G40
AG21
J12
AG23
J8
AG25
K10
AG3
K12
AG4
K18
AA21
K26
AG6
K37
AG7
K4
AG8
K40
AG9
K8
AH1
AU1
AH10
L40
AH11
L43
W26
L5
AH2
M10
AA23
M34
W28
M35
AH25
M37
AH21
Y28
AH3
Y33
AH4
Y34
AH5
Y35
AH6
Y37
AH7
Y38
AH9
AB17
AA24
AB16
W21
AN26
W23
AD7
W25 AF12
M11
+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6 +VDD_CORE7 +VDD_CORE8 +VDD_CORE9 +VDD_CORE10 +VDD_CORE11 +VDD_CORE12 +VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19 +VDD_CORE20 +VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30 +VDD_CORE31 +VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37 +VDD_CORE38 +VDD_CORE39 +VDD_CORE40 +VDD_CORE41 +VDD_CORE42 +VDD_CORE43 +VDD_CORE44 +VDD_CORE45 +VDD_CORE46 +VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54 +VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81
POWER
AH34
GND
(11 OF 11)
GND161 GND162 GND163 GND164 GND165 GND166 GND167 GND168 GND169 GND170 GND171 GND172 GND173 GND174 GND175 GND176 GND177 GND178 GND179 GND180 GND181 GND182 GND183 GND184 GND185 GND186 GND187 GND188 GND189 GND190 GND191 GND192 GND193 GND194 GND195 GND196 GND197 GND198 GND199 GND200 GND201 GND202 GND203 GND204 GND205 GND206 GND207 GND208 GND209 GND210 GND211 GND212 GND213 GND214 GND215 GND216 GND217 GND218 GND219 GND220 GND221 GND222 GND223 GND224 GND225 GND226 GND227 GND228 GND229 GND230 GND231 GND232 GND233 GND234 GND235 GND236 GND237 GND238 GND239 GND240 GND241 GND242 GND243 GND244 GND245 GND246 GND247 GND248 GND249 GND250 GND251 GND252
1
U1400
MCP79-TOPO-B
AH33
2
OMIT
U1400
AH26
3
=PP1V05_S0_MCP_FSB
+VTT_CPU1 +VTT_CPU2 +VTT_CPU3 +VTT_CPU4 +VTT_CPU5 +VTT_CPU6 +VTT_CPU7 +VTT_CPU8 +VTT_CPU9 +VTT_CPU10 +VTT_CPU11 +VTT_CPU12 +VTT_CPU13 +VTT_CPU14 +VTT_CPU15 +VTT_CPU16 +VTT_CPU17 +VTT_CPU18 +VTT_CPU19 +VTT_CPU20 +VTT_CPU21 +VTT_CPU22 +VTT_CPU23 +VTT_CPU24 +VTT_CPU25 +VTT_CPU26 +VTT_CPU27 +VTT_CPU28 +VTT_CPU29 +VTT_CPU30 +VTT_CPU31 +VTT_CPU32 +VTT_CPU33 +VTT_CPU34 +VTT_CPU35 +VTT_CPU36 +VTT_CPU37 +VTT_CPU38 +VTT_CPU39 +VTT_CPU40 +VTT_CPU41 +VTT_CPU42 +VTT_CPU43 +VTT_CPU44 +VTT_CPU45 +VTT_CPU46 +VTT_CPU47 +VTT_CPU48 +VTT_CPU49 +VTT_CPU50 +VTT_CPU51 +VTT_CPU52
R32
1139 mA
8 14 23
1182 mA (A01)
AC32 E40 J36 N32 T32
D
U32 V32 W32 P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32 B41 B42 C40 C41 C42 D39 D40 D41 E38 E39 F37 F38 F39
C
G36 G37 G38 H35 H37 J34 J35 K33 K34 K35 L32 L33 L34 M31 M32 M33 N31 P32 Y32 AA32
+VTT_CPUCLK
AG32
+3.3V_1 +3.3V_2 +3.3V_3 +3.3V_4 +3.3V_5 +3.3V_6 +3.3V_7 +3.3V_8
AD10
43 mA
=PP3V3_S0_MCP
8 21 23
450 mA (A01)
B
AE8 AB10 AD9 Y10 AB11 AA8 Y9
=PP3V3_S5_MCP
+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4
G18
+3.3V_DUAL_USB1 +3.3V_DUAL_USB2 +3.3V_DUAL_USB3 +3.3V_DUAL_USB4
G26
+VDD_AUXC1 +VDD_AUXC2 +VDD_AUXC3
T21
16 mA
8 23
266 mA (A01)
H19 J20 K20
250 mA
H27 J28 K28
=PP1V05_S5_MCP_VDD_AUXC
8 23
AA4 AB19
25 21 7
PP3V3_G3_RTC
AY13
10 uA (G3)
P11
80 uA (S0)
A20
+VBAT
105 mA (A01)
U21 V21
Y6
SYNC_MASTER=K24_MLB
T11
PAGE TITLE
SYNC_DATE=04/06/2009
Y11
DRAWING NUMBER
AH16
Apple Inc.
T22
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
C.0.0 BRANCH
PAGE
22 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
7
SIZE
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
8
A
MCP Power & Ground
V11
6
5
4
3
2
1
8
7
MCP Core Power 22 8
6
5
4
3
2
1
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
=PPVCORE_S0_MCP 23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
C2500 (No IG vs. EG data)
D
1
C2501
1
C2502
1
C2503
4.7UF
4.7UF
4.7UF
4.7UF
20% 4V X5R-1 402
20% 4V X5R-1 402
20% 4V X5R-1 402
20% 4V X5R-1 402
2
2
2
1
1
2
2
1
C2504
1
C2506
1
C2507
1
C2508
C2509
1
1
C2510
1
C2511
C2512
1UF
1UF
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10% 10V X5R 402-1
10% 10V X5R 402-1
10% 10V X5R 402-1
10% 10V X5R 402-1
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
2
MCP PCIE (DVDD) Power 8
1
C2505
1UF
2
2
2
2
2
2
2
1
C2513 0.1UF
2
20% 10V CERM 402
MCP SATA (DVDD) Power
=PP1V05_S0_MCP_PEX_DVDD 57 mA (A01)
8
43 mA (A01)
333 mA (A01)
Apple: 5x 2.2uF 0402 (11 uF)
30-OHM-5A
=PP1V05_S0_MCP_AVDD_UF
D
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
L2570
=PP1V05_S0_MCP_SATA_DVDD
8
1
PP1V05_S0_MCP_PEX_AVDD
8
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
206 mA (A01)
0603
C2515
1
1
2
2
C2516
4.7UF 20% 4V X5R-1 402
1
1UF
1
C2517 1UF
10% 10V X5R 402-1
2
1
C2518 0.1uF
10% 10V X5R 402-1
2
C2519
C2520
0.1uF
20% 10V CERM 402
2
1
1
2
2
4.7UF
20% 10V CERM 402
20% 4V X5R-1 402
1
C2521 0.1uF
1
C2570
C2571
2.2UF
20% 10V CERM 402
2
1
2.2UF
20% 6.3V CERM 402-LF
C2572 2.2UF
20% 6.3V CERM 402-LF
2
1
2
1
C2573 2.2UF
20% 6.3V CERM 402-LF
2
C2574 2.2UF
20% 6.3V CERM 402-LF
2
20% 6.3V CERM 402-LF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) MCP 1.05V AUX Power 22 8
MCP 1.05V RMGT Power
=PP1V05_S5_MCP_VDD_AUXC
18 8
105 mA (A01)
L2575
Apple: 2x 2.2uF 0402 (4.4 uF)
30-OHM-5A
=PP1V05_ENET_MCP_RMGT
PP1V05_S0_MCP_SATA_AVDD
1
131 mA (A01)
8
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
127 mA (A01)
0603
1
2
MCP FSB (VTT) Power 22 14 8
1
C2525
C2526
0.1uF
0.1uF
20% 10V CERM 402
20% 10V CERM 402
2
C2528
1
1
4.7UF 20% 4V X5R-1 402
2
2
1
C2529
2.2UF
20% 10V CERM 402
20% 6.3V CERM 402-LF
2
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
C2576 2.2UF 20% 6.3V CERM 402-LF
2
L2580
Apple: 7x 2.2uF 0402 (15.4 uF)
=PP1V05_S0_MCP_FSB
1
C2575
0.1uF
62 8
1182 mA (A01)
30-OHM-1.7A
=PP1V05_S0_MCP_PLL_UF 562 mA (A01)
PP1V05_S0_MCP_PLL_FSB
1
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
14
270 mA (A01)
0402
C
1
2
1
C2530
1
C2531
C2532
1
C2533
1
C2534
1
1
C2535
C2536
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
2
2
2
2
2
2
C2580
1
1
2
2
4.7UF
10UF 20% 6.3V X5R
2
603
MCP Memory Power 16 8
1
C2592
20% 4V X5R-1 402
C
C2581 0.1UF 20% 10V CERM 402
L2582 30-OHM-1.7A
=PP1V8R1V5_S0_MCP_MEM 1
4771 mA (A01, DDR3)
PP1V05_S0_MCP_PLL_PEX
17
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
84 mA (A01)
0402
C2540
1
1
20% 4V X5R-1 402
2
1
C2541
4.7UF 2
1
C2545
1
C2549
C2582
0.1UF
0.1UF
0.1UF
0.1UF
4.7UF
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
2
2
C2547
1
0.1UF
20% 10V CERM 402
2
C2546
1
0.1UF
20% 10V CERM 402
2
C2544
1
0.1UF
20% 10V CERM 402
2
C2543
1
0.1UF
20% 10V CERM 402
2
C2542
1
0.1UF
C2548
2
2
20% 4V X5R-1 402
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) MCP 3.3V Power 22 21 8
=PP3V3_S0_MCP
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
L2555
Apple: 4x 2.2uF 0402 (8.8 uF)
450 mA (A01)
1
19 mA (A01)
2
2
C2583 0.1UF
30-OHM-1.7A
PP3V3_S0_MCP_PLL_USB
20
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
2
1
20% 10V CERM 402
L2584
Apple: 1x 2.2uF 0402 (2.2 uF)
30-OHM-1.7A
=PP3V3_S0_MCP_PLL_UF
8
1
1
PP1V05_S0_MCP_PLL_SATA
20
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
19 mA (A01)
84 mA (A01)
0402
0402
1
2
1
C2550
1
C2551
C2552
1
1
C2553
2.2UF
2.2UF
2.2UF
2.2UF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
2
2
2
2
C2584
C2555
2.2UF
1
1
2
2
4.7UF 20% 4V X5R-1 402
C2585 0.1UF 20% 10V CERM 402
B
B L2586 MCP 3.3V AUX/USB Power 22 8
=PP3V3_S5_MCP
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
MCP 3.3V Ethernet Power
Apple: 1x 2.2uF 0402 (2.2 uF) 23 18 8
266 mA (A01)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
30-OHM-1.7A
Apple: 1x 2.2uF 0402 (2.2 uF)
=PP3V3_ENET_MCP_RMGT
1
1
2
PP1V05_S0_MCP_PLL_CORE
16
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
87 mA (A01)
0402
83 mA (A01) 1
C2560
C2564
C2586
2.2UF
2.2UF
4.7UF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
2
20% 4V X5R-1 402
1
1
2
2
C2587 0.1UF 20% 10V CERM 402
L2588 MCP 3.3V/1.5V HDA Power 21 8
=PP3V3R1V5_S0_MCP_HDA
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
30-OHM-1.7A
Apple: 1x 2.2uF 0402 (2.2 uF)
1
PP1V05_S0_MCP_PLL_NV
21
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
37 mA (A01)
0402
7 mA (A01) 1
C2562
C2588
2.2UF 2
1
1
4.7UF
MCP79 Ethernet VRef
20% 6.3V CERM 402-LF
23 18 8
20% 4V X5R-1 402
C2589
1
0.1UF 2
2
20% 10V CERM 402
C2590 0.1UF
2
20% 10V CERM 402
=PP3V3_ENET_MCP_RMGT
R2591
1
1.47K 1% 1/16W MF-LF 402
A L2595 8
5 mA (A01)
SYNC_MASTER=K24_MLB
2
PP1V05_ENET_MCP_PLL_MAC
1
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
MCP_MII_VREF
18
R2590 C2595
1
1
4.7UF 20% 4V X5R-1 402
C2596
A
2
MCP Standard Decoupling
18
DRAWING NUMBER
1 1
1.47K 1% 1/16W MF-LF 402
0.1UF 2
OUT
5 mA (A01)
0402
20% 10V CERM 402
C2591
Apple Inc.
0.1UF 20% 10V 2
2
7
051-7982
CERM 402
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
REVISION
C.0.0
R
BRANCH
PAGE
25 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
SYNC_DATE=04/06/2009
PAGE TITLE
30-OHM-1.7A
=PP1V05_ENET_MCP_PLL_MAC
6
5
4
3
2
1
8
7
6
5
4
3
2
1
WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) NO STUFF Apple: 1x 2.2uF 0402 (2.2 uF) 18 8
8
190 mA (A01, 1.8V)
C2610
1
D
PP3V3_S0_MCP_DAC
0402
NO STUFF 1
20% 6.3V CERM 402-LF
1
C2650 20% 6.3V CERM 402-LF
206 mA (A01)
R2651 0
2.2UF 2
18 8
18
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
2
2.2UF 2
Apple: 2x 2.2uF 0402 (4.4 uF)
30-OHM-1.7A
=PP3V3_S0_MCP_DAC_UF 206 mA (A01)
1
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
L2650
=PP3V3R1V8_S0_MCP_IFP_VDD
5% 1/16W
D
MF-LF
2
402
=PP1V05_S0_MCP_HDMI_VDD 95 mA (A01)
C2615
1
1
2
2
C2616
4.7UF 20% 4V X5R-1 402
72 18
MCP_HDMI_RSET
72 18
MCP_HDMI_VPROBE
C
1
NO STUFF
C2620
0.1UF
1
72 18
MCP_IFPAB_RSET
72 18
MCP_IFPAB_VPROBE
20% 10V 2
2
NO STUFF
R2620
NO STUFF
1K
C2630
1% 1/16W
0.1UF CERM 402
20% 10V CERM 402
1 1
CERM 402
C
1% 1/16W
20% 10V
MF-LF 402
R2630 1K
0.1UF 2
2
MF-LF 402
WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640 8
16 mA (A01)
Apple: ???
30-OHM-1.7A
=PP3V3_S0_MCP_VPLL_UF 1
PP3V3_S0_MCP_VPLL MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
2
18
16 mA (A01)
0402
C2640
1
1
2
2
4.7UF 20% 6.3V CERM 603
C2641 0.1uF 20% 10V CERM 402
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP Graphics Support
SYNC FROM T18 REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672 NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650) CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC REMOVE HDCP ROMS
DRAWING NUMBER
Apple Inc. NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
7
SIZE
D
REVISION
C.0.0
R
BRANCH
PAGE
26 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
051-7982
6
5
4
3
2
1
8
7
6
5
4
3
2
1
Platform Reset Connections LPC Reset (Unbuffered) R2820 0 8 =PP3V42_G3H_RTC_D
1
D
PP3V3_G3_RTC
2 5% 1/16W MF-LF 402
R2881
7 21 22
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
33
PLACEMENT_NOTE=Place close to U1400
73 19
LPC_RESET_L
IN
1
1
10%
38
2
SMC_LRESET_L
OUT
36
2
BKLT_PLT_RST_L
OUT
69
MINI_RESET_L
OUT
30
PCA9557D_RESET_L
OUT
26
D
33 1 5% 1/16W MF-LF 402
PLACEMENT_NOTE=Place close to U1400
2
CERM 402
OUT
R2883
1UF 6.3V
DEBUG_RESET_L
2 5% 1/16W MF-LF 402
C2819
PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79
PLACE C2819 CLOSE TO MCP79
PCIE Reset (Unbuffered) R2892 0 17
PCIE_RESET_L
IN
1 5% 1/16W MF-LF 402
R2891 0 1
RTC Crystal
2 5% 1/16W MF-LF 402
C2810
R2871 0 1
12pF 21
IN
1
RTC_CLK32K_XTALOUT
R2810
1
C
C
2
RTC_CLK32K_XTALOUT_R
NO STUFF 1
4
CRITICAL
10M 5% 1/16W MF-LF 402
21
OUT
Y2810 32.768K 2
C2811 1
R2811
5% 1/16W MF-LF 402
5% 50V CERM 402
0 5% 1/16W MF-LF 402
7X1.5X1.4-SM
12pF 1
RTC_CLK32K_XTALIN
2
5% 50V CERM 402
MCP 25MHz Crystal
C2815
R2870
12pF 21
IN
1
MCP_CLK25M_XTALOUT
R2815
1
1
R2816
MEM_VTT_EN_R
1
4
2
2
Y2815
OUT
58 64
LPC_CLK33M_SMC
OUT
36 73
LPC_CLK33M_LPCPLUS
OUT
38 73
PM_CLK32K_SUSCLK
OUT
36 73
33
PLACEMENT_NOTE=Place close to U1400
LPC_CLK33M_SMC_R
1
2 5% 1/16W MF-LF 402
NC NC
R2826 33 1
1
C2816
PLACEMENT_NOTE=Place close to U1400
12pF 1
MCP_CLK25M_XTALIN
2
5% 50V CERM 402
MCP S0 PWRGD & CPU_VLD
2 5% 1/16W MF-LF 402
B
R2829 22 73 21
IN
PM_CLK32K_SUSCLK_R
1 PLACEMENT_NOTE=Place close to U1400
8
=DDRVTT_EN
R2825 IN
3
CRITICAL
MEM_VTT_EN MAKE_BASE=TRUE
2 5% 1/16W MF-LF 402
73 19
25.0000M
B
IN
MCP_CLK25M_XTALOUT_R
SM-3.2X2.5MM
OUT
19
2
1M
21
33
2
5% 50V CERM 402
0 5% 1/16W MF-LF 402
NO STUFF
5% 1/16W MF-LF 402
2
2
=PP3V3_S5_MCPPWRGD
2 5% 1/16W MF-LF 402
MCPSEQ_SMC 1
C2850 0.1UF
2
20% 10V CERM 402
Reset Button 36
IN
PM_SYSRST_L
MCPSEQ_SMC 5 TC7SZ08AFEAPE 63 36
IN
ALL_SYS_PWRGD
2
U2850 59
IN
VR_PWRGOOD_DELAY
1
Y
4
XDP
R2853
SOT665
A
R2898
0 S0_AND_IMVP_PGOOD
1
OUT
21
13 10
IN
XDP_DBRESET_L
1
5% 1/16W MF-LF 402
B 3
33 2
5% 1/16W MF-LF 402
1
R2890
R2852
1
NO STUFF
PM_SYSRST_DEBOUNCE_L
2
OUT
21
NO STUFF
5% 1/16W MF-LF
0 5% 1/16W MF-LF 402
MCPSEQ_MIX
10K pull-up to 3.3V S0 inside MCP
R2899
0 MCP_PS_PWRGD
2
1
402
C2899 1UF 10% 10V
SILK_PART=SYS RST
2
2
X5R 402
0 1
2
5% 1/16W MF-LF 402
MCPSEQ_MIX
R2851 0 1
A
MCP_CPU_VLD
2
5% 1/16W MF-LF 402
OUT
21
MCPSEQ_SMC
R2850 0
21
IN
MCP_CPUVDD_EN
1
2
SYNC_MASTER=K24_MLB PLACEMENT_NOTE=Place close to U1400
5% 1/16W MF-LF 402
SYNC FROM T18 CHANGE RESET BUTTOM TO RESET PADS REMOVE UNUSED PCIE RESET SIGNALS REMOVE R2824 AND NET PCI_CLK33M_SLOT_A CHANGE RTC COIN CELL TO LDO & SUPERCAP ALIAS MEM_VTT_EN TO =DDRVTT_EN CHANGE Y2810 AND U2850 TO SMALLER PARTS
MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections, but results in MCP79 ROMSIP sequence happening after CPU powers up. MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization. SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).
7
A
SB Misc DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
REVISION
C.0.0
R
BRANCH
PAGE
28 OF 109 SHEET
OF
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
8
SYNC_DATE=02/15/2009
PAGE TITLE
6
5
4
3
2
1
8
7
6
5
4
3
2
1
Page Notes MEM A VREF DQ
Power aliases required by this page:
MEM A VREF CA
MEM B VREF DQ
MEM B VREF CA
CPU FSB VREF
- =PP3V3_S3_VREFMRGN
DAC channel
A
B
A
B
C
- =PP3V3_S5_VREFMRGN
Min DAC code
0x00
0x00
0x00
0x00
0x00
- =PPVTT_S3_DDR_BUF
Max DAC code Signal aliases required by this page:
Max sink I
- =I2C_VREFDACS_SCL
0x87
0x87
0x87
0x87
0x55
-3.75 mA
-3.75 mA
-3.75 mA
-3.75 mA
-0.91 mA
Max source I
5 mA
5 mA
5 mA
5 mA
- =I2C_VREFDACS_SDA
Nominal Vref
0.75 V
0.75 V
0.75 V
0.75 V
0.70 V
- =I2C_PCA9557D_SCL
Min Vref
0.375 V
0.375 V
0.375 V
0.375 V
0.091 V
- =I2C_PCA9557D_SDA
Max Vref
1.250 V
1.250 V
1.250 V
1.250 V
Vref Stepping
6.5 mV
6.5 mV
6.5 mV
6.5 mV
SO-DIMM A and SO-DIMM B Vref settings should be margined separately
0.52 mA
(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
1.044 V
=PPVTT_S3_DDR_BUF 58 8
D
D
11.2 mV
BOM options provided by this page:
10mA max load
(per DAC LSB) VREFMRGN NO_VREFMRGN
R2903
VREFMRGN
200 1
B1
VREFMRGN 1
A2
C2903
V+
0.1UF 2
=PP3V3_S3_VREFMRGN 8
U2902
A3
UCSP A1
1
VREFMRGN_DQ_SODIMMA_BUF
26 VREFMRGN_DQ_SODIMMA_EN
0.1UF 20% 10V CERM 402 B1 C2
V+
VREFMRGN C3
VDD
39
IN
=I2C_VREFDACS_SCL
6 SCL
BI
=I2C_VREFDACS_SDA
7 SDA 9 A0
ADDR=0x98(WR)/0x99(RD)
C
VOUTA
1
VREFMRGN_DQ_SODIMM
VOUTB
2
VREFMRGN_CA_SODIMM
VOUTC
4
VREFMRGN_CPUFSB
VOUTD
5
1
VREFMRGN_DQ_SODIMMB_BUF
5% 1/16W MF-LF 402 B1
VREFMRGN 1
GND 3
A2
C2904
V+
0.1UF 2
A3
1
1
VREFMRGN_CA_SODIMMA_BUF
U2903
2 1
UCSP C1
1
VREFMRGN_CA_SODIMMB_BUF
26 VREFMRGN_CA_SODIMMB_EN
B1
2
U2904
A3
2
Place close to J3200.126
1
VREFMRGN
MAX4253 UCSP A1
VREFMRGN
20% 10V CERM 402
5% 1/16W MF-LF 402
2 1% 1/16W MF-LF 402
C4
V+
28 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
100
V-
A2
0.1UF
PP0V75_S3_MEM_VREFCA_B
R2912
100K
C2905
2
1% 1/16W MF-LF 402
MAX4253
R2908
VREFMRGN
200
VREFMRGN
VREFMRGN
B4
1
Place close to J3100.126
R2911 1
100K 5% 1/16W MF-LF 402
2 1% 1/16W MF-LF 402
26 VREFMRGN_CA_SODIMMA_EN
VREFMRGN
27 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
100
A1
R2907
C3
C
PP0V75_S3_MEM_VREFCA_A
R2910
UCSP
B4
B1
2 1% 1/16W MF-LF 402
A4
V+
VREFMRGN
200
MAX4253
V-
C2
Place close to J3200.1
R2909 VREFMRGN
U2903
VREFMRGN
20% 10V CERM 402
2 1% 1/16W MF-LF 402
26 VREFMRGN_DQ_SODIMMB_EN
R2902
NC
28 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
100
C1 C4
V-
100K
10 A1
PP0V75_S3_MEM_VREFDQ_B
R2906
UCSP
B4
MSOP
DAC5574
39
1% 1/16W MF-LF 402
MAX4253
VREFMRGN
U2900
8
5% 1/16W MF-LF 402
U2902
2
VREFMRGN
1
2
VREFMRGN
200 1
100K
2
20% 6.3V CERM 402-LF
Place close to J3100.1
R2905
2
R2901
C2901
1
1
2.2UF
2 1% 1/16W MF-LF 402
A4
V-
VREFMRGN
C2900
27 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
100
B4
VREFMRGN
PP0V75_S3_MEM_VREFDQ_A
R2904
MAX4253
VREFMRGN
20% 10V CERM 402
2 1% 1/16W MF-LF 402
NC
A4
VB4
B
B B1 C2
VREFMRGN
V+
2
C3
U2901 QFN
4 5
39 39
IN BI
=I2C_PCA9557D_SCL
1
=I2C_PCA9557D_SDA
2
A0 A1 A2
SCL SDA THRM 17
PAD
26 VREFMRGN_CPUFSB_EN
RESET*
6
NC
7
R2913
VREFMRGN_CPUFSB_EN 26
100K
VREFMRGN_CA_SODIMMA_EN
9
5% 1/16W MF-LF 402
26 VREFMRGN_DQ_SODIMMA_EN
10
26 VREFMRGN_CA_SODIMMB_EN
11
14
OUT
10 70
VREFMRGN
26 VREFMRGN_DQ_SODIMMB_EN
12 13
CPU_GTLREF
Place close to U1000.AD26
26
NC NC PCA9557D_RESET_L
15
IN
25
GND 8
3
P0 P1 P2 P3 P4 P5 P6 P7
2 1% 1/16W MF-LF 402
C4
V-
VREFMRGN
100 1
VREFMRGN_CPUFSB_BUF
B4
PCA9557
ADDR=0x30(WR)/0x31(RD)
C1
VREFMRGN
VCC
20% 10V CERM 402
R2914
UCSP
2
0.1UF
U2904 MAX4253
VREFMRGN
1
C2902
16
1
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
FSB/DDR3 Vref Margining
Required zero ohm resistors when no VREF margining circuit stuffed
DRAWING NUMBER
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2903
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2905
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2909
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2911
CRITICAL
NO_VREFMRGN
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
29 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
Page Notes
3
2
1
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE) 8 =PP1V5_S3_MEM_A
Power aliases required by this page: - =PP1V5_S0_MEM_A 1
- =PP1V5_S3_MEM_A
C3100
1
10UF
- =PP0V75_S0_MEM_VTT_A - =PPSPD_S0_MEM_A (2.5 - 3.3V)
2
C3101
1
2
20% 6.3V X5R
2
603
603
1
C3110
1
C3111
0.1UF
10UF
20% 6.3V X5R
0.1UF
20% 10V CERM 402
1
C3112 0.1UF
20% 10V CERM 402
2
2
1
C3113 0.1UF
20% 10V CERM 402
2
1
C3114 0.1UF
20% 10V CERM 402
2
1
C3115 0.1UF
20% 10V CERM 402
2
1
C3116 0.1UF
20% 10V CERM 402
2
C3117 0.1UF
20% 10V CERM 402
2
20% 10V CERM 402
Signal aliases required by this page: - =I2C_SODIMMA_SCL - =I2C_SODIMMA_SDA
D
BOM options provided by this page:
26 PP0V75_S3_MEM_VREFDQ_A (NONE)
1
C3130
C3131
2.2UF
0.1UF
20% 6.3V 2
20% 10V 2
CERM 402-LF
CERM 402
1 3
75
NC 71 15
IN
77 79
MEM_A_BA
81 71 15
IN
MEM_A_A
71 15
IN
MEM_A_A
83 85 87
71 15
IN
MEM_A_A
71 15
IN
MEM_A_A
89 91 93
71 15
IN
MEM_A_A
71 15
IN
MEM_A_A
95 97 99
C
71 15 71 15
IN
MEM_A_CLK_P
101
IN
MEM_A_CLK_N
103 105
71 15 71 15
71 15
IN
MEM_A_A
107
IN
MEM_A_BA
109
IN
MEM_A_WE_L
113
MEM_A_CAS_L
115
111
71 15
IN
117 71 15 71 15
IN IN
MEM_A_A
119
MEM_A_CS_L
121 123
NC
125 127
71 15
BI
MEM_A_DQ
129
71 15
BI
MEM_A_DQ
131 133
71 15
BI
MEM_A_DQS_N
135
71 15
BI
MEM_A_DQS_P
137 139
71 15
BI
MEM_A_DQ
141
71 15
BI
MEM_A_DQ
143 145
BI
MEM_A_DQ
147
71 15
BI
MEM_A_DQ
149
71 15
IN
MEM_A_DM
153
71 15
151
155
B
71 15
BI
MEM_A_DQ
157
71 15
BI
MEM_A_DQ
159 161
71 15
BI
MEM_A_DQ
163
71 15
BI
MEM_A_DQ
165 167
71 15
BI
MEM_A_DQS_N
169
71 15
BI
MEM_A_DQS_P
171
BI
MEM_A_DQ
175
BI
MEM_A_DQ
177
173 71 15 71 15
179 71 15
BI
MEM_A_DQ
181
71 15
BI
MEM_A_DQ
183 185
71 15
IN
MEM_A_DM
187 189
71 15
BI
MEM_A_DQ
191
71 15
BI
MEM_A_DQ
193 195
MEM_A_SA
197
MEM_A_SA
201
199
8 =PPSPD_S0_MEM_A
203
1 1
A
C3140
10K
2.2UF
402-LF
2
MEM_A_CKE
IN
15 71
76
MEM_A_A
IN
9
2
71 15
BI
MEM_A_DQ
5
BI
MEM_A_DQ
7
80
MEM_A_A
IN
15 71
71 15
IN
11
MEM_A_DM
13
82 84
MEM_A_A
IN
15 71
71 15
86
MEM_A_A
IN
15 71
71 15
BI
MEM_A_DQ
15
BI
MEM_A_DQ
17 19
88 90
MEM_A_A
IN
15 71
71 15
BI
MEM_A_DQ
92
MEM_A_A
IN
15 71
71 15
BI
MEM_A_DQ
21 23 25
94 96
MEM_A_A
98
MEM_A_A
IN
15 71
71 15
BI
MEM_A_DQS_N
IN
15 71
71 15
BI
MEM_A_DQS_P
27 29 31
100 102
MEM_A_CLK_P
104
MEM_A_CLK_N
IN
15 71
71 15
IN
15 71
71 15
BI
MEM_A_DQ
33
BI
MEM_A_DQ
35 37
106 108
MEM_A_BA
110
MEM_A_RAS_L
MEM_A_CS_L
IN
15 71
71 15
IN
15 71
71 15
IN
15 71
71 15
BI
MEM_A_DQ
39
BI
MEM_A_DQ
41
BI
MEM_A_DQS_N
45
MEM_A_DQS_P
47
43
112 114 116
MEM_A_ODT
IN
71 15
15 71
BI
49
118 120 122
MEM_A_ODT
IN
15 71
71 15 71 15
NC
BI BI
MEM_A_DQ
51
MEM_A_DQ
53 55
124 126
71 15
128
71 15
130
MEM_A_DQ
BI
15 71
132
MEM_A_DQ
BI
15 71
BI
MEM_A_DQ
57
BI
MEM_A_DQ
59 61
71 15
IN
63
MEM_A_DM
65
134 136
MEM_A_DM
IN
15 71
138 140
MEM_A_DQ
BI
15 71
142
MEM_A_DQ
BI
15 71
146
MEM_A_DQ
BI
15 71
148
MEM_A_DQ
BI
15 71
152
MEM_A_DQS_N
BI
15 71
154
MEM_A_DQS_P
BI
15 71
158
MEM_A_DQ
BI
15 71
160
MEM_A_DQ
BI
15 71
164
MEM_A_DQ
BI
15 71
166
MEM_A_DQ
BI
MEM_A_DM
IN
174
MEM_A_DQ
BI
15 71
176
MEM_A_DQ
BI
15 71
180
MEM_A_DQ
BI
15 71
182
MEM_A_DQ
BI
15 71
71 15
BI
MEM_A_DQ
67
71 15
BI
MEM_A_DQ
69 71
VREFDQ VSS VSS OMIT DQ4 DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* J3100 DQS0 DM0 F-RT-THB VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 RESET* DQS1 VSS VSS DQ14 DQ10 DQ15 DQ11 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 VSS DQS2 DQ22 VSS DQ23 DQ18 VSS DQ19 DQ28 VSS DQ24 DQ29 VSS DQ25 VSS DQS3* DQS3 DM3 VSS VSS DQ30 DQ26 DQ31 DQ27 VSS VSS
2 4
MEM_A_DQ
BI
15 71
6
MEM_A_DQ
BI
15 71
10
MEM_A_DQS_N
BI
15 71
12
MEM_A_DQS_P
BI
15 71
16
MEM_A_DQ
BI
15 71
18
MEM_A_DQ
BI
15 71
22
MEM_A_DQ
BI
15 71
24
MEM_A_DQ
BI
8
14
20
15 71
26 28
MEM_A_DM
IN
15 71
30
MEM_RESET_L
IN
28 29
34
MEM_A_DQ
BI
36
MEM_A_DQ
BI
15 71
32 15 71
C
38 40
MEM_A_DQ
BI
15 71
42
MEM_A_DQ
BI
15 71
44 46
MEM_A_DM
IN
50
MEM_A_DQ
BI
15 71
52
MEM_A_DQ
BI
15 71
56
MEM_A_DQ
BI
15 71
58
MEM_A_DQ
BI
15 71
62
MEM_A_DQS_N
BI
15 71
64
MEM_A_DQS_P
BI
15 71
68
MEM_A_DQ
BI
15 71
70
MEM_A_DQ
BI
15 71
15 71
48
54
60
66
72
KEY
144
516-0201
150
156
B
162
15 71
168 170
15 71
172
PP0V75_S3_MEM_VREFCA_A
26
178
1
C3135
184
2.2UF
186
20% 6.3V
188
MEM_A_DQS_N
BI
15 71
MEM_A_DQS_P
BI
15 71
192
MEM_A_DQ
BI
15 71
194
MEM_A_DQ
BI
2
1
C3136 0.1UF 20% 10V
2
CERM 402-LF
CERM 402
190
15 71
196 198
MEM_EVENT_L
OUT
21 28 36
200
=I2C_SODIMMA_SDA
BI
202
=I2C_SODIMMA_SCL
IN
"Factory" (top) slot
39 39
204
=PP0V75_S0_MEM_VTT_A
8
R3141 1
C3150
1
2.2UF
1/16W
MF-LF 402
71 15
9
78
5%
1/16W
CERM
CKE0 CKE1 VDD OMIT VDD NC J3100 A15 A14 BA2 F-RT-THB VDD VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK0 CK1 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD ODT1 A13 NC S1* VDD VDD VREFCA TEST VSS VSS DQ36 DQ32 DQ33 DQ37 VSS VSS DQS4* DM4 DQS4 VSS DQ38 VSS DQ34 DQ39 DQ35 VSS VSS DQ44 DQ40 DQ45 DQ41 VSS VSS DQS5* DQS5 DM5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ55 DQ50 VSS DQ51 VSS DQ60 DQ61 DQ56 DQ57 VSS VSS DQS7* DM7 DQS7 VSS VSS DQ62 DQ58 DQ63 DQ59 VSS VSS SA0 EVENT* VDDSPD SDA SA1 SCL VTT VTT
74
10K
5%
20% 6.3V 2
1
R3140
KEY
(SYMBOL 2 OF 2)
IN
73
MEM_A_CKE
DDR3-SODIMM-DUAL-M97-3
71 15
(SYMBOL 1 OF 2)
1
DDR3-SODIMM-DUAL-M97-3
D
2
CERM 402-LF
C3151 2.2UF
20% 6.3V
MF-LF 402
SYNC_MASTER=K24_MLB
20% 6.3V 2
SYNC_DATE=02/05/2009
A
PAGE TITLE
DDR3 SO-DIMM Connector A
CERM 402-LF
DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
516-0201 SPD ADDR=0xA0(WR)/0xA1(RD)
SIZE
BRANCH
PAGE
31 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
Page Notes
3
2
1
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE) 8 =PP1V5_S3_MEM_B
Power aliases required by this page: - =PP1V5_S0_MEM_B 1
- =PP1V5_S3_MEM_B
C3200
1
10UF
- =PP0V75_S0_MEM_VTT_B - =PPSPD_S0_MEM_B (2.5 - 3.3V)
2
20% 6.3V X5R 603
C3201
1
20% 6.3V X5R
1
C3210
2
603
1
C3211
0.1UF
10UF 2
0.1UF
20% 10V CERM 402
1
C3212 0.1UF
20% 10V CERM 402
2
2
1
C3213 0.1UF
20% 10V CERM 402
2
C3214
1
0.1UF
20% 10V CERM 402
2
20% 10V CERM 402
1
C3215 0.1UF
2
1
C3216 0.1UF
20% 10V CERM 402
2
C3217 0.1UF
20% 10V CERM 402
2
20% 10V CERM 402
Signal aliases required by this page: - =I2C_SODIMMB_SCL - =I2C_SODIMMB_SDA
D
BOM options provided by this page:
26 PP0V75_S3_MEM_VREFDQ_B (NONE)
1
C3230
C3231
2.2UF
0.1UF
20% 6.3V 2
20% 10V 2
CERM 402-LF
CERM 402
1 3
75 77 71 15
MEM_B_BA
IN
79 81
71 15
IN
MEM_B_A
71 15
IN
MEM_B_A
83 85 87
71 15
IN
MEM_B_A
71 15
IN
MEM_B_A
89 91 93
71 15
IN
MEM_B_A
71 15
IN
MEM_B_A
95 97 99
C
71 15 71 15
IN
MEM_B_CLK_P
101
IN
MEM_B_CLK_N
103 105
71 15 71 15
71 15
IN
MEM_B_A
107
IN
MEM_B_BA
109
IN
MEM_B_WE_L
113
MEM_B_CAS_L
115
111
71 15
IN
117 71 15 71 15
IN IN
MEM_B_A
119
MEM_B_CS_L
121 123 125 127
71 15
BI
MEM_B_DQ
129
71 15
BI
MEM_B_DQ
131 133
71 15
BI
MEM_B_DQS_N
135
71 15
BI
MEM_B_DQS_P
137 139
71 15
BI
MEM_B_DQ
141
71 15
BI
MEM_B_DQ
143 145
BI
MEM_B_DQ
147
71 15
BI
MEM_B_DQ
149
71 15
IN
MEM_B_DM
153
71 15
151
155
B
71 15
BI
MEM_B_DQ
157
71 15
BI
MEM_B_DQ
159 161
71 15
BI
MEM_B_DQ
163
71 15
BI
MEM_B_DQ
165 167
71 15
BI
MEM_B_DQS_N
169
71 15
BI
MEM_B_DQS_P
171 173
71 15
BI
MEM_B_DQ
175
71 15
BI
MEM_B_DQ
177
BI
MEM_B_DQ
181
BI
MEM_B_DQ
183
179 71 15 71 15
185 1
R3240
71 15
MEM_B_DM
IN
189
10K 5% 1/16W
71 15
BI
MEM_B_DQ
191
71 15
BI
MEM_B_DQ
193
MF-LF 2
187
402
195
MEM_B_SA
197
MEM_B_SA
201
199
8 =PPSPD_S0_MEM_B
203
1 1
A
C3240
5%
20% 6.3V 2
R3241 10K
2.2UF
1/16W
CERM 402-LF
2
MF-LF 402
205 207 209 211
KEY
CKE0 CKE1 VDD VDD OMIT NC A15 BA2 A14 J3200 VDD VDD F-RT-BGA3 A11 A12/BC* A9 A7 VDD VDD A6 A8 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK1 CK0 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD A13 ODT1 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DQS4* DM4 VSS DQS4 VSS DQ38 DQ34 DQ39 DQ35 VSS VSS DQ44 DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ47 DQ43 VSS VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DM6 DQS6* DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS DQ60 VSS DQ56 DQ61 DQ57 VSS DQS7* VSS DQS7 DM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS SA0 EVENT* VDDSPD SDA SCL SA1 VTT VTT (2 OF 2)
IN
73
DDR3-SODIMM
71 15
MEM_B_CKE
MTG PINS
MTG PIN MTG PIN MTG PIN MTG PIN
74
MEM_B_CKE
IN
15 71
76
71 15
BI
MEM_B_DQ
71 15
BI
MEM_B_DQ
MEM_B_A
IN
9
80
MEM_B_A
IN
15 71
71 15
IN
11
MEM_B_DM
13
82 84
MEM_B_A
IN
15 71
71 15
86
MEM_B_A
IN
15 71
71 15
BI
MEM_B_DQ
15
BI
MEM_B_DQ
17 19
88 90
MEM_B_A
IN
15 71
71 15
BI
MEM_B_DQ
92
MEM_B_A
IN
15 71
71 15
BI
MEM_B_DQ
21 23 25
94 96
MEM_B_A
98
MEM_B_A
IN
15 71
71 15
BI
MEM_B_DQS_N
IN
15 71
71 15
BI
MEM_B_DQS_P
27 29 31
100 102
MEM_B_CLK_P
104
MEM_B_CLK_N
IN
15 71
71 15
IN
15 71
71 15
BI
MEM_B_DQ
33
BI
MEM_B_DQ
35 37
106 108
MEM_B_BA
110
MEM_B_RAS_L
MEM_B_CS_L
IN
15 71
71 15
IN
15 71
71 15
IN
15 71
71 15
BI
MEM_B_DQ
39
BI
MEM_B_DQ
41
BI
MEM_B_DQS_N
45
MEM_B_DQS_P
47
43
112
116
MEM_B_ODT
IN
71 15
15 71
BI
49
118 120
MEM_B_ODT
IN
71 15
15 71
122
71 15
BI BI
51
MEM_B_DQ
53
MEM_B_DQ
55
124 126
71 15
128
71 15
130
MEM_B_DQ
BI
15 71
132
MEM_B_DQ
BI
15 71
BI
MEM_B_DQ
57
BI
MEM_B_DQ
59 61
71 15
IN
63
MEM_B_DM
65
134 136
7 9
78
114
5
MEM_B_DM
15 71
IN
138 140
MEM_B_DQ
BI
15 71
142
MEM_B_DQ
BI
15 71
146
MEM_B_DQ
BI
15 71
148
MEM_B_DQ
BI
15 71
152
MEM_B_DQS_N
BI
15 71
154
MEM_B_DQS_P
BI
15 71
158
MEM_B_DQ
BI
15 71
160
MEM_B_DQ
BI
15 71
71 15
BI
MEM_B_DQ
67
71 15
BI
MEM_B_DQ
69 71
VREFDQ VSS OMIT DQ4 VSS DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* J3200 DQS0 DM0 F-RT-BGA3 VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ10 DQ14 DQ11 DQ15 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ18 DQ23 DQ19 VSS VSS DQ28 DQ24 DQ29 DQ25 VSS DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS (1 OF 2)
1
DDR3-SODIMM
D
2 4
MEM_B_DQ
BI
15 71
6
MEM_B_DQ
BI
15 71
10
MEM_B_DQS_N
BI
15 71
12
MEM_B_DQS_P
BI
15 71
16
MEM_B_DQ
BI
15 71
18
MEM_B_DQ
BI
15 71
22
MEM_B_DQ
BI
15 71
24
MEM_B_DQ
BI
8
14
20
15 71
26 28
MEM_B_DM
IN
15 71
30
MEM_RESET_L
IN
27 29
34
MEM_B_DQ
BI
36
MEM_B_DQ
BI
15 71
32 15 71
C
38 40
MEM_B_DQ
BI
15 71
42
MEM_B_DQ
BI
15 71
44 46
MEM_B_DM
IN
50
MEM_B_DQ
BI
15 71
52
MEM_B_DQ
BI
15 71
56
MEM_B_DQ
BI
15 71
58
MEM_B_DQ
BI
15 71
62
MEM_B_DQS_N
BI
15 71
64
MEM_B_DQS_P
BI
15 71
68
MEM_B_DQ
BI
15 71
70
MEM_B_DQ
BI
15 71
15 71
48
54
60
66
72
KEY
144
516S0706
150
156
B
162
DDR3 GROUND RETURN CAPS (MCP SIDE)
164
MEM_B_DQ
BI
15 71
166
MEM_B_DQ
BI
15 71
8 =PP1V5_S0_MEM_MCP
168 170
MEM_B_DM
IN
174
MEM_B_DQ
BI
15 71
176
MEM_B_DQ
BI
15 71
180
MEM_B_DQ
BI
15 71
182
MEM_B_DQ
BI
15 71
1
15 71
C3222
1
0.1UF
172 2
PP0V75_S3_MEM_VREFCA_B
26
20% 10V CERM 402
C3223
1
0.1UF 2
20% 10V CERM 402
C3224
1
0.1UF 2
20% 10V CERM 402
C3225
1
0.1UF 2
20% 10V CERM 402
C3226
1
0.1UF 2
20% 10V CERM 402
C3227
1
0.1UF 2
20% 10V CERM 402
1
C3228 0.1UF
2
C3229 0.1UF
20% 10V CERM 402
2
20% 10V CERM 402
178
1
C3235
184
2.2UF
186
20% 6.3V
188
MEM_B_DQS_N
BI
15 71
MEM_B_DQS_P
BI
15 71
192
MEM_B_DQ
BI
15 71
194
MEM_B_DQ
BI
2
1
C3236 0.1UF 20% 10V
2
CERM 402-LF
CERM 402
190
15 71
196 198
MEM_EVENT_L
OUT
200
=I2C_SODIMMB_SDA
BI
202
=I2C_SODIMMB_SCL
IN
21 27 36 39
"Expansion" (bottom) slot 39
204
=PP0V75_S0_MEM_VTT_B
MTG PIN
206
MTG PIN
208
MTG PIN
210
2.2UF
MTG PIN
212
20% 6.3V
1
2
C3250
CERM 402-LF
1
8
C3251 2.2UF
SYNC_MASTER=K24_MLB
20% 6.3V 2
SYNC_DATE=02/05/2009
A
PAGE TITLE
DDR3 SO-DIMM Connector B
CERM 402-LF
DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY:
516S0706
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
SPD ADDR=0xA2(WR)/0xA3(RD)
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1
D
D
DDR3 RESET Support Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.
R3309 0
MCP_MEM_RESET_L
2
1
MEM_RESET_L
27 28
R3310 1
Q3305
1K
1 2
B
R3305
3
5
C3300
Q1
6
D
MEM_RESET_RC_L
E
1
20K 5% 1/16W MF-LF 402
2
5% 1/16W MF-LF 402
C
1
3.3V S5 is used because MEM_RESET must be high before 1.5V starts to rise to avoid glitch on MEM_RESET_L.
100K
2
R3301 1
8
SOT-363
4
10K 5% 1/16W MF-LF 402
=PP3V3_S5_MEMRESET
DMB53D0UDW
S
R3300
5% 1/16W MF-LF 402
1
G
=PP1V5_S3_MEMRESET
C
OUT
5% 1/16W MF-LF 402
Q2
8
IN
C
16
2
MEM_RESET
0.1UF 2 2
20% 10V CERM 402
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
DDR3 Support DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
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33 OF 109 SHEET
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6 17
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2
1
OUT PCIE_MINI_PRSNT_L
3
D
Q3401 SSM6N15FEAPE SOT563
4
S
G
5
AP_PWR_EN
IN
21 32
3V S3 WLAN FET
D 17
MINI_CLKREQ_L
OUT
6
D
D
MOSFET
TPCP8102
CHANNEL
P-TYPE
Q3401 20-30 MOHM @2.5V
RDS(ON)
SSM6N15FEAPE SOT563
LOADING
0.727 A (EDP)
2
MINI_CLKREQ_Q_L
PCIE_MINI_R2D_P
72
PCIE_MINI_R2D_N
1 1
2
10%
PLACEMENT_NOTE=Place close to J3401.
CRITICAL
0.1uF 16V
X5R
402
PCIE_MINI_R2D_C_P
IN
17 72
PCIE_MINI_R2D_C_N
IN
17 72
7
C3422
PLACEMENT_NOTE=Place close to J3401.
72 7
CONN_PCIE_MINI_D2R_P 4
3
PCIE_MINI_D2R_P
J3401
OUT
17 72
C
72 7
CONN_PCIE_MINI_D2R_N 1
2
PCIE_MINI_D2R_N
PLACEMENT_NOTE=Place close to J3401.
OUT
47 30
PP3V3_WLAN_F
1 3
2 4
3
8
PP3V3_WLAN_R
C3421 0.1uF 20% 10V CERM 402
2
1
1
C3420
2
2
10% 16V X5R 402
C3450 0.1UF 1
90-OHM-100MA DLP11S
C3451
1
2
2
R3450 1
2
5% 1/16W MF-LF 402
PM_WLAN_EN_L
2
IN
30 32
5% 1/16W MF-LF 402
10% 16V X5R 402
PLACEMENT_NOTE=Place close to J3401.
R3451
100K
P3V3WLAN_SS
8 30
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
10K
0.033UF
20% 10V X5R 805
L3401
17 72
=PP3V3_S3_WLAN 1
10UF
AIRPORT
CRITICAL
F-ST-SM 32 31
1
20% 10V CERM 402
SYM_VER-1
500913-0302
2 0603
0.1uF
90-OHM-100MA DLP11S
CRITICAL
1
PP3V3_WLAN MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=3.3V
402
C3430
L3402
516S0582
X5R
2
10%
0.1uF 16V
1
72
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=3.3V
D
2
23V1K-SM
1% 1/4W MF 1206
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=3.3V
4 G
CONN_PCIE_MINI_R2D_N 1
FERR-120-OHM-3A
C3431
5
72 7
L3404
727 MA PEAK 606 MA NOMINAL MAX
PLACEMENT_NOTE=Place close to J3401.
3
TPCP8102
0.002
7
SYM_VER-1
CONN_PCIE_MINI_R2D_P 4
Q3450
R3452
155S0367
L3405 90-OHM-100MA DLP11S
72 7
CRITICAL
CRITICAL
CRITICAL
2
G
6
7
S
S
1
C
SYM_VER-1
NC NC
2
1
4
3
72 7
PCIE_CLK100M_MINI_CONN_P
6
5
72 7
PCIE_CLK100M_MINI_CONN_N
8
7
10
9
12
11
14
13
16
15
18
17
20
19
4
1
PLACEMENT_NOTE=Place close to Q3450.
PCIE_CLK100M_MINI_P
3
17 72
IN
17 72
PLACEMENT_NOTE=Place close to Q3450.
ISNS_AIRPORT_P
PCIE_CLK100M_MINI_N
2
IN
ISNS_AIRPORT_N
OUT OUT
47 76 47 76
PLACEMENT_NOTE=Place close to J3401.
BLUETOOTH
22
21
73 7
CONN_USB2_BT_P
24
23
73 7
CONN_USB2_BT_N
26
25
28
27
30
29
1 C3432
34
33
2
7
L3403 90-OHM DLP0NS
CRITICAL
SYM_VER-1
4
3
USB_BT_P
BI
20 73
1
2
USB_BT_N
BI
20 73
PP3V3_S3_BT_F
PLACEMENT_NOTE=Place close to J3401.
L3406
0.01UF 10% 16V CERM 402
2
1
=PP3V3_S3_BT
8
FERR-120-OHM-1.5A 0402-LF
PLACEMENT_NOTE=PLACE L3406 NEAR J3401.
PLACEMENT_NOTE=PLACE C3432 NEAR J3401
B
B
RC VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN 3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET
PP3V3_WLAN_F =PP3V3_S3_WLAN PCIE_WAKE_L
OUT
8 30
1
7 17
30 47
R3453 110K
U3402
5% 1/16W MF-LF
5
74LVC1G17 TC7SZ08AFEAPE 5 SOT665 7
2
A
2
SOT353-1 4
WLAN_SMIT_BUF
402
R3455
2
1
4
MINI_RESET_CONN_L
Y
U3401
WLAN_SMIT_RC
NC B
1
3
1
NC
3
1
C3453 MINI_RESET_L
A
IN
1
10% 6.3V CERM 402
2 5% 1/16W MF-LF 402
WLAN_SMIT_DISCHRG
Q3455 3
D
SSM3K15FV SOD-VESM-HF
62K
1UF
25
R3454
1
5%
NOSTUFF
1/16W MF-LF
2 2
SYNC_MASTER=K24_MLB
402
2
S
G
SYNC_DATE=01/27/2009
A
PAGE TITLE
1
PM_WLAN_EN_L
X16 WIRELESS CONNECTOR
30 32
DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
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2
=PP1V05_ENET_PHY
1
8
(221mA typ - 1000base-T)
D
(
C3710
1
C3711
0.1UF
8
10% 16V X5R 402
=PP3V3_ENET_PHY
1
1
0.1UF 10% 16V X5R 402
2
D
7mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
CRITICAL
L3715
2
FERR-120-OHM-1.5A 0402-LF
(43mA typ - 1000base-T) (19mA typ - Energy Detect) 1
1
WF: Marvell numbers, update for Realtek
1
C3700 0.1UF
CRITICAL
L3705 FERR-120-OHM-1.5A
1
C3701 0.1UF
10% 16V X5R 402
2
2
C3702
2
0.1UF
10% 16V X5R 402
2
10% 16V X5R 402
PP1V05_ENET_PHYAVDD
1
C3714
0402-LF
C3715
1
C3716
2.2UF
2.2UF
0.1UF
10% 6.3V X5R 402
10% 6.3V X5R 402
10% 16V X5R 402
2
2
2
1
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
PP3V3_ENET_PHYAVDD MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
1
C3705 0.1UF
2
C3706 0.1UF
10% 16V X5R 402
2
10% 16V X5R 402
=PP3V3_ENET_PHY_VDDREG
9
If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45. NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
9
=RTL8211_ENSWREG
IN
2
2
40
10
28
3
45
44
37
21
36
AVDD10
5% 1/16W MF-LF 402
DVDD10
4.7K
FB10
10K 5% 1/16W MF-LF 402
15
6
R3725
VDDREG
Alias to =PP3V3_ENET_PHY for internal switcher. Alias to GND for external 1.05V supply.
1
DVDD33
C
1
AVDD33
NO STUFF
R3720
41
R3750
1
1
R3751
R3752
4.7K
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
1
=RTL8211_REGOUT
9
If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
2
C
If internal switcher is not used, VDDREG and REGOUT can float.
CRITICAL 39
U3700 ENSWREG
RTL8251CA-VB-GR
REGOUT
48
RXC
19
TQFP
R3796 74 18
IN
ENET_CLK125M_TXCLK
1
0
22
74 ENET_CLK125M_TXCLK_R
2
5% 1/16W 402 MF-LF
PLACE R3796 CLOSE TO U1400, PIN D24
74 18
IN
ENET_TXD
23
74 18
ENET_TXD
24
IN
74 18
ENET_TXD
25
IN IN
ENET_TXD
26
74 18
74 18
ENET_TX_CTRL
IN
27
74 18
ENET_MDC
30
IN
74 18
BI
ENET_MDIO
31
TXC
TXD[0] TXD[1] TXD[2] TXD[3]
RGMII/MII
RXD[0] RXD[1]/TXDLY RXD[2]/AN0 RXD[3]/AN1
TXCTL
MDC MDIO
RXCTL
0
IN
ENET_RESET_L
1
RTL8211_PHYRST_L
2
5% 1/16W MF-LF 402
1
2
HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.
NO STUFF
PHYRSTB*
RTL8211_RSET
46
20% 10V CERM 402
B
9
TP_RTL8211_CLK125
32
RSET
REFERENCE
74
ENET_RXD_R
16
74
ENET_RXD_R
17
74
ENET_RXD_R
74
ENET_RXD_R
18
13
74
ENET_RXCTL_R
ENET_MDI_P
BI
33 74
2
ENET_MDI_N
BI
33 74
MDI+[1] MDI-[1]
4
ENET_MDI_P
BI
33 74
5
ENET_MDI_N
BI
33 74
MDI+[2] MDI-[2]
8
ENET_MDI_P
BI
33 74
9
ENET_MDI_N
BI
33 74
MDI+[3] MDI-[3]
11
ENET_MDI_P
BI
33 74
12
ENET_MDI_N
BI
33 74
LED0/PHYAD0 LED1/PHYAD1 LED2/RXDLY
34
RTL8211_PHYAD0
35
RTL8211_PHYAD1
22
1
2
R3791 R3792
22
1
2
22
1
2
R3793 R3794
22
1
2
22
1
2
R3795
1
RESET MEDIA DEPENDENT
C3725 0.1UF
ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.
29
14
MDI+[0] MDI-[0]
MANAGEMENT
R3724 74 18
R3790
74 ENET_CLK125M_RXCLK_R
22
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1
1/16W
MF-LF
ENET_CLK125M_RXCLK
OUT
18 74
ENET_RXD
OUT
18 74
ENET_RXD
OUT
18 74
ENET_RXD
OUT
18 74
ENET_RXD
OUT
18 74
ENET_RX_CTRL
OUT
18 74
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
B
CLK125
1
R3730
CLOCK
2.49K
IN
RTL8211_CLK25M_CKXTAL1
42
TP_RTL8211_CKXTAL2
43
CKXTAL1 CKXTAL2
LED
38
RTL8211_RXDLY NO STUFF
C3790
47
33
GND 20
74 32
2
7
1% 1/16W MF-LF 402
1
10PF 5% 50V CERM 402
2
R3755
1
R3756
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
1
1
R3757 4.7K
2
2
5% 1/16W MF-LF 402
Reserved for EMI per RealTek request.
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
Ethernet PHY (RTL8211CL) DRAWING NUMBER
Apple Inc.
051-7982
PHYAD
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
= 01 (PHY Address 00001)
AN[1:0] = 11 (Full auto-negotiation) RXDLY
= 0
(RXCLK transitions with data)
TXDLY
= 0
(No TXCLK Delay)
8
D
REVISION
C.0.0
R
Configuration Settings:
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1
3.3V ENET FET @ 2.5V Vgs:
CRITICAL
Rds(on) = 90mOhm max I(max)
Q3810
= 1.7A (85C)
NTR4101P SOT-23-HF
=PP3V3_S5_P3V3ENETFET
8
=PP3V3_ENET_FET
S
2
D R3800
1
1
D
C3811
8
3
D
G
0.033UF
10K 5% 1/16W
10% 16V X5R 402
2
MF-LF 402
1
C3810
R3810
2
0.01UF
100K P3V3ENET_EN_L
D
Q3801
1
2
P3V3ENET_SS
2 5% 1/16W MF-LF 402
3
1
10% 16V CERM 402
SSM6N15FEAPE SOT563
5
9
IN
G
S
4
=P3V3ENET_EN
MOBILE: Recommend aliasing PM_SLP_RMGT_L and =P3V3ENET_EN.
Nets separated on
ARB for alternate power options.
WLAN Enable Generation "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L
C
30
OUT
Q3805
D
C
1.05V ENET FET
Pull-up is with power FET. 6
SSM6N15FEAPE SOT563
8
=PP1V05_ENET_P1V05ENETFET
1.8V Vgs 2
30 21
IN
G
S
1
AP_PWR_EN
C3840
Q3805
D
3
6
D
8
Q3801
CRITICAL
SOT563
R3842
G
D
2
Q3840
100K 1
5
CERM 402
R3840
=PP3V3_S5_P1V05ENETFET
1
P1V05ENET_SS
2
G
SSM6N15FEAPE
SOT563
IN
3
20% 10V
SSM6N15FEAPE
37 36 21
1
0.1UF
AC_OR_S0_L
S
4
1
S
G
1
Q3841
6
SOT23
2
=PP1V05_ENET_FET
2 2
R3841
G
S
1 1
IN
1
10% 16V
2
PM_SLP_S3_L
2 1%
D
Q3841
1/16W MF-LF
3
C3841 0.01UF
10K
P1V05ENET_EN_L 67 63 36 21 7
8
SOT563
1% 1/16W MF-LF 402
D
SSM6N15FEAPE
69.8K
2
SMC_ADAPTER_EN
SI2312BDS
S
5% 1/16W MF-LF 402
CERM 402
P1V05ENET_EN_L_RC
402
SSM6N15FEAPE SOT563
5
B
9
IN
G
S
4
B
=P1V05ENET_EN
Non-ARB: Recommend aliasing PM_SLP_RMGT_L and =P1V05ENET_EN.
Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
A
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
Ethernet & AirPort Support
R3895 22 74 18
IN
MCP_CLK25M_BUF0_R
1
2
RTL8211_CLK25M_CKXTAL1
OUT
DRAWING NUMBER
31 74
5% 1/16W MF-LF 402
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
PLACEMENT_NOTE=Place close to U1400
NOTICE OF PROPRIETARY PROPERTY:
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38 OF 109 SHEET
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8
7
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2
1
- COPY THIS PAGE FROM K36 CSA.39
D
D
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902
ENET_CONN_CTAP
1
2
C3900
1
1
C3901 0.1UF
0.1UF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
2
2
1
C3902
0.1UF
C3903 0.1UF
2
10% 16V X5R 402
ETHERNET CONNECTOR CRITICAL
T3901 SM
OMIT CRITICAL
74 31
BI
ENET_MDI_P
1
12
74 31
BI
ENET_MDI_N
2
11
3
10
74
J3900
ENET_MDI_TRAN_P
RJ45-10/100TX-K83 74
TX
1 1%
1/16W
1%
1/16W
TLA-6T213HF
74 31
BI
5
ENET_MDI_P
75
2
MF-LF
1
ENET_CENTER_TAP
2 3
402
4
R3902
9
4
C
1
R3903 ENET_CENTER_TAP
75
2 MF-LF
5 6
402
8
74 74
74 31
BI
6
ENET_MDI_N
F-R-TH
ENET_MDI_TRAN_N
ENET_MDI_TRAN_P
7
ENET_MDI_TRAN_N
8
ENET_MDI TRAN_P0 TRAN_N0 TRAN_P1 TRAN_P2 TRAN_N2 TRAN_N1 TRAN_P3 TRAN_N3
C
7
RX
9 10
CRITICAL
74 31
74 31
BI
BI
ENET_MDI_N
1
ENET_MDI_P
2
T3902 SM
3
11
12
74
ENET_MDI_TRAN_N
11
74
ENET_MDI_TRAN_P
74
ENET_MDI_TRAN_N
10
R3901 1
ENET_CENTER_TAP
TX
1%
TLA-6T213HF 4
9
74 31
BI
ENET_MDI_N
5
8
BI
ENET_MDI_P
6
7
1/16W
2
1/16W
2
514-0692
75
MF-LF
R3900 1
ENET_CENTER_TAP 1%
74 31
SHIELD PINS
12
402
75
MF-LF
402
74 ENET_MDI_TRAN_P
RX ENET_BOB_SMITH_CAP MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1 1
B
2
1
C3911
C3913
10PF
10PF
5% 50V CERM 402-1
5% 50V CERM 402-1
2
1
10PF 2
CRITICAL
CRITICAL
C3915
2
CRITICAL CRITICAL
CRITICAL
1
1
C3912 10PF
2
2
1
C3910
B
1000PF
5% 50V CERM 402-1
2
CRITICAL
10% 2KV CERM 1206
CRITICAL
C3914
1
10PF
5% 50V CERM 402-1
CRITICAL
C3917 10PF
5% 50V CERM 402-1
5% 50V CERM 402-1
CRITICAL
C3916
1
10PF 2
5% 50V CERM 402-1
C3918 10PF
2
5% 50V CERM 402-1
PLACEMENT_NOTE=PLACE C3911-C3918 ON MDI LINES WITHOUT ANY STUBS
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
ETHERNET CONNECTOR DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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39 OF 109 SHEET
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CRITICAL
Q4590
ODD Power Control
TPCP8102 23V1K-SM
PP5V_SW_ODD_R 8
=PP5V_S3_ODD
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
1
100K 2
R4595 ODD_PWR_EN_LS5V_L
D
1
R4597 D
Q4596
6
D
10% 10V CERM 402
C4596 0.01UF 1
ODD_PWR_SS
2
6
10% 16V CERM 402
R4598 1
SOT563
Q4596
D
3
S
4
G
S
3
ISNS_ODD_P
1% 1/4W MF 1206 2 4
ISNS_ODD_N
47 76
OUT
0.002
SSM6N15FEAPE ODD_PWR_EN 2
D
2
CRITICAL
5% 1/16W MF-LF 402
100K 5% 1/16W MF-LF 402
100K
4
0.068UF
5% 1/16W MF-LF 402
=PP3V3_S0_ODD
C4595
G
R4596
NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5. 34 8
5
1
2
S
7
3
8
OUT
47 76
1
SSM6N15FEAPE SOT563
5 21
IN
G
ODD_PWR_EN_L
47 7
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
CRITICAL
SATA ODD
PP5V_SW_ODD
FL4520
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79
90-OHM-100MA DLP11S
PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
SYM_VER-1
34 8
3
=PP3V3_S0_ODD
4
72
R4590
OUT
1
72
Indicates disc presence
C4521
2
CERM
CERM
SATA_ODD_R2D_C_P
IN
20 72
SATA_ODD_R2D_C_N
IN
20 72
402
C4520
10% 16V
0.01UF
F-ST-SM
SMC_ODD_DETECT
1
SATA_ODD_R2D_UF_N
54722-0164
5% 1/16W MF-LF 402 2
36 7
2
J4500
1
33K
2
10% 16V
0.01UF
CRITICAL
C
1
SATA_ODD_R2D_UF_P
402
C
PLACEMENT_NOTE=Place FL4520 close to J4500
1
2
3
4
72 7
5
6
72 7
7
8
9
10
11
12
13
14
15
16
SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P
FL4525
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500
90-OHM-100MA DLP11S
PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
SYM_VER-1
C4526
1
2
C4525
1
2
72
CERM
CERM
OUT
20 72
OUT
20 72
402 1
SATA_ODD_D2R_UF_P
10% 16V
0.01UF
CRITICAL 3 SATA_ODD_D2R_N
4
SATA_ODD_D2R_UF_N
10% 16V
0.01UF
516S0616
72
2
SATA_ODD_D2R_P
402
PLACEMENT_NOTE=Place FL4525 close to J4500
CRITICAL
J4502 78171-0002 M-RT-SM
3 PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
R4531
B
4.7 37
SYS_LED_ANODE
2
1 5% MF-LF
PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
1
7 SYS_LED_ANODE_R
402
B
2
1/16W
4
SIL
1
1
1
C4501 0.1UF
518S0519 2
C4531
2
CRITICAL
CRITICAL
20% 10V CERM 402
R4599 0.002
L4500
0.001UF 2
C4502 0.1UF
20% 10V CERM 402
10% 50V CERM
1% 1/4W MF 1206
FERR-70-OHM-4A
402
7
1
PP5V_S0_HDD_FLT
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2MM VOLTAGE=5V
2
1 3
PP5V_S0_HDD_R MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
0603 PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
2 4
=PP5V_S0_HDD
8
ISNS_HDD_P CRITICAL
FL4502
ISNS_HDD_N
90-OHM-100MA
OUT OUT
47 76
47 76
DLP11S SYM_VER-1
72 7
C4515
SATA_HDD_D2R_C_N
CRITICAL
54722-0164
72 7
F-ST-SM
1
4
5
6
7
SATA HDD
A
NC
C4516
SATA_HDD_D2R_C_P
2
72
10% 16V 1
CERM
2 CERM
SATA_HDD_D2R_UF_N
4
3
SATA_HDD_D2R_N
OUT
20 72
2
SATA_HDD_D2R_P
OUT
20 72
402
72
10% 16V
0.01UF
2
3
1
0.01UF
J4501
SATA_HDD_D2R_UF_P
1
402 PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
PLACEMENT_NOTE=Place C4515 next to C4516 PLACEMENT_NOTE=Place C4516 close to J4501
8
9
10
11
12
13
14
15
16
CRITICAL
FL4501
90-OHM-100MA
PLACEMENT_NOTE=Place C4511 next to C4510 PLACEMENT_NOTE=Place C4510 close to MCP79
DLP11S
SYNC_MASTER=K24_MLB
SYM_VER-1
72 7
3
SATA_HDD_R2D_N
4
72
SATA_HDD_R2D_UF_N
C4511
1
10% 16V
0.01UF
516S0616 72 7
2
SATA_HDD_R2D_P
1
72
SATA_HDD_R2D_UF_P
C4510 0.01UF
PLACEMENT_NOTE=Place FL4501 close to J4501
2
1
2 10% 16V
SATA_HDD_R2D_C_N CERM
SATA_HDD_R2D_C_P CERM
SYNC_DATE=01/19/2009
SATA Connectors DRAWING NUMBER
IN
A
PAGE TITLE
IN
402
20 72
Apple Inc.
402
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
45 OF 109 SHEET
OF
8
7
6
5
4
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8
7
6
5
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1
D
D
POR IS PLASTIC USB CONNECTOR PARTS BUT METAL PART’S SCHEMATIC AND CAD SYMBOLS HAVE BEEN USED AS ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES
Port Power Switch
USB PORT A (FRONT PORT) PLACEMENT_NOTE=NEAR J4600
CRITICAL
CRITICAL
U4690
FERR-220-OHM-2.5A
L4605
TPS2064DGN 8
IN
OUT1
7
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
MSOP 20
20
8
USB_EXTA_OC_L
OUT
USB_EXTB_OC_L
OUT
OC1*
3
EN1
5
OC2*
4
EN2
OUT2
1
PP5V_S3_RTUSB_A_ILIM
6
2
C4605
PP5V_S3_RTUSB_B_ILIM
20% 16V CERM 402
PLACEMENT_NOTE=NEAR J4600 CRITICAL 2
1
C4690
1
1
10UF 20% 6.3V X5R 603
2
2
CRITICAL
C4695
0.1UF
1
1
10UF
20% 10V CERM 402
F-RT-TH 5
90-OHM DLP0NS
6
SYM_VER-1
9
C4691
USB-K83
L4600
GND TPAD NOSTUFF
OMIT CRITICAL
J4600
0.01uF
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
C
PP5V_S3_RTUSB_A_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
0603 1
20% 6.3V X5R 603
C4696 100UF
2
2
20% 6.3V POLY-TANT CASE-B2-SM
CRITICAL 1
C4617
1
10UF 2
2
3
73 CONN_USB_EXTA_N 1 2
C4616 100UF
20% 6.3V X5R 603
4
73 USB_EXTA_MUXED_N
1
73 USB_EXTA_MUXED_P
2
3
73 CONN_USB_EXTA_P
20% 6.3V POLY-TANT CASE-B2-SM
4
2 5 3 4
We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.
6 VBUS
NC IO NC IO
C
2
=PP5V_S3_EXTUSB
7 8
1 GND 63
CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION
=USB_PWR_EN
IN
514-0689
D4600 RCLAMP0502N SLP1210N6 CRITICAL NOSTUFF PLACEMENT_NOTE=NEAR J4610 CRITICAL We can add protection to 5V if we want, but leaving NC for now
L4615 FERR-220-OHM-2.5A 1
2
1
USB/SMC Debug Mux 8
B
C4615 0.01uF
2
20% 16V CERM 402
OMIT CRITICAL
=PP3V42_G3H_SMCUSBMUX
J4610 USB-K83
SMC_DEBUG_YES
1
C4650
1
0.1UF 2 2
10K
CRITICAL
5% 1/16W MF-LF 402
L4610
6
90-OHM DLP0NS
1
SYM_VER-1
9
20% 10V CERM 402
F-RT-TH 5
PLACEMENT_NOTE=NEAR J4610
R4650
73 20
BI
USB_EXTB_N
4
3
IN
SMC_RX_L
5
M+
38 37 36
OUT
SMC_TX_L
4
M-
73 20
BI
USB_EXTA_P
7
73 20
BI
USB_EXTA_N
6
D+ D-
2
CONN_USB_EXTB_P
3
73
VCC 38 37 36
73 CONN_USB_EXTB_N
4
SMC_DEBUG_YES
U4650
Y+
1
Y-
2
73 20
BI
USB_EXTB_P
1
2
7
PI3USB102ZLE
2 5 3 4
TQFN
6 VBUS
8
NC IO NC IO
B
Place L4600 and L4605 at connector pin
PP5V_S3_RTUSB_B_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
0603
CRITICAL
514-0689 1 GND
OE*
8
SEL
10
USB_DEBUGPRT_EN_L
IN
36
SEL=0 Choose SMC SEL=1 Choose USB
D4610
3
GND
RCLAMP0502N SLP1210N6 CRITICAL NOSTUFF SMC_DEBUG_NO
A
R4651
SYNC_MASTER=K24_MLB
0 1
2 5%
SYNC_DATE=02/05/2009
A
PAGE TITLE
1/16W MF-LF
External USB Connectors
USB PORT B (BACK PORT)
SMC_DEBUG_NO
R4652
402
DRAWING NUMBER
0 1
2
Apple Inc.
5% 1/16W
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
MF-LF 402
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
46 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
NOTE: Unused pins have "SMC_Pxx" names.
6
5
4
3
2
1
Unused
pins designed as outputs can be left floating, those designated as inputs require pull-ups.
37 7
PP3V3_S5_AVREF_SMC
37 8
=PP3V3_S5_SMC
D
D C4902
1
1
2
2
22UF 20% 6.3V CERM 805
U4900
21 59 21
37
OUT
PM_RSMRST_L
C13
OUT
IMVP_VR_ON
C12
OUT
PM_PWRBTN_L
D10
OUT
ESTARLDO_EN
D13
37
D12 F11
SMC_P24
E13 E12
NC 37
SMC_P26
F13 E10
NC BI
LPC_AD
A9
73 38 19
BI
LPC_AD
D9
73 38 19
BI
LPC_AD
C8
73 38 19
BI
LPC_AD
B7 A8
73 38 19
C
73 38 19
IN
LPC_FRAME_L
25
IN
SMC_LRESET_L
IN
LPC_CLK33M_SMC
D7
LPC_SERIRQ
D6
73 25 38 19
BI
SMB_MGMT_DATA
46
OUT
SMS_ONOFF_L
A5 B4
(OC)
A1 C2
NC NC 37
OUT
SMC_GFX_THROTTLE_L
9
OUT
SMC_SYS_KBDLED
38 37 36 35
OUT
SMC_TX_L
IN
SMC_RX_L
38 37 36 35 39
BI
P40 P41 P42 P43 P44 P45 P46 P47
D4
SMC_P41
BI
P30 P31 P32 P33 P34 P35 P36 P37
D8
NC 37 39
P20 P21 P22 P23 P24 P25 P26 P27
E11
NC NC NC
B2 C1 C3
F3 E4
(OC)
P70 P71 P72 P73 P74 P75 P76 P77
J12
7 57 63
4.7
OUT
NC SMC_PROCHOT_3_3_L
IN
37
H12
SMC_BIL_BUTTON_L
IN
37
N10
SMC_CPU_ISENSE
IN
41
M11
SMC_CPU_VSENSE SMC_GPU_ISENSE
IN
40
IN
37
SMC_GPU_VSENSE
IN
37
N12
SMC_DCIN_ISENSE
IN
41
M13
SMC_PBUS_VSENSE
IN
40
N13
SMC_BATT_ISENSE
IN
41
L12
SMC_NB_MISC_ISENSE
IN
37
SMC_WAKE_SCI_L
OUT
21
C7
PM_CLKRUN_L
OUT
19 38
D5
LPC_PWRDWN_L
IN
19 38
A6
SMC_TX_L
B5
SMC_RX_L
A7
P90 P91 P92 P93 P94 P95 P96 P97
J4
B6
C6
C4907
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
C4920
1
10% 6.3V CERM-X5R 402
0.1UF 20% 10V CERM 402
VCC
AVCC
1
0.47UF
VCL AVREF
2
2
1
H8S2117
PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PIN M12
LGA-HF
NC
E5
MD1 MD2
D1
NMI
E3
ETRST
H3
AVSS
L9
OMIT 38 37
SMC_RESET_L
D3
RES*
37
SMC_XTAL
A3
37
SMC_EXTAL
A2
XTAL EXTAL
IN
1
R4909
U4900
PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PIN M12
R4901
10K
NC
5% 1/16W MF-LF 402
(3 OF 3)
N11
P80 P81 P82 P83 P84 P85 P86
PP3V3_S5_SMC_AVCC
2 5% 1/16W MF-LF 402
21 32 37
J11
L10
SMC_VCL
R4999 1
SMC_ADAPTER_EN
K13 J10
OUT
10K
2
2
5% 1/16W MF-LF 402
SMC_MD1
IN
38
SMC_NMI
IN
38
SMC_TRST_L
IN
38
SMC_KBC_MDE
H1
NC
(OC)
OUT
35 36 37 38
IN
35 36 37 38
SMB_MGMT_CLK
BI
SMC_ONOFF_L
IN
VSS
39
G3
SMC_BC_ACOK
IN
H2
SMC_BS_ALRT_L
IN
37
G1
PM_SLP_S3_L
IN
7 21 32 63 67
H4
PM_SLP_S4_L
IN
7 21 37 63
G4
PM_SLP_S5_L
IN
37
F4
PM_CLK32K_SUSCLK
IN
25 73
F1
SMB_0_S0_DATA
BI
(OC)
1
R4902 10K
37 44
XW4900 SM 2
37 55
NOTE: P94 and P95 are shorted, P95 could be spare.
C
NO STUFF 1
2
1
R4998 10K
5% 1/16W MF-LF 402
2
R4903 0
5% 1/16W MF-LF 402
2
5% 1/16W MF-LF 402
1
GND_SMC_AVSS
37 40 41
39
P50 P51 P52
G2
SMB_0_S0_CLK
OMIT
K11
PLACEMENT_NOTE=PLACE C4907 CLOSE TO U4900 PIN E1
SMC_PM_G2_EN
NC NC NC
L11
D11
NC
(1 OF 3)
K12
E1
B13
L13
H10
A12
RSMRST_PWRGD
P60 P61 P62 P63 P64 P65 P66 P67
20% 10V CERM 402
M1
ALL_SYS_PWRGD
IN
LGA-HF
2
B1
IN
63
H8S2117
C4906 0.1UF
20% 10V CERM 402
C5
63 25
P10 P11 P12 P13 P14 P15 P16 P17
C4905 0.1UF
2
B11
A13
20% 10V CERM 402
2
F10
B12
SMC_RSTGATE_L
C4904 0.1UF
20% 10V CERM 402
M12
SMC_EXCARD_PWR_EN
OUT
0.1UF
1
L3
OUT
37
C4903
1
D2
37
1
U4900 (DEBUG_SW_1)
37
SMC_PA0
N3
(DEBUG_SW_2)
37
SMC_PA1
N1
25
OUT
PM_SYSRST_L
(OC)
M3
35
OUT
USB_DEBUGPRT_EN_L
(OC)
M2
BI
MEM_EVENT_L
(OC)
N2
(OC)
L1
28 27 21
B
37
SMC_PA5
55
BI
SYS_ONEWIRE
(OC)
K3
21
OUT
PM_BATLOW_L
(OC)
L2 B8
NC 21
OUT
SMC_RUNTIME_SCI_L
C9
IN
SMC_ODD_DETECT
B9
34 7
37
SMC_PB3
A10
(See below)
37
IN
SMC_EXCARD_CP
37
IN
SMC_EXCARD_OC_L
C11
37
IN
SMC_GFX_OVERTEMP_L
A11
C10 B10
NC
OUT
SMC_FAN_0_CTL
G11
37
OUT
SMC_FAN_1_CTL
G13
37
OUT
SMC_FAN_2_CTL
F12
37
OUT
SMC_FAN_3_CTL
H13
43
IN
SMC_FAN_0_TACH
G10
37
IN
SMC_FAN_1_TACH
G12
37
IN
SMC_FAN_2_TACH
H11
37
IN
SMC_FAN_3_TACH
J13
46
IN
SMS_X_AXIS
M10
46
IN
SMS_Y_AXIS
N9
46
IN
SMS_Z_AXIS
K10
43
A
37
IN
SMC_ANALOG_ID
L8
37
IN
SMC_NB_CORE_ISENSE
M9
37
IN
SMC_NB_DDR_ISENSE
N8
37
IN
ALS_LEFT
K9
37
IN
ALS_RIGHT
L7
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
H8S2117 LGA-HF
(2 OF 3) OMIT
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
PE0 PE1 PE2 PE3 PE4 PF0
K1
SMC_CASE_OPEN
IN
37
J3
SMC_TCK
IN
37 38
K2
SMC_TDI
IN
37 38
J1
SMC_TDO
OUT
37 38
K4
SMC_TMS
IN
37 38
PF1 PF2 PF3 PF4 PF5 PF6 PF7
N5
SMC_SYS_LED
M6
SMC_LID
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
M8
PH0 PH1 PH2 PH3 PH4 PH5
E2
SMC_PROCHOT
F2
SMC_THRMTRIP
J2
SMC_PH2
A4
ALS_GAIN
K5
L5 M5
M4
OUT IN
37 37 44 55
NC NC SMC_MCP_SAFE_MODE
N4 L4
B
NC
OUT
37
37
NC NC NC =SMC_SMS_INT
IN
K8
(OC)
SMB_BSA_DATA
BI
39
K7
(OC)
SMB_BSA_CLK
BI
39
K6
(OC)
SMB_A_S3_DATA
BI
39
N6
(OC)
SMB_A_S3_CLK
BI
39
M7
(OC)
SMB_B_S0_DATA
BI
39
L6
(OC)
SMB_B_S0_CLK
BI
N7
B3 C4
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
39
OUT
37
OUT
37
OUT
37
37
NC NC
SYNC_MASTER=K24_MLB
SYNC_DATE=04/02/2009
SMC
1 C4950
DRAWING NUMBER
0.033UF
2 PLACEMENT_NOTE=PLACE C4950 CLOSE TO U4900 PIN M10 PLACEMENT_NOTE=PLACE C4951 CLOSE TO U4900 PIN N9 PLACEMENT_NOTE=PLACE C4952 CLOSE TO U4900 PIN K10
10% 16V
1
C4951
Apple Inc.
0.033UF
X5R 402
10%
2
16V X5R
10% 16V
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
X5R 402
SMC_PB3: SMC_IG_THROTTLE_L for MG systems. Otherwise, TP/NC okay (was ISENSE_CAL_EN)
8
7
SIZE
D
REVISION
C.0.0
NOTICE OF PROPRIETARY PROPERTY:
0.033UF
2
051-7982
R
1 C4952
402
A
PAGE TITLE
BRANCH
PAGE
49 OF 109 SHEET
OF
6
5
4
3
2
.
1
8
7
6
5
4
3
2
1
SMC FSB to 3.3V Level Shifting 36
SMC_BIL_BUTTON_L
36
SMC_FAN_1_CTL
36
SMC_FAN_2_CTL
36
SMC_FAN_3_CTL
NC_SMC_BIL_BUTTON_L
37 8
=PP3V3_S0_SMC
MAKE_BASE=TRUE
NC_SMC_FAN_1_CTL MAKE_BASE=TRUE
1
NC_SMC_FAN_2_CTL MAKE_BASE=TRUE
SMC Reset "Button" / Brownout Detect 36
SMC_GFX_THROTTLE_L
1
R5061
R5060 10K
100K
NC_SMC_FAN_3_CTL MAKE_BASE=TRUE
SMC_IG_THROTTLE_L
21
2
5% 1/16W MF-LF 402
2
5% 1/16W MF-LF 402 TO SMC
MAKE_BASE=TRUE
36
ESTARLDO_EN
SMC_PROCHOT_3_3_L
NC_ESTARLDO_EN
37 36 8 =PP3V3_S5_SMC 55 37 36
SMC_BC_ACOK
=CHGR_ACOK
36
CPU_PROCHOT_BUF
56
6
MAKE_BASE=TRUE
D
C5000
1
36
1
1K
CRITICAL 2
5
SMC_MANUAL_RST_L NOSTUFF
4
NC
CD NC GND
36
SMC_P41
36
SMC_NB_CORE_ISENSE
36
SMC_NB_DDR_ISENSE
OUT IN
1
SMC_RESET_L
OUT
SMC_MCP_DDR_ISENSE
70 14 10
BI
36
ALS_LEFT
SMC_CPU_FSB_ISENSE
Q5032
10%
36
16V 2
SSM3K15FV
402
D
41
SMC_MCP_VSENSE
SMC_GPU_VSENSE
6
D
SOD-VESM-HF
36
SMC_EXCARD_PWR_EN
36
SMC_RSTGATE_L
36
SMC_PB3
SOT-563
S
4
1
Q5059 SSM6N15FEAPE
40
SOT563
MAKE_BASE=TRUE
3
G
Q5060
5
CPU_PROCHOT_L_R
DMB53D0UV
MAKE_BASE=TRUE
CERM
2
5% 1/16W MF-LF 402
41
MAKE_BASE=TRUE
3
MF-LF
3.3K
1
MAKE_BASE=TRUE
0.01UF
603
41
CPU_PROCHOT_L
2
3
R5062
TO CPU
SMC_MCP_CORE_ISENSE
36 38
2
5%
2
SOT-563
TP_SMC_P41
0 1/10W
DMB53D0UV
MAKE_BASE=TRUE
402
D
Q5060
TP_SMC_P26
2
1
C5001
SMC_P26
MAKE_BASE=TRUE
MF-LF
SOT23-5-HF
1
D
1/16W
NCP303LSN
402
36
5%
U5000
10V
R5001
TP_SMC_P24 MAKE_BASE=TRUE
20%
CERM
SMC_P24
R5000
0.1uF
SILK_PART=SMC_RST
OUT
MAKE_BASE=TRUE
TP_SMC_EXCARD_PWR_EN MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
1
MAKE_BASE=TRUE
1
37 36 8 =PP3V3_S5_SMC
G
S
2 36
ALS_GAIN
36
SMC_ANALOG_ID
36
ALS_RIGHT
SMC_PROCHOT
36
IN
NC_SMC_ANALOG_ID 70 14 10
MAKE_BASE=TRUE
SOT553-5
SMC_TPAD_RST
OUT
PM_THRMTRIP_L
NC_ALS_RIGHT MAKE_BASE=TRUE
2
44 37 36 SMC_ONOFF_L
2
MAKE_BASE=TRUE
SN74LVC1G02 4
G
NC_ALS_GAIN
U5001
5 1
44 SMC_TPAD_RST_L
S
NC_SMC_PB3 MAKE_BASE=TRUE
02
3
=PP3V3_S5_SMC
D
8 36 37
3
Q5059 SSM6N15FEAPE SOT563
R5095
1
R5010
0
36
OUT
SMC_EXCARD_OC_L
1
2
EXCARD_OC_L
IN
10K
20
5% 5%
SMC AVREF Supply
S
G
5
MF-LF
MF-LF
2
402
C
4
1/16W
1/16W
SMC_THRMTRIP
402
IN
36
C
CRITICAL
36
OUT
=SMC_SMS_INT
SMS_INT_L
IN
MAKE_BASE=TRUE
VR5020 8
REF3333
=PPVIN_S5_SMCVREF
PP3V3_S5_AVREF_SMC
37 36 8
7 36
SOT23-3
=PP3V3_S5_SMC
MIN_LINE_WIDTH=0.4 mm 1
OUT
IN
2
MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
GND 1
0.01UF 10%
SMC_PA0
R5091
100K
1
2
36
SMC_PA1
R5092
100K
1
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE
16V 2
36
C5026
3
CERM 402
1
C5020
C5025
0.47UF
1
RADAR 5925345
10uF
10%
20% 6.3V
6.3V 2
44 37 36
SMC_ONOFF_L
R5070
10K
1
2
55 44 36
SMC_LID
R5071
100K
1
2
36
SMC_PH2
R5072
10K
1
2
2 CERM-X5R
X5R
402
603
R5011 0 21 GND_SMC_AVSS
MCP_SPKR
38 36 35
1
2
SMC_MCP_SAFE_MODE
IN
36 40 41
R5073
SMC_TX_L
36 38 36 35
10K
R5074
SMC_RX_L
1
100K
1
2
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
402
2
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
353S1381
353S1912
BOM OPTION
REF DES
COMMENTS:
38 36
SMC_TMS
R5077
10K
1
2
38 36
SMC_TDO
R5078
10K
1
2
38 36
SMC_TDI
R5079
10K
1
2
5%
1/16W
MF-LF
402
TABLE_ALT_ITEM
ALL
ISL60002-33, INTERSIL
38 36 55 37 36 36
B System (Sleep) LED Circuit
R5080
10K
1
2
SMC_BC_ACOK
R5087
470K
1
2
SMC_GFX_OVERTEMP_L
R5050
10K
1
2
SMC_BS_ALRT_L
R5076
100K
1
2
SMC_FAN_1_TACH
R5051
10K
1
2
36
SMC_FAN_2_TACH
R5052
10K
1
2
36
SMC_FAN_3_TACH
R5053
10K
1
2
36
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
B
36
36
36
8
SMC_TCK
5%
SMC_GPU_ISENSE
R5054
10K
1
2
SMC_NB_MISC_ISENSE
R5055
10K
1
2
SMC_ADAPTER_EN
R5085
10K
1
2
SMC_CASE_OPEN
R5086
10K
1
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
=PP5V_S3_SYSLED 36 32 21
SMC Crystal Circuit
Debug Power "Button" 36
1
R5031
R5030
523
80.6
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
2
2
C5010 2
1
SILK_PART=PWR_BTN
5X3.2-SM 2
SOD
MF-LF
402
MF-LF
402
15pF
1
Q5030
36
1
SMC_EXTAL
36 37 44
36
SMC_EXCARD_CP
R5088
10K
1
2
36
PM_SLP_S5_L
R5090
100K
1
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
63 36 21 7
NOSTUFF
402
R5016
0
0 1/10W MF-LF
MF-LF
603
603 2
2
SILK_PART=PWR_BTN
1.47K
OUT
R5089
SMC_PA5
10K
1
2
5%
5% 50V CERM 402
3
SYS_LED_ANODE
=PP3V3_S0_SMC
37 8
5%
1/10W
2
PLACE R5015,R5001 ON BOTTOM SIDE PLACE R5016 ON TOP SIDE
36 1
PM_SLP_S4_L
1
R5015 5%
C5011
2SA2154MFV-YAE
SYS_LED_L_VDIV
OUT
NOSTUFF 1
20.00MHZ 2
SMC_ONOFF_L
5% 50V CERM 402
CRITICAL
Y5010
1% 1/16W MF-LF 402
1/16W
1/16W
15pF 1
36 SMC_XTAL
SYS_LED_ILIM
R5032
5%
5%
1
34
1/16W
MF-LF
402
2
SYS_LED_L
A
SYNC_MASTER=K24_MLB
Q5033 SSM3K15FV
D
IN
DRAWING NUMBER
SMC_SYS_LED
Apple Inc. 1
G
S
A
SMC Support
SOD-VESM-HF
36
SYNC_DATE=02/04/2009
PAGE TITLE 3
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
2
SIZE
BRANCH
PAGE
50 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
LPC+SPI Connector CRITICAL LPCPLUS
J5100 55909-0374 M-ST-SM
D
=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS
38 8 8
73 36 19
BI
73 36 19
BI
73 38
IN
73 38
OUT
73 36 19
Alternate SPI ROM Support
36 19
OUT
37 36
OUT
25
IN
36 37 36
OUT
36 37 36 35
48 38 8
IN
IN OUT IN
31
LPC_AD LPC_AD SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS DEBUG_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L
D
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
LPC_CLK33M_LPCPLUS LPC_AD LPC_AD SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
IN BI BI
OUT IN IN BI
25 73 19 36 73 19 36 73
38 38 73 38 19 36
IN
19 36
OUT
36 37
OUT
36 37
OUT
36 37
OUT
36
OUT
35 36 37
OUT
18
=PP3V3_S5_ROM
R5190 1
516S0573
10K 5% 1/16W MF-LF 402 2 73 48 38 21
IN
SPI_CLK_R
C
73 48 38 21
R5191
IN
C
SPI_MOSI_R
1
10K 5% 1/16W MF-LF 402 2
LPCPLUS_NOT
R5146 0 1
SPI_MLB_CS_L
2
5% 1/16W MF-LF 402
PLACEMENT_NOTE=PLACE NEXT TO U5110
=PP3V3_S5_LPCPLUS
38 8
=PP3V3_S5_ROM
R5144
LPCPLUS 1
20K 5% 1/16W MF-LF 402 2
C5124 0.1UF
1
LPCPLUS SEL HIGH OUTPUTS TO B1(ON BOARD ROM) SEL LOW OUTPUTS TO B0 (FRANKCARD ROM)
100K 5% 1/16W MF-LF 402
21
VCC
38
U5110 SPIROM_USE_MLB MAKE_BASE=TRUE
73 21
IN
20% 10V CERM 402
NC7SB3157P6XG 6 S SC70 B1 1
2
=SPI_CS1_R_L_USE_MLB
BI
2
5
R5140
8 38 48
1
SPI_MLB_CS_L
OUT
38 4838 48
OUT
38
CRITICAL
SPI_CS0_R_L
4 A
SPI_ALT_CS_L
B0 3
Pull-up on debug card
2
GND
B
B
PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO
LPCPLUS R5156 0 73 38
OUT
SPI_ALT_CLK
1
2 5% 1/16W MF-LF 402
SPI_CLK_R
IN
21 38 48 73
SPI_MOSI_R
IN
21 38 48 73
LPCPLUS R5157 0
73 38
OUT
SPI_ALT_MOSI
1
LPCPLUS R5158
2 5% 1/16W MF-LF 402
PLACEMENT_NOT=PLACENEXT TO WHERE IT BRANCHES INTO TWO
0 73 38
IN
SPI_ALT_MISO
1
SPI_MISO
2
OUT
21 48 73
5% 1/16W MF-LF 402
A
SYNC_MASTER=K24_MLB
PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO
SYNC_DATE=02/15/2009
A
PAGE TITLE
LPC+SPI Debug Connector DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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MCP79 SMBUS "0" CONNECTIONS
4
3
2
SMC "0" SMBus Connections
1
SMC "A" SMBus Connections
D
NOTE: SMC RMT bus remains powered and may be active in S3 state
D
8 =PP3V3_S0_SMBUS_MCP_0
8 =PP3V3_S0_SMBUS_SMC_0_S0
R5200
MCP79 U1400 (MASTER)
1
1
R5201
2.0K
2.0K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
73 21 13 SMBUS_MCP_0_CLK
SO-DIMM "A"
SMC
J3100
U4900
(Write: 0xA0 Read: 0xA1)
(MASTER)
8 =PP3V3_S3_SMBUS_SMC_A_S3
R5250
=I2C_SODIMMA_SCL
27
36 SMB_0_S0_CLK
75 SMBUS_SMC_0_S0_SCL
=I2C_SODIMMA_SDA
27
36 SMB_0_S0_DATA
75 SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
1
1
R5251
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
MCP Temp
SMC
EMC1403-5: U5535
U4900
(Write: 0x98 Read: 0x99)
(MASTER)
=I2C_MCPTHMSNS_SCL
42
36 SMB_A_S3_CLK
=I2C_MCPTHMSNS_SDA
42
36 SMB_A_S3_DATA
MAKE_BASE=TRUE
73 21 13 SMBUS_MCP_0_DATA
1
1
1K 5% 1/16W MF-LF 402
R5271
TRACKPAD
1K
2
2
J5800
5% 1/16W MF-LF 402
SMBUS_SMC_A_S3_SCL
(Write: 0x90 Read: 0x91)
=I2C_TPAD_SCL
45
=I2C_TPAD_SDA
45
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R5270
SMBUS_SMC_A_S3_SDA MAKE_BASE=TRUE
SO-DIMM "B"
SENSOR ADC
J3200
U6000
(Write: 0xA2 Read: 0xA3)
(WRITE: 0X10 READ: 0X11)
1
R5203
0 MCPSMC_DIGITEMP_YES
5% 1/16W MF-LF 2 402
=I2C_SODIMMB_SCL
28
=I2C_SMC_ADCS_SCL
47
=I2C_SODIMMB_SDA
28
=I2C_SMC_ADCS_SDA
47
SENSOR ADC CAN ONLY WORK IN S0 AS IT HAS I2C BUS PULLED UP TO S0 POWER RAIL
1MCPSMC_DIGITEMP_YES
R5204
0
Mikey
5% 1/16W MF-LF 2 402
C
39 I2C_MIKEY_SCL_R
U6880
=I2C_MIKEY_SCL
39 54
=I2C_MIKEY_SDA
39 54
C 8 =PP3V42_G3H_SMBUS_SMC_BSA
MAKE_BASE=TRUE
39 I2C_MIKEY_SDA_R
SMC "B" SMBus Connections
SMC "Battery A" SMBus Connections
(WRITE: 0X72 READ: 0X73)
8 =PP3V3_S0_SMBUS_SMC_B_S0
MAKE_BASE=TRUE
1
1
R5280
SMC
5% 1/16W MF-LF 402
(MASTER)
MCP79 SMBUS "1" CONNECTIONS 36 SMB_BSA_CLK
1
R5281
1K
U4900
1K
2
2
5% 1/16W MF-LF 402
SMBUS_SMC_BSA_SCL
BATTERY
SMC
J6950
U4900
(See Table)
(MASTER)
=SMBUS_BATT_SCL
39 36 SMB_B_S0_CLK
55
MAKE_BASE=TRUE
36 SMB_BSA_DATA
R5261
2.0K
2.0K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
75 SMBUS_SMC_B_S0_SCL
CPU Temp EMC1403-5: U5515 (Write: 0x98 Read: 0x99)
=I2C_CPUTHMSNS_SCL
42
=I2C_CPUTHMSNS_SDA
42
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
8 =PP3V3_S0_SMBUS_MCP_1
1
R5260
=SMBUS_BATT_SDA
39 36 SMB_B_S0_DATA
55
MAKE_BASE=TRUE
75 SMBUS_SMC_B_S0_SDA MAKE_BASE=TRUE
MCPSMC_DIGITEMP_NO 1
MCP79
R5230
U1400
2.0K
(MASTER) (SLAVE: WRITE:0XE0 READ:0XE1)
5% 1/16W MF-LF 402
1
MCPSMC_DIGITEMP_NO
Mikey
R5231 2.0K
2
Battery Charger
U6880
5% 1/16W MF-LF 402
SMC "B" SMBUS SIGNALS ALSO GET CONNECTED TO MCP SMBUS 1 CONNECTIONS(SEE LEFT SIDE)
ISL6258A - U7000
MCPSMC_DIGITEMP_NO
R5232 0 2 1
2
73 21 SMBUS_MCP_1_CLK
5%39 I2C_MIKEY_SCL_R 1/16W MF-LF 402
73 21 SMBUS_MCP_1_DATA
(WRITE: 0X72 READ: 0X73)
Battery
=I2C_MIKEY_SCL
39 54
=I2C_MIKEY_SDA
39 54
(Write: 0x12 Read: 0x13)
Battery Manager - (Write: 0x16 Read: 0x17)
=SMBUS_CHGR_SCL
56
=SMBUS_CHGR_SDA
56
Battery Temp - (Write: 0x90 Read: 0x91)
R5233 0 2 1
39 I2C_MIKEY_SDA_R
5% 1/16W MF-LF 402 MCPSMC_DIGITEMP_NO
B
B
SMC "Management" SMBus Connections 1MCPSMC_DIGITEMP_YES
The bus formerly known as "Battery B"
R5235
0
8 =PP3V3_S3_SMBUS_SMC_MGMT
5% 1/16W MF-LF 2 402
R5234
U4900
0 MCPSMC_DIGITEMP_YES
R5290
SMC
1
5% 1/16W MF-LF 2 402
(MASTER)
SMC
36 SMB_MGMT_CLK
75 SMBUS_SMC_MGMT_SCL
36 SMB_MGMT_DATA
75 SMBUS_SMC_MGMT_SDA
1
1
R5291
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
Vref DACs U2900 (Write: 0x98 Read: 0x99)
=I2C_VREFDACS_SCL
26
=I2C_VREFDACS_SDA
26
MAKE_BASE=TRUE
U4900
MAKE_BASE=TRUE
(MASTER)
SMC "B" SMBUS SMB_B_S0_CLK
36 39
SMB_B_S0_DATA
36 39
Margin Control U2901 (Write: 0x30 Read: 0x31)
=I2C_PCA9557D_SCL
26
=I2C_PCA9557D_SDA
26
MCP SMBUS1 ACTS AS SLAVE DEVICE FOR MCPSMC_DIGITEMP_YES STUFFED
A
SYNC_MASTER=K24_MLB
SYNC_DATE=01/19/2009
A
PAGE TITLE
K84 SMBUS CONNECTIONS DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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CPU Voltage Sense / Filter XW5309 8
=PPVCORE_S0_CPU_VSENSE
R5309
SM
4.53K 1
2
CPUVSENSE_IN
1
SMC_CPU_VSENSE
2
PLACEMENT_NOTE=Place near U1000 center
OUT
36
1% 1/16W 1
MF-LF 402
C5309 0.22UF 20% 6.3V
2
D
X5R 402
GND_SMC_AVSS
D
36 37 40 41
Place RC close to SMC
MCP Voltage Sense / Filter XW5359 8
=PPVCORE_S0_MCP_VSENSE
R5359
SM
4.53K 1
2
MCPVSENSE_IN
1
SMC_MCP_VSENSE
2
PLACEMENT_NOTE=Place near U1400 center
OUT
37
1% 1/16W MF-LF
1
402
C5359 0.22UF 20% 6.3V
2
X5R 402
GND_SMC_AVSS
36 37 40 41
Place RC close to SMC
C
C PBUS VOLTAGE SENSE ENABLE & FILTER
Q5315 NTUD3169CZ SOT-963
N-CHANNEL
6
PBUSVSENS_EN_L
D 1
R5316 63
IN
2
=PBUSVSENS_EN
100K
G
1%
S
Enables PBUS VSense
1/16W MF-LF 402
1
divider when high.
3
2
PPBUS_G3HRS5_VSENSE MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=18.5V
D
1
R5385 5 8
27.4K
G
1%
S
=PPBUS_G3HRS5
1/16W MF-LF 402
4
2
RTHEVENIN = 4573 OHMS
P-CHANNEL
B
R5315
SMC_PBUS_VSENSE
36
B
1
R5386
1% 1/16W
1
5.49K
MF-LF 402
OUT
1
100K
0.22UF
1%
20% 6.3V
1/16W MF-LF
2
402
PBUSVSENS_EN_L_DIV
C5385
2 2
X5R 402
GND_SMC_AVSS
36 37 40 41
Place RC close to SMC
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
VOLTAGE SENSING DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
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MCP VCore Current Sense Filter R5416 4.53K 60
1
MCPCORES0_IMON
2
SMC_MCP_CORE_ISENSE
OUT
37
1% 1/16W MF-LF
1
C5472
402
0.22UF 20% 6.3V 2
D
X5R
D
402
GND_SMC_AVSS
36 37 40 41
Place RC close to SMC
MCP MEM VDD Current Sense
=PP3V3_S0_MCPDDRISNS
8
64
IN
64
IN
P1V5_S0_KELVIN
MEM_SENSE P1V5_S0_SENSE
MEM_SENSE
U5400 5
1 1
R5410
2
5% 1/16W MF-LF 402
Gain: 50x
R5417 4.53K 1
MEM_SENSE R5411
2SA2154MFV-YAE SOD
1
SMC_MCP_DDR_ISENSE
1
37
C5435
402
0.22UF
C
20% 6.3V 2
X5R 402
P1V5_S0_SENSE_C GND_SMC_AVSS
1
OUT
MEM_SENSE
1/16W MF-LF
P1V5_S0_SENSE_AMP
2 5% 1/16W MF-LF 402
3
2 1%
0
P1V5_S0_SENSE_B
1
C
MCP MEM VDD Current Sense Filter MEM_SENSE
Q5401 MEM_SENSE
20% 10V CERM 402
2
2
10% 16V X5R 402
P1V5_S0_SENSE_E
2
2
3
0.1UF 1
C5400 0.1uF
4
MEM_SENSE C5434
0
MEM_SENSE
1
OPA348 SC70-5
36 37 40 41
Place RC close to SMC
R5412 118
2
1% 1/16W MF-LF 402
MEM_SENSE
CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE =PP3V3_S0_CPUVTTISNS 1
R5492 0.01 1W
2
MF 0612-1
8
IN
=PPCPUVCORE_VTT_ISNS_R
1
2
3
4
=PPCPUVCORE_VTT_ISNS
OUT
CPU VCore Load Side Current Sense / Filter
C5417 0.1uF
1P05_HIGH_SIDE_SENSE
0.5%
1P05_HIGH_SIDE_SENSE
20% 10V CERM 402
Place RC close to SMC
3
8
1P05_HIGH_SIDE_SENSE
R5471
V+
8
6.19K
1P05_HIGH_SIDE_SENSE
U5402 5
IN-
76 ISNS_CPUVTT_P
4
IN+
SC70
59
IN
IMVP6_IMON
R5418
INA213 76 ISNS_CPUVTT_N
OUT
CPUVTT_IOUT
1
1
SMC_CPU_FSB_ISENSE
OUT
37
MF-LF 402
1P05_HIGH_SIDE_SENSE
R5480
1
1
36
C5470 0.22UF
17.4K
20%
1/16W MF-LF
1
OUT
1/16W
2 1%
REF
SMC_CPU_ISENSE
2
1%
4.53K
6
1
C5436
1% 1/16W
0.22UF
MF-LF 402
X5R
402 20% 6.3V
GND 2
2
6.3V 2 402
2
GND_SMC_AVSS
36 37 40 41
X5R 402
GND_SMC_AVSS
B
36 37 40 41
B
Place RC close to SMC
DC-IN (AMON) CURRENT SENSE
DC-IN (BMON) CURRENT SENSE R5401
R5481
4.53K 56
IN
CHGR_BMON
1
4.53K
SMC_BATT_ISENSE
2
OUT
36
56
IN
CHGR_AMON
1% 1/16W MF-LF
SMC_DCIN_ISENSE
2
OUT
36
1% 1/16W
1
402
C5490
MF-LF
1
402
0.22UF 2
20% 6.3V
C5487 0.22UF
2
X5R 402
GND_SMC_AVSS 36 37 40 41
A
1
20% 6.3V X5R 402
GND_SMC_AVSS
PLACE R5401 AND C5490 CLOSE TO SMC
36 37 40 41
SYNC_MASTER=K24_MLB
SYNC_DATE=01/27/2009
A
PAGE TITLE
Current Sensing DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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CPU T-Diode Thermal Sensor INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE 8
R5515
=PP3V3_S0_CPUTHMSNS
47 1
PP3V3_S0_CPUTHMSNS_R
2
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
5% 1/16W MF-LF 402
D 76 10
BI
APN 353S2571
C5521 0.0022uF
3 DN1
10% 50V CERM 402
BI
2
DFN 2 DP1
1
R5516
C5515
THERM*/ADDR
CRITICAL
1
1
10K
0.1uF
EMC1413 SIGNAL_MODOL=EMPTY
76 10
1
U5515
CPU_THERMD_P
DETECT CPU DIE TEMPERATURE
1 VDD
1% 1/16W MF-LF 402
20% 10V CERM 402
7
CPUTHMSNS_THERM_L
D
R5517 10K
2
2
5% 1/16W MF-LF 402
ALERT*
8
CPUTHMSNS_ALERT_L
4 DP2/DN3
SMDATA
9
=I2C_CPUTHMSNS_SDA
BI
39
5 DN2/DP3 GND 6
SMCLK
10
=I2C_CPUTHMSNS_SCL
BI
39
2
CPU_THERMD_N
THRM_PAD 11
76 CPUTHMSNS_D2_P 3
SIGNAL_MODOL=EMPTY
Q5501 DETECT FIN-STACK TEMPERATURE
PLACEMENT NOTE: PLACE U5515 NEAR CPU
1
C5520
1
0.0022uF
BC846BMXXH
10% 50V CERM 402
SOT732-3 2
2
76 CPUTHMSNS_D2_N
C
C
MCP T-Diode Thermal Sensor INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
MCP_T_DIODE_SENSOR 8
R5535
=PP3V3_S0_MCPTHMSNS
MCP_T_DIODE_SENSOR
47 1
2 5% 1/16W MF-LF 402
PP3V3_S0_MCPTHMSNS_R MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
MCP_T_DIODE_SENSOR
MCP_T_DIODE_SENSOR
APN 353S2571 1
1
VDD 76 21
C5522
B
76 21
DFN
1
0.0022uF 10% 50V CERM 402
2 DP1 3 DN1
THERM*/ADDR
CRITICALALERT*
20% 10V CERM 402
7
MCPTHMSNS_THERM_L
8
MCPTHMSNS_ALERT_L
1
1
R5536
R5537
10K 1% 1/16W MF-LF 402
10K
2
2
5% 1/16W MF-LF 402
MCP_T_DIODE_SENSOR
2
MCP_THMDIODE_N
BI
2
EMC1413 SIGNAL_MODOL=EMPTY
DETECT MCP DIE TEMPERATURE
0.1uF
U5535
MCP_THMDIODE_P
BI
C5535
MCP_T_DIODE_SENSOR
4 DP2/DN3
SMDATA
9
=I2C_MCPTHMSNS_SDA
BI
39
5 DN2/DP3 GND 6
SMCLK
10
=I2C_MCPTHMSNS_SCL
BI
39
B
THRM_PAD 11
MCP_T_DIODE_SENSOR 76 MCPTHMSNS_D2_P SIGNAL_MODOL=EMPTY
3
C5540
1
PLACEMENT NOTE: PLACE U5535 NEAR MCP
0.0022uF
1
Q5502
10% 50V CERM 402
DETECT HEAT-PIPE TEMPERATURE
BC846BMXXH SOT732-3
2
2
76 MCPTHMSNS_D2_N
MCP_T_DIODE_SENSOR
PLACEMENT_NOTE=PLACE CLOSE TO J4501 IN A CONVENIENT LOCATION
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/04/2009
A
PAGE TITLE
Thermal Sensors DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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D
D
8
=PP5V_S0_FAN_RT
8
=PP3V3_S0_FAN_RT CRITICAL
R5660 1
C
47K 5% 1/16W MF-LF 402
R5665 36
1
SMC_FAN_0_TACH
47K 2
7
J5601
C
78171-0004 NC
M-RT-SM 5
2 1
FAN_RT_TACH
2
5V DC TACH
3
5% 1/16W MF-LF 402
4
NC
MOTOR CONTROL GND
6
R5661 1
36
518S0521
G
SSM3K15FV 7
FAN_RT_PWM
3
D
SOD-VESM-HF 2
SMC_FAN_0_CTL
Q5660
2 S
1/16W MF-LF 402
1
100K 5%
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
Fan DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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KEYBOARD CONNECTOR PIN NAME
CURRENT
R_SNS
V_SNS
POWER
10UA
2.55 KOHM
0.0255 V
0.255E-6 W
0.204 V
16.32E-6 W
TMP102
V+
3V3 LDO
VDD
60MA MAX
VOUT
60MA MAX
80UA
USB INTERFACES TO MLB
TRACKPAD PICK BUTTONS
SPI HOST TO Z2
KEYBOARD SCANNER
D
PSOC
VDD
18V BOOSTER
VIN
10 OHM
8MA (TYP)
0.6 V
0.2 OHM
0.012 V
1.5 OHM
0.012 V
14MA (MAX)
PP3V3_S3_PSOC
45 7 45 7
PSOC_F_CS_L
45 7
PSOC_MOSI
45 7
PSOC_SCLK
45 7
Z2_MISO
45 7
Z2_CS_L
45 7
Z2_MOSI
45 7
Z2_SCLK
44
44
44
44
44
44
7
7
7
7
7
7
4MA (MAX)
4.7 OHM
WS_KBD18
U5701 CY8C24794 MLF
(SYM-VER2) APN 337S2983 OMIT
113
P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 THRML PAD
WS_KBD17
7 44
41
WS_KBD16N
44
44 WS_KBD15_C
1
2
WS_KBD1
44 7
WS_KBD2
44 7
WS_KBD3
44 7
WS_KBD4
44 7
WS_KBD5
44 7
WS_KBD6
44 7
WS_KBD7
44 7
WS_KBD8
44 7
WS_KBD9
44 7
WS_KBD10
44 7
WS_KBD11
44 7
WS_KBD12
44 7
WS_KBD13
44 7
WS_KBD14
40
WS_KBD15_C
39
WS_KBD14
7 44
WS_KBD13
7 44
38 37
WS_KBD12
36
WS_KBD11
35
26 25 24 23 22 21 20 19 18 17 16 15
7 WS_KBD15_CAP
402
14
7 WS_KBD16_NUM 13
44 7
WS_KBD17
R5715
44 7
WS_KBD18
10K
44 7
WS_KBD19
44 7
WS_KBD20
44 7
WS_KBD21
44 7
WS_KBD22
44 7
WS_KBD23
7 44 7 44
WS_KBD10
44 WS_KBD16N
7 44
WS_KBD9
7 44
33
WS_KBD8
7 44
1
WS_KBD7 WS_KBD1
7 44
WS_KBD2
7 44
R5710
37 36
OUT
9 8 7 6
1K
SMC_ONOFF_L
1
7 WS_KBD_ONOFF_L
2
5
44 8 =PP3V42_G3H_TPAD
5%
WS_KBD3
10
MF-LF
7 44
30
11
2
402
31
12
1% 1/16W
29
27
MF-LF
44
34
32
28
1% 1/16W
4
1/16W
7 44
44 7 WS_LEFT_SHIFT_KBD
MF-LF
1
57
2
C5710
44 7 WS_LEFT_OPTION_KBD
0.1UF
44 7 WS_CONTROL_KBD
20% 10V CERM
2 1
402
WS_KBD4
7 44
WS_KBD5
7 44
WS_KBD6
7 44
31 F-RT-SM
FF14-30A-R11B-B-3H C5725 0.1UF
=PP3V42_G3H_TPAD
2
44 8
1
SMC_MANUAL_RESET LOGIC
TP_PSOC_SDA TP_ISSP_SDATA_P1_0
20%
CRITICAL
5
ISSP SDATA/I2C SDA 44 8
=PP3V3_S3_TPAD
2
WS_LEFT_SHIFT_KBD
1
10V CERM
TC7SZ08AFEAPE SOT665
402
A
44 8
WS_LEFT_SHIFT_KEY
4
TP_PSOC_P1_3 Z2_CLKIN
NC
PLACEMENT_NOTE=NEAR J5713
ISOLATION CIRCUIT
C
3
402
TP_PSOC_SCL
D
29
44 7 75.2E-6 W
R5714 42
32
30
294E-6 W
0.0188 V
43
WS_KBD19 44
WS_KBD20 45
WS_KBD21
WS_KBD22
46
47
49
50
51
CRITICAL
15
C
Z2_DEBUG3
PSOC_MISO
48
WS_KBD23 NC
Z2_RESET
52
2
Z2_KEY_ACT_L
45 7
P2_5 P2_7 P0_1 P0_3 P0_5 P0_7 VSS VDD P0_6 P0_4 P0_2 P0_0 P2_6 P2_4
P2_3 P2_1 3 P4_7 4 P4_5 5 P4_3 6 P4_1 7 P3_7 8 P3_5 9 P3_3 10 P3_1 11 P5_7 12 P5_5 13 P5_3 14 P5_1
WS_CONTROL_KEY
TP_P4_5 45 7
0.021 V
44
P1_7 P1_5 P1_3 18 P1_1 19 VSS 20 D+ 21 D22 VDD 23 P7_7 24 P7_0 25 P1_0 26 P1_2 27 P1_4 28 P1_6
44
1
55
44
WS_LEFT_OPTION_KEY
56
WS_LEFT_SHIFT_KEY
53
Z2_HOST_INTN
44
45 7
NC =PP3V3_S3_TPAD
IN
96E-6 W
BUTTON_DISABLE
54
45 7
APN 518S0637
36E-3 W 0.72E-3 W
17
44
PICKB_L
16
45 7
CRITICAL
J5713
44 8
IC
PSOC USB CONTROLLER
U5725
7 45 44 7
=PP3V42_G3H_TPAD 1
44
Y
C5758 0.1UF
B 2
3
10% 16V X7R-CERM 402
TP_P7_7 TP_ISSP_SCLK_P1_1 ISSP SCLK/I2C SCL
C5726 0.1UF
=PP3V42_G3H_TPAD
2
44 8
1
APN 311S0406 5
R5701 44 8
24 USB_TPAD_P
73 20
1
=PP3V3_S3_TPAD
CRITICAL
10V
TC7SZ08AFEAPE
2
5
CERM 402
SOT665
A
2 73 USB_TPAD_R_P
WS_LEFT_OPTION_KEY
4 44
44 7
1/16W MF-LF 402
WS_LEFT_OPTION_KBD
1
44
Y
U5726
PP3V3_S3_PSOC
5%
B
20%
CRITICAL
DIFFERENTIAL_PAIR=USB2_TPAD
B
44 7 WS_LEFT_SHIFT_KBD
1
44 7 WS_LEFT_OPTION_KBD
3
WS_CONTROL_KBD
6
44 7
B
SN74LVC1G10 SC70
A
4 U5703
37
Y SMC_TPAD_RST_L
C
3
B
2
TO MLB CONNECTOR
R5702 24 USB_TPAD_N
73 20
1
2 73 USB_TPAD_R_N
C5727 5%
1
R5769
0.1UF
1/16W MF-LF 402
=PP3V42_G3H_TPAD
2
44 8
20%
CRITICAL
5
=PP3V3_S3_TPAD
2
10V CERM
TC7SZ08AFEAPE SOT665
A
1
R5771
33K
33K
WS_CONTROL_KEY
Y
U5727
WS_CONTROL_KBD
1
2
5%
1/16W MF-LF 402 2
5%
1/16W MF-LF 402
1/16W MF-LF 402 2
402
4 44 7
R5770
5%
DIFFERENTIAL_PAIR=USB2_TPAD
44 8
1
33K
1
44
B 3
U5701 CHIP DECOUPLING
Alternate Parts
PLACE C5701, C5702 & C5703
PLACE C5704, C5705 & C5706
CLOSE TO U5701
CLOSE TO U5701
TABLE_ALT_HEAD
VDD PIN 22
VDD PIN 49
PART NUMBER
ALTERNATE FOR PART NUMBER
311S0406
311S0447
TPAD BUTTONS DISABLE
BOM OPTION
REF DES
COMMENTS: TABLE_ALT_ITEM
ALL
NXP PART AS ALTERNATE
R5704 =PP3V3_S3_TPAD
1.5 44
PP3V3_S3_PSOC
1
MIN_LINE_WIDTH=0.50MM
2
44
BUTTON_DISABLE
PLACE THESE COMPONENTS CLOSE TO J5800
8 44
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
MIN_NECK_WIDTH=0.20MM
1
C5701
1
4.7UF 2
C5702
1
100PF
20% 6.3V X5R 603
2
5% 50V CERM 402
C5703
1
0.1UF 2
10% 16V X7R-CERM 402
C5704
1
100PF 2
5% 50V CERM 402
C5705
1
0.1UF 2
10% 16V X7R-CERM 402
C5706
5% 1/16W MF-LF 402
4.7UF 2
Q5701
20% 6.3V X5R 603
SSM3K15FV
D
3
SOD-VESM-HF
A
SYNC_MASTER=K24_MLB PLACEMENT_NOTE=PLACE C5702 CLOSE TO U5701 VDD PIN 22
PLACEMENT_NOTE=PLACE C5704 CLOSE TO U5701 VDD PIN 49
SMC_LID 55 37 36
G
S
2
SYNC_DATE=03/04/2009
A
PAGE TITLE
THE TPAD BUTTONS WILL BE DISABLE 1
WELLSPRING 1
WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V
DRAWING NUMBER
IN LID CLOSE => SMC_LID_LC < 0.50V
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
57 OF 109 SHEET
OF
8
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6
5
4
3
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8
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1
BOOSTER +18.5VDC FOR SENSORS BOOSTER DESIGN CONSIDERATION: - POWER CONSUMPTION - DROOP LINE REGULATION - RIPPLE TO MEET ERS - 100-300 KHZ CLEAN SPECTRUM - STARTUP TIME LESS THAN 2MS
D
45 8
=PP5V_S3_TPAD
D
- R5812,R5813,C5818 MODIFIED
APN 152S0504
CRITICAL CRITICAL
L5801
D5802
3.3UH-870MA
R5806
0
5% 1/16W MF-LF 402
R5805
2
SOD-323
INPUT_SW
1
MIN_LINE_WIDTH=0.50MM
2
PP18V5_S3
IPD FLEX CONNECTOR
7 45
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
5%
MIN_NECK_WIDTH=0.20MM
0.20MM
0
PP18V5_S3_SW
BOOST_SW VLF3010AT-SM-HF
0.50MM
1/16W
B0520WSXG
MF-LF
SWITCH_NODE=TRUE
1
APN 371S0313
402
1 1
PP5V_S3_BOOSTER
MIN_LINE_WIDTH=0.50MM
R5812
C5818 39PF
MIN_NECK_WIDTH=0.20MM 5% 50V
2
2
CERM
APN 353S1401
APN 516S0689
1M
2
402
1% 1/16W MF-LF 402
CRITICAL
J5800 55560-0228
VIN
0.50MM
1
U5805
L
1 1
FB
10%
TPS61045
C5800
2
QFN
3
0.1UF
DO
CTRL
C5819
5
Z2_BOOST_EN
44 7
25V
10V
2
CRITICAL
CERM
2.2UF 10%
PGND
GND
C5817
10%
6
1
0.1UF
9
C5816
7
PAD 1
1
4
3
6
5
8
7
Z2_KEY_ACT_L
7 44
Z2_RESET
7 44
PSOC_F_CS_L
7 44
1
SW
402
THRML
2
44 7 Z2_MOSI
44 7 Z2_DEBUG3
603-1
7 45
Z2_CS_L
X5R
20%
PLACEMENT_NOTE=NEAR J5800
M-ST-SM
1UF
BOOST_FB
4
0.20MM
R5813
8
1% 1/16W
1
MF-LF
R5811
402
10
9
12
11
PSOC_MISO
45 7 Z2_BOOST_EN
14
13
PSOC_MOSI
16
15
PSOC_SCLK
18
17
=I2C_TPAD_SDA
20
19
22
21
44 7 Z2_HOST_INTN
2
100K
Z2_MISO
44 7 Z2_SCLK
44 7
71.5K
1%
NC
PICKB_L
7 44 7 44 7 44 7 44 39
1/16W
2
16V X7R-CERM 402
2
16V MF-LF
X5R
2
603
402
44 7
Z2_CLKIN
45 7
PP3V3_S3_LDO
=I2C_TPAD_SCL
0.50MM
0.50MM
0.20MM
0.20MM
39
PP18V5_S3
7 45
C
C
3V3 LDO FOR IPD
R5873 =PP5V_S3_TPAD 45 8
10 1
2
PP5V_S3_VR
1% 1/16W MF-LF 402
PP3V3_S3_LDO
45 7
VR5802
2.2UF
MM3243DRRE
10% 16V
2
MF
402-HF
1%
1/6W
1
0.1UF
1
CE
VOUT
3
PP3V3_S3_LDO_R
C5854 4.7UF
10%
2
MLF
1
C5838
20%
16V
6.3V
2
X7R-CERM 402
X5R 603
GND
B
4
B
X5R 603
0.2
2
C5853
1
1
R5836
2
CRITICAL
APN 353S1364
VDD
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/25/2009
A
PAGE TITLE
WELLSPRING 2 DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
58 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
D
D
C
C
Analog SMS
R5921 PULLS UP SEL PINS TO ENTER STANDBY MODE WHEN PIN IS NOT BEING DRIVEN BY SMC
R5922 1
2
PP3V3_S3_SMS_FILT
5% 1/16W MF-LF 402
=PP3V3_S3_SMS
1 2
8
10
1
VDD R5921 5% 1/16W MF-LF 402
B 36
IN
SMS_ONOFF_L
2
BMA141
10K
LGA 2
NC
7
AMUX
11
AX
10
10% 16V X5R 402
1 C5926 0.01UF
2
10% 16V CERM 402
Desired orientation when placed on board top-side:
NC
B
DNC CRITICAL
12 6
SMS_PWRDN MAKE_BASE=TRUE
C5922 0.1UF
U5920
1
SMS_X_AXIS
OUT
36
SEL0 SEL1
AY
9
SMS_Y_AXIS
OUT
36
ST
AZ
8
SMS_Z_AXIS
OUT
36
+Y Front of system
5
+X +Z (up)
3 4
GND
1
NOSTUFF C5923
NOSTUFF 1 C5924
0.033UF 2
10% 16V X5R 402
NOSTUFF 1 C5925 0.033UF
0.033UF
2
10% 16V X5R 402
2
Circle indicates pin 1 location when placed
10% 16V X5R 402
in correct orientation
C4950-C4952 CAP VALUES WILL BE USED TO GET CUT-OFF FREQUENCY OF ~146HZ
A
A PAGE TITLE
SMS DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
59 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
DEBUG_ADC
DEBUG_ADC
R6003
PP3V3_WLAN_F_XW
34 7
1
PP5V_SW_ODD
2
D
R6020
1% 1/16W MF-LF 2 402
R6012
PP3V3_WLAN_F_DIV DEBUG_ADC
226K
1
ADC_CH0
2
1% 1/16W MF-LF 402
1
R6011
DEBUG_ADC 1
2
47
DEBUG_ADC 1
47
C6022
47
2.2UF
1% 1/16W MF-LF 402
2
10% 6.3V X5R 402
47 47
47
DVDD
ADC_CH0 ADC_CH1 ADC_CH2 ADC_CH3 ADC_CH4 ADC_CH5 ADC_CH6 ADC_CH7
22
5
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
6
COM
23 24 1 2 3 4
R6001
QFN
DEBUG_ADC
AD0 AD1
14
I2C ADDRESS: 0X10 / 0X11
SDA SCL
17 16
VREF
7
REFCOMP
8
ADC_SDA ADC_SCL
DEBUG_ADC
ISNS_AIRPORT_P
243 1
2
76
3
+IN
10UF
20% 10V CERM 402
20% 6.3V X5R 603
ISNS_AIRPORT_N
243 1
2
76
76 34
ISNS_AIRPORT_IOUT
1
226K
2
ADC_CH2
47
DEBUG_ADC 1
2
R6032
76 34
2
1
1
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
47 8
DEBUG_ADC
OPA330 4
ISNS_ODD_IOUT
2
76
2
ADC_CH4
10% 50V CERM 402
R6052 280K
2 2
10% 6.3V X5R 402
DEBUG_ADC
DEBUG_ADC 1 1
470PF
C6033
C6054 2.2UF
2
DEBUG_ADC
47
DEBUG_ADC 1
1% 1/16W MF-LF 402
2
R6053 1
1% 1/16W MF-LF 402
280K
2
DEBUG_ADC
1% 1/16W MF-LF 402
C6053
470PF
470PF
1
1
2
2 10% 50V CERM 402
=PP5V_S3_DEBUG_ISNS DEBUG_ADC 1
3.65K 1
2
76
20% 10V 2 CERM 402
DEBUG_ADC
ISNS_1V5_S3_R_P 5
1
DEBUG_ADC
3
R6041
0.1UF 20% 10V
V+
-IN
V-
76
DEBUG_ADC
SC70-5
R6044
R6060
4
226K
412
ISNS_1V5_S3_IOUT
1
2
ADC_CH3
1% 1/16W MF-LF 402
GAIN: 273X
ISNS_1V5_S3_R_N
1
IN
ISNS_HDD_P
1
2
76
ISNS_HDD_R_P
DEBUG_ADC
5
1
R6043
1M 2 2
1M
1
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
3
R6061 76 34
R6042
470PF
DEBUG_ADC
DEBUG_ADC
DEBUG_ADC 1 1
10% 6.3V X5R 402
IN
+IN
V+
1
2
DEBUG_ADC
OPA330
R6064
SC70-5
4
ISNS_HDD_IOUT
76
1
GAIN: 845X
ISNS_HDD_R_N
226K
2
ADC_CH5
1% 1/16W MF-LF 402
V-
-IN
2
412
ISNS_HDD_N
PLACEMENT_NOTE=PLACE RC NEAR U6000
U6041
1% 1/16W MF-LF 402
C6044
B
DEBUG_ADC
2.2UF 2
10% 50V CERM 402
76 34
47
DEBUG_ADC
1% 1/16W MF-LF 402
C6042
402
DEBUG_ADC
OPA330
2
3.65K 2
+IN
C6041
2 CERM
PLACEMENT_NOTE=PLACE RC NEAR U6000
U6031
1% 1/16W MF-LF 402
1
DEBUG_ADC 1
C6031 0.1UF
R6040
ISNS_1V5_S3_N
226K 1% 1/16W MF-LF 402
GAIN: 561X
ISNS_ODD_R_N
C6052
DEBUG_ADC
ISNS_1V5_S3_P
1
V-
-IN
C
R6054
SC70-5
V+ 2
499
ISNS_ODD_N
IN
10% 6.3V X5R 402
DEBUG_ADC
301K
+IN
3
R6033
301K 2
1
R6051
C6034
PLACEMENT_NOTE=PLACE RC NEAR U6000
U6040 5
10% 50V CERM 402
2
DEBUG_ADC
1
2.2UF
DEBUG_ADC
DEBUG_ADC 1
C6062
2
10% 50V CERM 402
R6063
348K 2 2
10% 6.3V X5R 402
DEBUG_ADC
R6062
1
470PF
10% 50V CERM 402
C6064
2
C6043
47
DEBUG_ADC 1
1% 1/16W MF-LF 402
470PF
1
1% 1/16W MF-LF 402
348K 1% 1/16W MF-LF 402
PLACEMENT_NOTE=PLACE NEAR D9710
2
DEBUG_ADC
C6063 470PF
OMIT
1
2
XW6080
=PP5V_S3_DEBUG_ISNS 1
SM
PPVOUT_S0_LCDBKLT
DEBUG_ADC
1
68 65 7
C6050 0.1UF
2
3
A IN-
SC70
ISNS_LCDBKLT_IOUT
6
ISNS_LCDBKLT_P
4
IN+
REF
1
GAIN: 200X
1
226K
ADC_CH6
2
1% 1/16W MF-LF 402
47
1
C6074 2.2UF
GND 2
2
SYNC_MASTER=K19_IMLB
R6082 1
226K
2
1% 1/16W MF-LF 402
R6081
10% 6.3V X5R 402
2
2
DIVIDER: 1/22
A
DEBUG SENSORS AND ADC
DEBUG_ADC 1
DRAWING NUMBER
C6082
Apple Inc.
2.2UF
1% 1/16W MF-LF 402
SYNC_DATE=02/25/2009
PAGE TITLE
ADC_CH7
47.0K
DEBUG_ADC 1
DEBUG_ADC
PPVOUT_S0_LCDBKLT_DIV DEBUG_ADC
R6074
DEBUG_ADC
PLACEMENT_NOTE=PLACE RC NEAR U6000
1% 1/16W MF-LF 2 402
DEBUG_ADC
OUT
R6080 1M
PLACEMENT_NOTE=PLACE RC NEAR U6000
INA210 5
10% 50V CERM 402
PPVOUT_S0_LCDBKLT_XW
1
U6050 ISNS_LCDBKLT_N
2
DEBUG_ADC
20% 10V CERM 402
V+
IN
20% 6.3V CERM 402-LF
20% 10V CERM 402
DEBUG_ADC
ISNS_ODD_R_P
DEBUG_ADC
DEBUG_ADC 1 10% 50V CERM 402
76
DEBUG_ADC
2.2UF
470PF
2 1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
GAIN: 1239X
1
1
R6034
ISNS_AIRPORT_R_N
C6032
499
ISNS_ODD_P
IN
DEBUG_ADC
4
V-
-IN
PLACEMENT_NOTE=PLACE RC NEAR U6000
2
DEBUG_ADC
76 68
2.2UF 2
0.1UF
R6050
1% 1/16W MF-LF 402
IN
2
C6006
C6040
2
SC70-5
V+
R6031
76 68
39
DEBUG_ADC 1
C6005
0.1UF
DEBUG_ADC
OPA330
5
1
DEBUG_ADC
47 8
DEBUG_ADC 1
C6004
25
20
19
18
9
11
10
1
20% 10V CERM 402
U6030
ISNS_AIRPORT_R_P
1% 1/16W MF-LF 402
C
2
DEBUG_ADC
R6030
IN
IN
DEBUG_ADC
C6030 0.1UF
76 58
=I2C_SMC_ADCS_SCL
5% 1/16W MF-LF 402
ADC_REFCOMP DEBUG_ADC
DEBUG_ADC
IN
PLACEMENT_NOTE=PLACE CLOSE TO U4900
2
=PP5V_S3_DEBUG_ISNS 1
B
R6002 33
2
39
BI
DEBUG_ADC
ADC_VREF
LSB: 0.001V
76 58
=I2C_SMC_ADCS_SDA
1
1
D
PLACEMENT_NOTE=PLACE CLOSE TO U4900
2
5% 1/16W MF-LF 402
THRM PAD
GND
ADC RANGE: 0V TO 4.096V
IN
20% 6.3V X5R 603
33 1
15
DIVIDER: ~ 2/5
76 30
8
DEBUG_ADC
LTC2309
DIVIDER: ~ 2/3
IN
C6003
=PP5V_S3_DEBUG_ADC_DVDD
10UF 2
U6000
47
76 30
1
20% 10V CERM 402
2
47
47
47 8
C6002 0.1UF
20% 6.3V X5R 603
AVDD ADC_CH1
2
681K
10% 6.3V X5R 402
2
226K 1% 1/16W MF-LF 402
R6021
2.2UF
1% 1/16W MF-LF 402
1
10UF
R6022 1
1
C6012
1M
C6001
2
DEBUG_ADC
2
5% 1/16W MF-LF 402
DEBUG_ADC
PP5V_SW_ODD_DIV DEBUG_ADC
47
1
20% 10V CERM 402
PLACEMENT_NOTE=PLACE RC NEAR U6000
1M
DEBUG_ADC
C6000
10
1
DEBUG_ADC
12
PLACEMENT_NOTE=PLACE RC NEAR U6000
1% 1/16W MF-LF 402
2
2
1
R6010
DEBUG_ADC
0.1UF
DEBUG_ADC
1
2
1
PP5V_SW_ODD_XW
DEBUG_ADC 634K
DEBUG_ADC
PP5V_S3_DEBUG_ADC_DVDD_FILT
21
SM 2
R6004 PP5V_S3_DEBUG_ADC_AVDD_FILT
2
5% 1/16W MF-LF 402
XW6020
SM 1
10
1
OMIT
XW6010 PP3V3_WLAN_F
8
13
OMIT
30
=PP5V_S3_DEBUG_ADC_AVDD
PLACEMENT_NOTE=PLACE NEAR Q4590
PLACEMENT_NOTE=PLACE NEAR Q3450
10% 6.3V X5R 402
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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D
D
38 8
=PP3V3_S5_ROM
R61901
R6100 1
10K
R6150 73 38 21
IN
IN
5% 1/16W MF-LF 402 2
R6101 3.3K
1
20% 10V CERM 402
1
C
CRITICAL
VCC
U6100
2
32MBIT
R6152
SOP
2
73
SPI_CLK
5% 1/16W MF-LF 402
SPI_MLB_CS_L
C6100 0.1UF
5% 1/16W MF-LF 2 402
0
SPI_CLK_R
PLACEMENT_NOTE=PLACE CLOSE TO U6100 38
1
3.3K
5% 1/16W MF-LF 402 2
8
NO STUFF
C
6
SCLK
SI/SIO0
5
73
0
SPI_MOSI
1
MX25L3205DM2I-12G 1
SPI_WP_L SPI_HOLD_L
3 7
CE* WP*/ACC HOLD*
R6105
OMIT SO/SIO1
2
73
SPI_MISO_R NO STUFF
1
GND
R6191
1
0 5% 1/16W MF-LF 402
2
2 5% 1/16W MF-LF 402
SPI_MOSI_R
IN
21 38 73
PLACEMENT_NOTE=PLACE CLOSE TO U6100
SPI_MISO
OUT
21 38 73
PLACEMENT_NOTE=PLACE CLOSE TO U6100
4
10K
2
5% 1/16W MF-LF 402
MCP79 SPI Frequency Select Frequency
B
SPI_MOSI
SPI_CLK
31 MHz
0
0
42 MHz
0
1
25 MHz
1
0
1 MHz
1
1
B
25MHz is selected with R5190 and R5191 Any of the 4 frequencies can be selected with R6190, R6191, R5190 and R5191
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/15/2009
A
PAGE TITLE
SPI ROM DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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AUDIO CODEC APPLE P/N 353S2355
L6201
U6201 CONSUMES 33MA MAX. FROM 1.8V RAIL
FERR-220-OHM 8
1
=PP1V8_S0_AUDIO
IN
2
VOLTAGE=1.8V MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM
C6210
D
1
1
C6211
4.7UF
0.1UF
20% 4V X5R 402
10% 16V X5R 402
2
2
C6216
C6221 R6210 2.67K
2
GPIO1 = HP AMP CONTROL GPIO3 = SPKR AMP SHDN CONTROL
1
10UF
20% 6.3V X5R 603-1
20% 6.3V X5R 603-1
2
2
VBIAS_DAC CS4206_FP CS4206_FN
CRITICAL
1% 1/16W MF-LF 402
29 44 41
OUT AUD_GPIO_0
2
51
OUT AUD_GPIO_1
12
TP_AUD_GPIO_2 NC AUD_GPIO_3 OUT
54
25
46
VD VA_REF VA_HP VA VBIAS_DAC HPOUT_L VHP_FILT+ VHP_FILTU6201 HPOUT_R CS4206ACNZC HPREF
C6222
1
1
2.2UF 20% 6.3V CERM 402-LF
73 21
73 21
IN
73 21
IN
1
HDA_SDIN0
OUT
NC
2
2
2
20% 16V TANT-POLY 2012-LLP
1
2
2
10UF 20% 6.3V X5R 603-1
CRITICAL
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM
AUD_HP_PORT_L AUD_HP_PORT_R
OUT
40
OUT
51
39
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM
AUD_HP_PORT_REF
IN
53
LINEIN_L+ LINEIN_CLINEIN_R+
21
MICIN_L+ MICIN_LMICIN_R+ MICIN_R-
18
VREF+_ADC
27
CS4206_VREF_ADC
NC
4
TP_AUD_DMIC_CLK
NC
1
VL_IF
6
BITCLK
8 5 11
47
AUD_SPDIF_OUT_CHIP
22
1
48
34 36 37
NC NC
AUD_LO2_P_L AUD_LO2_N_L AUD_LO2_P_R AUD_LO2_N_R
30 32 33
51
AUD_CODEC_MICBIAS
OUT
52
OUT
52
OUT
FR SPKR AMP. SIG. SOURCE
52
OUT
52
OUT
52
OUT
52
OUT
54
LFT. SPKR AMP. SIG. SOURCE RT. SPKR AMP. SIG. SOURCE
C
CS4206_VCOM
AUD_LI_P_L AUD_LI_REF AUD_LI_P_R
22
23
IN
50
IN
50
IN
50
IN
54
IN
54
IN
54
IN
54
SYNC SDI SDO RESET*
SPDIF_IN SPDIF_OUT
2
DMIC_SCL
5% 1/16W MF-LF 402
TP_AUD_LO1_P_L TP_AUD_LO1_N_L AUD_LO1_P_R AUD_LO1_N_R
28
VL_HD
49 51 53 49 50 53 54
38
VCOM
3
7 49
C6213
GND_AUDIO_HP_AMP
16
FLYP FLYC FLYN CRITICAL
AUD_SDI_R
AUD_SPDIF_OUT
OUT
10% 16V X5R 402
MICBIAS
42
10
R6212 53
1
0.1UF
31
43
20% 6.3V CERM 402-LF
5% 1/16W MF-LF 402
HDA_SDOUT HDA_RST_L TP_AUD_SPDIF_IN
C6214 2
LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+ LINEOUT_R2-
2.2UF
R6211 22
D IN
AUD_MIC_INP_L AUD_MIC_INN_L AUD_MIC_INP_R AUD_MIC_INN_R
17 19 20
EXT MIC CODEC INPUT BI MIC CODEC INPUT
7
DGND THRM_PAD AGND 26
HDA_SYNC
2
10% 16V X5R 402
SENSE_A
49
IN
2
2
13
C 73 21
10UF
C6215 0.1UF
10% 10V X5R 402-1
15
C6223
CS4206_FLYN
HDA_BIT_CLK
C6217
35
45
IN
1
LINEOUT_L1+ LINEOUT_L1LINEOUT_R1+ LINEOUT_R1-
CS4206_FLYP CS4206_FLYC
73 21
8 49 53 54
1
GPIO0/DMIC_SDA1 GPIO1/DMIC_SDA2 /SPDIF_OUT2 GPIO2 GPIO3
14
AUD_SENSE_A
IN
=PP3V3_S0_AUDIO
QFN
53
52
10% 16V X5R 402
C6220
1
10UF
1
0.1UF
2
9
CRITICAL
PP4V5_AUDIO_ANALOG
IN
C6218 24
GND_AUDIO_HP_AMP
1
GPIO0 = ANALOG SW CONTROL
20% 16V TANT-POLY 2012-LLP
1
1UF
1
10UF
49 7
8 49 51 53
PP4V5_AUDIO_ANALOG
C6219 53 51 49
=PP5V_S3_AUDIO PP1V8_S0_AUDIO_DIG
0402
CRITICAL
C6224
1
20% 16V TANT 0603-SM
1
C6225
NOSTUFF
10UF
1UF 2
1
20% 2 16V POLY-TANT CASE-B2-SM
100K
B
2
54 53 50 49
R6213 5% 1/16W MF-LF 402
B
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
GND_AUDIO_CODEC
4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2456 NOTES ON CODEC I/O L6200
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM VOLTAGE=5V
FERR-220-OHM 53 51 49 8
IN
=PP5V_S3_AUDIO
1
2
TPS71745
4V5_REG_IN
6
IN
4V5_REG_EN
4
EN
0402
IN
=PP3V3_S0_AUDIO
2.21K 1
SON
OUT
1
PP4V5_AUDIO_ANALOG
OUT
DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS
7 49
CRITICAL
R6200 54 53 49 8
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM VOLTAGE=4.5V
U6200 NR/FB
3
NC
5
4V5_NR
2 1% 1/16W MF-LF 402
GND 1
C6200
1
1UF 2
10% 10V X5R 402
C6201
2
1
C6202
1UF
PLACE NEAR U6200
XW6200
2
10% 16V X7R-CERM 402
SM 1
1
2 2
C6203 1UF
0.1UF
10% 10V X5R 402
10% 10V X5R 402
GND_AUDIO_CODEC
2
49 50 53 54
NOSTUFF
A
R6201
SYNC_MASTER=AUDIO
0 1
SYNC_DATE=06/09/2009
AUDIO: CODEC/REGULATOR
5% 1/16W MF-LF 402
DRAWING NUMBER
Apple Inc.
XW6201 SM 1
A
PAGE TITLE
2
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
2
PLACE NEAR C6220 AND C6221
051-7982 C.0.0
49 51 53
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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D
D LINE INPUT VOLTAGE DIVIDER CODEC RIN = 20K OHMS NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS) FC_HP = 3.6 HZ FC_LP = 43KHZ VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
C6301
R6301 53
IN
AUD_LI_L MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
2.2UF
7.87K2
AUD_LI_L_DIV
1
1
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1% 1/16W MF-LF 402
2
20% 10V X5R-CERM 402
C NOSTUFF 1
C6303 820PF
10% 50V 2 CERM 402
AUD_LI_P_L
49
OUT
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
C
1
R6302 21.5K
1% 1/16W MF-LF 2 402
CRITICAL
C6302 2.2UF 1
2
20% 10V X5R-CERM 402
53
IN
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
AUD_LI_GND
AUD_LI_REF MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
OUT
49
1
R6300 10
CRITICAL
1% 1/16W MF-LF 2 402
C6312 2.2UF 1
54 53 49
IN
GND_AUDIO_CODEC 1
2
20% 10V X5R-CERM 402
NOSTUFF
C6313 820PF
10% 50V 2 CERM 402
B
1
R6312
B
21.5K 1% 1/16W MF-LF 2 402
CRITICAL
C6311
R6311 53
IN
AUD_LI_R MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
7.87K2
1
1% 1/16W MF-LF 402
2.2UF
AUD_LI_R_DIV MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1
2
20% 10V X5R-CERM 402
AUD_LI_P_R MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
OUT
49
A
A PAGE TITLE
AUDIO: LINE INPUT FILTER DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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D
D L6520
53 49 8
FERR-120-OHM-1.5A =PP5V_S3_AUDIO 1 2
HP/LO AMP APN: 353S1637
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_PP5V_F
0402-LF 1
C6520
1
0.1UF
C6521 10UF
20% 2 6.3V X5R 603
MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM 12
10% 2 16V X7R-CERM 402
AUD_LO_AMP_INL_M
AUD_LO_AMP_INR_M
6 INL 8 INR
AUD_GPIO_1_R
5 SHDN*
51 51
U6500 MAX9724A
2
5% 1/16W MF-LF 402
AUD_HP_PORT_L CRITICAL
C6500
1 1
R6522
0.1UF
NC
10% 16V X7R-CERM 402
IN
C6522 1UF
39
53 51 49
OUT
51 53
R6523 2.21K
C6524
1
R6524
1% 1/16W MF-LF 2 402
1UF
CRITICAL 1
10% 10V 2 X5R 402
GND_AUDIO_HP_AMP 53 51 49
2
51 53
10% 2 10V X5R 402
2.21K
1% 1/16W MF-LF 2 402
MAX9724_SVSS
5% 1/16W MF-LF 2 402
R65001 5% 1/16W MF-LF 402
1
MAX9724_C1N
AUD_LO_AMP_OUTR
OUT
1
CRITICAL
C1P 1 C1N 3
100K 2
AUD_HP_ZOBEL_L
C
MAX9724_C1P
4 PVSS
0
9 SVSS
1
7 SGND
IN
AUD_GPIO_1
13 THRM PAD
51 49
IN
OUTL 11 OUTR 10
TQFN
R6520 49
2 PGND
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
VDD CRITICAL
AUD_LO_AMP_OUTL
MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM
CRITICAL 1
C6523
C
1UF
10% 10V 2 X5R 402
GND_AUDIO_HP_AMP
R65101 39 5% 1/16W MF-LF 402
NC
MAX9724 GAIN/FILTER COMPONENTS
2
AUD_HP_ZOBEL_R
AV_PB = -1V/V, FC_LPF = 35.2KHZ CRITICAL
C6510
CRITICAL 1
C6530
0.1UF 10% 16V X7R-CERM 402 51 49
IN
330PF 1
2
AUD_HP_PORT_R
2 5% 50V COG 402
R6531 13.7K2
1
1% 1/16W MF-LF 402
B
AUD_HP_PORT_L 51 49
IN
R6530 13.7K2
AUD_LO_AMP_INL_M
1
B
AUD_LO_AMP_OUTL
51
OUT
51 53
OUT
51 53
1% 1/16W MF-LF 402
AUD_HP_PORT_R 51 49
IN
R6532 13.7K2
AUD_LO_AMP_INR_M
1
AUD_LO_AMP_OUTR
51
1% 1/16W MF-LF 402
R6533 13.7K2
1
1% 1/16W MF-LF 402
CRITICAL
C6531 330PF 1
2 5% 50V COG 402
A
SYNC_MASTER=AUDIO
SYNC_DATE=06/09/2009
A
PAGE TITLE
AUDIO: HEADPHONE FILTER DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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DYNAMIC (SUB) AND PIEZO (SATELLITE) SPKR AMPLIFIERS NO STUFF
C6612 180PF
SATELLITE
HPF FC = 775 HZ
SUB SUB GAIN SAT GAIN
80 HZ < HPF FC < 132 HZ 6DB (2V/V) 5.6DB (1.91V/V)
1
2
5% 50V CERM 402
R6615 26.1K2
1
NO STUFF
1% 1/16W MF-LF 402
C6613 180PF 1
D
D
2
5% 50V CERM 402
R6616 26.1K2
1
ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
=PP5V_S3_AUDIO_AMP
D3
CRITICAL
C6607 1
1
A2
52 8
1% 1/16W MF-LF 402
APN:353S2630 10% 10V X5R 2 402
CRITICAL
IN
0.015UF 1
0402 CRITICAL
L6611
49
IN
52
C
IN
R6613
10% 16V X7R 402
1% 1/16W MF-LF 402
10% 16V X7R 402
AUD_GPIO_3
BGA
C3
C2 D1
C1P C1N
100K
R6610 0
5% 1/16W MF-LF 2 402
2
5% 1/16W MF-LF 402
R6617 SPKRAMP_R_N_OUT_R LM48556_C1P_R
6.8
2
6.8
5% 1/8W MF-LF 805
2
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_P_OUT 7 53 MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_N_OUT 7 53
5% 1/8W MF-LF 805
C6604 4.7UF
10% 10V 2 X5R 805
SVSS
LM48556_VSS_R
1
CRITICAL 1
C1
CPVSS PGND
R6611
1
OMIT
OUT+ B2 OUT- A1
CRITICAL
SD*
1
1
SPKRAMP_SHDN
A3 IN+ B3 IN-
LM48311_R_P LM48311_R_N
1% 1/16W MF-LF 402
R6612
SPKRAMP_R_P_OUT_R
LM48556TL
LM48311_R_P_C 113.7K2
C6611 FERR-1000-OHM R6614 0.015UF 2 SPKRAMP_INR_N 1 2 LM48311_R_N_C 113.7K2 AUD_LO2_N_R 1 0402
49
2
OMIT
10% 16V 2 X5R-CERM 0805
SVDD
U6610
D2
49
C6610
FERR-1000-OHM 1 2 SPKRAMP_INR_P AUD_LO2_P_R
PVDD
B1
L6610
C6601 10UF
1UF
LM48556_C1N_R
CRITICAL 1
C6602 10UF
10% 16V 2 X5R-CERM 0805
C
ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM 52 8
=PP5V_S3_AUDIO_AMP CRITICAL
APN:353S2621 C6608 L6620
49
IN
AUD_LO1_P_R
1
2
0.1UF
SPKRAMP_INSUB_P
0402
IN
1
AUD_LO1_N_R
2
SPKRAMP_INSUB_N
0402
52
CRITICAL
C6621
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_P_OUT 7 53
20% 2 6.3V TANT1 2012-LLP
U6620 LM48311 BGA
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_N_OUT 7 53
OUTA A3 OUTB C3
A2 SD*
0.1UF 1
C6603 47UF
B2 B1 PVDD VDD CRITICAL
A1 IN+ C1 IN-
LM48311_SUB_P LM48311_SUB_N
2
10% 16V X5R 402
L6621
FERR-1000-OHM 49
10% 10V X5R 2 402
C6620 1
1
1UF
CRITICAL
FERR-1000-OHM
1
2
PGND GND 10% 16V X5R 402
B3
C2
SPKRAMP_SHDN NO STUFF
C6634 180PF 1
R6634
B
2
5% 50V CERM 402
26.1K2
B
1
1% 1/16W MF-LF 402
NO STUFF
C6635 180PF 1
2
5% 50V CERM 402
R6635 26.1K2
1
ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM 52 8
1% 1/16W MF-LF 402
APN:353S2630
=PP5V_S3_AUDIO_AMP
C6609 1
L6630
IN
AUD_LO2_P_L
1
2
SPKRAMP_INL_P
0402
L6631
49
IN
AUD_LO2_N_L
A
1UF
C6630
FERR-1000-OHM 49
R6631
0.015UF 1
2 10% 16V X7R 402
LM48311_L_P_C
13.7K2
1
1% 1/16W MF-LF 402
CRITICAL
LM48311_L_P
LM48311_L_N
BGA
C3
1/16W MF-LF 402
SPKRAMP_L_P_OUT_R
CRITICAL
D2
OMIT
R6630 1
OMIT
OUT+ B2 OUT- A1 C1P C1N
C2 D1
CPVSS
C1
SD*
PGND
SPKRAMP_SHDN
10UF
LM48556TL A3 IN+ B3 IN-
C6605
10% 16V 2 X5R-CERM 0805
SVDD
U6630
10% 10V X5R 2 402
C6631 FERR-1000-OHM R6632 0.015UF 13.7K2 1 2 SPKRAMP_INL_N 1 2 1 0402 LM48311_L_N_C 1% 10% 16V X7R 402
52
PVDD
R6633 SPKRAMP_L_N_OUT_R LM48556_C1P_L CRITICAL 1
C6633
1
6.8
6.8
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_P_OUT 7 53
2
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_N_OUT
5% 1/8W MF-LF 805
2
7 53
5% 1/8W MF-LF 805
4.7UF
SVSS
LM48556_C1N_L
B1
CRITICAL
A2
D3
CRITICAL 1
10% 10V 2 X5R 805
SYNC_MASTER=AUDIO
SYNC_DATE=06/09/2009
AUDI0: SPEAKER AMP
CRITICAL 1
A
PAGE TITLE
LM48556_VSS_L
DRAWING NUMBER
C6632
Apple Inc.
10UF
10% 16V 2 X5R-CERM 0805
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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PAGE
66 OF 109 SHEET
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8
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AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX 54 49 8
=PP3V3_S0_AUDIO
AUD_SPDIF_OUT
IN
49
HS_MIC_HI
OUT
54
HS_MIC_LO
OUT
54
L6701 FERR-1000-OHM 1
2
0402
AUD_CONNJ1_MIC
L6702
PLACE NEAR J6700
FERR-1000-OHM 1
D
2
L6703
MIN_LINE_WIDTH=0.4MM
FERR-120-OHM-1.5A
APN:514-0694
1
AUDIO-JACK-TRANS-K83
SM 1
8
1
AUD_CONNJ1_SLEEVEDET AUD_CONNJ1_TIP AUD_CONNJ1_RING
7
AUD_LI_GND 2
50
AUD_CONN_GND
L6705
5353
FERR-220-OHM
AUDIO
AUD_CONN_R
2
BI
53
0402
5
AUD_IP_PERPH_DET_JACK
3 4
AUD_CONNJ1_TIPDET
L6706 FERR-1000-OHM
HP DETECT
1
9
MIC CONNECTOR
AUD_IP_PERPH_DET
2
OUT
54
10 11
CRITICAL
J6701
APN:518S0520
0402
78171-0003 M-RT-SM
R6700 CRITICAL
OPERATING VOLTAGE 3.3 1
12
2
2
10% 2
14
2
CRITICAL
CERM 402
4
AUD_J1_SLEEVEDET_R 2
OUT
54
402
54 7 54 7
CRITICAL
2
6.3V
10K 5% 1/16W MF-LF 402
6.8V-100PF
402
1UF
13
DZ6703
6.8V-100PF
C6700
1
CRITICAL
DZ6705
POF
SHIELD PINS
1
53
BI
CRITICAL
1
A - VIN B - VCC C - GND
SM
AUD_CONN_L
2 0402
6
PHS DETECT GND
49 51
XW6701
FERR-220-OHM
F-RT-TH
GND_AUDIO_HP_AMP 2
PLACE NEAR J6700
L6704
1
49
XW6700
0402-LF
2
OUT
PLACE NEAR J6700 AUD_CONN_GND
CRITICAL
CRITICAL
D
AUD_HP_PORT_REF
2
MIN_NECK_WIDTH=0.2MM
2
OMIT
J6700
C
SM
1
CRITICAL
AUD_CONNJ1_SLEEVE
SHELL
XW6702
0402
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
54 7
2
CRITICAL
DZ6704
CRITICAL
1
DZ6702
DZ6701
6.8V-100PF
6.8V-100PF
402
402
DZ6700
1
6.8V-100PF
402 1
2
1
1 1
4.7
3
AUD_J1_TIPDET_R 2
OUT
C
5
54
5% 1/16W MF-LF 402
402
1
1
R6701
2
1
6.8V-100PF
BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI
C6701 100PF 5%
2
50V
CERM 402
SPEAKER CONNECTORS
APN:518S0519 CRITICAL
J6702 78171-0002 M-RT-SM 3
R6724 51 49 8
=PP5V_S3_AUDIO
1
0
AUD_LO_AMP_OUTL
1
2
AUD_LO_AMP_OUTL_SWITCH
2
10% 10V X5R 402
2
R6718 1
NC1
C1
NC2
A4
NO1 NO2
C2 5% 1/16W MF-LF 402
WLP
A2
CB
COM2
B1
EN*
C6711
1
0.0033UF
5% 1/16W MF-LF 402
10% 50V CERM 402
B2
24K
52 7
IN
5% 1/16W MF-LF 2 402
52 7
IN
0
1
IN
2
54 50 49
0 1
2 5% 1/16W MF-LF 402
GND STUFFING OPTIONS FOR CMOS SWITCH GND_AUDIO_CODEC
1
2 CERM
B DYN. FULL RANGE
4
2
402
0603
CRITICAL
53
J6704
78171-0003 M-RT-SM 4
CRITICAL
L6709
FERR-120-OHM-3A
1
R6713
2
24K
52 7
IN
5% 1/16W MF-LF 2 402
52 7
IN
1
SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT
2
SPKRAMP_R_P_OUT_CONN
1 2
0603
SPKRAMP_R_N_OUT_CONN
RT. PIEZO
3
CRITICAL
1
1
L6710
C6706
FERR-120-OHM-3A
5
100PF
5%
5%
50V
2 50V CERM
402
R6715 AUD_CONN_GND
5% 50V
CERM 2
402
1
2 0603
R6721 100K
53
L6708
FERR-120-OHM-3A
100PF
100PF
2
2
CRITICAL
1C6704
5% 50V
C6707
1
1
SPKRAMP_SUB_N_OUT_CONN
AUD_CONN_R
AUD_SWITCH_CTRL
5% 1/16W MF-LF 402
A
1
2 SPKRAMP_SUB_P_OUT_CONN 0603
100PF CERM 2 402
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
1
SPKRAMP_SUB_P_OUT SPKRAMP_SUB_N_OUT
C6705
R6720 AUD_GPIO_0 49
3
L6707
GND AUD_LI_R_SWITCH
2
CRITICAL
NEG
B3
1
B4
BI
SWITCH_CP
0
AUD_LI_R IN
402
CRITICAL 53
R6712
COM1
CRITICAL
R6719 50
5%
FERR-120-OHM-3A
AUD_LI_L_SWITCH
2
100PF
M-RT-SM
AUD_CONN_L BI
MAX14504
C4
A1
0
AUD_LI_L IN
C6702
J6703
U6700 AUD_LO_AMP_OUTR_SWITCH
5% 1/16W MF-LF 402
50
2 50V CERM
1
C3
1
2
4
78171-0002
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
A3
0
AUD_LO_AMP_OUTR
1
APN: 353S2536
VCC OUT
LEFT PIEZO
2
1
5% 50V
CERM 402
R6717 51
1
100PF
C6710
5% 1/16W MF-LF 402
B
SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT
1UF
0
OUT
IN
C6703 1
R6716 51
IN
52 7
PP_MAX14504_VCC
2
5% 1/16W MF-LF 402
52 7
5% 1/16W MF-LF 402
ANALOG AUDIO IO SWITCH GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED
AUD_SWITCH_GND
SYNC_MASTER=AUDIO 0 1
0 1
5% 1/16W MF-LF 402
A
AUDIO: JACK
R6727
2
SYNC_DATE=06/09/2009
PAGE TITLE
NOSTUFF
R6714
DRAWING NUMBER
2
Apple Inc.
5% 1/16W MF-LF 402
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
67 OF 109 SHEET
OF
8
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6
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8
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1
PORT B LEFT(HEADSET MIC) HP=80HZ, LP=8.82KHZ
CODEC OUTPUT SIGNAL PATHS
MIKEY
FUNCTION
VOLUME
CONVERTER
PIN COMPLEX
MUTE CONTROL
DET ASSIGNMENT
HP/LINE OUT
0X02 (2)
0X02 (2)
0X09 (9,A)
GPIO_0 AND GPIO_1
0X09 (A)
LINE IN
0X05 (5)
0X05 (5)
0X0C (12)
GPIO_0 AND GPIO_1
0X09 (A) AND UI ELEMENT
L6880 54 53 49 8
SATELLITES
0X04 (4)
0X04 (4)
0X0B (11)
GPIO_3
N/A
SUB
0X03 (3)
0X03 (03)
0X0A (10)
GPIO_3
N/A
N/A
0X08 (8)
0X10 (16)
1
=PP3V3_S0_AUDIO
2
DRC MIKEY APN:353S2256
CRITICAL MIKEY
0X0D (B)
N/A
PP3V3_S0_HS_RX
0402
C6880
CODEC INPUT SIGNAL PATHS
1
3
SPDIF OUT
MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V
FERR-1000-OHM
1UF
MIKEY
10%
FUNCTION
D
CONVERTER
PIN COMPLEX
VREF/ENABLE
AVDD
6.3V
DET ASSIGNMENT
2
CERM 402
BUILT-IN MIC
0X06 (6)
0X0D (13,B,RIGHT)
MIC_BIAS (80%)
N/A
HEADSET MIC
0X06 (6)
0X0D (13,V22,B,LEFT)
MCP79 GPIO_38
MCP79 GPIO_17 (PERIPH DETECT) MCP79 GPIO_4 (LOAD DETECT)
U6880
PORT A DETECT (HEADPHONES)
D
CD3275
PULLUPS ON MCP PAGE
DRC 39
PORT B DETECT(SPDIF DELEGATE)
IN
=I2C_MIKEY_SCL
6
SCL
1
54 MICBIAS
HS_MIC_BIAS MIKEY
39
BI
=I2C_MIKEY_SDA
5
SDA
DETECT
2
21
OUT
AUD_I2C_INT_L
7
INT*
BYPASS
10
19
IN
AUD_IPHS_SWITCH_EN
HS_SW_DET
CRITICAL 1
1
APN:376S0613
R6801 300K
2
AUD_OUTJACK_INSERT_L 2
5% 1/16W MF-LF 402
R6806
R6805
39.2K
20.0K
1% 1/16W MF-LF 402
2
AUD_PORTA_DET_L
Q6800
D
8
1
MIKEY
R6880
Q6801
SOT563
3
D
Q6801
SSM6N15FEAPE
R6802 53
IN
5% 1/16W MF-LF 402
G
S
54 53 50 49
G
S
2 4
G
S
1
OUT AUD_MIC_INP_L
1
MIKEY CRITICAL 0.1UF 1
OUT AUD_MIC_INN_L
C 2
54 53
IN
AUD_J1_SLEEVEDET_INV
5% 1/16W MF-LF 402
Q6800
5% 1/16W MF-LF 402
6
1/16W MF-LF 402
2
2
HS_MIC_HI_RC
1
HS_MIC_HI
2
MIKEY 1
IN
53 54
IN
53
5% 1/16W
R6883
MIKEY
1
MF-LF 402
5% 1/16W MF-LF 402
C6885
0.0082UF 10% X7R
2
MIKEY
1
C6884
100K
27PF
25V 402 2
CRITICAL
50V 402
5% CERM
CRITICAL
XW6880 SM
54 53 50 49 GND_AUDIO_CODEC
D
5%
2
2.2K
2
10% 25V X5R 402
220K
220K
2.2K
R6884
2
R6803
R6804
MIKEY
10% 25V X5R 402
C6886
10V 402
49
1
402
C6883 49
5
2
R6882
1/16W MF-LF
MIKEY CRITICAL
54 53 50 49 GND_AUDIO_CODEC
1
1
1%
0.1UF
54 PP3V3_S0_AUDIO_F
1
R6881
SOT563
49 50 53 54
MIKEY
2
GND_AUDIO_CODEC
4
C6801 20% CERM
MIKEY
10% CERM
0.1UF
1
2
16V 402
2
NC
6
AUD_J1_DET_RC 5
GND_AUDIO_CODEC
0.01UF
402
SSM6N15FEAPE
SOT563 2
1
C6881
MF-LF
47K 1
MIKEY
5% 1/16W
1K
D
20% 6.3V TANT 402
2
THM
3
SSM6N15FEAPE
AUD_J1_TIPDET_R
1
2.2UF
100K
1% 1/16W MF-LF 402
AUD_PORTB_DET_L
NC
ENABLE GND
C6882
11
1
4
54 PP3V3_S0_AUDIO_F
9
OUT AUD_SENSE_A
49
HS_RX_BP
1
HS_MIC_LO
2
PLACE NEAR C6886
54 53 AUD_J1_SLEEVEDET_R
C
SSM6N15FEAPE SOT563
PORT B RIGHT(BUILT-IN MIC)
AUD_J1_SLEEVEDET_R 1
C6802
2
G
S
R6850 1
2
54 53 50 49 GND_AUDIO_CODEC
R6851
100
0.01UF
49
10% 16V CERM 402
IN
AUD_CODEC_MICBIAS
2.4K
1
2 1% 1/16W MF-LF 402
MIC_BIAS_FILT
1
1
2 1% 1/16W MF 402-1
CRITICAL
C6852 2.2UF 20% 6.3V TANT 402
2
MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM
54 53 50 49 GND_AUDIO_CODEC
54 PP3V3_S0_AUDIO_F
VOLTAGE=3.3V
CRITICAL
IN
=PP3V3_S0_AUDIO
1
1
OUT AUD_MIC_INP_R
2
MIKEY
1 1
0.1UF 10V 402
20% CERM
0.1UF
R6864
49
220K
C6861 2
2
5% 1/16W MF-LF 402
1
R6865
MIKEY
300K
2
Q6802
5% 1/16W MF-LF 402
D
2
54 53 50 49 GND_AUDIO_CODEC
5% 1/16W MF-LF 402
AUD_PERPH_DET_R
AUD_IP_PERIPHERAL_DET
OUT
2
G
S
Q6802 1
15K
3
S
4
BI_MIC_HI
IN
7 53
5% 1/16W MF-LF 402
2
2
IN
7 53
IN
7 53
C6854
0.001UF 50V 402
10% CERM
CRITICAL
27PF 5% CERM
50V 402
L6851 FERR-1000-OHM 1
BI_MIC_LO_F
2
BI_MIC_LO
2 1% 1/16W MF 402-1
BI_MIC_SHIELD
2
PLACE NEAR J6701
HP=80HZ
B
SSM6N15FEAPE SOT563
R6860 1
D
1
C6853
100K
5% 1/16W MF-LF 402
MIKEY MIKEY
17
1
0402
1
SOT563
CRITICAL
R6852
2.4K
SM
0
2
R6853
XW6851
MIKEY
1
2
1
R6861
6
SSM6N15FEAPE
1
BI_MIC_HI_F
2
10% 25V X5R 402
100K
R6862
1
OUT AUD_MIC_INN_R
MIKEY
1MIKEY
53 AUD_IP_PERPH_DET
10% 25V X5R 402
C6851
PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA
2
0402
CRITICAL
0402
B
FERR-1000-OHM
0.1UF 49
54 53 49 8
L6850
C6850
EXTRACTION NOTIFICATION CKT
L6862 FERR-1000-OHM
PERPH_DET_FILT 2
5% 1/16W MF-LF 402
MIKEY 1
0.1UF 2
5
G
C6860 AUD_J1_TIPDET_INV
20% 10V CERM 402
54 53 50 49 GND_AUDIO_CODEC
MIKEY MIC LOAD DET CKT PP3V3_S0_AUDIO_F 54 54
HS_MIC_BIAS
MIKEY_LOAD_DET
MIKEY_LOAD_DET CRITICAL
1
R6870
B1
HS_MIC_BIAS_COMP
COMP. TRIP PT. = 2.64V
A
MIKEY_LOAD_DET 1
R6871 100K
1% 1/16W MF-LF 2 402
VCC
B3
HS_MIC_HI
UCSP
A2
VEE1
54 53
MAX9028EBT+
A1
VEE0
1% 1/16W MF-LF 2 402
1
C6870 27PF
5% 2 50V CERM 402
R6872 100K
1% 1/16W MF-LF 2 402
MIKEY_LOAD_DET
R6873 0 5% 1/16W MF-LF 402
B2 OUTPUT HIGH WHEN MIC BIAS LOADED OUTPUT LOW WHEN MIC BIAS UNLOADED
MIKEY_LOAD_DET 1
10% 16V 2 X5R 402
MIKEY_LOAD_DET 1
MIC_LOAD_COMP_OUT 1
A3 MIKEY_LOAD_DET
C6872 0.1UF
U6870
2.21K
MIKEY_LOAD_DET 1
C6871
2 MIKEY_MIC_LOAD_DET
OUT
9
SYNC_MASTER=AUDIO
SYNC_DATE=06/09/2009
A
PAGE TITLE
AUDIO: JACK TRANSLATORS
27PF
DRAWING NUMBER
5% 2 50V CERM 402
Apple Inc.
051-7982
GND_AUDIO_CODEC
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
54 53 50 49
SIZE
BRANCH
PAGE
68 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
MagSafe DC Power Jack CRITICAL
J6900
CRITICAL
78048-0573
F6905
M-RT-SM
6AMP-24V
1
1
7 PP18V5_DCIN_FUSE MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V
2 3
1
R6928 1
2 5% 1/16W MF-LF 402
518S0656
=PP3V42_G3H_ONEWIRE
20% 50V CERM 603
2
SMC_BC_ACOK_VCC
R6929 2.0K
5
402 MF-LF 1/16W 5%
U6901
U6900
1
36 37
4
Y
B
1 1
MAX9940 SC70-5
SYS_ONEWIRE
BI
SMC_BC_ACOK
2
A
VCC ONEWIRE_PU
EXT 5
NC
2
2
GND
C6908 0.1UF
3
4 INT
3
36
D
8
SOT665 TC7SZ08AFEAPE
1
7 ADAPTER_SENSE
8 55
C6905 0.01UF
0 5
=PP18V5_DCIN_CONN
2
4
D
2
1206-1
20% 10V CERM 402
PLACEMENT_NOTE=PLACE NEAR U6901
NC
1-Wire OverVoltage Protection ADAPTER_SENSE_R
C
C 516S0787
J6955 ASP-146700-03 F-ST-SM 8
1
2 5% 1/8W MF-LF 805
SOT665
PPDCIN_S5_P3V42G3H MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V
4
5
6
3.425V "G3Hot" Supply R6961
5
1
0
Supply needs to guarantee 3.31V delivered to SMC VRef generator
7 SMC_LID_R
1
2
1/16W
4
3
SMC_LID
NOSTUFF
PPVIN_G3H_P3V42G3H
NC
C6990
P3V42G3H_BOOST
1
C6994
VIN
BOOST
20% 6.3V X5R 402
LT3470A
NC
7
SHDN* NC
SW
4
BIAS
2
DFN CRITICAL
5
GND
FB THRM PAD
10% 50V CERM 402
1
0.22uF
U6990
2
8
B
2
DIDT=TRUE
10UF 10% 25V X5R 805
C6955 0.001UF
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V
3
2
CRITICAL
L6995
2
33UH-20%-0.44A-0.455OHM
1
P3V42G3H_SW MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE
=PP3V42_G3H_REG
8
HALL EFFECT CONNECTOR
2
Vout = 3.425V
D52LC-SM
250MA MAX OUTPUT
1
1
9
NC
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 mm VOLTAGE=12.6V
6
BATT_POS_F
36 37 44
402 5% MF-LF
1 56 55 7
2
3
HN2D01JEAPE
47 =PP18V5_DCIN_CONN
1
D6905
R6905 55 8
=PP3V42_G3H_HALL
C6995 22pF
2
5% 50V CERM 402
R6995
B
(Switcher limit)
1
348K 1% 1/16W MF-LF 402
CRITICAL 2
1
C6999 22UF
P3V42G3H_FB
R6996
1
2
20% 6.3V CERM 805
200K 1% 1/16W MF-LF 402
2
Vout = 1.25V * (1 + Ra / Rb) CRITICAL
J6950
BATTERY CONNECTOR
BAT-K24 M-RT-TH
56 55 7 BATT_POS_F 7 SYS_DETECT_L
=SMBUS_BATT_SDA
5 6
39
7
=SMBUS_BATT_SCL
39
CRITICAL
8
1
2
D6950
9
RCLAMP2402B 11 12 13
R6950
1
5% 1/16W MF-LF 402
C6950
SYNC_MASTER=K24_MLB
1
10% 25V X5R 402
SYNC_DATE=02/05/2009
A
PAGE TITLE
DC-In & Battery Connectors
0.1UF
10K
SC-75
10
2
DRAWING NUMBER
2
Apple Inc.
3
SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
1 2 3 4
NOSTUFF
A
P1 P2 P3 P4 P5 P6 P7 P8 P9
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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PBUS SUPPLY / BATTERY CHARGER Q7001 HAT1128R01 SOI
Q7000 8
PPVDCIN_G3H_PRE2
CRITICAL
3 2
D
D7010
1
2
1SS418
R7098
SOD-723-HF
C7063
1
1
10% 25V X5R 402
5% 1/16W MF-LF 402
2
6
7
5
D2 D1
1% 1/16W MF-LF 402
56
3
PPVDCIN_G3H_PRE
2
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM
1
S1
D
GATE
5
4
=PP3V42_G3H_CHGR GATE
R7099
56 8
4
R7060 1
CHGR_SGATE
2
1% 1/16W MF-LF 402 2
2 5% 1/16W MF-LF 402
R7062
10% 25V X5R 402
57.6K
62K
1
0.1UF
1
62K
2
5% 1/16W MF-LF 402
1
5% 1/16W MF-LF 402
5 1
CHGR_AMON
56 41
100K
1
CHGR_LOWCURRENT_GATE_R
C7060
1
2
30.1K
CHGR_DCIN
D2 D1
6
R7001 R7010
S3 S2
D3
MIN_NECK_WIDTH=0.3 MM
1
100K
0.1UF
MIN_LINE_WIDTH=0.6 MM
8
D3
S1
D4
7
D4
S3 S2
CRITICAL
8
HAT1128R01 SOI
=PP18V5_G3H_CHGR
2
VCC 4
2
1
R7061
GND
CHGR_LOWCURRENT_REF3
1.82K
CHGR_LOWCURRENT_GATE
CRITICAL
U7060
2
1% 1/16W MF-LF 402
TL331 SOT23-5 2
R7023 (CHGR_ACIN)
56 1
1
1
CHGR_VDD
2
R7011
1
C7047
9.31K 1% 1/16W MF-LF 402
5% 1/16W MF-LF 402
1UF
=PP3V42_G3H_CHGR
10% 10V X5R 402-1
1
1
5% 1/16W MF-LF 402 1 2
C7040 1UF
2
10% 10V X5R 402-1
C7024
1UF
0.047UF
10% 10V X5R 402-1
10% 10V CERM 402
2
VDD
2 12 39 39
=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA
11 10
AGATE CSIP CSIN
1
BGATE DCIN
16
28 27
56.2K 1
0.01UF 2
10% 16V CERM 402
C7045 56
1UF
1% 1/16W MF-LF 402 2 CHGR_VCOMP_R
C7044
17
C7043 1
2 10% 16V X5R 402
1
10% 50V CERM 402
25 24 23
LGATE
21
TRKL*
13
AMON BMON ACOK
CHGR_AGATE CHGR_CSIP CHGR_CSIN
9 15 14
2
1
MIN_LINE_WIDTH=0.6 MM
PP18V5_S5_CHGR_SW_R CRITICAL
2
1
C7061
1
2
0.1UF 10% 25V X5R 402
C7062
1
2
2
0.1UF 10% 25V X5R 402 GND_CHGR_SGND
CHGR_BOOT CHGR_UGATE CHGR_PHASE
C7023 1UF
2
2
10% 25V X5R 603-1
1
C7027 0.001UF
2
C
20% 50V CERM 402
CRITICAL 1
LFPAK-HF
C7025 0.1UF 10% 25V X5R 402
1
2
3
L7000
PPVBAT_G3H_CHGR_REG
2
1206
0.5% 1W MF 0612-1
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM
4.7UH-9.5A
1
2
3
4
PPVBAT_G3H_CHGR_OUT 1
IHLP4040DZ-SM
C7028
1
0.001UF 20% 50V CERM 402
2
CRITICAL 1
2
2
20% 16V POLY-TANT CASED2E-SM
10% 25V X5R 603-1
CRITICAL
2
PWM FREQ. = 400 kHz MAX CURRENT = 7A
Q7021
C7026
RJK0305DPB
0.001UF
1
LFPAK-HF
2
3
10% 50V 2 X7R 402
PLACEMENT_NOT=PLACE XW7000 CLOSE TO U7000
56
C7011 1UF
C7008 33UF
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
1
8
7AMP
0.01
CRITICAL 2
56
SM
=PPBUS_G3H
F7000
R7008
1
56
TO SYSTEM 2
CRITICAL
1
5
XW7000
56
1
RJK0305DPB
4
2
C7022 1UF 10% 25V X5R 603-1
Q7020
(??? limited)
GND_CHGR_SGND
R7031
CHGR_VNEG_R
2.2
(CHGR_CSOP)
1
2
1 5% 1/16W MF-LF 402
470PF 10% 50V CERM 402
2
1
CRITICAL
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE 1
C7021 22UF 20% 25V POLY-TANT CASE-D2-SM
5 56
4
CHGR_LGATE TP_CHGR_TRKL CHGR_AMON 41 56 CHGR_BMON 41 =CHGR_ACOK 37
CHGR_PIN26
3.01K
C7046
1
22UF 20% 25V POLY-TANT CASE-D2-SM
DIDT=TRUE
DIDT=TRUE
2
PLACEMENT_NOTE=PLACE C7027 ACROSS PIN 5 OF Q7020 AND PINS 1/2/3 OF Q7021
CRITICAL
C7020
CHGR_CSIN_XW7021
56 CHGR_BGATE CHGR_DCIN 56
CHGR_PIN6
R7046 1
B
0.5% 1W MF 2 0612-1
SM
OMIT
1% 1/16W MF-LF 402
MIN_NECK_WIDTH=0.3 MM
0.02
XW7021
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
0.001UF
GND_CHGR_SGND
2
R7020
5% 1/16W MF-LF 402
2
DIDT=TRUE
PGND
R7045 1
18
BOOT UGATE PHASE
AGND
2
8
29
10% 16V X5R 402
7
ICOMP VCOMP VNEG CSOP CSON THRM_PAD
1
0.033UF
5
ISL6258AHRTZ
CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSOP CHGR_CSON
QFN
VREF ACIN
6
3
26
C7042
4
CRITICAL
1
OMIT
22
NC
2
R7021
U7000 CHGR_ACIN
1
10
VDDP
VHST SCL CRITICAL SDA
XW7020
CHGR_CSIP_XW7020
1
1
C
PLACEMENT_NOT=PLACE XW7020 ON PAD OF R7020 PLACEMENT_NOT=PLACE XW7021 ON PAD OF R7020 SM OMIT
10
CHGR_VDDP
4.7
C7041 56 8
2
19
10% 25V X5R 402
2
R7040
0.1UF
20
C7010
2
CHGR_CSO_R_P
76
CHGR_CSO_R_N
B
R7047 0 1
(CHGR_CSON)
76
2 5% 1/16W MF-LF 402
(CHGR_CSO_R_N)
AMON PULLDOWN LOGIC CHGR_AMON
56 41
=PP3V42_G3H_CHGR
1
56
2
G
S
OMIT 1
Q7050 2
GND_CHGR_SGND
56
SI7137DP SO-8
2
XW7052
1
56
Q7070
D
CHGR_PIN6 2
3
OMIT
SSM6N15FEAPE
A
PPVBAT_G3H_CHGR_OUT 1
CHGR_VDD_L 56
1
SOT563 56 CHGR_VDD
CRITICAL
PLACEMENT_NOT=PLACE XW7052 CLOSE TO U7000
SM
2
GND_CHGR_SGND
C7050
C7051
0.01uF
0.1UF
10% 16V CERM 402
10% 16V X5R 402
1
2
D
5% 1/16W MF-LF 402
BATT_POS_F
7 55
5
5% 1/16W MF-LF 402 2
BATTERY CHARGE LIMITING FETS
CHGR_PIN26
1M
S
R7075
3
NOSTUFF
2
6
SOT563
1
SSM6N15FEAPE D
1
1M
G
Q7070 R7074
4
56 8
56
SYNC_MASTER=K24_MLB
SM
5
R7073
G
S
4
CHGR_BGATE
A
PBUS Supply/Battery Charger
56
PLACEMENT_NOT=PLACE XW7054 CLOSE TO U7000
1
SYNC_DATE=02/05/2009
PAGE TITLE
XW7054
DRAWING NUMBER
Apple Inc.
1K 5% 1/16W MF-LF 402 2
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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- COPY THIS PAGE FROM K36 CSA.76
5V S3/3.3V S5 POWER SUPPLY D
D VOUT = (2 * RA / RB) + 2
R7267 R7268 R7269 R7270 15.0K 10K 10K 6.49K
OMIT
ROUTING NOTE:
XW7203
Place XW7203 by Pin1 OF L7260.
1% 1/16W MF-LF 402
SM 2
VOUT = (2 * RC / RD) + 2
1
1% 1/16W MF-LF 402
1
5V_S3_VFB_XW7203
2
1
1% 1/16W MF-LF 402
2
OMIT
XW7204
1% 1/16W MF-LF 402
1
2
1
SM 2
2
3V3S5_VFB_R7270
PLACEMENT_NOT=PLACE XW7203 BY PIN 1 OF L7260
ROUTING NOTE: Place XW7204 by Pin 2 of L7220.
1
PLACEMENT_NOT=PLACE XW7204 BY PIN 2 OF L7220 57
GND_5V3V3S5_SGND OMIT
ROUTING NOTE:
XW7205 SM 2
C
Place XW7205 by C7252. 1
C
PLACEMENT_NOT=PLACE XW7205 BY C7252
=PPVIN_S3_5VS3 57 8
OMIT
ROUTING NOTE:
XW7202
Place XW7202 by C7292.
1
C7272 1UF
SM 2
10% 25V 2 X5R 603-1
1
PLACEMENT_NOT=PLACE XW7202 BY C7292
PLACEMENT_NOTE=PLACE C7230 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7220
C7260 0.1UF 10% 16V X5R 402
D
CRITICAL
2
Q7260 PWRPK-12128
B
EMI request
1
C7233 0.001UF
20% 2 50V CERM 402
CRITICAL 1
C7290 10UF 20%
2 6.3V X5R
C7291 1
150UF-.025-OHM 20% 6.3V TANT 2 CASE-B2-SM
CRITICAL
C7292 1
U7200 QFN
19 DRVL1
NO STUFF
24 VO1
1
5V_S3_VFB
2.2 2
150UF-.025-OHM
603
VREG5 17 5V3V3S5_REG5
20 LL1
5V_S3_DRVL
R7294 D
CRITICAL
5% 1/16W MF-LF 402
2 VFB1
MIN_LINE_WIDTH=0.6 MM
10% 16V X5R 402
2
3V3S5_VBST
DIDT=TRUE
2
2
VO2 7
Q7220
1
S
1
R7271 75K
100PF 5% 50V
2
2 CERM
1
NO STUFF
3V3S5_ENTRIP 4
NC
5
2
1
C7273
1
=PP3V3_S5_REG
2 6.3V X5R
603
R7272
2
1
1% 1/16W MF-LF 402
C7231 C7252
1
1 150UF-.025-OHM 0.001UF 20% 20%
C7295
2
100PF
50V CERM 402
8
VOLTAGE=3.3V MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm
CRITICAL
EMI request 1
EMI request NO STUFF
75K
10UF 20%
B
CRITICAL
5% 1/16W MF-LF 402
3V3S5_LL_SNUBBER
EN0 13 GND THRM_PAD
2 PCMC063T-SM
R7295 2.2
PGOOD 23
1% 1/16W MF-LF 402
4.7UH-10A EMI request
6
PWM FREQ. = 375 KHZ MAX CURRENT = 4A
L7220
8
DIDT=TRUE
3V3S5V02VO2
VCLK 18
C7294
20% 2 16V POLY B1A-SM
SIZ700DT
3V3S5_VFB
ENTRIP2 6
1
10% 2 25V X5R 603-1
3V3S5_DRVL
MIN_LINE_WIDTH=0.6 MM
VFB2 5
1
POWERPAK-6X3.7
1
PWRPK-12128
G
50V CERM 402
CRITICAL
MIN_LINE_WIDTH=0.6 MM 3V3S5_LL MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 DIDT=TRUE
LL2 11
CRITICAL C7230 C7241 C7240 0.001UF 20% 1UF 39UF-0.027OHM
7
MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 3V3S5_DRVH
DRVH2 10
DRVL2 12
1 ENTRIP1
3
1 DIDT=TRUE
SIS426DN
EMI request NO STUFF 1
5V_S3_ENTRIP
Q7261
VREG3 8
4 TONSEL
21 DRVH1
C7220 0.1UF
VREF
22 VBST1 CRITICAL VBST2 9
5V_S3_VBST
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 5V_S3_VO1
5V_S3_LL_SNUBBER
20% 6.3V TANT 2 CASE-B2-SM
DIDT=TRUE
DIDT=TRUE
=PP5V_S3_REG VOLTAGE=5V
402
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
2
CRITICAL
VIN 14 SKIPSEL
MIN_LINE_WIDTH=0.6 MM DIDT=TRUE MIN_NECK_WIDTH=0.2 MM 5V_S3_LL
S
L7260
PCMB104E4R7-SM
8
G
4.7UH-13A-15MOHM 1
0.22UF 10%
2 10V CERM
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 5V_S3_DRVH
SIS426DN
PWM FREQ. = 300 KHZ MAX CURRENT = 10A
1
C7271
3
1
20% 2 16V POLY B1A-SM
EMI request 1
20% 2 6.3V X5R 603
25
10% 2 25V X5R 603-1
20% 2 16V ELEC C6-SM
50V CERM 402
C7282 39UF-0.027OHM
8
C7270 10UF
1
CRITICAL 1
16
2
C7281 1UF
TPS51125
0.001UF 20%
1
15
C7232
=PPVIN_S5_3V3S5
5VS3_3V3S5_VREF
CRITICAL 1 C7280 68UF
EMI request 1
5V3V3S5_REG3
=PPVIN_S3_5VS3
57 8
6.3V TANT 2 CASE-B2-SM
C7250 10UF 20%
2 6.3V X5R
603
5% 50V
2 CERM 402
402
OMIT 57
D
6
63 36 7
SMC_PM_G2_EN
=P5VS3_EN_L
2
G
S
IN
1
100K 2
2
XW7201 SM PLACEMENT_NOT=PLACE XW7201 BETWEEN PIN 15 AND PIN 25 OF U7200 5V3V3_REG_EN
P5V3V3_PGOOD
5% 1/16W MF-LF 402
SOT563
63
1
R7273
Q7221 SSM6N15FEAPE
GND_5V3V3S5_SGND
63
ROUTING NOTE:
Q7221
1
D
3
Place XW7201 between Pin 15 and Pin 25 of U7200.
SSM6N15FEAPE SOT563
A
=P3V3S5_EN_L 5 63
IN
G
S
A
4
PAGE TITLE
5V/3.3V SUPPLY DRAWING NUMBER
Apple Inc. SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
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1
1.5V/0.75V(DDR3) POWER SUPPLY D
D
VOUT = 0.75V * (1 + RA / RB) NO STUFF 1 2 1 2 1V5S3_VDDQSET R7322 C7303 20K 0.1% 100PF 1/16W MF 402
26 8
5% 50V CERM 402
R7321
=PPVTT_S3_DDR_BUF
20.0K
1
1% 1/16W MF-LF 402
2
C7340
1
0.033UF 10% 16V X5R 402
PLACEMENT_NOT=PLACE XW7304 BY C7300
C7301 10UF
20% 6.3V 2 X5R 603
XW7304 1
OMIT
2
1V5S3_V5FILT_XW 1
2
1
1V5S3_V5FILT
C7300
SM
=PP5V_S3_1V5S30V75S0
2
R7307
1
5% 1/16W MF-LF 402
2
C7302 10UF
4.7
1UF
10% 10V X5R 402-1
20% 6.3V X5R 603
PLACEMENT_NOTE=PLACE XW7301 BY L7320 OMIT
=PP0V75_S0_REG
1V5S3_VDDQSNS
1
ISNS_1V5_S3_P OUT ISNS_1V5_S3_N OUT
Place XW7301 by L7320.
2
8
1
1V5S3_VBST
2
1
R7310 10.7K
VDDQSET VTTREF VLDOIN VTT V5FILT
R7300
2
8
15
22
14
24
23
5
9
DIDT=TRUE
0
5% 1/16W MF-LF 402
VBST V5IN VDDQSNS VTTSNS
1% 1/16W MF-LF 2 402
PGOOD DRVH LL
2
1V5S3_CS
1
5
QFN
DRVL
19 1V5S3_DRVL
MODE
4
D 4
G
ROUTING NOTE:
ROUTING NOTE: CONNECT CS_GND TO Q7321 PIN1,2.3 USING KEVIN CONNECTION.
NC0 NC1
2 6.3V X5R-CERM-1 603
THRM_PAD
CS_GND
GND
PGND
VTTGND
1
22UF 20%
18
C7308
3
2 6.3V X5R-CERM-1 603
1
17
22UF 20%
25
C7307
C
20% 50V CERM 402
PLACEMENT_NOTE=PLACE C7333 ACROSS Q7320 PWR AND Q7321 GND
1 2 3
1 NO STUFF
2 PP1V5_S3_REG_R
R7390
CRITICAL Q7321
2
5% 1/16W MF-LF 402
2 4
C7343 330UF
1
MF-1 0612
1V5S3_LL_SNUBBER
2
3.3X3.3-QFN
1
8
MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm
0.001
PLACE NEXT TO L73201% 1W
CSD58858Q3 S
=PP1V5_S3_REG CRITICAL
VOLTAGE=1.5V
1 3
R7350
2.2 EMI request
G
C7333 0.001UF
L7320
1
4
2
CRITICAL
NO STUFF
1
47 76
1.0UH-13A-5.6M-OHM SM-IHLP-1
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm 5
7 NC 12 NC
20% 2 16V POLY B1A-SM
CRITICAL
S
D
1
39UF-0.027OHM
10% 2 25V X5R 603-1
CSD58858Q3 3.3X3.3-QFN
2
20% 2 16V POLY B1A-SM
CRITICAL Q7320
DIDT=TRUE
Place XW7303 by C7308.
1
39UF-0.027OHM
DIDT=TRUE
DIDT=TRUE
16 CS
=PPVIN_S5_1V5S30V75S0 CRITICAL CRITICAL 1 C7332 C7331 C7345 1UF
47 76
8
DIDT=TRUE MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm
21 1V5S3_DRVH 20 1V5S3_LL
TPS51116
6 COMP
OMIT
16V 10% X5R 402
13
CRITICAL
U7300 SYM (1 OF 2)
SM
=DDRREG_EN
PLACEMENT_NOT=PLACE XW7303 BY C7308
1 C7309 0.1uF
10 S3 11 S5
1
63
=DDRVTT_EN
XW7303
64 25
1V5S3_VBST_RC
C
ROUTING NOTE:
XW7301 SM
1V5S3_VTTSNS
C7344 C7342 0.001UF 330UF 20% 50V CERM 402
20% 2.5V TANT CASE-B2-SM
PLACE CLOSE TO L7320
C7390
1
C7341 10UF
20% 2 6.3V X5R 603
20% 2.5V TANT CASE-B2-SM
MAX CURRENT = 13A PWM FREQ. = 400 KHZ
CRITICAL
100PF 5%
2 50V CERM
1 2 3
402
EMI request
B
B
OMIT
GND_1V5S3_SGND
1
XW7300 SM
ROUTING NOTE: PUT 6 VIAS UNDER THE THERMAL PAD
OMIT GND_1V5S3_CSGND
1
DDRREG_PGOOD
2
R7399 100K
ROUTING NOTE: Place XW7300 between Pin 3 and Pin 25 of U7300. 1
2
XW7302 SM
63
5% 1/16W MF-LF 402 2
=PP3V3_S3_PDCISENS
8
ROUTING NOTE: Place XW7302 by Q7321.
PLACEMENT_NOT=PLACE XW7300 BETWEEN PIN 3 AND PIN 25 OF U7300
STATE
PM_SLP_S4_L
PM_SLP_S3_L
PP1V5_S3
PP0V75_S0
PLACEMENT_NOT=PLACE XW7302 BY Q7321
S0
HIGH
HIGH
1.5V
0.75V
S3
HIGH
LOW
1.5V
0.0V
S5/G3HOT
LOW
LOW
0.0V
0.0V
A
A PAGE TITLE
1.5V/0.75V DDR3 SUPPLY DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
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NOTICE OF PROPRIETARY PROPERTY:
SIZE
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73 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
7
6
4
=PP5V_S0_CPU_IMVP
8
1
R7412
1UF
10
59 8
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
C7426
2
10% 6.3V CERM 402
1
R7420
DPRSTP*
2
1
1
2-PHASE CCM
0
1
0
1-PHASE CCM
1
0
1
1-PHASE DCM
0 1
R7421
0.1uF
10
10% 16V X5R 402
1
1
1
R7447
VID6
42
VID5
70 11 70 11
CPU_VID
70 11
1% 1/16W MF-LF 2 402
22
IN CPU_DPRSTP_L IMVP_DPRSLPVR
C
10
(NC) 36
FROM SMC
25
2
0.015uF
VR_PWRGOOD_DELAY
OUT
IMVP6_VR_TT IMVP6_NTC
9
147K
IMVP_VR_ON
IN
9
C7405
1% 1/16W MF-LF 402
10% 16V X7R 402
1
1
2
1K
2
1% 1/16W MF-LF 402
1
VID2
38
VID1
37
VID0
46
DPRSTP*
45
DPRSLPVR
3V3 CLK_EN*
44
VR_ON
1
4
IMVP6_VDIFF
13
2
59
1K
59 59 59
IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
PHASE1 LGATE1
35
59
IMVP6_UGATE1
34
59
IMVP6_PHASE1
32
59
IMVP6_LGATE1
24
59
IMVP6_ISEN1
27
59
IMVP6_UGATE2
PHASE2
59
IMVP6_PHASE2
LGATE2
30
59
IMVP6_LGATE2
PGND2
29
23
VO
18
DROOP
16
RBIAS
12
X5R 402
R7400
C7407
59
IRF6710 S1
IMVP6_ISEN2
4
59
IMVP6_VSUM
59
IMVP6_OCSET
59
IMVP6_VO
NO STUFF
59
IMVP6_DROOP
C7416
59
IMVP6_DFB
1
C7408
2
R7404 1
0.22uF
5% 1/16W MF-LF 402
10% 6.3V CERM-X5R 402
2
C74111
1
10% 25V X5R 603-1
20% 16V 2 POLY-TANT CASED2E-SM
2
C7422 0.001UF
1UF
33UF
20% 16V POLY-TANT CASED2E-SM
20% 50V CERM 402
2
1
C7431 0.001UF 1 2
VW
NC TPAD 49
2
20% 50V CERM 402
59
R7418
R7417
1K
5.36K
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
1
3.65K
180pF 2
1
5% 50V
2
2
6
5
1
DIRECTFET-MX
S 4
R7430
NOSTUFF 1
C7434
1
C7428
0.12UF
0.47UF
2
10% 10.0V CERM-X5R 402
2
10% 6.3V CERM-X5R 402
1
R7415
2
2
2
20% 50V CERM 402
1
2 PPVCORE_S0_CPU_XW_2
R7405
C7404
10K
0.22uF
1% 1/16W MF-LF 402
R7407 1 5% 1/16W MF-LF 402
10% 6.3V CERM-X5R 402
1% 1/16W MF-LF 402
B 1
IMVP6_VO_R
10.5K 1% 1/16W MF-LF 402
C7423 0.001UF
1 1
2
3.92K
2
1
2
SM
1
IRF6795
G
3
XW7404
SM PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7401
Q7403
(IMVP6_VO)
2
OMIT
XW7403
7
CRITICAL
D
DIDT=TRUE
PLACEMENT_NOTE=PLACE C7423 CLOSE TO PIN 2 OF L7401
PLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7401
PIMA104E-R36MN0R755 DCR=0.75MOHM
2
1% 1/16W MF-LF 402
2 PIMA104E-SM
OMIT
R7416
1
1
DIDT=TRUE
R7443 3.65K
1
CRITICAL
R7431
2
1% 1/16W MF-LF 402
10KOHM-5% (IMVP6_ISEN2)
0603-LF
1% 1/16W MF-LF 402
CRITICAL
(IMVP6_PHASE2)
1
0.001UF 1 2
R7410
L7401
0.36UH-20%-40A-0.00075OHM
1
13.7K
CERM 402
1% 1/16W MF-LF 402
6 S
CERM 402
C7429
R7401
2
2
10% 50V
2
6.81K
2
1
C7401 33UF
2
G
3
14
RTN 15
COMP
9
1
1
D
DIDT=TRUE
1
VSEN
FB
10
=PPVIN_S5_CPU_IMVP CRITICAL CRITICAL
Q7402
20% 50V CERM 402
1
C7403
10K 1% 1/16W MF-LF 402
CRITICAL
C7432
10% 50V CERM 402
1
IMVP6_PHASE1_XW
X5R 402
GND_IMVP6_SGND
0.001UF
R7414
0.1UF 10% 16V
2
2
C
C7433
2
0.1UF 10% 16V
2
PPVCORE_S0_CPU_XW
1
2
PLACEMENT_NOTE=PLACE C7422 ACROSS PINS 1/2/5/6 OF Q7402 AND PINS 3/4 OF Q7403
FB2
11
(IMVP6_VW)
1
1
4
(IMVP6_ISEN1)
0.001UF
220PF
2
SM
PLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7400
1
0.001UF
1
5% 25V CERM 402
1
0
1
VDIFF
VOLTAGE=0V
2
3
20% 50V CERM 402
XW7402
SM
C7415
C7427
(GND)
59
1
OMIT
XW7401 1
IMVP6_BOOT2_RC
0.001UF
2
OMIT
DIRECTFET-MX
59 8
28
21
IMVP6_COMP_RC
2
IRF6795
G
C7420
1
PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7400
(GND)
PGND1 33
VSUM 19 OCSET 8
SOFT
1% 1/16W MF-LF 402
C7413
7
CRITICAL
5
GND
10% 50V CERM 402
6
NTC
C7414
1
UGATE1
ISEN2
25
470PF
2
5% 1/16W MF-LF 402
DIDT=TRUE
R7411
59
2
IMVP6_BOOT2
VR_TT*
6
7
1% 1/16W MF-LF 402
B
2
D
PGOOD
5
IMVP6_RBIAS
IMVP6_BOOT1
59
UGATE2
47
IMVP6_SOFT
59
26
ISEN1
IMON
48
59
DIDT=TRUE
36
BOOT2
DFB 17
(IMVP6_FB)
1
8
PSI*
255
2
=PPVCORE_S0_CPU_REG
2
DIDT=TRUE
IMVP6_VDIFF_RC 1
1
S
R7425
BOOT1
R7413
C7406 0.001UF 10% 50V CERM 402
R7409
VID3
39
59
2
59
1
1 PIMA104E-SM
5
QFN
40
3
IMVP6_IMON OUT 41
R7408
D
CRITICALL7400 0.36UH-20%-40A-0.00075OHM
Q7401
31
PVCC
U7400
VID4
2
CPU_PSI_L
IN
VDD
CRITICAL
41
70 14 10
70
MAX CURRENT = 44A
1-PHASE DCM
IMVP6_BOOT1_RC
2
1 20
43
70 11
R7445
PWM FREQ. = 300 KHZ
2
(IMVP6_PHASE1)
5% 1/16W MF-LF 402
CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID
499
2
20% 50V CERM 402
S
0
CPU_VID
70 11
0.001UF
1UF 10% 25V X5R 603-1
LOAD LINE SLOPE = -2.1 MV/A
DIDT=TRUE
5% 1/16W MF-LF 2 402
2
70 11
2
C7419
1
C7418
1
20% 16V POLY-TANT CASED2E-SM
6
G
3
DIDT=TRUE
2.0K
70 11
2
2 5
R7424
VIN
1
0
PP3V3_S0_IMVP6_3V3
IMVP6_RTN
GND_IMVP6_SGND
C7417 33UF
20% 16V POLY-TANT CASED2E-SM
PIMA104E-R36MN0R755 DCR=0.75MOHM
C7430
59
1
C7409
CRITICAL
1
2
5% 1/16W MF-LF 402
CRITICAL
33UF
DIDT=TRUE
IMVP6_VSEN
1
1 1
D
0.01UF 10% 16V CERM 402
ISL9504BCRZ
=PP3V3_S0_IMVP
OPERATION MODE
0
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM 8
PSI*
4
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
C7496
1
5% 1/16W MF-LF 402
CRITICAL
DIDT=TRUE
20% 6.3V X5R 603
PPVIN_S5_IMVP6_VIN
2
10
IN
C7435 10UF
1
PM_DPRSLPVR
DPRSLPVR
1
PLACEMENT_NOTE=PLACE C7419 ACROSS PINS 1/2/5/6 OF Q7400 AND PINS 3/4 OF Q7401
S1
2
=PPVIN_S5_CPU_IMVP
2
Q7400 IRF6710
PP5V_S0_IMVP6_VDD
2
5% 1/16W MF-LF 402
D
3
=PPVIN_S5_CPU_IMVP
59 8
1
70 21
5
IMVP6_PHASE2_XW
8
20% 50V CERM 402
2
(IMVP6_VSUM)
ERT-J1VR103J
97.6K
2
1% 1/16W MF-LF 402
(IMVP6_VO) (IMVP6_COMP) 1
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
2
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY. PLACEMENT_NOTE=PLACE CLOSE TO PIN 21 OF U7400
2
OMIT
C7421 0.22uF
XW7400 SM 1
10% 6.3V CERM-X5R 402
1
R7423
1
0
R7422 0
5% 1/16W MF-LF 2 402
2
5% 1/16W MF-LF 402
CPU_VCCSENSE_P CPU_VCCSENSE_N
MIN_LINE_WIDTH
11 70 11 70
59 59 59
IMVP6 CPU VCORE REGULATOR
59 59 59
A
59 59
MIN_LINE_WIDTH 59 59 59 59 59
IMVP6_PHASE1 IMVP6_BOOT1 IMVP6_UGATE1 IMVP6_LGATE1 IMVP6_ISEN1
MIN_NECK_WIDTH
MIN_LINE_WIDTH
1.5 MM
0.25 MM
59
0.25 MM
0.25 MM
59
1.5 MM
0.25 MM
59
1.5 MM
0.25 MM
59
0.25 MM
0.25 MM
59
IMVP6_PHASE2 IMVP6_BOOT2 IMVP6_UGATE2 IMVP6_LGATE2 IMVP6_ISEN2
MIN_NECK_WIDTH
59
0.25 MM
0.25 MM
59
0.25 MM
0.25 MM
59
0.25 MM
0.25 MM
59
0.25 MM
0.25 MM
59
0.25 MM
0.25 MM
IMVP6_OCSET IMVP6_VSUM GND_IMVP6_SGND IMVP6_VO IMVP6_DROOP IMVP6_DFB IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
0.25 MM
IMVP6_RTN IMVP6_VSEN
MIN_NECK_WIDTH 0.20 MM
0.25 MM
0.20 MM
0.50 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
SYNC_MASTER=K24_MLB
SYNC_DATE=03/03/2009
IMVP6 CPU VCore Regulator DRAWING NUMBER
Apple Inc.
59
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
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NOTICE OF PROPRIETARY PROPERTY: 59
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1
PLACEMENT_NOTE=PLACE C7563 ACROSS PIN 5 OF Q7560 AND PINS 1/2/3 OF Q7565
=PPVIN_S0_MCPCORE
R7560
D
5V_S0_MCPREG_VIN
2.2
1
VOLTAGE=5V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM
R7593 C7550
2
1
1
1
10% 16V X5R 402
R7561 1K
R7590 21
21
IN
MCP_VID
IN
MCP_VID
0
1
2
2
R7591 0
1
21
IN
0
1
2
RBIAS
2
SOFT
MCPCORES0_IMON_R 63 OUT MCPCORES0_PGOOD MCP_VID0_R MCP_VID1_R MCP_VID2_R MCPCORES0_OS0 MCPCORES0_OS1 =MCPCORES0_EN 63 IN MCPCORES0_FDE
5% 1/16W MF-LF 402
NOSTUFF
1
NOSTUFF
1
R7580 20.0K
PLACEMENT_NOTE=PLACE R7580 ON THE BOTTOM SIDE PLACEMENT_NOTE=PLACE R7581 ON THE BOTTOM SIDE
R7581 20.0K
1% 1/16W MF-LF 2 402
28
1% 1/16W MF-LF 2 402
31 25 26 27 23 24 29 30 32
MCPCORES0_VSEN MCPCORES0_RTN
C
8 9
1
R7582
VIN UGATE
18
MCPCORES0_UGATE
BOOT
17
MCPCORES0_BOOT DIDT=TRUE
PGOOD VID0 VID1 VID2 OFFSET0 OFFSET1 VR_ON AF_EN FDE VSEN RTN
PHASE
1
1
1
C7564 0.25 MM 0.2 MM DIDT=TRUE
2
MCPCORES0_PHASE
4
VW
MCPCORES0_COMP
5
COMP
MCPCORES0_LGATE
1
SWITCHNODE
1NO
5
PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP 60 8 =PPMCPCORE_S0_REG
1
100
60 8
=PPMCPCORE_S0_REG
1
MCPCORES0_RSEN_P
2
1
OMIT
1
2
MCPCORES0_RSEN_N
20
1
OMIT
1% 1/16W MF-LF 402
1
10% 16V CERM-X5R 402
FB
7
VDIFF
OCSET
VSS
S
1
3
C7566
2
3
20% 4V X5R 603
C7569
8 60
1
2
f = 300 kHz CRITICAL 1
1
NO STUFF
C7567 10UF
C7589 0.001UF
2
50V 10% X7R 402
12
MCPCORES0_VO
20% 4V X5R 603
C7565
CRITICAL 1
270UF 20% 2 2V TANT CASE-B4-SM
C7568 270UF
20% 2 2V TANT CASE-B4-SM
C
(MCPCORES0_VO)
R7569
3
ISP ISN
13 11
MCPCORES0_OCSET MCPCORES0_ISP MCPCORES0_ISN
ICOMP
10
MCPCORES0_ICOMP
1
11.3K
2
1% 1/16W MF-LF 402
1
R7573 10K
THRM_PAD 2
1% 1/16W MF-LF 402
C7573
1
47PF 5% 50V CERM 402
2
R7572
R7500
2
OMIT
1
MCPCORES0_ISP_R
2 (MCPCORES0_ISN)
1
(MCPCORES0_RTN)
2
1% 1/16W MF-LF 402
XW7561 VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM
10% 50V X7R 402
100
1
1% 1/16W MF-LF 2 402
GND_MCPCORES0_AGND
0.001UF 2
4
=PPMCPCORE_S0_REG
10% 50V 2 X7R 402
MCPCORE_SNUBBER
SM
C7570
2
1
0.001UF
150K
0.022UF
(MCPCORES0_VSEN)
1
R7568
SM
C7576
1% 1/16W MF-LF 402
2
1% 1/16W MF-LF 402
XW7563
2
1
PWRPK-12128
1
2
10UF
5% 1/10W MF-LF 2 603
DIDT=TRUE
20
R7563
20
6
PGND
1
R7566
PCMB065T-SM
(Q7560 Limit)
PPMCPCORE_S0_R MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V
1
CRITICAL Q7565 SIS426DN G
GATE_NODE=TRUE
1% 1W MF 0612 2
STUFF
MAX CURRENT: 13A
0.001
R7589
4
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
R7525
L7560
(MCPCORES0_PHASE)
(MCPCORES0_LGATE)
VO
1% 1/16W MF-LF 2 402
MCPCORES0_FB
SM
10% 2 16V X5R 603
R7583
MCPCORES0_VDIFF
XW7562
10% 25V X5R 603-1
C7590 2.2UF
0.68UH-16A
D
20.0K
1% 1/16W MF-LF 2 402
2
1
CRITICAL
SWITCH_NODE=TRUE DIDT=TRUE
21
1UF
3
CERM-X7R 10V 603 5%
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
LGATE
20% 2 16V ELEC C6-SM
C7561
0.22UF 1 2 MCPCORES0_BOOT_R
2
5% 1/10W MF-LF 603
0.2 MM 0.25 MM
19
1
68UF
20% 2 16V ELEC C6-SM
2
D
C7571
S
33
20.0K
MCPCORES0_VW
1
C7560
PWRPK-12128
G
GATE_NODE=TRUE DIDT=TRUE
14
R7565
15
1
PLACEMENT_NOTE=PLACE R7583 ON THE BOTTOM SIDE
CRITICAL
1
68UF
2
PLACEMENT_NOTE=PLACE R7582 ON THE BOTTOM SIDE
CRITICAL
CRITICAL Q7560 SIS426DN
4
(MCPCORES0_UGATE) MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
QFN
IMON
1
D
10% 16V X5R 402
U7500 1
2
5% 1/16W MF-LF 402
R7592 MCP_VID
MCPCORES0_SOFT
2
10% 50V X7R 402
5
C7562
PVCC
VDD
5% 1/16W MF-LF 402
MCPCORES0_RBIAS 5% 1/16W MF-LF 402
C7563
1UF 2
22
1UF
5% 1/16W MF-LF 402
ISL6263D
0
1
8
0.001UF
16
41
MCPCORES0_IMON
=PP5V_S0_MCPREG
2
5% 1/10W MF-LF 603
R7575
1% 1/16W MF-LF 2 402 OCP=14.5A
1
R7571 100
1
C7575 47PF
47.0K
PLACEMENT_NOTE=PLACE XW7561 CLOSE TO PIN 15 OF U7500
2
5% 50V CERM 402
(MCPCORES0_ICOMP)
1% 1/16W MF-LF 2 402
B
B (MCPCORES0_VW)
C7579 10% 50V X7R 402
68PF 1
1
0.001UF
C7580 2
2
1
VID
R7576
MCP TARGET
6.98K 5% 50V CERM 402-1
R7577 1
133K
C7581 2
560PF
MCPCORES0_COMP_C
2
1
1% 1/16W MF-LF 402
10% 50V CERM 402
(MCPCORES0_FB)
C7582
R7578 1
100
2
560PF MCPCORES0_VDIF_C
1% 1/16W MF-LF 402
R7579 1
2.21K 1% 1/16W MF-LF 402
+1.05V
001
+1.00V
010
+0.95V
011
+0.90V
100
+0.85V
101
+0.80V
110
+0.75V
111
+0.70V
2 (MCPCORES0_COMP)
1% 1/16W MF-LF 402
000
2
1
2 10% 50V CERM 402
(MCPCORES0_VDIFF)
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/15/2009
A
PAGE TITLE
MCP CORE REGULATOR DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
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CPUVTT POWER SUPPLY
D
8
D
=PPVIN_S0_CPUVTTS0 PLACEMENT_NOTE=PLACE C7696 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7620
CRITICAL
C7630
1
1
2
2
20% 16V POLY-TANT CASED2E-SM
C7695
C7696
1
0.001UF
1UF
33UF
10% 25V X5R 603-1
20% 50V CERM 402
2
C
C 5 D 4 8
CRITICAL Q7620
G
CSD58858Q3
=PPCPUVTT_S0_REG
L7620
3.3X3.3-QFN
=PP5V_S0_CPUVTTS0
8
2.2UH-8.0A S R7601
1
2
CRITICAL
VOUT = 1.052V 7.2A MAX OUTPUT F = 320 KHZ
301 1% 1/16W MF-LF
1 2 3
PP5V_S0_CPUVTTS0_V5FILT
R7603
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
C7601
402
1
1UF 10% 10V X5R 402-1
10
2
4
1
1
2
2
CRITICAL
1% 1/16W
PLACEMENT_NOTE=Place XW7665 next to L7620
5
MF-LF
10% 6.3V X5R-CERM 603
402
2
2
D
U7600
4
G
SYM 2 QFN
63
IN
63
OUT
CPUVTTS0_PGOOD
1
EN_PSV
6
PGOOD
TON
2
CPUVTTS0_TON
14
CPUVTTS0_VBST
C7603
(=PPCPUVTT_S0_REG)
3
VOUT
5
VFB
13
LL
12
CPUVTTS0_LL SWITCH_NODE=TRUE
CPUVTTS0_TRIP
11
TRIP
DRVL
9
THRM_PAD
C7660
S
DIDT=TRUE
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
20% 2.5V TANT CASE-B2-SM
PGND
B
8
C7670
OMIT
XW7600
2
5% 50V CERM 402
402
1
B 2
OMIT
SM 1
2
100PF
1/16W MF-LF
6.04K
2
1
NO STUFF
R7670 1%
R7604 1% 1/16W MF-LF 402
2
0.001UF
CPUVTTS0_VSNS
8.06K 1
2
C7661 20% 50V CERM 402
330UF
2
1
15
7
CRITICAL
1 2 3
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
1
20% 6.3V X5R 603
1
CPUVTTS0_DRVL GATE_NODE=TRUE
GND
OMIT
C7665 10UF
2
603-1
CPUVTTS0_DRVH GATE_NODE=TRUE
CPUVTTS0_VFB
10% 50V X7R
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
DRVH
SM
3.3X3.3-QFN
1
1
XW7665
0.1UF DIDT=TRUE
VBST
CRITICAL Q7621 CSD58858Q3
TPS51117RGY_QFN14 =CPUVTTS0_EN
PCMB065T-SM
200K
C7604 4.7UF
V5DRV
V5FILT
1
2
XW7601
(GND) SM
PLACEMENT_NOT=PLACE XW7600 BETWEEN PIN 7 AND PIN 15 OF U7600
1
R7671
1
PLACEMENT_NOT=PLACE XW7601 BY C7660
20.0K
ROUTING NOTE: 1%
1/16W MF-LF
Place XW7600 between Pin 7 and Pin 15 of U7600. 2
ROUTING NOTE:
402
GND_CPUVTTS0_SGND
Place XW7601 by C7660.
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
Vout = 0.75V * (1 + Ra / Rb) (CPUVTTS0_VFB) CPUVTTS0_VOUT
(=PPCPUVTT_S0_REG)
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/04/2009
A
PAGE TITLE
CPU VTT(1.05V) SUPPLY DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
76 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
1.8V S0 SWITCHER
D
D
=PP3V3_S0_P1V8S0
8
1
C7760 10uF 20% 6.3V X5R 603
CRITICAL
CRITICAL
VI U7760
1
L7760 10UH-0.55A-330MOHM
TPS62202 4
2
=P1V8S0_EN
63
3
PCAA031B-SM
SOT23-5
FB EN
SW 5
1
P1V8S0_SW
MAX CURRENT = 200MA
=PP1V8_S0_REG
2
8
DIDT=TRUE
GND C7762
2
1
10uF 20% 6.3V X5R 603
2
C
C 1.05V S0 PLL LDO LDO_YES
R7743 =PP3V3_S0_MCP_PLL_VLDO
1
8
100
PP3V3_S0_MCP_PLL_VLDO_BIAS
2
MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
5% 1/16W MF-LF 402
LDO_NO
C7740
R7745
1
1UF LDO_YES
10% 6.3V CERM 402
8
=PP1V05_S0_MCP_PLL_UF_R
0
1
4
Vout = 1.05V
2
IN0 OUT0 IN1 LDO_YES OUT1
5
EN
PP1V05_S0_MCP_PLL_UF_LDO
9
LDO_YES
10
SON
1UF 2
P1V05S0_LDO_SS NOSTUFF
B
C7743
1
8
U7740 7
SS
1
MCP 1.05V S5 (AUXC) SUPPLY
10% 6.3V CERM 402
FB
PG
3
4.42K
11
6
C7750
2
NOSTUFF
20% 6.3V CERM 805
R7782 0
=P1V05_S5_EN
PP3V3_S5_P1V05S5_R_SKIP
IN
CRITICAL
IHLP1616BZ-SM
2
EN CRITICAL
3
POR
4
SKIP
LX
8
1V05S5_SW
VFB
6
1V05S5_FB
RSI
GND
2
=PP1V05_S5_REG
DIDT=TRUE
5
THRM_PAD
7
1
0
2
P1V05S0_LDO_PGOOD
63
5% 1/16W MF-LF 402
2.2UH-3.25A
DFN
R7783 0
P1V05S0_PGOOD1
L7770
ISL8009B
1
R7748
1
VIN
U7750 63
R7747
LDO_YES
5% 1/16W MF-LF 2 402
P1V05_S5_PGOOD
B
LDO_YES
LDO_YES
VOUT = 0.8V * (1 + RA / RB)
1
63
LDO_YES
20% 4V X5R 402
22UF
=PP3V3_S5_P1V05S5
8
2
1
CRITICAL 1
2
C7742
2
4.7UF
R7746
P1V05S0_LDO_FB
GND THRML_PAD
0.0022UF 10% 50V CERM 402
DIDT=TRUE
1
0 5% 1/16W MF-LF 402
2
LDO_YES
1.37K
1
2
TPS74701
C7741
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
1% 1/16W MF-LF 402
1
8 23
R7744
1% 1/16W MF-LF 402
=PP1V5_S0_MCP_PLL_VLDO
=PP1V05_S0_MCP_PLL_UF
MAX CURRENT = 0.5A
CRITICAL BIAS 8
2
5% 1/16W MF-LF 402
2
1
C7776
1
8
Vout = 1.05V
R7780
47PF 5% 50V CERM 402
25.5K
2 2
9
1% 1/16W MF-LF 402
CRITICAL 1
1
2
R7781
MAX CURRENT = 0.8A FREQ = 1.6MHZ
47UF
5% 1/16W MF-LF 2 402
C7771 20% 6.3V X5R 0805
80.6K
2
A
1% 1/16W MF-LF 402
SYNC_MASTER=K24_MLB
SYNC_DATE=03/24/2009
A
PAGE TITLE
MISC POWER SUPPLIES
VOUT = 0.8V * (1 + RA / RB)
DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
77 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
3.3V 1.05V S5 ENABLE
Power Control Signals
R7802 100K 63 8
2
=PP3V42_G3H_PWRCTL
1
PM_G2_P3V3S5_EN_L
=P3V3S5_EN_L
57
OUT
3.3V_S0, 1.8V_S0 ENABLE
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
State
NO STUFF
1
D
2
3
MCPDDR, CPUVTT,MCPCORES0 ENABLE 1.5V S0 AND 1.05V S0 ENABLE
Run (S0)
1
1
1
Sleep (S3)
1
1
0
Soft-Off (S5)
1
0
0
Battery Off (G3Hot)
0
0
0
D
10V CERM 402
SMC_PM_G2_EN
IN
PM_SLP_S3_L
10%
D
SOD-VESM-HF
57 36 7
PM_SLP_S4_L
C7802 0.068UF
Q7800 SSM3K15FV
SMC_PM_G2_ENABLE
1
R7800 1
100K
G
S
2
5% 1/16W
R7801
MF-LF 402
5.1K
2
2
1 PM_G2_P1V05S5_EN
=P1V05_S5_EN
OUT
62
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
1
C7801 0.47UF 10% 6.3V
2
CERM-X5R
R7859
402
(PM_SLP_S3_L)
67 36 32 21 7
IN
PM_SLP_S3_L
100 2
1
PM_SLP_S3_L_BUF MAKE_BASE=TRUE
5% 1/16W MF-LF
=P5VS0_EN
OUT
64
=PBUSVSENS_EN
OUT
40
402
R7880
2
5% 1/16W
100K
S3 ENABLE
R7881
2
5%
5% 1/16W
MF-LF
1/16W
33K
1
0
R7884
5% 1/16W
5% 1/16W MF-LF
MF-LF
MF-LF 402
402 1
22K
R7883
2
5% 1/16W
MF-LF
402 1
MF-LF
R7882
2
2
1
R7879
402 1
402
10K
2
R7813
5.1K
1
402
68K 63 8
=PP3V42_G3H_PWRCTL
2
1 5% 1/16W
D
MF-LF
Q7813 3
PM_SLP_S3_L_INVERT
SSM3K15FV
=P5VS3_EN_L
OUT
P3V3S0_EN
57
MAKE_BASE=TRUE
402
=P3V3S0_EN
OUT
64
=P1V8S0_EN
OUT
62
=MCPDDR_EN
OUT
64
=CPUVTTS0_EN
OUT
61
=MCPCORES0_EN
OUT
60
MAKE_BASE=TRUE
SOD-VESM-HF
NO STUFF
1
C
37 36 21 7
IN
PM_SLP_S4_L
P1V8S0_EN
C7813
C
MAKE_BASE=TRUE
MAKE_BASE=TRUE
0.068UF
MCPDDR_EN
10%
2 1
1
R7810
G
S
10V
MAKE_BASE=TRUE
CERM
CPUVTTS0_EN
402
2
MAKE_BASE=TRUE
(PM_S4_STATE_L) 100K
MCPCORES0_EN
5%
MAKE_BASE=TRUE
1/16W MF-LF 402 2
NO STUFF
C7810 1
R7811
0.47UF
5.1K 1 1
2 5%
2
1/16W
10%
MF-LF
6.3V
1
C7880 0.47UF
2
C7881
1
1
C7882
C7883
0.47UF
0.47UF
10%
10%
10%
10%
6.3V
6.3V
6.3V
6.3V
2
CERM-X5R 402
CERM-X5R 402
2
1
C7884
0.47UF
2
CERM-X5R
0.47UF
402
10% 6.3V
2
CERM-X5R
CERM-X5R
402 402
CERM-X5R
402
402
DDRREG_EN
=DDRREG_EN
OUT
58
=USB_PWR_EN
OUT
35
MAKE_BASE=TRUE
NO STUFF
C7812 R7812
0.47UF
0 1 1
VOLTAGE MONITOR
2
2 5% 1/16W
10%
MF-LF
6.3V
402
CERM-X5R
63 8 =PP3V42_G3H_PWRCTL
402
P3V3S3_EN
=P3V3S3_EN
OUT
MAKE_BASE=TRUE
64 8 =PP3V3_S5_PWRCTL
C7840
1 1
0.1uF
B
10V CERM
100K
2
5%
402
1/16W MF-LF
6 2
VDD 5
SENSE
U7840 RESET*
1
402
RSMRST_PWRGD
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
=PP5V_S0_VMON
CT
8
4
CT
MR*
2
R7870 10K
OTHER S0 RAILS PGOOD
1%
C7841
1/16W
TP_U7840_MR_L
0
2
P1V05_S5_PGOOD 62
5% 1/16W
TPS3808 MR* HAS INTERNAL PULLUP
MF-LF 402
1
0.001UF
8 =PP3V3_S0_PWRCTL
MF-LF
1
3
GND 1
36
R7895
TPS3808G33DBVRG4 SOT23-6
B
R7840
20%
20%
402
50V
2
CERM
PP3V3_VMON_VDD
1
2
402
R7820 7
10K
2
353S2310
1
C7870
VDD
OMIT
1
2
402 2
57
3
V2MON
MR*
1
5
=PP1V05_S0_VMON
6
V3MON V4MON
RST*
8
1
P5V3V3_PGOOD
IN
0
2
5% 1/16W MF-LF 402
NC S0PGOOD_PWROK
R7892
THRM_PAD 9
GND
2
R7890
MF-LF
402
=PP1V5_S0_VMON
4
402
1/16W
10V CERM
TDFN
8
MF-LF
1%
U7870 8 =PP3V3_S0_VMON
1/16W
20.0K 20%
ISL88042IRTEZ
8
5%
R7871
0.1uF
60
MCPCORES0_PGOOD
IN
0
1
2
Unused PGOOD signal
5% 1/16W MF-LF 402
A
TP_DDRREG_PGOOD
DDRREG_PGOOD
V2MON THRESHOLD IS 2.866V
61
CPUVTTS0_PGOOD
IN
1
0
5% 1/16W MF-LF 402
62
V3MON THRESHOLD IS 0.6V V4MON THRESHOLD IS 0.6V
P1V05S0_LDO_PGOOD
IN
R7894 1
0
2
PAGE TITLE
POWER SEQUENCING
2
DRAWING NUMBER
Apple Inc.
R7893 1
0
7
6
5
051-7982
NOTICE OF PROPRIETARY PROPERTY:
5% 1/16W MF-LF 402
ALL_SYS_PWRGD
OUT
25 36
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
(S0PGOOD_PWROK)
SIZE
D
REVISION
C.0.0
R
2
5% 1/16W MF-LF 402
8
A
58
MAKE_BASE=TRUE
R7891
BRANCH
PAGE
78 OF 109 SHEET
OF
4
3
2
1
8
7
6
5
4
3
2
1
1.5V S0 FET
3.3V S3 FET
CRITICAL (1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
Q7910 FDC638P_G
3.3V S3 FET
SM
=PP3V3_S3_FET
8
8
=PP3V3_S5_P3V3S3FET 6
MOSFET
FDC638P
CHANNEL
P-TYPE
=PP1V5_S3_P1V5S0FET
8
5 4 2
R7912
C7911
1
RDS(ON)
48 mOhm @4.5V
Q7901
10% 5% 16V
LOADING
MF-LF
2
3
R7910 P3V3S3_EN_L
1
DFN
C7902
0.01UF
47K
1
P3V3S3_SS
2
Q7903
20% 10V CERM 402
R7901
8 =PP5V_S3_MCPDDRFET
16V
4
KELVIN
6
G
2
10K
CERM
402
1
402
D
SSM3K15FV
8
2
10%
MF-LF
NC
1
0.1UF
5% 1/16W
D
ROME
0.182 A (EDP)
C7910
MCPDDR_SS
2
41
402 402
SENSE
D
D
2 X5R
OUT
P1V5_S0_KELVIN
S GND
1/16W
CRITICAL
1
0.033UF
10K
9
1
3 7
1/16W
R7903
MF-LF 402
1
Q7971
1
G
S
2
2
3
5
OUT
P1V5_S0_SENSE =PP1V5_S0_FET
SOT563
5% 1/16W
8
MF-LF 402
=P3V3S3_EN
IN
1
6
SSM6N15FEAPE
100K
63
D
41
5% SOD-VESM-HF
2
R7971
G
2
S
1 1
1 5%
D
1/16W MF-LF
3
1.5V S0 FET
10% 10V
2 2
Q7971
C7903 0.068UF
47K MCPDDR_EN_L
CERM 402
402
MOSFET
Rome SenseFET
CHANNEL
N-TYPE
MCPDDR_EN_L_RC
SSM6N15FEAPE RDS(ON)
SOT563
6.3 mOHM @4.5V VGS
CRITICAL LOADING
Q7930
3.3V S0 FET
FDC606P_G
5
SOT-6
6
3.3V S0 FET =PP3V3_S0_FET
63
8
IN
S
5A (EDP)
4
=MCPDDR_EN
D
2 1
S
5
=PP3V3_S5_P3V3S0FET
4
8
G
C7931
1
0.033UF
100K
C
FDC606P
CHANNEL
P-TYPE
1
G
R7932
MOSFET
RDS(ON)
26 MOHM @4.5V
C
10%
3
5% 16V 2
1/16W X5R
LOADING
MF-LF
1.431 A (EDP)
402
C7930
402 2
R7930
0.01UF
47K P3V3S0_EN_L
1
1
P3V3S0_SS
2
2
5% 10% 1/16W 16V
MF-LF
Q7905
CERM
402
SSM3K15FV
402
D
3
S
2
SOD-VESM-HF
1 63
G
=P3V3S0_EN
IN
376S0778
CRITICAL
MCP79 DDRVTT FET
Q7940
5.0V RT S0 FET
TPCP8102
5.0V RT S0 FET
23V1K-SM
=PP5VRT_S0_FET
8
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
8
=PP5V_S3_P5VRTS0FET
TPCP8102
CHANNEL
P-TYPE
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP. IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
6
D
S
0.033UF
47K
MOSFET
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
5
C7941
1
G
R7942
1
1
2
7
3
8
RDS(ON)
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
13.5 MOHM @4.5V
4
10% 5% 16V
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
2
1/16W X5R
LOADING
MF-LF 402 402 2
B
R7940 47K P5V0RTS0_EN_L
1
C7940
WILL EXIT SELF-REFRESH PREMATURELY.
0.01UF
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
1
P5V0RTS0_SS
2
0.48 A (EDP)
2
LOW THROUGH VTT TERMINATION RESISTORS. 10%
1/16W
16V
MF-LF
Q7945 SSM3K15FV
B
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
5%
CERM
402
402
D
3
S
2
SOD-VESM-HF
1 64 63
IN
G
R7975 10
=P5VS0_EN
8
=PPVTT_S0_VTTCLAMP
2
1
VTTCLAMP_L
90mA max load @ 0.9V 81mW max power
5% 1/10W
376S0778
MF-LF 603
CRITICAL 8
Q7948
5.0V LT S0 FET
5.0V LT S0 FET
23V1K-SM
=PP5VLT_S0_FET
R7976
8
7
TPCP8102
SOT563
CHANNEL
P-TYPE
5% 1/16W 402
6
D
6
MF-LF 2
2
G
S
1
VTTCLAMP_EN
G
0.033UF
47K
MOSFET
5
1
S
2
C7942
1
1
R7943
D
SSM6N15FEAPE
1
100K
8
=PP5V_S3_P5VLTS0FET
3
8
CKT FROM T18
=PP5V_S3_VTTCLAMP
Q7975
TPCP8102
RDS(ON)
13.5 MOHM @4.5V
4
10% 5% 16V 1/16W
2 X5R
LOADING
MF-LF
1.302 A (EDP)
Q7975
402
C7943
402 2
R7944 P5V0LTS0_EN_L
1
2
P5V0LTS0_SS
1
D
3
NO STUFF
C7976
SSM6N15FEAPE
0.01UF
47K
1
0.001UF
SOT563
20% 50V
2
CERM
2
5%
A
1/16W MF-LF
Q7947 SSM3K15FV
402
D
402
10% 16V
5
CERM
G
S
4
SYNC_MASTER=K24_MLB
SYNC_DATE=02/15/2009
58 25
IN
PAGE TITLE
=DDRVTT_EN
POWER FETS DRAWING NUMBER
1 64 63
IN
G
S
A
402
3
SOD-VESM-HF
Apple Inc. 2
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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=P5VS0_EN
NOTICE OF PROPRIETARY PROPERTY:
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8
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1
D
D
CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP 18
LCD
CONNECTOR
LVDS CONNECTOR:518S0650
LVDS_IG_PANEL_PWR
FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY
1
R9014
CRITICAL
1K
J9000
5% 1/16W MF-LF 2 402
20474-030E-11 F-RT-SM 31
C9015
CRITICAL
U9000
0.001UF
FPF1009 1 ON 8
=PP3V3_S5_LCD
GND
C9009
6
VOUT_1 4
PP3V3_LCDVDD_SW
VOUT_2 5
VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM
1
2
1
1
C9011 0.1UF
10% 16V 2 X5R 402
10% 16V X5R 402
1
2
2
L9008 1
10UF
=PP3V3_S0_LCD 1
R9008 100K
2
LVDS_IG_DDC_CLK
18 7
LVDS_IG_DDC_DATA
3
MIN_LINE_WIDTH=0.30 MM
7
4
MIN_LINE_WIDTH=0.25 MM
5% 1/16W MF-LF 402
2
C
6
PP3V3_S0_LCD_F VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20 MM
72 18 7
LVDS_IG_A_DATA_N
7
72 18 7
LVDS_IG_A_DATA_P
8
72 18 7
LVDS_IG_A_DATA_N
10
9
(LVDS DDC POWER) 1
18 7
VOLTAGE=3.3V
5
2 0402-LF
8
MIN_NECK_WIDTH=0.20 MM
CRITICAL
120-OHM-0.3A-EMI
C9012
20% 6.3V 2 X5R 603
PP3V3_LCDVDD_SW_F
7
0402-LF
MIN_NECK_WIDTH=0.20 MM
THRM PAD 7
0.1UF 2
32
10% 50V X7R 402
2
FERR-120-OHM-1.5A
3 VIN_2
1
1
0.001UF
10% 50V X7R 402
L9004
MFET-2X2
2 VIN_1
C
C9010
1
R9009
72 18 7
LVDS_IG_A_DATA_P
11
100K
72 18 7
LVDS_IG_A_DATA_N
12
72 18 7
LVDS_IG_A_DATA_P
13
5% 1/16W MF-LF 402
72 7
LVDS_IG_A_CLK_F_N
14
72 7
LVDS_IG_A_CLK_F_P
15
LVDS I/F
16
CRITICAL
L9080
NC
90-OHM-200MA AMC2012-SM
68 47 7
PPVOUT_S0_LCDBKLT
17 18
SYM_VER-1
72 18
72 18
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_P
4
3
1
C9017 1000PF
NC
5% 2 50V C0G-CERM 603
2
L9050 8
2
=PP5V_S3_CAMERA MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
19
PLACEMENT_NOTE=PLACE CLOSE TO J9000
1
1
7
LED_RETURN_6
21
68 7
LED_RETURN_5
22
68 7
LED_RETURN_4
23
68 7
LED_RETURN_3
24
68 7
LED_RETURN_2
25
68 7
LED_RETURN_1
26 27
PP5V_S3_CAMERA_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
FERR-120-OHM-1.5A 0402-LF
C9016
LED BKLT I/F
20
68 7
28 29
1
30
CAMERA I/F
0.1uF 20% 10V CERM 402
B
2
B
33 34
CRITICAL
CAMERA
L9060 90-OHM DLP0NS SYM_VER-1
73 20
73 20
USB_CAMERA_P
OUT
OUT
USB_CAMERA_N
3
4
2
1
73 7
73 7
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
PLACEMENT_NOTE=PLACE CLOSE TO J9000.
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/15/2009
A
PAGE TITLE
LVDS CONNECTOR DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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90 OF 109 SHEET
OF
8
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8
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6
5
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18
=MCP_HDMI_TXC_P
DP_ML_P
18
=MCP_HDMI_TXC_N
DP_ML_N
18
=MCP_HDMI_TXD_P
DP_ML_P
18
=MCP_HDMI_TXD_N
DP_ML_N
18
=MCP_HDMI_TXD_P
DP_ML_P
1
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
18
=MCP_HDMI_TXD_N
DP_ML_N
18
=MCP_HDMI_TXD_P
DP_ML_P
18
=MCP_HDMI_TXD_N
DP_ML_N
18
=MCP_HDMI_HPD
DP_HPD
18
=MCP_HDMI_DDC_CLK
DP_IG_DDC_CLK
18
=MCP_HDMI_DDC_DATA
DP_IG_DDC_DATA
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
D
67
D
MAKE_BASE=TRUE
66 MAKE_BASE=TRUE
66 MAKE_BASE=TRUE
DP_AUX_CH_C_N BI
C9300
R9300 DP_IG_DDC_DATA 66
0.1UF
33 1
BI
67 72
1
2 5% 1/16W MF-LF 402
2
72
DP_AUX_CH_SW_N
10% 16V X5R 402
Display Port Interoperability spec says that sources
DP_AUX_CH_C_P
or sinks which do both DP and DVI must depend on the
BI
67 72
external adapter for pull ups on DDC lines (since DP AUX CH has 100K pull up/down on the MLB)..
R9301 DP_IG_DDC_CLK 66
33 1
BI
2 5% 1/16W MF-LF 402
C9301 0.1UF 1
2
72
DP_AUX_CH_SW_P
10% 16V X5R 402
C
3
D
Q9300
Q9300
SSM6N15FEAPE
4
S
G
D
6
S
1
C
SSM6N15FEAPE
SOT563
SOT563
5
2
G
DP_IG_AUX_CH_P 72 18
BI
72 18
BI
DP_IG_AUX_CH_N =PP5V_S0_DP_AUX_MUX 8
1
R9302 100K
R9306
1
1K 5% 1/16W MF-LF 402
2
5% 1/16W MF-LF 402
2
DDC_CA_DET_LS5V_L
B
B Q9301 3
D
SSM3K15FV SOD-VESM-HF
2
S
G
1
DP_CA_DET 67
IN
DP_IG_CA_DET OUT
18
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
DISPLAYPORT SUPPORT DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
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1
POR IS PLASTIC MINI DP CONNECTOR BUT METAL PART’S SCHEMATIC AND CAD SUMBOLS HAVE BEEN USED BEACUSE ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES
Port Power Switch CRITICAL
L9400
63 36 32 21 7
5
=PP3V3_S5_DP_PORT_PWR
4
PM_SLP_S3_L
IN
IN
OUT OC*
EN
1
1
PP3V3_S0_DPILIM
3
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
TP_DPPWR_OC_L
2 0603
1
GND
RCLAMP0524P
SLP2510P8
SLP2510P8
PP3V3_S0_DPPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
2
C9400
9
4.7UF
2 2
D
D9410
RCLAMP0524P
FERR-120-OHM-3A
TPS2051B SOT23 8
DP_ESD CRITICAL
D9410
IO NC
20% 6.3V X5R-CERM 402
IO NC
1
5
10
6
IO NC
IO NC GND
U9480
DP_ESD CRITICAL
GND
D
3
3
4 7
CRITICAL
C9480
1
1
2
2
22UF 20% 6.3V X5R-CERM-1 603
C9481
C9485
4.7UF
1
1
2
2
20% 6.3V X5R-CERM-1 603
C9486 22UF
22UF
20% 6.3V X5R-CERM 402
20% 6.3V X5R-CERM-1 603
1
R9420 100K 5% 1/16W MF-LF 402
2
OMIT
CRITICAL
HDMI_CEC
J9400 MINIDSPLYPRT-K83 F-RT-THSM
FL9400
1
R9425
C
1M 5% 1/16W MF-LF
FL9403 72 66
IN
DP_ML_P
C9414
72 66
IN
DP_ML_N
C9415
BI
DP_AUX_CH_C_P
BI
DP_AUX_CH_C_N
2
1
2
10%
SYM_VER-2
X5R
6 8
402
0.1uF
0.1uF 72 66
10%
3
72 DP_ML_C_N 16V
X5R
SM PINS
1
72 DP_ML_C_P 16V
TH PINS
4
12-OHM-100MA TCM1210-4SM 4 1
TOP ROW
2
402
2
BOT ROW
2
72
DP_ML_CONN_P
10
72
DP_ML_CONN_N
12
402
14 16 18
72 66
67 8
20
R9443
1
72
DP_ML_CONN_N
100K
5% 1/16W MF-LF 402
R9421
5%
1
1/16W MF-LF
2
402
DP_CA_DET
9
72
DP_ML_CONN_P
ML_LANE3N GND AUX_CHP AUX_CHN DP_PWR
11
72
DP_ML_CONN_N
C9410
2
12-OHM-100MA TCM1210-4SM
5 1
SYM_VER-2
3
C9411
72 DP_ML_C_N
2
22
1
2 10%
72 DP_ML_C_P
C9412
72 DP_ML_C_N
C9413
72 DP_ML_C_P
C9416
72 DP_ML_C_N
C9417
1
2
DP_ML_N 16V
X5R
IN
66 72
IN
66 72
IN
66 72
IN
66 72
IN
66 72
402
10%
DP_ML_P 16V
X5R
402
0.1uF 2
FL9402
3
12-OHM-100MA TCM1210-4SM 1
SYM_VER-2
1
2 10%
0.1uF
DP_ML_N 16V
X5R
402
4
72 DP_ML_CONN_P
1
2 10%
17
DP_ML_P 16V
X5R
402
0.1uF 2
72 DP_ML_CONN_N
3
1
2 10%
DP_ML_N 16V
X5R
402
21
514-0691
MF-LF 402
2 2
IO NC
IO NC
1 10
DP_ESD CRITICAL DP_ESD
D9411
CRITICAL
RCLAMP0524P
3
D9400 3
SLP2510P8
RCLAMP0504F SC70-6-1
D
Q9440
B
66 72
1/16W
2
DP_CA_DET_L_Q
1
IN 402
0.1uF
GND G
X5R
5%
2N7002DW-X-G
S
16V
SLP2510P8
9
SOT-363
DP_ML_P
0.1uF
4
13
19
2 10%
FL9401
3
15
1
SHIELD PINS
RCLAMP0524P
1
D
Q9440
5
2N7002DW-X-G 6
SOT-363
S
G
5
6
1
DP_CA_DET_Q
4
1
Q9440 must have Drain to Gate leakage of 5MOhm
R9422
Cable Adapter
1M
(CA) has 100k
2
IO NC
IO NC
B
4 7
GND
DP to DVI/HDMI 5
3
5%
402
4
pull-up to DP_PWR.
1/16W MF-LF
3
2
=PP3V3_S0_DPCONN
R9445
1
R9444
10K
5% 1/16W
MF-LF 402
MF-LF 402
2
DP_HPD
OUT
1
10K
5% 1/16W
66
C
4
0.1uF
7
ML_LANE1N GND ML_LANE2P ML_LANE2N RETURN
SYM_VER-2
100K
6
67 8
1
72 DP_ML_C_P
HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2 ML_LANE0N GND GND ML_LANE3P ML_LANE1P
D9411
1
R9442
100K
OUT
DP_ML_CONN_P
DP_ESD
=PP3V3_S0_DPCONN
CRITICAL
66
12-OHM-100MA TCM1210-4SM 72
2
6
R9446
1
MCP79 requires pull down HPD input with
D
Q9441 2N7002DW-X-G
100K
100K if DP_HPD is used.
5% 1/16W
SOT-363
S
G
2
DP_HPD_L_Q
MF-LF 402
2
3
1
D
Q9441
A
2N7002DW-X-G SOT-363
S
G
5
SYNC_MASTER=K24_MLB
DP_HPD_Q
SYNC_DATE=04/06/2009
A
PAGE TITLE 4
R9423
1
DisplayPort Connector
DP Source must pull down HPD input with
100K
DRAWING NUMBER greater than or equal
5%
Apple Inc.
1/16W MF-LF 402
to 100K (DPv1.1a). 2
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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8
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6
5
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1
D
D
PLACEMENT_NOTE=PLACE NEAR L9710
CRITICAL
R9700
CRITICAL
0.020
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=9V
69
1 3
2 4
PLACEMENT_NOTE=PLACE CLOSE TO L9710
2 OUT ISNS_LCDBKLT_P
76 47
OUT ISNS_LCDBKLT_N
PLACEMENT_NOTE=PLACE CLOSE TO L9710
10% 25V X5R 402
C9710
1
1
10% 25V X5R 805
GND_LCDBKLT_PGND
68
R9730 10
10UF
PLACEMENT_NOTEs:
D9710
2 2
SOD-123 2
IHLP2020BZ11-SM
CRITICAL
0.1UF
76 47
1
1 C9713
CRITICAL
L9710 10UH-2.1A
PPVIN_BKL
PPVOUT_S0_LCDBKLT_SW
1
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=50V SWITCH_NODE=TRUE
PLACEMENT_NOTE=PLACE C9717 CLOSE TO D9710 PIN 2 & XW9701
2
CRITICAL RB160M-40
1
DIDT=TRUE
5% 1/16W MF-LF 402
4.7UF
f = 600kHz 2 68
LCDBKLT_VIN MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM
PP2V5_S0_LCDBKLT
2
1
C
PLACEMENT_NOTE=PLACE CLOSE TO U9700 PIN 1
C9727 1000PF
20
10% 25V X5R 603-1
SWA SWB
PP5V5_S0_LCDBKLT
23
VDC2
VOUT
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5.5V
5% 50V 2 C0G-CERM 603
C9700
1
1
2.2UF
20% 10V X5R-CERM 402
20% 10V X5R-CERM 402
2
2
IN
2
LVDS_IG_BKL_PWM
1
LVDS_IG_BKL_PWM_R
24
NOSTUFF
R9715 1M
LLP
OVP 16
1% 1/16W MF-LF 402
OVP = Vovp * (1 + Ra/Rb) VOVP = 6.9V +/- 0.35V
MC34845
18
5% 1/16W MF-LF 402
OMIT
10% 100V X7R 603
XW9701 SM
2
3
U9700
R9725 69 18
2
4
CRITICAL
(SGND)
0
1000PF
10% 50V X7R 1206
1
1
C9701
2.2UF
2
C9717
WF: C9711 AND C9717 NOT IN REF SCHEMATIC.
VDC1
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=2.5V
1UF
2.2UF
20% 50V X7R-CERM 1206
PWM WAKE
CH1
22
7
2
1
C9723
1
100PF
5% 50V CERM 402
2
NOSTUFF
C9722
2
LCDBKLT_OVP
NOSTUFF
C9721 100PF
1
1
C9725
2
NOSTUFF
C9724
100PF
100PF
5% 50V CERM 402
5% 50V CERM 402
1
6
EN
CH2
8
17
COMP
CH3
9
5% 50V CERM 402
(C9721-C9726)
NOSTUFF
C9726
1
100PF 2
BKL_MC_CH1
5% 50V CERM 402
2
R9717 1
15
ISET
MIN_LINE_WIDTH=0.2 MM
R9726
LCDBKLT_ISET
22K
MIN_LINE_WIDTH=0.2 MM
5%
C9705 10%
1
1
50V
0.0022UF
R9710 7.68K
CERM 402
1% 1/16W MF-LF 2 402
2
LCDBKLT_COMP_RC
CH5
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 11 BKL_MC_CH5
CH6
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 12 BKL_MC_CH6
FAIL
B
2
2
13
5% 50V CERM 402
19
56PF
5
GND
1
21
C9706
1% 1/16W MF-LF 2 402
PGNDA PGNDB
R9705
14
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
R9718 10.2 1
LED_RETURN_2
2
10.2
1
2
2
R9721
LED_RETURN_4 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
10.2 1
LED_RETURN_5
2 1% 1/16W MF-LF 402
LED_RETURN_3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
1% 1/16W MF-LF 402
10.2 1% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
R9719
1% 1/16W MF-LF 402
R9720 1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
1
10K
CH4
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 10 BKL_MC_CH4
LED_RETURN_1
2
BKL_MC_CH3
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
R9722 10.2 1
2 1% 1/16W MF-LF 402
LED_RETURN_6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
IN
7 65
IN
7 65
IN
7 65
IN
7 65
IN
7 65
IN
7 65
LCDBKLT_FAIL
R9702 1 THRM
0
PAD
5% 1/16W MF-LF 402
R9716
1
243K 1% 1/16W MF-LF 402 2
NOSTUFF
25
1/16W MF-LF
2 402
10.2 1% 1/16W MF-LF 402
BKL_MC_CH2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
1
C
PLACE NEAR U9700
100PF
5% 50V CERM 402
2
PLACEMENT_NOTEs:
NOSTUFF
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
LCDBKLT_COMP
7 47 65
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.24 MM VOLTAGE=50V
GND_LCDBKLT_PGND
VIN
C9711
C9716
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 MM
(C9710-C9711)
1
C9715
PPVOUT_S0_LCDBKLT
NOSTUFF CRITICAL 1
1
1% 0.25W MF-LF 805
PPBUS_S0_LCDBKLT_PWR
2
GND_LCDBKLT_SGND
OMIT
XW9700 SM 1
B
2
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.24 MM VOLTAGE=0V
ISET = 153mA /
PLACEMENT_NOT=PLACE XW9700 FAR FROM THE NOISY
PINS 3 AND 4
13.3 Inch Panel (9 LEDs per string) TARGET: ISET = 20MA, ACTUAL: ISET = 19.9MA,
OVP = 35V OVP = 35.2V
A
SYNC_MASTER=VEMURI_K19I
SYNC_DATE=02/09/2009
A
PAGE TITLE
LCD Backlight Driver (MC34845) DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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CRITICAL
Q9806
PPBUS S0 LCDBkLT FET
FDC638APZ_SBMS001 SSOT6-HF 6
F9800
MIN_LINE_WIDTH=0.4 mm
4
PPBUS_S0_LCDBKLT_FUSED
FDC638APZ
CHANNEL
P-TYPE
D
2
2
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
0402-HF
1
D
1
=PPBUS_S0_LCDBKLT
IN
5
2AMP-32V
8
MOSFET
1
VOLTAGE=12.6V
R9808
1
43 mOhm @4.5V
C9802
301K
LOADING
0.1UF
0.4 A (EDP)
3
1%
10% 1/16W
RDS(ON)
16V
2
MF-LF
X5R 402
402
2
PPBUS_S0_LCDBKLT_EN_DIV
1
R9809 147K 1% 1/16W MF-LF 402
2
PPBUS_S0_LCDBKLT_EN_L
Q9807
D
3
SSM6N15FEAPE SOT563
5
69 18
LVDS_IG_BKL_ON
IN
G
S
PPBUS_S0_LCDBKLT_PWR 4
OUT
68
MIN_LINE_WIDTH=0.4 mm
BKLT_EN_L
MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
Q9807
D
6
SSM6N15FEAPE SOT563
C
2
25
BKLT_PLT_RST_L
IN
G
S
C 1
B
B
1
R9840
1
1K
18 68
R9841 5%
1/16W MF-LF 402
18 69
LVDS_IG_BKL_PWM
1K
5%
2
LVDS_IG_BKL_ON
1/16W MF-LF
2
402
MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
LCD Backlight Support DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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FSB (Front-Side Bus) Constraints
3
2
1
CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
NET_TYPE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
FSB_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_D_L
10 14
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DINV_L
10 14 10 14
TABLE_PHYSICAL_RULE_ITEM
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
*
=2x_DIELECTRIC
?
FSB_DSTB
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
FSB_DATA
TOP,BOTTOM
=4x_DIELECTRIC
?
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
D
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
FSB_ADDR
*
=STANDARD
?
FSB_ADSTB
*
=2x_DIELECTRIC
?
FSB_1X
*
=STANDARD
?
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_N
10 14
10 14
WEIGHT
TABLE_SPACING_RULE_ITEM
FSB_DATA
FSB_DSTB0
FSB_DSTB_L_P
TABLE_SPACING_RULE_HEAD
WEIGHT
FSB 4X Signal Groups
FSB_DSTB_50S
TABLE_SPACING_RULE_ITEM
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
?
FSB_ADSTB
TOP,BOTTOM
=4x_DIELECTRIC
?
FSB_1X
TOP,BOTTOM
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_D_L
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DINV_L
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_P
10 14 10 14
10 14
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_N
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_D_L
10 14 10 14
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DINV_L
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_P
10 14
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_N
10 14
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_D_L
10 14
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DINV_L
10 14 10 14 10 14
D
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended. FSB 4X signals / groups shown in signal table on right. Signals within each 4x group should be matched within 5 ps of strobe. FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_P
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_N
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps. Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
FSB 2X
FSB 2X signals / groups shown in signal table on right. Signals within each 2x group should be matched within 20 ps.
ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
Signals
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_A_L
10 14
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_REQ_L
10 14
FSB_ADSTB0
FSB_50S
FSB_ADSTB
FSB_ADSTB_L
10 14
FSB_ADDR_GROUP1
FSB_50S
FSB_ADDR
FSB_A_L
10 14
FSB_ADSTB1
FSB_50S
FSB_ADSTB
FSB_ADSTB_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_ADS_L
10 14
FSB_BREQ0_L
FSB_50S
FSB_1X
FSB_BREQ0_L
10 14
FSB_BREQ1_L
FSB_50S
FSB_1X
FSB_BREQ1_L
14
FSB_1X
FSB_50S
FSB_1X
FSB_BNR_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_BPRI_L
10 14 10 14
FSB 1X signals shown in signal table on right. Signals within each 1x group should be matched to CPU clock, +0/-1000 mils. Design Guide recommends each strobe/signal group is routed on the same layer.
FSB 1X Signals
Intel Design Guide recommends FSB signals be routed only on internal layers. NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints
FSB_1X
FSB_50S
FSB_1X
FSB_DBSY_L
FSB_1X
FSB_50S
FSB_1X
FSB_DEFER_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_DRDY_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_HIT_L
FSB_1X
FSB_50S
FSB_1X
FSB_HITM_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_LOCK_L
10 14
FSB_CPURST_L
FSB_50S
FSB_1X
FSB_CPURST_L
10 13 14
FSB_1X
FSB_50S
FSB_1X
FSB_RS_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_TRDY_L
10 14
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_A20M_L
10 14
CPU_BSEL
CPU_50S
CPU_AGTL
CPU_BSEL
9 10
CPU_FERR_L
CPU_50S
CPU_8MIL
CPU_FERR_L
10 14
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_IGNNE_L
10 14
CPU_INIT_L
CPU_50S
CPU_AGTL
CPU_INIT_L
10 14
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_INTR
10 14
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_NMI
10 14 37 10 13 14
10 14
TABLE_PHYSICAL_RULE_HEAD
C
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
CPU_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
C
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance. TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CPU_AGTL
*
=STANDARD
?
CPU_8MIL
*
8 MIL
?
TABLE_SPACING_RULE_ITEM
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
CPU_COMP
*
25 MIL
10 14
? CPU_PROCHOT_L
CPU_50S
CPU_AGTL
CPU_PROCHOT_L
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_SMI_L
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_STPCLK_L
10 14
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
PM_THRMTRIP_L
10 14 37
FSB_CPUSLP_L
CPU_50S
CPU_AGTL
FSB_CPUSLP_L
10 14
CPU_FROM_SB
CPU_50S
CPU_AGTL
CPU_DPSLP_L
10 14
CPU_DPRSTP_L
CPU_50S
CPU_AGTL
CPU_DPRSTP_L
10 14 59
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
CPU_ASYNC
CPU_50S
CPU_AGTL
FSB_DPWR_L
10 14
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_BCLK_VML_COMP_VDD
14
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_BCLK_VML_COMP_GND
14 14
TABLE_SPACING_RULE_ITEM
CPU_GTLREF
*
25 MIL
?
CPU_ITP
*
=2:1_SPACING
?
CPU_VCCSENSE
*
25 MIL
?
SR DG recommends at least 25 mils, >50 mils preferred TABLE_SPACING_RULE_ITEM
10 14
TABLE_SPACING_RULE_ITEM
Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance.
MCP FSB COMP Signal Constraints
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP_VCC
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP_GND
14
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU_P
10 14
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU_N
10 14
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP_P
13 14 13 14
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
MCP_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
B
=50_OHM_SE
=STANDARD
=STANDARD
B
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
MCP_FSB_COMP
*
8 MIL
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP_N
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP_P
14
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP_N
14
CPU_IERR_L
CPU_50S
CPU_IERR_L
10
PM_DPRSLPVR
CPU_50S
CPU_AGTL
PM_DPRSLPVR
21 59
(See above)
CPU_50S
CPU_AGTL
IMVP_DPRSLPVR
59
CPU_GTLREF
CPU_50S
CPU_GTLREF
CPU_GTLREF
10 26
?
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
FSB Clock Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
CLK_FSB_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
*
=3x_DIELECTRIC
CPU_50S
CPU_COMP
CPU_COMP
10
CPU_27P4S
CPU_COMP
CPU_COMP
10
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
10
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_COMP
10
XDP_TDI
CPU_50S
CPU_ITP
XDP_TDI
10 13
XDP_TDO
CPU_50S
CPU_ITP
XDP_TDO
10 13
XDP_TMS
CPU_50S
CPU_ITP
XDP_TMS
10 13
XDP_TCK
CPU_50S
CPU_ITP
XDP_TCK
10 13
XDP_TRST_L
CPU_50S
CPU_ITP
XDP_TRST_L
10 13
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_L
10 13 10 13
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CLK_FSB
CPU_COMP CPU_COMP
TABLE_SPACING_RULE_ITEM
?
CLK_FSB
TOP,BOTTOM
=4x_DIELECTRIC
?
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
A
XDP_BPM_L5
CPU_50S
CPU_ITP
XDP_BPM_L
(FSB_CPURST_L)
CPU_50S
CPU_ITP
XDP_CPURST_L
13
CPU_50S
CPU_8MIL
CPU_VID
11 59
CPU_50S
CPU_8MIL
IMVP6_VID
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE_P
11 59
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE_N
11 59
(CPU_VCCSENSE)
CPU_27P4S
CPU_VCCSENSE
IMVP6_VSEN_P
(CPU_VCCSENSE)
CPU_27P4S
CPU_VCCSENSE
IMVP6_VSEN_N
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
CPU/FSB Constraints DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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Memory Bus Constraints
4
3
2
1
Memory Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
NET_TYPE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CLK_P
15 27
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CLK_N
15 27
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CKE
15 27
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CS_L
15 27 15 27
TABLE_PHYSICAL_RULE_ITEM
MEM_40S_VDD
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD TABLE_PHYSICAL_RULE_ITEM
MEM_70D
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_70D_VDD
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_ODT
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_A
15 27
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_BA
15 27
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_RAS_L
15 27
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CAS_L
15 27 15 27
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
D
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4:1_SPACING
?
D
TABLE_SPACING_RULE_ITEM
MEM_CLK2MEM
*
TABLE_SPACING_RULE_ITEM
MEM_CTRL2CTRL
*
=2:1_SPACING
?
MEM_CTRL2MEM
*
=2.5:1_SPACING
?
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_WE_L
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ
15 27 15 27
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MEM_CMD2CMD
*
=1.5:1_SPACING
? TABLE_SPACING_RULE_ITEM
MEM_CMD2MEM
*
=3:1_SPACING
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ
15 27
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ
15 27 15 27
? TABLE_SPACING_RULE_ITEM
MEM_DATA2DATA
*
=1.5:1_SPACING
?
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ
15 27
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ
15 27 15 27
TABLE_SPACING_RULE_ITEM
MEM_DATA2MEM
*
=3:1_SPACING
? TABLE_SPACING_RULE_ITEM
MEM_DQS2MEM
*
=3:1_SPACING
?
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQ
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27 15 27
TABLE_SPACING_RULE_ITEM
MEM_2OTHER
*
25 MIL
?
Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
*
MEM_CLK2MEM
MEM_CLK
MEM_CTRL
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CLK
*
MEM_CMD2MEM
MEM_CMD
MEM_CTRL
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CMD
*
MEM_CLK2MEM
MEM_CLK
MEM_DATA
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CMD
*
MEM_CMD2CMD
MEM_CMD
MEM_DATA
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_DQS
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK2MEM
MEM_CMD
MEM_DQS
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
C
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
*
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
*
MEM_CTRL2MEM
MEM_DATA
MEM_CTRL
*
MEM_DATA2MEM
MEM_DATA
MEM_CMD
*
MEM_DATA2MEM
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_CTRL2MEM
MEM_DATA
*
MEM_DQS
*
NET_SPACING_TYPE2
AREA_TYPE
MEM_DATA
SPACING_RULE_SET
MEM_DQS
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
MEM_CLK
*
MEM_DQS2MEM
MEM_DQS
MEM_CTRL
*
MEM_DQS2MEM
MEM_CLK
*
*
MEM_2OTHER
MEM_CTRL
*
*
MEM_2OTHER
*
MEM_DATA
MEM_DQS2MEM
*
15 27
MEM_A_DQS4
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CLK_P
15 28
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CLK_N
15 28
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CKE
15 28
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CS_L
15 28
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_ODT
MEM_CMD
*
*
MEM_2OTHER
15 28
15 28
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS2MEM
MEM_DATA
*
*
MEM_2OTHER MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_A
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_BA
15 28
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_RAS_L
15 28
DDR2:
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CAS_L
15 28
DQ signals should be matched within 20 ps of associated DQS pair.
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_WE_L
15 28
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_DQS
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS2MEM
MEM_DQS
*
*
MEM_2OTHER
Need to support MEM_*-style wildcards!
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. All DQS pairs should be matched within 100 ps of clocks. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
B
All memory signals maximum length is 1.005 ps.
CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric. MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
DDR3:
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
DQ signals should be matched within 5 ps of associated DQS pair.
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DM
15 28
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DM
15 28
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DM
15 28
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DM
15 28
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DM
15 28 15 28
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. A/BA/cmd signals should be matched within 5 ps of CLK pairs. All memory signals maximum length is 1.005 ps.
C
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_A_DQS_P
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_DQS
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_70D
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
15 27
MEM_A_DQS4
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
MEM_A_DQS_N
MEM_DATA2DATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DQS
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_DQS
MEM_70D
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_70D
MEM_A_DQS3
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_A_DQS3
MEM_A_DQS_P
CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric. MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DM
15 28
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DM
15 28
MCP MEM COMP Signal Constraints
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28 15 28
B
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS_P
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28 15 28
TABLE_PHYSICAL_RULE_ITEM
MCP_MEM_COMP
*
Y
7 MIL
7 MIL
=STANDARD
=STANDARD
=STANDARD
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS_N
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28 15 28
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
MCP_MEM_COMP
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
A
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_B_DQS_N
MEM_B_DQS7
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28
MEM_B_DQS7
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP_VDD
16
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP_GND
16
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
Memory Constraints DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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1
NET_TYPE
PCI-Express
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP PCIE_90D
PCIE
PCIE_MINI_R2D_P
30
PCIE_90D
PCIE
PCIE_MINI_R2D_N
30
PCIE_90D
PCIE
PCIE_MINI_R2D_C_P
17 30
PCIE_90D
PCIE
PCIE_MINI_R2D_C_N
17 30
PCIE_90D
PCIE
PCIE_MINI_D2R_P
17 30
PCIE_90D
PCIE
PCIE_MINI_D2R_N
17 30
PCIE_90D
PCIE
PCIE_FW_R2D_P
PCIE_90D
PCIE
PCIE_FW_R2D_N
PCIE_90D
PCIE
PCIE_FW_R2D_C_P
9 17
PCIE_90D
PCIE
PCIE_FW_R2D_C_N
9 17
PCIE_90D
PCIE
PCIE_FW_D2R_P
9 17
PCIE_90D
PCIE
PCIE_FW_D2R_N
9 17
PCIE_90D
PCIE
PCIE_FW_D2R_C_P
PCIE_90D
PCIE
PCIE_FW_D2R_C_N
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_MINI_P
17 30
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_MINI_N
17 30
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_MINI_CONN_P
7 30
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_MINI_CONN_N
7 30
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_FC_P
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_FC_N
PCIE_90D
PCIE
CONN_PCIE_MINI_R2D_P
7 30
PCIE_90D
PCIE
CONN_PCIE_MINI_R2D_N
7 30
TABLE_PHYSICAL_RULE_ITEM
PCIE_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM
CLK_PCIE_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
PCIE_MINI_R2D
=100_OHM_DIFF
PCIE_MINI_D2R TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PCIE
*
TABLE_SPACING_RULE_ITEM
?
=3X_DIELECTRIC
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
D
CLK_PCIE
*
20 MIL
?
MCP_PEX_COMP
*
8 MIL
?
TABLE_SPACING_RULE_ITEM
PCIE_FW_R2D
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4
PCIE_FW_D2R
MCP_PE1_REFCLK
MCP_PE4_REFCLK
D
PCIE_90D PCIE
CONN_PCIE_MINI_D2R_P
7 30
PCIE
CONN_PCIE_MINI_D2R_N
7 30
PCIE_90D
MCP_PEX_CLK_COMP
C
MCP_PEX_COMP
MCP_PEX_CLK_COMP
17
C
Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
DP_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LVDS_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_DV_COMP
*
Y
20 MIL
20 MIL
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TMDS_IG_TXC
DP_100D
DISPLAYPORT
TMDS_IG_TXC_P
TMDS_IG_TXC
DP_100D
DISPLAYPORT
TMDS_IG_TXC_N
TMDS_IG_TXD
DP_100D
DISPLAYPORT
TMDS_IG_TXD_P
TMDS_IG_TXD
DP_100D
DISPLAYPORT
TMDS_IG_TXD_N
DP_ML
DP_100D
DISPLAYPORT
DP_ML_P
66 67
DP_100D
DISPLAYPORT
DP_ML_C_P
67
DP_100D
DISPLAYPORT
DP_ML_N
66 67
DP_100D
DISPLAYPORT
DP_ML_C_N
67
DP_100D
DISPLAYPORT
DP_IG_AUX_CH_P
18 66
DP_100D
DISPLAYPORT
DP_IG_AUX_CH_N
18 66
DP_100D
DISPLAYPORT
DP_AUX_CH_SW_P
66
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
DP_100D
DISPLAYPORT
DP_AUX_CH_SW_N
66
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
DP_100D
DISPLAYPORT
DP_AUX_CH_C_P
66 67
DP_100D
DISPLAYPORT
DP_AUX_CH_C_N
66 67
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
DISPLAYPORT
*
=3x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
DP_ML
LVDS
*
=3x_DIELECTRIC
LVDS intra-pair matching should be 5 mils.
?
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
?
Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. DIsplayPort AUX CH intra-pair matching should be 5 ps.
DP_AUX_CH
Inter-pair matching should be within 150 ps. No relationship to other signals.
SATA Interface Constraints MCP_HDMI_RSET
MCP_DV_COMP
MCP_HDMI_RSET
18 24
MCP_HDMI_VPROBE
MCP_DV_COMP
MCP_HDMI_VPROBE
18 24
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_CLK_P
18 65
LVDS_100D
LVDS
LVDS_IG_A_CLK_F_P
7 65
LVDS_100D
LVDS
LVDS_IG_A_CLK_N
18 65
LVDS_100D
LVDS
LVDS_IG_A_CLK_F_N
7 65
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA_P
7 18 65
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA_N
7 18 65
DP_ML
DP_100D
DISPLAYPORT
DP_ML_CONN_P
67
DP_100D
DISPLAYPORT
DP_ML_CONN_N
67
MCP_IFPAB_RSET
18 24
MCP_IFPAB_VPROBE
18 24
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
SATA_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SATA_90D_HDD
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
LVDS_IG_A_CLK
TABLE_SPACING_RULE_HEAD
B
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SATA
*
=4x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
SATA
TOP,BOTTOM
=3x_DIELECTRIC
B
?
TABLE_SPACING_RULE_ITEM
SATA_TERMP
*
8 MIL
? I183
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
I182
MCP_IFPAB_RSET
MCP_DV_COMP
MCP_IFPAB_VPROBE
SATA_HDD_R2D
SATA_HDD_D2R
SATA_ODD_R2D
A
SATA_ODD_D2R
MCP_SATA_TERMP
SATA_90D_HDD
SATA
SATA_HDD_R2D_C_P
20 34
SATA_90D_HDD
SATA
SATA_HDD_R2D_C_N
20 34
SATA_90D_HDD
SATA
SATA_HDD_R2D_P
7 34
SATA_90D_HDD
SATA
SATA_HDD_R2D_N
7 34
SATA_90D_HDD
SATA
SATA_HDD_R2D_UF_P
34
SATA_90D_HDD
SATA
SATA_HDD_R2D_UF_N
34
SATA_90D_HDD
SATA
SATA_HDD_D2R_P
20 34
SATA_90D_HDD
SATA
SATA_HDD_D2R_N
20 34
SATA_90D_HDD
SATA
SATA_HDD_D2R_C_P
7 34
SATA_90D_HDD
SATA
SATA_HDD_D2R_C_N
7 34
SATA_90D_HDD
SATA
SATA_HDD_D2R_UF_P
34
SATA_90D_HDD
SATA
SATA_HDD_D2R_UF_N
34
SATA_100D
SATA
SATA_ODD_R2D_C_P
20 34
SATA_100D
SATA
SATA_ODD_R2D_C_N
20 34
SATA_100D
SATA
SATA_ODD_R2D_P
7 34
SATA_100D
SATA
SATA_ODD_R2D_N
7 34
SATA_100D
SATA
SATA_ODD_R2D_UF_P
34
SATA_100D
SATA
SATA_ODD_R2D_UF_N
34
SATA_100D
SATA
SATA_ODD_D2R_P
20 34
SATA_100D
SATA
SATA_ODD_D2R_N
20 34
SATA_100D
SATA
SATA_ODD_D2R_C_P
7 34
SATA_100D
SATA
SATA_ODD_D2R_C_N
7 34
SATA_100D
SATA
SATA_ODD_D2R_UF_P
34
SATA_100D
SATA
SATA_ODD_D2R_UF_N
34
SATA_TERMP
MCP_SATA_TERMP
20
SYNC_MASTER=K24_MLB
SYNC_DATE=03/30/2009
A
PAGE TITLE
MCP Constraints 1 DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD
NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
PCI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PHYSICAL
ELECTRICAL_CONSTRAINT_SET
SPACING
TABLE_PHYSICAL_RULE_ITEM
MCP_DEBUG
PCI_55S
PCI
MCP_DEBUG
PCI_AD
PCI_55S
PCI
PCI_AD
13 19
TABLE_PHYSICAL_RULE_ITEM
CLK_PCI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PCI_AD24
PCI_55S
PCI
PCI_AD
PCI_AD
PCI_55S
PCI
PCI_AD
PCI_AD
PCI_55S
PCI
PCI_PAR
PCI_C_BE_L
PCI_55S
PCI
PCI_C_BE_L
PCI_CNTL
PCI_55S
PCI
PCI_IRDY_L
PCI_CNTL
PCI_55S
PCI
PCI_DEVSEL_L
PCI_CNTL
PCI_55S
PCI
PCI_PERR_L
PCI_CNTL
PCI_55S
PCI
PCI_SERR_L
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
PCI
*
=STANDARD
? TABLE_SPACING_RULE_ITEM
CLK_PCI
D
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LPC Bus Constraints
D
PCI_CNTL
PCI_55S
PCI
PCI_STOP_L
PCI_CNTL
PCI_55S
PCI
PCI_TRDY_L
PCI_CNTL
PCI_55S
PCI
PCI_FRAME_L
PCI_REQ0_L
PCI_55S
PCI
PCI_REQ0_L
PCI_GNT0_L
PCI_55S
PCI
PCI_GNT0_L
PCI_REQ1_L
PCI_55S
PCI
PCI_REQ1_L
PCI_GNT1_L
PCI_55S
PCI
PCI_GNT1_L
PCI_INTW_L
PCI_55S
PCI
PCI_INTW_L
PCI_INTX_L
PCI_55S
PCI
PCI_INTX_L
PCI_INTY_L
PCI_55S
PCI
PCI_INTY_L
PCI_INTZ_L
PCI_55S
PCI
PCI_INTZ_L
MCP_PCI_CLK2
CLK_PCI_55S
CLK_PCI
PCI_CLK33M_MCP_R
CLK_PCI_55S
CLK_PCI
PCI_CLK33M_MCP
19
LPC_AD
LPC_55S
LPC
LPC_AD
19 36 38
LPC_FRAME_L
LPC_55S
LPC
LPC_FRAME_L
19 36 38
LPC_RESET_L
LPC_55S
LPC
LPC_RESET_L
19 25
MCP_LPC_CLK0
CLK_LPC_55S
CLK_LPC
LPC_CLK33M_SMC_R
19 25
CLK_LPC_55S
CLK_LPC
LPC_CLK33M_SMC
25 36
CLK_LPC_55S
CLK_LPC
LPC_CLK33M_LPCPLUS
25 38
USB_90D
USB
USB_EXTA_P
20 35
USB_90D
USB
USB_EXTA_N
20 35
USB_90D
USB
USB_EXTA_MUXED_P
35
USB_90D
USB
USB_EXTA_MUXED_N
35
USB_90D
USB
CONN_USB_EXTA_P
35
USB_90D
USB
CONN_USB_EXTA_N
35
USB_90D
USB
USB_CAMERA_P
20 65
USB_90D
USB
USB_CAMERA_N
20 65
USB_90D
USB
USB_CAMERA_CONN_P
7 65
USB_90D
USB
USB_CAMERA_CONN_N
7 65
USB_90D
USB
USB_BT_P
20 30
USB_90D
USB
USB_BT_N
20 30
USB_90D
USB
CONN_USB2_BT_P
USB_90D
USB
CONN_USB2_BT_N
7 30
USB_90D
USB
USB_TPAD_P
20 44
USB_90D
USB
USB_TPAD_N
20 44
USB_90D
USB
USB_TPAD_R_P
44
USB_90D
USB
USB_TPAD_R_N
44
USB_90D
USB
USB_IR_P
9 20
USB_90D
USB
USB_IR_N
9 20
USB_90D
USB
USB_EXTB_P
20 35
USB_90D
USB
USB_EXTB_N
20 35
USB_90D
USB
CONN_USB_EXTB_P
35
USB_90D
USB
CONN_USB_EXTB_N
35
USB_90D
USB
USB_CARDREADER_P
9 20
USB_90D
USB
USB_CARDREADER_N
9 20
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
LPC_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
19
=STANDARD TABLE_PHYSICAL_RULE_ITEM
CLK_LPC_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LINE-TO-LINE SPACING
WEIGHT
LPC
LAYER *
6 MIL
?
CLK_LPC
*
8 MIL
?
19
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.
USB 2.0 Interface Constraints
19
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
MCP_USB_RBIAS
*
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD TABLE_PHYSICAL_RULE_ITEM
USB_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_HEAD
USB_EXTA
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
USB
C
*
TABLE_SPACING_RULE_ITEM
USB
TOP,BOTTOM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.
C
SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SMB_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
USB_CAMERA TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
SMB
*
USB_BT
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.
HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
USB_TPAD
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
7 30
TABLE_PHYSICAL_RULE_ITEM
HDA_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
USB_IR
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
HDA
=2x_DIELECTRIC
*
?
USB_EXTB TABLE_SPACING_RULE_ITEM
MCP_HDA_COMP
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1. USB_SD
B
SIO Signal Constraints
B
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
MCP_USB_RBIAS
MCP_USB_RBIAS
MCP_USB_RBIAS_GND
20
SMBUS_MCP_0_CLK
SMB_55S
SMB
SMBUS_MCP_0_CLK
13 21 39
SMBUS_MCP_0_DATA
SMB_55S
SMB
SMBUS_MCP_0_DATA
13 21 39
SMBUS_MCP_1_CLK
SMB_55S
SMB
SMBUS_MCP_1_CLK
21 39
SMBUS_MCP_1_DATA
SMB_55S
SMB
SMBUS_MCP_1_DATA
21 39
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.
HDA_BIT_CLK
HDA_55S
HDA
HDA_BIT_CLK
21 49
HDA_55S
HDA
HDA_BIT_CLK_R
21
SPI Interface Constraints
HDA_SYNC
HDA_55S
HDA
HDA_SYNC
HDA_55S
HDA
HDA_SYNC_R
21
HDA_55S
HDA
HDA_RST_R_L
21
HDA_55S
HDA
HDA_RST_L
21 49
HDA_55S
HDA
HDA_SDIN0
21 49
HDA_55S
HDA
HDA_SDIN_CODEC
HDA_55S
HDA
HDA_SDOUT
21 49
HDA_55S
HDA
HDA_SDOUT_R
21
CLK_SLOW_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
8 MIL
?
TABLE_SPACING_RULE_ITEM
CLK_SLOW
*
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
=55_OHM_SE
=55_OHM_SE
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP HDA_RST_L
21 49
TABLE_PHYSICAL_RULE_ITEM
SPI_55S
*
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD HDA_SDIN0
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT HDA_SDOUT TABLE_SPACING_RULE_ITEM
SPI
*
8 MIL
?
MCP_HDA_COMP
MCP_HDA_PULLDN_COMP
21
CLK_SLOW_55S
CLK_SLOW
PM_CLK32K_SUSCLK_R
21 25
CLK_SLOW_55S
CLK_SLOW
PM_CLK32K_SUSCLK
25 36
SPI_55S
SPI
SPI_CLK_R
21 38 48
SPI_55S
SPI
SPI_CLK
48
SPI_55S
SPI
SPI_ALT_CLK
38
SPI_55S
SPI
SPI_MOSI_R
21 38 48
SPI_55S
SPI
SPI_MOSI
48
SPI_55S
SPI
SPI_ALT_MOSI
38
SPI_55S
SPI
SPI_MISO
21 38 48
SPI_55S
SPI
SPI_MISO_R
48
SPI_55S
SPI
SPI_ALT_MISO
38
SPI_55S
SPI
SPI_CS0_R_L
21 38
SPI_55S
SPI
SPI_CS0_L
SPI_55S
SPI
SPI_CS1_R_L
SPI_55S
SPI
SPI_CS1_R_L_USE_MLB
MCP_HDA_PULLDN_COMP
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14. MCP_SUS_CLK
SPI_CLK
A
SPI_MOSI
SPI_MISO
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
MCP Constraints 2 DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
REVISION
C.0.0
R SPI_CS0
A
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MCP RGMII (Ethernet) Constraints TABLE_PHYSICAL_RULE_HEAD
NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MCP_MII_COMP
*
=STANDARD
7.5 MIL
7.5 MIL
=STANDARD
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP_VDD
18
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP_GND
18
MCP_CLK25M_BUF0
ENET_MII_55S
MCP_BUF0_CLK
MCP_CLK25M_BUF0_R
18 32
ENET_MII_55S
MCP_BUF0_CLK
RTL8211_CLK25M_CKXTAL1
31 32
ENET_MII_55S
ENET_MII
ENET_INTR_L
ENET_MDIO
ENET_MII_55S
ENET_MII
ENET_MDIO
18 31
ENET_MDC
ENET_MII_55S
ENET_MII
ENET_MDC
18 31
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII
ENET_CLK125M_RXCLK_R
31
ENET_MII_55S
ENET_MII
ENET_CLK125M_RXCLK
18 31
ENET_MII_55S
ENET_MII
ENET_RXD_R
31 18 31
TABLE_PHYSICAL_RULE_ITEM
ENET_MII_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
MCP_BUF0_CLK
*
=3:1_SPACING
?
ENET_MII
*
12 MIL
?
ENET_INTR_L TABLE_SPACING_RULE_ITEM
D
D
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
88E1116R (Ethernet PHY) Constraints
ENET_RXCLK TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ENET_MDI_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_RXD
ENET_RXD_STRAP
ENET_MII_55S
ENET_MII
ENET_RXD
18 31
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_RX_CTRL
18 31
ENET_MII_55S
ENET_MII
ENET_RXCTL_R
31
ENET_MII_55S
ENET_MII
ENET_CLK125M_TXCLK_R
31 18 31
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
25 MIL
?
TABLE_SPACING_RULE_ITEM
ENET_MDI
*
ENET_TXCLK
ENET_MII_55S
ENET_MII
ENET_CLK125M_TXCLK
ENET_TXD0
ENET_MII_55S
ENET_MII
ENET_TXD
18 31
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_TXD
18 31
ENET_MII_55S
ENET_MII
ENET_TX_CTRL
18 31
ENET_MII_55S
ENET_MII
ENET_RESET_L
18 31
ENET_MDI_100D
ENET_MDI
ENET_MDI_P
31 33
ENET_MDI_100D
ENET_MDI
ENET_MDI_N
31 33
ENET_MDI_100D
ENET_MDI
ENET_MDI_TRAN_P
33
ENET_MDI_100D
ENET_MDI
ENET_MDI_TRAN_N
33
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4 ENET_TXD
ENET_MDI
C
C
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
Ethernet Constraints DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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104 OF 109 SHEET
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SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
NET_TYPE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
D
SMBUS_SMC_A_S3_SCL
SMB_55S
SMB
SMBUS_SMC_A_S3_SCL
7 39
SMBUS_SMC_A_S3_SDA
SMB_55S
SMB
SMBUS_SMC_A_S3_SDA
7 39 39
SMBUS_SMC_B_S0_SCL
SMB_55S
SMB
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMB_55S
SMB
SMBUS_SMC_B_S0_SDA
39
SMBUS_SMC_0_S0_SCL
SMB_55S
SMB
SMBUS_SMC_0_S0_SCL
39
SMBUS_SMC_0_S0_SDA
SMB_55S
SMB
SMBUS_SMC_0_S0_SDA
39
SMBUS_SMC_BSA_SCL
SMB_55S
SMB
SMBUS_SMC_BSA_SCL
7 39
SMBUS_SMC_BSA_SDA
SMB_55S
SMB
SMBUS_SMC_BSA_SDA
7 39
SMBUS_SMC_MGMT_SCL
SMB_55S
SMB
SMBUS_SMC_MGMT_SCL
39
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB
SMBUS_SMC_MGMT_SDA
39
D
SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET
PHYSICAL
CHGR_CSI
CHGR_CSO
SPACING
1TO1_DIFFPAIR
CHGR_CSI_P
1TO1_DIFFPAIR
CHGR_CSI_N
1TO1_DIFFPAIR
CHGR_CSO_P
1TO1_DIFFPAIR
CHGR_CSO_N
C
C
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
SMC Constraints DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
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PAGE
106 OF 109 SHEET
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K84 SENSOR NET PROPERTIES TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
NET_TYPE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP PHYSICAL
ELECTRICAL_CONSTRAINT_SET
SPACING
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
D
DIFFPAIR
CHGR_CSO_R_P
56
DIFFPAIR
CHGR_CSO_R_N
56
DIFFPAIR
CPUTHMSNS_D2_P
42
DIFFPAIR
CPUTHMSNS_D2_N
42
DIFFPAIR
CPU_THERMD_P
10 42
DIFFPAIR
CPU_THERMD_N
10 42
DIFFPAIR
ISNS_CPUVTT_P
41
DIFFPAIR
ISNS_CPUVTT_N
41
DIFFPAIR
ISNS_HDD_P
34 47
DIFFPAIR
ISNS_HDD_N
34 47
DIFFPAIR
ISNS_HDD_R_P
47
DIFFPAIR
ISNS_HDD_R_N
47
DIFFPAIR
MCPTHMSNS_D2_P
42
DIFFPAIR
MCPTHMSNS_D2_N
42
DIFFPAIR
MCP_THMDIODE_P
21 42
DIFFPAIR
MCP_THMDIODE_N
21 42
DIFFPAIR
ISNS_ODD_P
34 47
DIFFPAIR
ISNS_ODD_N
34 47
DIFFPAIR
ISNS_ODD_R_P
47
DIFFPAIR
ISNS_ODD_R_N
47
DIFFPAIR
ISNS_AIRPORT_P
30 47
DIFFPAIR
ISNS_AIRPORT_N
30 47
DIFFPAIR
ISNS_AIRPORT_R_P
47
DIFFPAIR
ISNS_AIRPORT_R_N
47
DIFFPAIR
ISNS_1V5_S3_P
47 58
DIFFPAIR
ISNS_1V5_S3_N
47 58
DIFFPAIR
ISNS_1V5_S3_R_P
47
DIFFPAIR
ISNS_1V5_S3_R_N
47
DIFFPAIR
ISNS_LCDBKLT_P
47 68
DIFFPAIR
ISNS_LCDBKLT_N
47 68
D
C
C
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=01/19/2009
A
PAGE TITLE
K84 SPECIAL CONSTRAINTS DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
107 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
K84 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS (MIL or MM)
ALLEGRO VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA_P1MM
MM
15.5.1
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.1 MM
?
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
*
*
BGA_P1MM
BGA_P1MM
TABLE_SPACING_RULE_ITEM
DEFAULT
*
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
STANDARD
*
=DEFAULT
?
DEFAULT
*
Y
=50_OHM_SE
0.100MM
30 MM
0 MM
0 MM
*
Y
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
MEM_CLK
*
BGA_P1MM
BGA_P1MM
*
=DEFAULT
?
BGA_P2MM
*
=DEFAULT
?
CLK_FSB
*
BGA_P1MM
BGA_P2MM
CLK_LPC
*
BGA_P1MM
BGA_P2MM
BGA_P3MM
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
=DEFAULT
*
?
TOP,BOTTOM
Y
STANDARD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
CLK_PCI
*
BGA_P1MM
BGA_P2MM
CLK_PCIE
*
BGA_P1MM
BGA_P2MM
CLK_SLOW
*
BGA_P1MM
BGA_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
DIFFPAIR NECK GAP
D
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
BGA_P1MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
MEM_40S_VDD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
LAYER
STANDARD
BGA_P2MM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
BGA_P1MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
D
AREA_TYPE
MEM_40S
DIFFPAIR NECK GAP
STANDARD
ALLOW ROUTE ON LAYER?
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM
0.090 MM
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.090 MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
1.5:1_SPACING
*
0.15 MM
?
2:1_SPACING
*
0.2 MM
?
TABLE_SPACING_ASSIGNMENT_ITEM
FSB_DSTB
=STANDARD
FSB_DSTB
BGA_P1MM
BGA_P3MM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
50_OHM_SE
TOP,BOTTOM
Y
0.115 MM
0.115 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAP
2.5:1_SPACING
*
0.25 MM
?
3:1_SPACING
*
0.3 MM
?
4:1_SPACING
*
0.4 MM
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
50_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
TOP,BOTTOM
Y
0.165 MM
0.100 MM
40_OHM_SE
*
Y
0.126 MM
0.100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
2X_DIELECTRIC
TOP,BOTTOM
0.140 MM
?
3X_DIELECTRIC
TOP,BOTTOM
0.210 MM
?
4X_DIELECTRIC
TOP,BOTTOM
0.280 MM
?
5X_DIELECTRIC
TOP,BOTTOM
0.350 MM
?
2X_DIELECTRIC
*
0.126 MM
?
3X_DIELECTRIC
*
0.189 MM
?
4X_DIELECTRIC
*
0.252 MM
?
5X_DIELECTRIC
*
0.315 MM
?
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
0.310 MM
27P4_OHM_SE
*
Y
0.222 MM
0.222 MM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
TABLE_SPACING_RULE_ITEM
=STANDARD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
70_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
70_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.151 MM
0.100 MM
=STANDARD
0.224 MM
=STANDARD
0.224 MM
70_OHM_DIFF
TOP,BOTTOM
Y
0.185 MM
0.100 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
90_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.095 MM
0.095 MM
0.234 MM
0.234 MM
90_OHM_DIFF
TOP,BOTTOM
Y
0.112 MM
0.112 MM
0.220 MM
0.220 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.075 MM
0.075 MM
0.244 MM
0.244 MM
100_OHM_DIFF
TOP,BOTTOM
Y
0.091 MM
0.091 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_OHM_DIFF_HDD
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF_HDD
ISL3,ISL4,ISL9,ISL10
Y
0.083 MM
0.083 MM
0.400 MM
0.400 MM
100_OHM_DIFF_HDD
TOP,BOTTOM
Y
0.095 MM
0.095 MM
0.400 MM
0.400 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
110_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.075 MM
0.075 MM
0.330 MM
0.330 MM
TABLE_PHYSICAL_RULE_ITEM
C
C
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
B
B
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
110_OHM_DIFF
TOP,BOTTOM
Y
0.077 MM
0.077 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
1:1_DIFFPAIR
*
Y
=STANDARD
=STANDARD
0.330 MM
0.330 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
0.1 MM
0.1 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
A
SYNC_MASTER=K24_MLB
SYNC_DATE=01/19/2009
A
PAGE TITLE
K84 RULE DEFINITIONS DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
109 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
7
6
5
4
3
2
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
1
REV
ECN
DESCRIPTION OF REVISION
C
0000813234
CK APPD DATE
PRODUCTION RELEASED
2009-11-01
K84 MLB SCHEMATIC PROD OK2FAB 11/01/2009
D
D (.csa)
Date
Page TABLE_TABLEOFCONTENTS_HEAD
Contents 1
Table of Contents System Block Diagram
3
37 01/19/2009
4 TABLE_TABLEOFCONTENTS_ITEM
BOM Configuration
01/19/2009
5
Revision History Revision History
02/04/2009
7
FUNC TEST
02/04/2009
8 TABLE_TABLEOFCONTENTS_ITEM
Power Aliases
K24_MLB
SIGNAL ALIAS
K24_MLB
9
10
CPU FSB
04/06/2009
11
CPU Power & Ground CPU Decoupling
WELLSPRING 2
K24_MLB
SMS
K24_MLB
47
DEBUG SENSORS AND ADC
K19_IMLB
SPI ROM
K24_MLB
AUDIO: CODEC/REGULATOR
AUDIO
AUDIO: LINE INPUT FILTER
AUDIO
AUDIO: HEADPHONE FILTER
AUDIO
AUDI0: SPEAKER AMP
AUDIO
AUDIO: JACK
AUDIO
AUDIO: JACK TRANSLATORS
AUDIO
DC-In & Battery Connectors
K24_MLB
PBUS Supply/Battery Charger
K24_MLB
K24_MLB
SMC Constraints
K24_MLB
K84 SPECIAL CONSTRAINTS
K24_MLB
K84 RULE DEFINITIONS
K24_MLB
04/06/2009
04/06/2009
01/19/2009
01/19/2009
TABLE_TABLEOFCONTENTS_ITEM
03/04/2009
02/25/2009
03/04/2009
60
02/25/2009
13
eXtended Debug Port(MiniXDP)
02/25/2009
61
48
K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
02/15/2009
TABLE_TABLEOFCONTENTS_ITEM
14
04/06/2009
14
MCP CPU Interface
62
49
K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
06/09/2009
C
TABLE_TABLEOFCONTENTS_ITEM
15
04/06/2009
15 TABLE_TABLEOFCONTENTS_ITEM
MCP Memory Interface
K24_MLB
MCP Memory Misc
K24_MLB
MCP PCIe Interfaces
K24_MLB
16
TABLE_TABLEOFCONTENTS_ITEM
17
18
MCP Ethernet & Graphics MCP PCI & LPC
20 TABLE_TABLEOFCONTENTS_ITEM
MCP SATA & USB MCP HDA & MISC MCP Power & Ground
K24_MLB
MCP Standard Decoupling
K24_MLB
25
26
TABLE_TABLEOFCONTENTS_ITEM
MCP Graphics Support 28
SB Misc FSB/DDR3 Vref Margining DDR3 SO-DIMM Connector A DDR3 SO-DIMM Connector B DDR3 Support
K24_MLB
X16 WIRELESS CONNECTOR
K24_MLB
34
TABLE_TABLEOFCONTENTS_ITEM
37
Ethernet PHY (RTL8211CL) Ethernet & AirPort Support ETHERNET CONNECTOR 45
SATA Connectors
K24_MLB
External USB Connectors
K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
POWER SEQUENCING
K24_MLB
POWER FETS
K24_MLB
LVDS CONNECTOR
K24_MLB
DISPLAYPORT SUPPORT
K24_MLB
DisplayPort Connector
K24_MLB
LCD Backlight Driver (MC34845)
VEMURI_K19I
LCD Backlight Support
K24_MLB
CPU/FSB Constraints
K24_MLB
03/24/2009
02/15/2009
02/15/2009
02/15/2009
04/06/2009
TABLE_TABLEOFCONTENTS_ITEM
B
04/06/2009
97
02/09/2009
98
69
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
94
68 01/19/2009
34
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
MISC POWER SUPPLIES
02/04/2009
93
67 04/06/2009
33 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
39
K24_MLB
90
66 04/06/2009
32 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
38
CPU VTT(1.05V) SUPPLY
02/15/2009
79
65 04/06/2009
31 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
64 01/27/2009
30
K24_MLB
78
63 04/06/2009
29 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
33
MCP CORE REGULATOR
77
62 02/05/2009
28 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
32
K24_MLB
76
61 02/05/2009
27 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
31
03/03/2009
IMVP6 CPU VCore Regulator 75
60 04/06/2009
26 TABLE_TABLEOFCONTENTS_ITEM
1.5V/0.75V DDR3 SUPPLY 74
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
29
5V/3.3V SUPPLY 73
TABLE_TABLEOFCONTENTS_ITEM
59 02/15/2009
25 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
02/05/2009
72
58 04/06/2009
24
TABLE_TABLEOFCONTENTS_ITEM
57 04/06/2009
23 TABLE_TABLEOFCONTENTS_ITEM
02/05/2009
70
56 04/06/2009
22 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
22
06/09/2009
69
55 03/24/2009
21 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
21
06/09/2009
68
54 04/06/2009
06/09/2009
67
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
20
06/09/2009
66
TABLE_TABLEOFCONTENTS_ITEM
53 04/06/2009
19 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
19
06/09/2009
65
52 04/06/2009
18 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
51 04/06/2009
17 TABLE_TABLEOFCONTENTS_ITEM
63
50 04/06/2009
16
B
K24_MLB
Ethernet Constraints
04/06/2009
TABLE_TABLEOFCONTENTS_ITEM
13
C
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
WELLSPRING 1
59
46 03/30/2009
12
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
12
Fan
K24_MLB
109
77 04/06/2009
58
45
K24_MLB
11
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
57
44 04/06/2009
10 TABLE_TABLEOFCONTENTS_ITEM
Thermal Sensors
MCP Constraints 2
03/30/2009
107
76 02/04/2009
56
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
K24_MLB
106
75 01/27/2009
Current Sensing
43 02/04/2009
9 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
55
42
K24_MLB
8
VOLTAGE SENSING
MCP Constraints 1
104
74 04/06/2009
54
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
K24_MLB
103
73 01/19/2009
K84 SMBUS CONNECTIONS
41
K24_MLB
7
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
53
40 01/19/2009
6
LPC+SPI Debug Connector
04/06/2009
Memory Constraints 102
72 02/15/2009
Sync
101
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
52
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
6
TABLE_TABLEOFCONTENTS_ITEM
SMC Support
39
K24_MLB
5
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
Contents
71 02/04/2009
Date
Page
K24_MLB
51
38
Power Block Diagram 4
04/02/2009
SMC 50
TABLE_TABLEOFCONTENTS_ITEM
(.csa)
Sync
49
TABLE_TABLEOFCONTENTS_ITEM
K24_MLB
3
TABLE_TABLEOFCONTENTS_ITEM
Contents
36 01/19/2009
2 TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
K24_MLB
2
Date
Page
01/19/2009
1 TABLE_TABLEOFCONTENTS_ITEM
(.csa)
Sync
04/06/2009
TABLE_TABLEOFCONTENTS_ITEM
46
02/05/2009
35
100
70
TABLE_TABLEOFCONTENTS_ITEM
04/06/2009
TABLE_TABLEOFCONTENTS_ITEM
A
A DRAWING TITLE
SCHEM,MLB,K84 DRAWING NUMBER
Schematic / PCB #’s
Apple Inc.
051-7982 REVISION
R
PART NUMBER
DESCRIPTION
REFERENCE DES
051-7982
1
SCHEM,MLB,K84
SCH
CRITICAL
820-2567
1
PCBF,MLB,K84
PCB
CRITICAL
8
QTY
7
CRITICAL
BOM OPTION
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6
5
4
3
2
C.0.0 BRANCH
PAGE
1 OF 109 SHEET
1 OF 77
1
SIZE
D
8
7
6
5
4
3
2
1
U1000
U1300
J6950,J6900
INTEL CPU CORE 2 DUO
XDP CONN
2.26 GHZ
DC/BATT CONN
PG 13
DC-DC POWER SUPPLIES
PENRYN PG 55
PG 56-64
PG 10
FSB
D
J5800
D
TRACKPAD
64-Bit
PG 45
1067 MHZ
PG 14 U5515,U5535 J3100,J3200
2 SODIMMS MAIN
CPU & MCP THERMAL SENSORS
FSB INTERFACE
GPIOs
MEMORY
DDR3 1067MHZ
DIMM PG 42
PG 15,16
PG 27,28
U5920
SUDDEN MOTION SENSOR PG 46
Misc
U6100
CLK
SPI
PG 21
SYNTH
CURRENT & VOLTAGE SENSORS
Boot ROM
PG 53,54,60
PG 48
J5601
J4501
FAN CONN AND CONTROL
SPI
SATA
PG 43
Conn
PG 21 PG 34
HD
NVIDIA
J4500
U4900
A
SATA
B,0
ADC
BSA
Fan
Ser J5100
PG 34
C
MCP79 B03
SATA
Conn
PG 20
Prt
SMC
LPC Conn
H8S/2117
LPC
ODD
Port80,serial
PG 36,37
C
PG 38
PG 19
U1400
J9000
PWR
LVDS CONN
LVDS OUT
PG 65
CTRL
RGB OUT J3401
J5800
DP OUT
Bluetooth
J9400
J9000
J4600,4610
TRACKPAD/
EXTERNAL CAMERA
KEYBOARD MINI DISPLAY PORT
USB 2.0
HDMI OUT
Connectors PG 30
PG 45
PG 65 PG 35
CONN
PG 17
8 7 6 5
PCI-E
UP TO 20 LANES3
B
0
1
2
3
4
USB
PG 18
PG 20
TMDS OUT
(UP TO 12 DEVICES)
PG 67
9
DVI OUT
B SMB PG 21
RGMII
HDA
PCI
DIMMS
(UP TO FOUR PORTS)
MIKEY
SMC
PG 18 PG 19
PG 21
U6201
Audio Codec CIRRUS LOGIC CS4206 PG 49
U6500
HEADPHONE/LINE OUT Amp U6610,U6620,U6630 PG 51
U3700
LINE-IN
A
GIGABIT
Speaker
MIC
10/100/1000M E-NET
U6700
RTL8211CL
SYNC_MASTER=K24_MLB
DRAWING NUMBER
PG 53
Apple Inc. J3401
J3900
J6700,J6701,J6702,J6703,J6704
NOTICE OF PROPRIETARY PROPERTY:
E-NET
SIZE
051-7982
D
REVISION
C.0.0
R
MINI PCI-E
A
System Block Diagram
PG 52
MUX
PG 31
SYNC_DATE=01/19/2009
PAGE TITLE
Amps
LINE-IN/LINE OUT
BRANCH
Audio
AirPort
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
Conn Conns
PG 30 PG 33
PG 53
PAGE
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K84 POWER SYSTEM ARCHITECTURE PP18V5_DCIN_CONN
D6905 02 ENABLE
PPVIN_G3H_P3V42G3H
D6905
3.425V G3HOT LT3470
PBUS_VSENSE
03
PP3V42_G3H_REG
04
SMC RESET "BUTTON" NCP303LSN
VOUT
V
7A FUSE
D
PPVBAT_G3H_CHGR_REG
U6990
PPBUS_G3H
01
U5000
Q5315
23
PPCPUVCORE_VTT_ISNS
PPCPUVCORE_VTT_ISNS_R
02
F7000
D
0.01 OHM
R5492
PPVIN_S0_CPUVTTS0 VIN
6A FUSE
AC ADAPTER IN
PPCPUVTT_S0_REG
CPUVTTS0_EN (S0)
CHGR_EN (S5)
F6905
EN_PSV
VOUT
CPUVTT
ENABLES
(7.2A MAX CURRENT)
(1.05V)
DCIN(16.5V)
MCP79
TPS51117 U7600
VIN VOUT
PBUS SUPPLY/
06-1
PWRBTN*
31
PGOOD
CPUVTTS0_PGOOD
BATTERY CHARGER
PLTRST*
PPVIN_S5_CPU_IMVP
LPC_RESET_L
RSMRST*
ISL6258AHRTZ
V
01
U7000
CPU VCORE
02
MCP_PS_PWRGD
SMC_CPU_VSENSE
CPU_PWRGD
VIN
CPUPWRGD(GPIO49)
29
PPVCORE_S0_CPU_REG
26
VOUT
30
(44A MAX CURRENT)
U2850
CPU_RESET#
FSB_CPURST_L
J6950
PS_PWRGD
ISL9504BCRZ U1400 IMVP_VR_ON
C
VR_ON
Q7050
3S2P BATT_POS_F
(9 TO 12.6V)
28
25
PPVBAT_G3H_CHGR_OUT
VR_PWRGOOD_DELAY
PGOOD
U7400
06
P1V05ENET_EN
1.05V SO
22
EN
1.05V (S5)
MCP79
11
11-1
P3V3S3_EN
VIN ISL8009B
U7750
P1V05_S5_EN
RC DELAY
PM_SLP_S4_L
PP4V5_AUDIO_ANALOG
U6200 RESET*
VOUT
EN
06
PWRGOOD
4.5V AUDIO TPS71745 VIN
(Q3841,Q3840)
PPVIN_S3_5VS3/PPVIN_S5_3V3S5
U1000
PP1V05_S5_REG
32
VOUT
08
Q7940
PP5V_S3_REG
02
SMC
C
CPU
PP1V05_ENET_FET
FETS
CHGR_BGATE
PP5VRT_S0_FET
P16
15 SLP_S3#
11-3
RC DELAY
U1400
P5VS3_EN_L
04
U4900
DDRREG_EN
VIN
5V
EN1
VOUT1
(RT)
SMC_PM_G2_EN P60
Q7800
(S5)
PP3V3_S5_REG (4A MAX
3.3V
EN2
PPBUS_S0_LCDBKLT_PWR
07
PP5VLT_S0_FET
Q7910 PP3V3_S3_FET
02 EN0
SMC_PM_G2_EN
P5VS3_EN_L
RC DELAY
P5VS0_EN Q7948
CURRENT)
TPS51125 11-2
17
PP3V3_S5
VOUT2
P3V3S5_EN_L
PP3V42_G3H_REG PCI_RESET0#
15-1
PP5V_S3
PP5V_S3_REG (10A MAX CURRENT)
05
U7200
PGOOD1,2
13
P5VS0_EN
VREG3
VIN
P3V3S3_EN
MC34845 U9700
P5V3V3_PGOOD
PPVOUT_S0_LCDBKLT VOUT
B
SMC
24
NAND GATE 04-1
SMC_ADAPTER_EN Q3801,Q3805
PWRGD(P12)
18
PM_RSMRST_L
99ms DLY
IMVP_VR_ON IMVP_VR_ON(P16)
PP3V3_S0_FET
09
PM_WLAN_EN_L
RSMRST_PWRGD
25
RSMRST_IN(P13) PLT_RST*
OR GATE
PM_SLP_S3_L
ALL_SYS_PWRGD
Q7930
16
Q3801,Q3805
B
10
RSMRST_OUT(P15)
AP_PWR_EN
SMC_ONOFF_L PWR_BUTTON(P90)
P3V3S0_EN
15
P17(BTN_OUT)
05
Q3810
RST*
P3V3_ENET_FET
PM_PWRBTN_L SMC_RESET_L
P1V05S0_LDO_PGOOD P5V3V3_PGOOD
SLP_S5_L SLP_S5_L(P95)
P3V3ENET_EN_L
MCPCORESO_PGOOD
SLP_S4_L SLP_S4_L(P94)
CPUVTTS0_PGOOD
SLP_S3_L SLP_S3_L(P93)
PP3V3_S0_PWRCTL
PPVIN_S5_1V5S30V75S0
S3 TO S0 PP1V5_S0_FET
PP1V5_S0
FETS
02
21 1.8V LDO
(Q7901 & Q7971)
TPS62202
VIN
=DDRREG_EN
=DDTVTT_EN
PM_SLP_S3_L
S3
RC
P1V8S0_EN
U7760
PP1V5_S3_REG (13A MAX CURRENT)
VOUT1
RST*
14
0.75V
PP3V3_S0 VOUT2
A
PP0V75_S0_REG (1A MAX CURRENT)
V1
PP1V5_S0
TPS51116 U7300
16-4
DELAY
PP1V8_S0_REG 19-1
1.5V S5
V2
PP1V05_S0
V3
20 RC
MCPDDR_EN 16-2
DELAY
RC
MCP_CORE
P3V3S0_EN
16-3
U4900
S0PGOOD_PWROK
MCPCORES0_EN
DELAY
PPMCPCORE_S0_R VOUT
LTC2909
A PAGE TITLE
Power Block Diagram
U7870
R7525 PPMCPCORE_S0_REG
DRAWING NUMBER
Apple Inc.
(13A MAX CURRENT)
EN
RC
CPUVTTS0_EN
C.0.0
ISL6263D
16-1 16-6
NOTICE OF PROPRIETARY PROPERTY:
PBUSVSENS_EN U7500 (S0)
RC
MCPCORES0_EN 16-5
DELAY
VIN
16-1
P5VS0_EN
02
(S0)
8
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
PPVIN_S0_MCPCORE
D
REVISION
R
DELAY
SIZE
051-7982 BRANCH
PAGE
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BOM Variants TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
639-0035
PCBA,MLB,FOX DDR CONN,K84
K84_COMMON,CPU_2_0GHZ,FOX_DDR_CONN,EEE_8CG
Bar Code Labels / EEE #’s TABLE_BOMGROUP_ITEM
PART NUMBER
DESCRIPTION
REFERENCE DES
826-4393
QTY 1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:8CG]
CRITICAL CRITICAL
BOM OPTION EEE_8CG
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:A36]
CRITICAL
EEE_A36
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:CXR]
CRITICAL
EEE_CXR
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:CY1]
CRITICAL
EEE_CY1
TABLE_BOMGROUP_ITEM
639-0254
PCBA,MLB,MLX DDR CONN,K84
K84_COMMON,CPU_2_0GHZ,MLX_DDR_CONN,EEE_A36 TABLE_BOMGROUP_ITEM
085-0748
K84 MLB DEVELOPMENT BOM
K84_DEVEL_ENG TABLE_BOMGROUP_ITEM
639-0554
PCBA,MLB,FOX DDR CONN,PVT K84
K84_COMMON_PVT,CPU_2_0GHZ,FOX_DDR_CONN,EEE_CXR TABLE_BOMGROUP_ITEM
639-0555
PCBA,MLB,MLX DDR CONN,PVT K84
K84_COMMON_PVT,CPU_2_0GHZ,MLX_DDR_CONN,EEE_CY1 TABLE_BOMGROUP_ITEM
085-1076
D
K84 MLB DEVELOPMENT PVT
K84_DEVEL_PVT
D
BOM Groups TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
K84_COMMON
COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_ENG,K84_PROGPARTS
K84_COMMON_PVT
COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_PROD,K84_PROGPARTS
K84_MCP
MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC
K84_MISC
ONEWIRE_PU,DP_ESD,MIKEY,LDO_NO,MEM_SENSE,1P05_HIGH_SIDE_SENSE,MCP_T_DIODE_SENSOR,MCPSMC_DIGITEMP_YES
K84_PROGPARTS
BOOTROM_PROG,SMC_PROG,WELLSPRING_PROG
K84_DEBUG_ENG
DEVEL_BOM,SMC_DEBUG_YES,XDP
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
K84_DEBUG_PVT
DEVEL_BOM_PVT,SMC_DEBUG_YES,XDP,NO_VREFMRGN
K84_DEBUG_PROD
SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN
K84_DEVEL_ENG
DEBUG_ADC,XDP_CONN,LPCPLUS,VREFMRGN
K84_DEVEL_PVT
XDP_CONN,LPCPLUS
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Module Parts
PART NUMBER
C
DESCRIPTION
REFERENCE DES
337S3769
1
PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7550
U1000
CRITICAL
338S0710
1
IC,GMCP,MCP79,35X35MM,BGA1437,B03
U1400
CRITICAL
MCP_B03
516S0706
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA
J3200
CRITICAL
FOX_DDR_CONN
516-0201
1
CONN,204P,SODIMM,P=0.6MM
J3100
CRITICAL
FOX_DDR_CONN
516S0790
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,NON/SC
J3200
CRITICAL
MLX_DDR_CONN
516-0213
1
CONN,204P,SODIMM,P=0.6MM,HF
J3100
CRITICAL
MLX_DDR_CONN
452-1708
4
SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97
SCREW1,SCREW2,SCREW3,SCREW4
CRITICAL
514-0704
1
CONN,RCPT,RJ45,PLASTIC,HF,K83/K84
J3900
CRITICAL
514-0705
2
CONN,RCPT,USB,4P,PLASTIC,HF,K83/K84
J4600,J4610
CRITICAL
514-0706
1
CONN,RCPT,MDP,20P,PLASTIC,HF,K83/K84
J9400
CRITICAL
514-0718
1
CONN,RCPT,S/PDIF,TX,HF,CFR,K83/K84
J6700
CRITICAL
353S2718
1
IC,ISL88042,4X V MONTR,2.78/2.86V,TDFN8
U7870
CRITICAL
870-1885
4
POGO PIN,MED,NOISE-IMPROVED,K84
ZS0900,ZS0901,ZS0902,ZS0903
CRITICAL
CRITICAL
870-1885
3
POGO PIN,MED,NOISE-IMPROVED,K84
ZS0908,ZS0909,ZS0911
CRITICAL
870-1886
5
POGO PIN,TALL,NOISE-IMPROVED,K84
ZS0904,ZS0905,ZS0906,ZS0907,ZS0910
CRITICAL
870-1886
5
POGO PIN,TALL,NOISE-IMPROVED,K84
ZS0912,ZS0913,ZS0914,ZS0915,ZS0919
CRITICAL
870-1887
3
POGO PIN,THIN,NOISE-IMPROVED,K84
ZS0917,ZS0918,ZS0916
CRITICAL
104S0033
4
RES,MF,1/4W,6.8OHM,5%,0805,SMD
R6612,R6617,R6630,R6633
CRITICAL
1
CONN,RCPT,60P,P=0.4,STK HT 1.0
J1300
CRITICAL
518S0774
B
QTY
353S2718 514-0704 514-0705 514-0706 514-0718
IS IS IS IS IS
NEW INTERSIL PART FOR FIXING B4 CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI
DONGLE ISSUE PLATING VERSION PLATING VERSION PLATING VERSION PLATING VERSION
OF OF OF OF
514-0692 514-0689 514-0691 514-0694
PART PART PART PART
FOR FOR FOR FOR
BOM OPTION CPU_2_0GHZ
C
K84 BOARD STACK-UP
XDP_CONN
RJ45 CONNECTOR USB CONNECTORS MINI DP CONNECTOR AUDIO CONNECTOR
DEVELOPMENT BOM
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
085-0748
1
K84 MLB DEVELOPMENT BOM
DEVEL
CRITICAL
DEVEL_BOM
085-1076
1
K84 MLB DEVELOPMENT PVT
DEVEL_PVT
CRITICAL
DEVEL_BOM_PVT
Top
SIGNAL
2
GROUND
3
SIGNAL(High Speed)
4
SIGNAL(High Speed)
5
GROUND
6
POWER
7
POWER
8
GROUND
B
9
SIGNAL(High Speed)
10
SIGNAL(High Speed)
Programmable Parts 338S0563
1
IC,SMC,HS8/2117,9X9MM,TLP,HF
U4900
CRITICAL
SMC_BLANK
341S2485
1
IC,SMC,K84
U4900
CRITICAL
SMC_PROG
335S0610
1
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
U6100
CRITICAL
BOOTROM_BLANK
341S2487
1
IC,PRGRM,EFI BOOTROM,UNLOCK,K84
U6100
CRITICAL
BOOTROM_PROG
337S2983
1
IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794
U5701
CRITICAL
WELLSPRING_BLANK
341S2491
1
IC,WELLSPRING CONTROLLER,K84
U5701
CRITICAL
WELLSPRING_PROG
11
GROUND
BOTTOM
SIGNAL
LOCKED BOOTROM APN IS 341S2488
Alternate Parts TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
152S0693
152S0778
ALL
DALE/VISHAY, MAGLAYERS AS ALTERNATE
152S0796
152S0685
ALL
CYNTEC AS ALTERNATE
TABLE_ALT_ITEM
A
SYNC_MASTER=K24_MLB
TABLE_ALT_ITEM
157S0058
157S0055
ALL
DELTA AS ALTERNATE
138S0603
138S0602
ALL
MURATA AS ALTERNATE
SYNC_DATE=01/19/2009
BOM Configuration DRAWING NUMBER
TABLE_ALT_ITEM
Apple Inc.
TABLE_ALT_ITEM
128S0093
128S0218
ALL
KEMET AS ALTERNATE
152S0516
ALL
MAGLAYERS AS ALTERNATE
152S0586
ALL
MAGLAYERS AS ALTERNATE
NOTICE OF PROPRIETARY PROPERTY:
D
REVISION
C.0.0
R
152S0847
SIZE
051-7982
TABLE_ALT_ITEM
152S0874
A
PAGE TITLE TABLE_ALT_ITEM
BRANCH
TABLE_ALT_ITEM
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
TABLE_ALT_ITEM
104S0018
104S0023
ALL
DALE/VISHAY AS ALTERNATE
PAGE
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8 Revision History
D
C
B
A
7 NOTE: All page numbers are .csa, not PDF.
6
5
4
3
2
1
See page 1 for .csa -> PDF mapping.
1/19/2009:INITIAL RELEASE 0.0.1- ALL PAGES SYNC’ED FROM K24 - REPLACED K24 REFERENCES WITH K84 3/20/2009: RELEASE 7.1.0 (MAJOR)3/25/2009: RELEASE 7.3.0 (MAJOR)- UPDATED SCHEMATIC AND PCB PART NUMBER INFO - PAGE 31 & 32: PIN SWAPS ON THE DDR3 CONNECTOR PAGES FOR ROUTING PURPOSES (REFER TO RON’S EMAIL) - DELETED PAGE 71 (5V S3 LT POWER SUPPLY) AS THERE IS NO NEED OF A SEPARATE 5V S3/S0 SUPPLY 1/21/2009: RELEASE 0.0.2- PAGE 7: DELETED PP5VLT_S3 NETS - DELETED PAGES 41,42,43,48,97,98,105 [FIREWIRE, IR CONTROLLER, BACKLIGHT CKT] ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.0.0*** - PAGE 7: RENAMED PP5VRT_S3 TO PP5V_S3 ["LT" & "RT" NOMENCLATURE CLEAN-UP] - UPDATED BOM CONFIGURATIONS - PAGE 8: COMBINED 5V S3 LT AND RT ALIASES INTO ONE =PP5V_S3_REG AND RENAMED NETS - DELETED IR SPECIFIC NETS ON SATA CONNECTOR -PG. 67, DELETED R6726 (LT & RT NOMENCLATURE CLEAN-UP) -PG. 66, CHANGED C6610/11/30/31 TO 0.015UF - PAGE 8: DELETED =PPVIN_S3_5VLTS3, =PP5VLT_S3_V5IN NETS 1/21/2009: RELEASE 0.0.3-PG. 68, ADDED MIKEY MIC LOAD COMPARATOR CKT - PAGE 9: ADDED ALIAS MCP_GPIO_4 FOR MIKEY MIC LOAD DETECT CIRCUIT - CORRECTD BOM CONFIG TABLES -PG. 68, ADDED R6873 - PAGE 21: UNSTUFFED R2143 PU ON MCP_GPIO_4 AS THERE IS ALREADY A 100K PU ON AUDIO PAGE -PG. 68, CORRECTED CODEC OUTPUT SIGNALS TABLE COMMENTS - PAGE 45: ADDED APN TEXT NOTE FOR SIL CONNECTOR 1/21/2009: RELEASE 0.0.4- PAGE 55: ADDED BC846BM NPN TRANSISTOR (APN 372S0129) TO MCP T-DIODE SENSOR CIRCUIT SIMILAR TO - CORRECTED BOM CONFIG TABLE (ADDED BACK BKLT_ENG) THAT IN CPU T-DIODE SENSOR AND STUFFED C5540 - ADDED BACK PAGES 97-98 (LCD BACKLIGHT DRIVER AND SUPPORT CKT) 3/24/2009: RELEASE 7.2.0 (MAJOR)- PAGE 72: RENAMED NETS AND NOTES TO REMOVE REFERENCES TO RT POWER SUPPLY - DELETED KB BACKLIGHT DRIVER/DETECTION CKT - PAGE 72: REPLACED L7260 WITH APN 152S0959 AS PER DAYU - PAGE 4: CHANGE THE CPU TO NEW APNB 337S3704 - PAGE 72: ADDED C7282 APN 128S0218 IN PARALLEL WITH C7280 AS PER DAYU 1/23/2009: RELEASE 0.0.5- PAGE 7: DELETED PPBUS_R_G3H AS NO NEED OF TWO PPBUS BRANCHES - PAGE 73: REPLACED Q7320 AND Q7321 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU - UPDATED PAGES 72-73 : 5V/3.3V & DDR3 POWER SUPPLIES AS PER FLO’S RECOMMENDATIONS - PAGE 8: COMBINED TWO SEPARATE PPBUSA/B BRANCHES INTO ONE =PPBUS_G3H - PAGE 74: REPLACED C7433 AND C7431 WITH 0.001UF CAPS APN 132S1035 - SET SOURCE SYNC OF AUDIO PAGES (62-63, 65-68) FROM LENG’S AUDIO PAGES - PAGE 9: ADDED LVDS HOLE APN 998-1521 - PAGE 75: REPLACED C7576 WITH 0.022UF APN 132S0102 CAP TO INCREASE THE SLEW RATE - PAGE 75: ADDED A NOTE OCP=14.5A TO R7575 - PAGE 34: CHANGED J3401 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA 1/27/2009: TMLB FIRST RELEASE 0.0.1- PAGE 45: MIRROR’ED J4500 AND RECONNECTED PINS AS PER NEW PIN OUT DESCRIPTION FROM DIANA - PAGE 75: REPLACED Q7560 AND Q7565 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU - NAME CHANGED TO TMLB. SO CALLING IT RELEASE 0.0.1 - PAGE 45: CHANGED J4501 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA - PAGE 76: CORRECTED MAX OUTPUT NOTE TO REFLECT 7.2A INSTEAD OF 8A - UPDATED SCHEM AND PCBF PART NUMBER INFO - PAGE 50: DELETED SMC_PPBUSA_ISENSE ALIAS AND STUFFED R5055 - PAGE 76: REPLACED Q7620 WITH 2 CSD58858 APN 376S0790 MOSFETS AS PER DAYU - UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_PROD AND BLANK PROGRAMMED PARTS. ALSO, DELETED BMON_ENG BOM OPTION - PAGE 54: DELETED U5470 INA210 CIRCUIT AS THERE IS NO NEED - PAGE 77: ADDED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL VIA A 0 OHM RESISTOR TO PIN 3 (PG) OF THE LDO - PAGE 54: REMOVED BMON CURRENT SENSE CIRCUIT - PAGE 70: REMOVED R7080 SENSE RESISTOR AND RENAMED =PPBUSB_G3H TO =PPBUS_G3H AS NO NEED - PAGE 78: DELETED P5V_LTS3_PGOOD AS THERE IS NO 5V LT POWER SUPPLY ANYMORE - REMOVED ALS SPECIFIC NETS (PAGE 34 & 52) TO HAVE TWO PPBUS BRANCHES - PAGE 78: RENAMED =P5VRTS3_EN_L TO =P5VS3_EN_L - PAGE 70: DELETED R7050 CONNECTION BETWEEN CHGR_AGATE AND CHGR_LOWCURRENT_GATE - PAGE 78: ROUTED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL TO THE WIRED AND CIRCUIT 2/5/2009: RELEASE 0.0.2 AS PER DAYU - COPIED TMLB OVER TO MLB AS K84 WILL BE PENRYN SKU WHILE K83 WILL BE ATOM SKU - PAGE 70: ADDED R7050 (6259_YES) CONNECTION FROM PIN 4 (VREF) TO PM_SLP_S3_L AS PER DAYU - UPDATED THE SCHEMATICS, PCBF AND PCBA PART NUMBER INFO - PAGE 70: AS PER DAYU, ADDED: 3/26/2009: RELEASE 7.4.0 (MAJOR)- REPLACED TEXT TMLB WITH MLB THROUGH OUT THE SCHEMATICS R7051 (6259_YES) CONNECTION BETWEEN CHGR_PIN26 AND CHGR_LOWCURRENT_GATE; - PAGE 4: UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_ENG FOR K84_COMMON BOM GROUP R7052 (6259_NO) CONNECTION BETWEEN CHGR_PIN26 AND GND_CHGR_SGND; - PAGE 4: UPDATED EEE NUMBER - 8CG - PAGE 60: REPLACED DUAL PACKAGE OPA330 OPAMPS WITH SINGLE PACKAGE ONES - APN 353S2179 R7053 (6259_YES) CONNECTION BETWEEN CHGR_PIN6 AND PIN 12 (VHST); - PAGE 4: ADDED 085 DEVELOPMENT BOM VARIANT & K84_DEVEL_ENG, K84_DEVEL_PVT BOM GROUPS R7054 (6259_NO) CONNECTION BETWEEN CHGR_PIN6 AND GND_CHGR_SGND [U6030, U6031, U6040, U6041]. ALSO, ADDED C6031 & C6041 - PAGE 7: DELETED IR_RX_OUT, PP5V_S3_IR_R, KBDLED_ANODE, SMC_KBDLED_PRESENT_L - PAGE 73: RENAMED TEXT NOTE FOR =PP1V5_S3_REG NET TO VOLTAGE=1.5V - PAGE 9: DELETED EXTRA MEDIUM POGO PIN ZS0912 AND SCREW HOLES Z0908, Z0909 - PAGE 8: DELETED FIREWIRE, IR AND BMON SPECIFIC NETS - PAGE 97: STUFF R9716 AS PER KIRAN’S FEEDBACK - PAGE 9: DELETED R0950 PCIE_FW_PRSNT_L ’S PD RESISTOR 3/26/2009: RELEASE 7.5.0 (MAJOR)- PAGE 9: ADDED UNUSED FIREWIRE LANE NETS AS TEST POINTS - PAGE 9: CHANGED ALIAS OF FW_PME_L TO TP_FW_PME_L - PAGE 73: ADDED SHORT XW7304 FROM PIN 1 OF C7300 TO POWER GND (PIN 18) - PAGE 9: ADDED SMC_SYS_KBDLED TP ALIAS - PAGE 72: REPLACED C7282 WITH OSCON APN 128S0248 IN PARALLEL WITH C7280 AS PER DAYU - PAGE 55: REPLACED CPU/MCP THERMAL SENSORS U5515 ANDB U5535 WITH THE CHEAPER VERSION APNB 353S2573 - PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 & C7240 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS 3/26/2009: RELEASE 7.6.0 (MAJOR)- PAGE 72: REPLACE Q7220 WITH SIZ700DT - PAGE 73: REPLACE 16V INPUT SIDE CAPS C7331 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS - PAGE 76: REPLACE Q7620 WITH SIZ700DT - ADDED PLACEMENT NOTES TO XW SHORTS AS PER DAYU - ADDED OMIT BOM OPTION TO ALL THE XW SHORTS 2/6/2009: MAJOR RELEASE 0.1.0 - ADDED DIDT=TRUE ATTRIBUTE TO BOOT/VBST SIGNALS OF ALL THE SWITCHING SUPPLIES - NO CHANGES SINCE LAST MINOR RELEASE 0.0.2 - PAGE 8: DELETED =PP3V42_G3H_BATT AS THERE IS NO BIL CONNECTOR - PAGE 8: ADDED =PP3V42_G3H_HALL FOR THE HALL EFFECT CONNECTOR 2/6/2009: WEEKLY RFA BOM RELEASE 1.0.0- PAGE 8: ADDED =PP3V3_S3_AUDIO ALIAS NET FOR CASEY’S NEW CHANGES BELOW - NO CHANGES SINCE LAST MAJOR RELEASE 0.1.0 - PAGE 8: DELETED =PP3V42_G3H_PPBUSAISNS AS PPBUS SENSE CIRCUIT HAS BEEN REMOVED - PAGE 8: RENAMED ALIAS =PP5V_S3_P5VS0FET TO =PP5V_S3_P5VLTS0FET AS THIS GOES TO 5V LT S0 FET CIRCUIT 2/15/2009: RELEASE 2.0.0 (WEEKLY RFA)- PAGE 8: ADDED =PP5V_S3_P5VRTS0FET ALIAS, GOING TO 5V RT S0 FET CIRCUIT 1. PAGE 3: POWER BLOCK DIAGRAM - ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR. ALSO, ADDED SENSE RESISTOR ON PPBUS - PAGE 8: ADDED PLACEMENT NOTE TO Q5502 2.CKT E PAGE 8: ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR, WHILE PPBUSB FEEDS 5V/3.3 V SUPPLY, LCD BKLT & PPBUS VOLTAGE SENS - PAGE 9: ADDED OMIT ATTRIBUTE TO THE LVDS HOLE 3. PAGES 31, 32: REPLACED 0.1UF 0204 TYPE DDR3 DECOUPLING CAPS WITH 0402 TYPE CAPS ( APPLE P/N : 132S1059) - PAGE 69: ADDED HALL EFFECT CONNECTOR CIRCUIT J6955 APN 516S0787 4. PAGE 34: REPLACED AIRPORT CONNECTOR WITH PN 516S0580 AND UPDATED CONNECTIONS ACCORDINGLY - PAGE 79: RENAMED INPUT VOLTAGE NETS OF 5V S0 FET CIRCUITS TO REFLECT RT AND LT 5. PAGE 34: REPLACED SCHMITT’S TRIGGER WITH PN 311S0449 (MATCHES UPDATED ALIASES ON PAGE 8) 6. PAGE 45: REPLACED SATA HDD CONNECTOR WITH APPLE PN 516S0350 AND UPDATED CONNECTIONS ACCORDINGLY 7. PAGE 45: ADDED 2 PIN CONNECTOR (APPLE PN 518S0519) FOR SIL 8. PAGE 46: REPLACED ESD DIODES WITH CHEAPER PN 377S0066 ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.5.0*** 9. PAGE 54: ADDED BOM OPTION- DEBUG_SENSE- TO CPU 1.05V/CPU VCORE HIGH SIDE CURRENT SENSE AND MCP MEM VDD CURRENT SENSE CIRCUITS FOR DEVELOPMENT BOM -PG. 67, ADDED R6725 10. PAGE 4: ADDED DEBUG_SENSE BOM OPTION TO THE K84_DEVEL_ENG BOM GROUP -PG. 67 ADDED =PP3V3_S3_AUDIO NET 11. UPDATED PAGE THESE 58: DELETED NET NAMES IPD ON FLEX PAGE CONNECTOR 7 ALSO J5800. RENAMED PP18V5_S3, PP3V3_S3_LDO_R, PP3V3_S3_LDO TO PP18V5_S3_LDO, PP3V3_S3_IPD_R AND PP3V3_S3_IPD RESPECTIVELY TO MATCH WITH NEW ADDED PAGE 60 NET NAMES. -PG. 67, DELETED L6706 12. ADDED PAGE 60 AND COPIED OVER ZEPHYR2 SCHEMATICS PAGE FROM M97 IPD_FLEX_WELLSPRING. DELETED THE IPD BOARD CONNECTOR. CALLING IT WELLSPRING 3 -PG. 67, ADDED XW6702 13. PAGE 69: REPLACED BATTERY CONNECTER WITH PN 518S0540 AND BIL CONNECTOR WITH PN 518S0588. UPDATED CONNECTIONS ACCORDINGLY -PG. 66, UPDATED 5V S3 ALIAS NOTES 14. PAGE POWER) ALIAS 70: ON DIVIDED PAGE 8 PPBUS INTO TWO BRANCHES - PPBUSA & PPBUSB. ADDED SENSE RESISTOR R7080 (2 MOHMS) ON PPBUSA. ALSO ADDED INA210 AMPLIFIER CKT ACROSS SENSE LINES. ADDED PP3V42_G3H_PPBUSAISNS (IN210 -PG. 67, NO STUFFED R6724 15: PAGE 97: REPLACED BKLT DRIVER CKT WITH THAT OF FREESCALE PART, SIMILAR TO K19I 16. PAGE 69: MOVED THE DECAP C6908 TO CORRECT PART U6901.5 ( SIMILAR TO K24) 17. PAGE 4: REMOVED BKLT_ENG BOM OPTION 3/29/2009: RELEASE 8.0.0 (RFA)***PAGES SYNC’ED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 1.0.0*** 1. REPLACED MIKEY CD3272 WITH CD3282 - PAGE 7: SCRUBBED THROUGH THE FUNCTIONAL TEST POINTS AGAINST TOM’S SPREADSHEET 2. ADAPT JACK INSERT DETECT CIRCUIT TO CD3282 JACK INSERT DETECT FUNCTION. 3/6/2009: RELEASE 6.0.0 (RFA:)- PAGE 7: RENAMED RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR 3. REMOVED JACK EXTRACT CIRCUITRY, FUNCTION IS TAKEN OVER BY CD3282 - PAGE 7: DELETED BATT SIGNAL CONN AND ADDED HALL EFFECT CONNECTOR TEST POINTS 4. REMOVE FM ANTENNA NET. - PAGE 4: ADDED 152S0693 AS ALT FOR 152S0778 FOR SUPPLY REDUNDANCY - PAGE 7: DELETED THERMAL FUNC_TEST SECTION - PAGE 4: ADDED 138S0603 AS ALT FOR 138S0602B FOR SUPPLY REDUNDANCY - PAGE 9: ADDED TP_ ALIASES FOR - CARDREADER_RESET, USB_CARDREADER_N/P, AND ***PAGES SYNC’ED FROM K24 SINCE LAST RELEASE 1.0.0*** - PAGE 4: ADDED CYNTEC ALTERNATES FOR 107S0074 --> 107S0138 [R7020] AND 107S0075 USB_IR_N/P 1. PAGE 75: MCP VCORE INDUCTOR CHECK FOR PD: CHANGED L7560 TO 152S0966 AND THEN TO 152S0867. BUT NOW IT IS BACK TO 13A PART FOR NOW [R7008] --> 107S0139 - PAGE 9: FIXED BAD_TP_NC NETS - TP_RTL8211_CLK125, TP_PP3V3_ENET_PHY_VDDREG 2. ADDED DIDT TO ALL THE GATE AND PHASE NETS - PAGE 4: ADDED DALE/VISHAY ALTERNATES FOR 104S0023 --> 104S0018 - PAGE 9: DELETED Z0912 MLB MOUNTING HOLE AS NO LONGER NEEDED - PAGE 4: ADDED BOM OPTION 6259_NO TO THE TABLE UNDER K84_MISC BOM GROUP - PAGE 34: RENAMED TITLE: RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR - PAGE 7: DELETED SMC_BIL_BUTTON_L NET FROM BATT SIGNAL CONN GROUP AS BIL IS NO LONGER A POR - PAGE 50: REPLACED R5030 WITH APN: 114S0114,(IT’S A 1% TOL, 1/16W, 0402, 84.5OHM RESISTOR) 2/25/09: WEEKLY RFA RELEASE (3.0.0) - PAGE 8: DELETED =PP3V42_G3H_AUDIO AS IT IS NO LONGER USED - PAGE 66: FIXED UNNAMED NETS CONNECTED TO - R6632 - ADDED DIDT ATTRIBUTE - PAGE 8: DELETED =PP3V3_S0_TPAD AS THERE IS NO KEYBOARD BACKLIGHT DRIVER - PAGE 74: FIXED UNNAMED NETS CONNECTED TO - XW7401, XW7402, XW7403 AND XW7404 - PAGE 4: REMOVED SUPERCAP_NO BOM OPTION. ADDED DEBUG_ADC BOM OPTION UNDER K84_DEVEL_ENG - PAGE 8: DELETED =PP3V42_G3H_5V3V3_EN AS IT IS NO LONGER USED - PAGE 78: FIXED BAD_TP_NC NETS - TP_DDRREG_PGOOD (THIS IS FOR NEW SENSOR PAGE 60) - PAGE 9; ADDED 3 ADDITIONAL TALL POGO PINS AS PER NEW MCO AND DELETED ZS0909 SHORT POGO AS IT WAS EXTRA - PAGE 76: REPLACED L7620 WITH ITS REPLACEMENT - APN 152S0518 - PAGE 4: CORRECTED APN FOR PROGRAMMED PARTS - SMC, BOOT ROM, WELLSPRING - PAGE 9: ADDED TP ALIASES TO IMVP6_VR_TT AND IMVP6_NTC - PAGE 69: CHANGE PIN OUTS OF J6955 AS PER CHINMAY - PAGE 4: REMOVED LDO_YES BOM OPTION - PAGE 34: ADDED LC FILTER (L3406 AND C3432) ON PP3V3_S3_BT POWER RAIL AS PER JOHN SCHEN’S FEEDBACK - PAGE 34: REPLACED THE AIRPORT CONNECTOR WITH 1.8 MM HEIGHT CONNECTOR APN 516S0582 - PAGE 8: DIVIDED PP5V_S0_FET INTO TWO BRANCHES - PP5VRT_S0_FET & PP5VLT_S0_FET (FOR ROUTING PURPOSE, - PAGE 39: REPLACED ETHERNET CONNECTOR WITH THAT OF M97A/K24 PART APN 514-0636 (SYNC’ED WITH K24) 3/31/2009: RELEASE 9.0.0 (RFA)5V S3 IS DIVIDED INTO RT AND LT POWER SUPPLY AND WILL HAVE CORRESPONDING S0 FETS) - PAGE 8: DIVIDED PP5V_S3_REG INTO TWO BRANCHES - PP5VRT_S3_REG & PP5VLT_S3_REG - PAGE 45: RENAMED =PP5V_S0_HDD_R TO PP5V_S0_HDD_R (AS PER UNALIASED.LST REPORT) - PAGE 8: ADDED PP5V_S3_DEBUG_ADC_AVDD/DVDD & PP5V_S3_DEBUG_ISNS ALIASES FOR NEW SENSOR PAGE 60 - PAGE 50: ADDED UNUSED NET ALIAS FOR SMC_BIL_BUTTON_L (NC_SMC_BIL_BUTTON_L) - PAGE 4: DELETED DEBUG_SENSE BOM OPTION AND ADDED MEM_SENSE AND - PAGE 8: ADDED PP3V3_S3_BT ALIAS FOR BLUETOOTH ON RIGHT CLUTCH CONNECTOR PAGE - PAGE 52: DELETED TERM BIL FROM SMC BATTERY & BIL CONNECTIONS 1P05_HIGH_SIDE_SENSE OPTIONS UNDER K84_COMMON BOM GROUP - PAGE 8: ADDED ALIAS PPVIN_S3_5VLTS3 UNDER PPBUSB - PAGE 57: ADDED PLACEMENT NOTES TO C5702 AND C5704 AS PER JOHN SCHEN’S FEEDBACK - PAGE 4: ADDED MCP_T_DIODE_SENSOR, MCPSMC_DIGITEMP_NO BOM OPTIONS UNDER - PAGE 8: ADDED ALIAS PP5VLT_S3_V5IN UNDER PP5VRT_S3_REG - PAGE 59: REPLACED SMS PART WITH THE NEW BOSCH BMA141 ANALOG PART. ADDED R5923 10K PU RESISTOR ON K84_COMMON BOM GROUP - PAGE 4: ADDED SHORT POGO PIN 870-1699 AS ALTERNATE FOR THE MEDIUM ONES - PAGE 28: REMOVED RTC POWER SOURCES CIRCUIT AND SUPERCAP_NO BOM OPTION FROM R2820 SEL1 SIGNAL AND REMOVED 10K PD ON ST PIN. REPLACED C5926 WITH 0.01UF CAP AS PER DATA SHEET. AND, - PAGE 34: SINCE X16 AIRPORT CARD SOLUTION IS BEING USED, PP5V_S3_WLAN IS REPLACED BY PP3V3_S3_WLAN REPLACED C5923-C5925 CAPS WITH 0.033 UF VALUES FOR CUT-OFF FREQUENCY OF ~146HZ - PAGE 4: UPDATED DESCRIPTION FOR THE CPU (GOING TO Q3450). ALSO, REPLACED PP5V_WLAN WITH PP3V3_WLAN ON PAGE 6 (FUNCTIONAL TEST POINTS) - PAGE 60: CORRECTED PLACEMENT NOTE ASSOCIATED TO XW6080 TO REFLECT D9710 INSTEAD OF D9701 - PAGE 7: UPDATED TPS AS PER NEW UPDATE FROM TOM (SPREADSHEET ATTACHED TO THE RADAR) - PAGE 34: R3453 IS MODIFIED TO 110K RESISTOR, R3454 IS NOSTUFF AND R3453 IS PULLED UP TO PP3V3_WLAN_F. - PAGE 69: CHANGED L6995 TOB APN 152S1017 FOR COT SAVING AND EFFICIENCY - PAGE 12: REPLACED C1260 WITH APN 128S0267 AS PER DAYU THIS IS TO ENSURE 3.3V LEVEL AT THE INPUT OF U3402 AND MAINTAIN 100MS DELAY SPEC BETWEEN 3.3V POWER - PAGE 69: REMOVED BIL CIRCUIT AS IT NO LONGER A POR [R6960, C6954, D6951, C6953, C6952, J6955, C6951] - PAGE 34: DELETED TEXT NOTE ASSOCIATED WITH J3401 TO THE CARD GETTING STABLE AND AIRPORT GETTING OUT OF RESET - PAGE 70: MOVED C7028 TO PPVBAT_G3H_CHGR_REG AS PER JOHN SCHEN’S FEEDBACK - PAGE 45: ADDED VOLTAGE, MIN LINE AND NECK WIDTH FOR PP5V_S0_HDD_FLT - PAGE 34: DISCONNECTED PP5V_S3_BTCAMERA_F POWER RAIL FROM THE CONNECTOR AND REPLACED IT WITH PP3V3_S3_BT - PAGE 70: ADDED PLACEMENT NOTE TO C7027 AS PER JOHN SCHEN’S FEEDBACK - PAGE 52: ADDED 0 OHMS STUFFING OPTION TO CONNECT MIKEY SMBUS CONNECTIONS TO MCP SMBUS 0. (SIMILAR TO M96). CAMERA SIGNALS ARE ROUTED VIA LVDS CONNECTOR. MOVED PP5V_S3_BTCAMERA POWER CIRCUIT - PAGE 70: REPLACED R7080 WITH APN 107S0142 WHICH IS TRUE 4-TERMINAL SENSE RESISTOR WITH SMALLER PACKAGE ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0 OHMS ALONG WITH THE USB CAMERA SIGNALS TO LVDS PAGE. ALSO, RENAMED THIS POWER RAIL TO PP5V_S3_CAMERA ON LVDS (DAYU’S RECOMMENDATION) - PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN MIKEY AND MCP SMBUS 1 CONNECTIONS. PAGE - PAGE 70: ADDED BOM OPTION 6259_YES TO R7050 AND 6259_NO TO U7060 AND AMON PULLDOWN LOGIC AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_NO WITH THESE 0 OHMS - PAGE 34: ADDED SENSE RESISTOR R3452 ON PP3V3_WLAN SIGNAL CIRCUIT COMPONENTS. TURNED ON 6259_NO, FOR NOW, ON PAGE 4 TABLE - PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN SMC B SMBUS AND MCP SMBUS 1 - PAGE 34: ADDED CHOKES ON PCIE TX/RX SIGNALS. UPDATED PAGE 6 (FUNCTIONAL TEST POINTS) ACCORDINGLY - PAGE 72: CONNECTED SMC_PM_G2_EN SIGNAL TO EN0 PIN 13 OF U7200 VIA A 100K RESISTOR FOR KEEPING THE POWER SUPPLY CONNECTIONS. AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0 - PAGE 34: REPLACED L3404 WLAN INDUCTOR WITH LOW DCR 0603 PART - APN 155S0367 OFF IN CASE IF SMC TURNS OFF OHMS - PAGE 39: REPLACED ETHERNET CONNECTOR WITH APN 514-0668 (SIMILAR TO K36B) - PAGE 72: ADDED PLACEMENT NOTE TO C7230 AS PER JOHN SCHEN’S FEEDBACK - PAGE 52: ADDED BOM OPTION MCPSMC_DIGITEMP_NO TO R5230 AND R5231 - PAGE 72: REMOVED NOSTUFF’ED C7251 AS PER DAYU - PAGE 54: REPLACED DEBUG_SENSE BOM OPTION WITH MEM_SENSE FOR MCP MEMORY VDD - PAGE 45: CHANGED SATA HDD CONNECTOR TO APN 516S0616 - PAGE 73: REPLACED C7307,C7308 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY) CURRENT SENSE CIRCUIT AND WITH 1P05_HIGH_SIDE_SENSE FOR CPU 1.05V AND - PAGE 73: ADDED PLACEMENT NOTE TO C7333 AS PER JOHN SCHEN’S FEEDBACK - PAGE 45: ADDED SENSE RESISTORS R4598 AND R4599 ON 5V ODD AND 5V HDD RAILS RESPECTIVELY CPU VCORE HIGH SIDE CURRENT SENSE CIRCUIT - PAGE 50: UNSTUFFED R5055 AND USED SMC_NB_MISC_ISENSE SIGNAL PORT (SMC) FOR CONNECTING PPBUSA ISENSE SIGNAL. - PAGE 73: DELETED NOTES AT THE BOTTOM RIGHT AFTER CONSULTING WITH DAYU - PAGE 55: ADDED MCP_T_DIODE_SENSOR BOM OPTION TO THE MCP T-DIODE THERMAL ADDED ALIAS ON THIS PAGE - PAGE 73: MOVED C7344 NEXT TO R7350 AND ADDED PLACEMENT NOTE (JOHN SCHEN WANTED IT TO BE NEXT TO L7320 SENSOR CIRCUIT DAYU PERFERRED IT TO BE AFTER THE SENSE RESISTOR - PAGE 51: REPLACED TWO DEMUX SOLUTION WITH A SINGLE DEMUX 1X2 SOLUTION. APN USED - 353S2220 - PAGE 59: DELETED R5923 FROM THE TEXT NOTE [ONLY CHIP SELECT IS BEING DEMUXED] - PAGE 74: ADDED PLACEMENT NOTES TO C7419,C7422 AND C7423 AS PER JOHN SCHEN’S FEEDBACK - PAGE 60: MANUALLY UPDATED RESISTORS VALUES (VOLTAGE DIVIDERS,AMPLIFIER GAINS, RC) TO MATCH WITH - PAGE 51: R5156, R5157 AND R5158 ARE NOW 0 OHM ISOLATION RESISTORS PLACED ON SPI BUS NEXT TO THE LOCATION WHERE - PAGE 74: STUFFED C7432 AS PER DAYU K19I UPDATES, EXCEPT VOLTAGE DIVIDER FOR PP3V3_WLAN [K19I USES 5V RAIL]. FOR IT BRANCHES INTO TWO - ONE GOING TO MLB SPI ROM AND THE OTHER GOING TO LPC CONNECTOR. THESE RESISTORS ARE - PAGE 74: REMOVED C7400, C7402, R7451 AND R7452 AS PER DAYU PP3V3_WLAN, R6010 HAS BEEN CHANGED TO 634K TO GET VDIVIDER = ~2V PLACED ON THE LPC CONNECTOR BRANCH. THIS IS TO AVOID STUBS IN PRODUCTION - PAGE 75: ADDED PLACEMENT NOTE TO C7563 AS PER JOHN SCHEN’S FEEDBACK - PAGE 75: ADDED C7590 (2.2UF) APN 138S0579 IN PARALLEL WITH C7563 AS PER DAYU - PAGE 52: ADDED SENSOR ADC CONNECTION BLOCK UNDER ’SMC 0 SMBUS CONNECTIONS’ SECTION - PAGE 74: CHANGE L7400 AND L7401 TO 152S1019 AS PER DAYU FOR COST SAVING. ALSO, UPDATED ASSOCIATED TEXTS - PAGE 102: ADDED CONN_PCIE_MINI_R2D_P/N AND CONN_PCIE_MINI_D2R_P/N NETS IN THE - PAGE 75: MOVED C7569 TO PPMCPCORE_S0_R AS PER JOHN SCHEN’S FEEDBACK - PAGE 54: MOVED PBUS INA210 CIRCUIT TO THIS CURRENT SENSOR PAGE. RENAMED REF DES AS PER THIS PAGE 54 CONSTRAINT SET - PAGE 55: DELETED J5590 CONNECTOR (CONNECTED TO HEAT-PIPE TEMPERATURE DETECTION RAILS) - PAGE 90: ADDED EMI CAPS (C9017-C9025) ON I2C, LED_RETURNS AND LCD_BKLT POWER RAILS GOING TO LVDS. - PAGE 70: ADDED TP TO PIN 13 - PAGE 55: REPLACED U5515 & U5535 WITH CHEAPER APN 353S2571 ADDED PLACEMENT NOTES TOO - PAGE 4: ADDED MIKEY_LOAD_DET BOM OPTION UNDER K84_MISC BOM GROUP - PAGE 60: REMOVED WELLSPRING 3 PAGE (GOING BACK TO K24 SOLUTION) AND REPLACED IT WITH K19I DEBUG SENSOR PAGE (SCHUTIL SYNC) - PAGE 94: REPLACED C9486 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY) - PAGE 61: RENAMED SPI SIGNALS TO MATCH WITH CHANGES ON PAGE 51 ***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 8.0.0*** - PAGE 69: ADDED BOM OPTION NOSTUFF TO D6950 FOR NOW - CHANGED R6211 & R6212 FROM 39 OHMS TO 22 OHMS ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 5.0.0*** - PAGE 69: ADDED D6951 ESD DIODE ON BIL SMBUS SIGNALS (NOSTUFF FOR NOW) -PG. 67, CHANGED U6700 CB INPUT TO BE CONTROLLED BY CS4206 GPIO0. - DELETED NOTE ABOVE U6500 - PAGE 69: REPLACED BATTERY CONNECTOR J6950 WITH APN 518S0540 (M96) CONNECTOR -PG. 62, CHANGED TP_AUD_GPIO_0 TO AUD_GPIO_0. - ADDED BOMOPTION = MIKEY_LOAD_DET ATTRIBUTE TO R6870, R6871, C6870, - PAGE 70: ADDED BYPASS 0 OHM RESISTOR R7050 (NOSTUFF FOR NOW) OPTION FOR NEW CHIP WHICH WON’T REQUIRE U7060 SOLUTION -PG.66, REPLACED THE LM48310’S (U6610/20/30) WITH LM48311’S - UPDATED SIGNAL PATH CHART TO INCLUDE MCP79 GPIO ASSIGNMENTS - PAGE 71: ADDED NEW PAGE FOR PP5V_LT_REG POWER SUPPLY. UPDATED ALL THE REF DES AS PER THE PAGE NUMBER -PG. 67, CONNECTED HP OUTPUTS TO NC OF U6700 AND LINE INPUTS TO NO OF U6700. - ADDED BOMOPTION = MIKEY ATTRIBUTE TO R6860, C6860, Q6802, R6864, R6865, & R6861 - PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 WITH 68UF OSCON CAP (APN 128S0275) & C7240 WITH 39UF (APN 128S0248) -PG. 68, CHANGED AUD_PORTB_DET_L TO AUD_PORTA_DET_L. C6871, U6870, C6872, R6872, & R6873 - PAGE 71: CHANGED C7160 TO 39UF OSCON CAP (APN 128S0248) - REMOVED NOTE RE: ROUTING TO MCP79 GPIO ABOVE U6870 -PG. 68, CHANGED AUD_PORTG_DET_L TO AUD_PORTB_DET_L. - PAGE 72: REPLACE Q7220 WITH SIZ700DT AND L7260 WITH SMALLER 10A PART (APN 152S0778) -PG. 67, SET MIN. LINE AND NECK WIDTHS FOR AUD_CONN_L AND AUD_CONN_R - REMOVED BOMOPTION = NOSTUFF ATTRIBUTE FROM R6724 - PAGE 73: ADDED SENSE RESISTOR R7350 ON 1.5V DDR3 SUPPLY RAIL - ADDED BOMOPTION = NOSTUFF ATTRIBUTE TO R6725 - PAGE 77: REMOVED 1.05V S0 PLL LDO CIRCUIT. AND, REMOVED LDO_NO BOM OPTION FROM R7745 ***PAGES SYNCED FROM K24 SINCE LAST RELEASE 5.0.0*** - PAGE 75: CHANGED C7571 & C7560 TO 68UF OSCON CAPS (APN 128S0275) - PAGE 25: CHANGED C2500,C2501,C2502,C2503,C2515,C2520,C2528,C2540,C2580,C2582,C2584,C2586,C2588, - PAGE 78: RENAMED P5VS3_EN_L TO P5VRTS3_EN_L (RT POWER SUPPLY ENABLE) AND ADDED R7814, C7814 S3 ENABLE CIRCUIT C2595 TO 138S0653 4/1/2009: RELEASE 9.1.0 (MAJOR)FOR GENERATING P5VLTS3_EN ENABLE SIGNAL FOR LT POWER SUPPLY - PAGE 26: CHANGED C2615,C6210 TO 138S0653 - PAGE 78: ADDED P5V_LTS3_PGOOD POWER GOOD SIGNAL (WIRED AND WITH OTHER S0 RAILS PGOOD) CORRESPONDING TO 5V LT - PAGE 77: CHANGED U7740 TO 500MA 1.05V LDO - PAGE 4: CHANGED MCP P/N TO 338S0702 AS PER CHALLEE POWER SUPPLY - PAGE 52: FIXED SENSOR ADC SMBUS CONNECTIONS (BOTH SCL AND SDA WERE WRONGLY CONNECTED - PAGE 78: ADDED 0 OHM ISOLATION RESISTORS ON POWER GOOD SIGNALS (BEFORE WIRED AND) TO SMB_0_S0_DATA NETS - PAGE 79: ADDED 5V LT S0 FET AND UPDATED NET NAMES FOR BOTH RT AND LT S0 FET CIRCUITS ACCORDINGLY 3/17/2009: RELEASE 7.0.0 (RFA)- PAGE 69: REFRESHED HALL EFFECT SENSOR WITH THE NEW SYMBOL - PAGE 90: UPDATED LVDS CONNECTOR CONNECTIONS AS PER STEVE’S RECOMMENDATION. ADDED CAMERA SIGNALS - ADDED PLACEMENT NOTES (ATTRIBUTE) TO ALL XW SHORTS - PAGE 90:RE-ROUTED LED_RETURN SIGNALS FOR LAYOUT FEASIBILITY(CHIP WAS MOVED TO TOP SIDE) - PAGE 97: ADDED BOM OPTION - NOSTUFF- TO R9702 AS PER K19I - PAGE 4: DELETING ENTRIES FOR 107S0138 AND 107S0139 FROM ALTERNATES PARTS TABLE AS THEY WOULD BE REPLACING - PAGE 90: ADDED C9017 (1000PF) CAP AS PER JOHN SCHEN - PAGE 8: DELETED PP5V_S0_BKL, RENAMED PP1V05_S0_MCP_PLL_UF_R TO PP1V05_S0_MCP_PLL_UF THE 107S0074/75 PARTS - PAGE 97: FIXED THE LCDBKLT_VIN SIGNAL NAME ASSOCIATION TO THE CORRECT NET INSTEAD OF - PAGE 8: DELETED PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_BKL_VDDIO, PP3V3_S0_MCP_PLL_VLDO - PAGE 7: RENAMED PP5V_S3_BTCAMERA_F WITH PP3V3_S3_BT_F R9730 PIN - PAGE 8: RENAMED PPVIN_S5_1V5S3_0V75S0 TO PPVIN_S5_1V5S30V75S0 - PAGE 7: DELETED PP5V_S0, PP5V_S3 AND ADDED PP5VRT_S0,PP5VLT_S0, PP5VRT_S3, PP5VLT_S3 DEBUG - PAGE 97: DISCONNECTED PGND (OF CAPS) FROM XW9700 AND ADDED A SEPARATE XW9701 - PAGE 28: DELETED FW_RESET_L SIGNAL VOLTAGE TEST POINTS SHORT TO ISOLATE NOISY PGND FROM THE SYSTEM GND. NAMED IT - PAGE 58: DELETED KB BKLT CIRCUIT - PAGE 7: ADDED PPBUS_R_G3H DEBUG VOLTAGE TEST POINT GND_LCDBKLT_PGND AND ASSIGNED MIN_LINE/NECK_WIDTH ATTRIBUTES - PAGE 60: UPDATED WLAN DIVIDER CIRCUIT WITH 3V3 POWER RAIL INSTEAD OF 5V - PAGE 8: DELETED ALIAS =PP1V05_S0_SMC_LS AS IT IS NO LONGER NEEDED - PAGE 97: RENAMED GND_LCDBKLT TO GND_LCDBKLT_SGND - PAGE 73: UPDATED 1.5V/0.75V POWER SUPPLY WITH CORRECT NET NAMES REFLECTING 1.5V/0.75V INSTEAD OF 1.8V/0.9V AND - PAGE 9: REMOVING 2 EXTRA TALL POGO PINS (ZS0911, ZS0912) AS PER NEW MCO - PAGE 97:DISCONNECTED PINS 2 AND 5 FROM GND PINS(13,19,21)AND CONNECTED SEPARATELY TO IN SYNC WITH PAGE 8 ALIASES - PAGE 9: REPLACED 5 SHORT POGO PINS WITH MEDIUM ONES AND ADDED THREE EXTRA MEDIUM ONES (TOTAL MEDIUM SYSTEM GND - PAGE 4: REMOVED 152S0778 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE SINCE L7260 AS HAS BEEN REPLACED WITH THIS PART POGO PINS = 8) AS PER NEW MCO - PAGE 97: REPLACED D9710 WITH 40V PART- APN 371S0580 AS PER DEREK - PAGE 97: STUFFED R9726 AND SWAPPED C9705 AND R9705 AS PER FREESCALE FOR COMPENSATION. - PAGE 4: REMOVED 104S0018 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE - PAGE 34: REPLACE Q3450 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 - PAGE 45: REPLACE Q4590 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 ALSO, CHANGED R9705 TO 10K 1% VALUE - APN 114S0315 - PAGE 52: DELETE J6955 REFERENCE AS THERE IS NO BIL CONNECTOR ***PAGES SYNCED FROM K24 SINCE LAST RELEASE 2.0.0*** - PAGE 52: REMOVED REFERENCES TO THE LED BACKLIGHT AS FREESCALE PART DOESN’T HAVE I2C BUS ACCESS 4/2/2009: RELEASE 9.2.0 (MAJOR): - PAGE 54: REPLACING R5492 WITH APN 107S0139 PART FOR COST SAVING - PAGE 7: SCRUBBED TPS AS PER UPDATE FROM TOM - PG 50: SWAPPED THE PART NUMBER AND THE ALTERNATE PART NUMBER FOR VR5020. MADE ISL60002 THE ALTERNATE PART - PAGE 59: REMOVING R5923 AND ONLY 1 PU ON SEL LINES IS ENOUGH - PAGE 49: FIXED PLACEMENT NOTE ASSOCIATED WITH C4907 (SHOULD BE: PLACE NEAR PIN E1) - PAGE 70: REPLACING R7020 WITH APN 107S0138 PART FOR COST SAVING - PAGE 49:FIXED PLACEMENT NOTES ASSOCIATED WITH R4999,C4920(SHOULD BE:PLACE NEAR PIN M12) - PAGE 70: REPLACING R7008 WITH APN 107S0139 PART FOR COST SAVING ***PAGES SYNCED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 2.0.0*** - PAGE 51: FIXED PLACEMENT NOTE ASSOCIATED WITH R5146 - PLACE NEAR U5110 INSTEAD OF SMC - CHANGED SPEAKER AMPS TO LM48310, PLACEHOLDERS FOR LM48311. LM48311 IS THE CSP VERSION OF THE LM48310. - PAGE 70: R7080 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER - PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH SMBUS_SMC_B_S0_SCL/SDA - CHANGED LDO TO B LP5900. - PAGE 97: RENAMED SINGLE PIN NET GND_LCDBKLT TO GND_LCDBKLT_PGND - PAGE 73: R7350 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER - REMOVED OPTIONAL STUFFING RESISTORS AROUND THE RE-TASKING JACK ANALOG SWITCH. - PAGE 79: REPLACE Q7940 AND Q7948 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 - PAGE 90: REMOVED EMI CAPS [C9017-C9025] ON LED_RETURN, I2C AND LCD_BKLT POWER NETS 2/26/2009: RELEASE 4.0.0 (RFA RELEASE): - PAGE 90: UPDATED LVDS CONNECTOR PINOUT CONNECTIONS AS PER STEVE’S NEW SPREADSHEET - PAGE 4: ADDED LDO_NO BOM OPTION - PAGE 97: ADDED DIDIT=TRUE ATTRIBUTE TO THE SWITCHING NODE PINS 3 & 4 - PAGE 8: RENAMED PP1V05_S0_MCP_PLL_UF BACK TO PP1V05_S0_MCP_PLL_UF_R - PAGE 97: CHANGED C9711 FROM 0.1UF TO 1.0UF 0603 TYPE CAP AS PER FREESCALE FEEDBACK - PAGE 8: ADDED BACK - PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_MCP_PLL_VLDO - PAGE 97: CHANGED C9715 AND C9716 TO 50V CAPS FOR COST SAVING AND AS PER FREESCALE FEEDBACK - PAGE 13: REPLACED XDP CONNECTOR WITH MINI XDP CONNECTOR APN 516S0625 - PAGE 97: CHANGED R9717 - R9722 FROM 0.1% TO 1% PARTS FOR COST SAVINGS AND AS PER FREESCALE FEEDBACK - PAGE 34: ADDED NOTE WITH REGARD TO SMBUS CONNECTIONS TO THE AIRPORT CONNECTOR - PAGE 97: NO STUFF’ED C9721 - C9726 AS PER FREESCALE FEEDBACK - PAGE 34: ADDED NOTE WITH REGARD TO 100 MS DELAY REQUIREMENT BETWEEN 3.3 WLAN - PAGE 97: FOR 25KHZ OPERATION, CHANGE R9726 TO NO STUFF, INTERCHANGE R9705(6.8K) WITH C9705 POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET AS IN K19I - PAGE 54: REMOVED NOTE ON AMON AND BMON - PAGE 97: CHANGED R9710 TO 6.65K APN 114S0298 AND R9716 TO 226K APN 114S0445 PARTS AS PER - PAGE 57: REPLACED KEYBOARD CONNECTOR WITH APN 518S0738 FREESCALE FEEDBACK - PAGE 77: ADDED BACK - 1.05 PLL LDO CIRCUIT - PAGE 107: ADDED CONSTRAINTS FOR FOLLOWING SENSOR NETS: ISNS_HDD_P/ISNS_HDD_N; ISNS_ODD_P/ISNS_ODD_N; - PAGE 90: REFRESHED THE SYMBOL OF U9000, PART NUMBER CHANGED TO 353S2603 ISNS_AIRPORT_P/ISNS_AIRPORT_N; ISNS_1V5_S3_P/ISNS_1V5_S3_N; ISNS_LCDBKLT_P/ ISNS_LCDBKLT_N 3/4/2009: RELEASE 5.0.0 (RFA)- PAGE 107: REMOVED FOLLOWING SENSOR NETS CONSTRAINTS: ISNS_P1V5S0MCP_P/ISNS_P1V5S0MCP_N; - PAGE 34: ADDED A TEXT NOTE THAT J3401 (AIRPORT CONNECTOR) COULD CHANGE TO 1.8MM HEIGHT APN 516S0582 ISNS_PVCORES0MCP_P/ISNS_PVCORES0MCP_N SYNC_MASTER=K24_MLB SYNC_DATE=01/19/2009 - PAGE 57: REPLACED KEYBOARD CONNECTOR WITH THAT OF K24 (APN 518S0637) - SYNC’ED FROM K24 - PAGE 74: ADDED XW7401-XW7404 SHORTS ACROSS L7400 AND L7401 PAGE TITLE - PAGE 69: REPLACED BATTERY CONNECTOR WITH THAT OF K24 (APN 518-0359) - PAGE 69: DELETED NOTE REGARDING INDUCTOR FILTER REQUIREMENT ON BATT_POS_F (AS PER JOHN SCHEN) ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 6.0.0*** - PAGE 70: CHANGED Q7050 TO 376S0761 AS PER DAYU & K24 DESIGN -PG. 67, DELETED R6725 AND NET =PP3V42G3H_AUDIO -PG. 66, ADDED R6613/14/15/16/17 - PAGE 70: CHANGED Q7000 AND Q7001 CHEAPER TO 376S0667 (HAT1128) AS PER DAYU’S RECOMMENDATION - PAGE 71: DISCONNECTING EN_PSV (PIN 34) FROM P5VLTS3_EN SIGNAL AND CONNECTING IT TO -PG. 66, ADDED C6612/13 DRAWING NUMBER SIZE PP5VLT_S3_V5IN (5VRT PS) -PG. 66, ADDED R6631/2/3/4/5 -PG. 66, ADDED C6634/5 - PAGE 72: L7220 CHANGED TO 152S0778 FOR COST SAVING AS PER DAYU - PAGE 73: ADDED ONE MORE OSCON 39UF CAP ON INPUT SIDE -PG. 66, CHANGED C6610/11 TO 0.022UF - PAGE 73: MOVED THE SENSE RESISTOR NEXT TO INDUCTOR -PG. 66, CHANGED C6630/31 TO 0.022UF REVISION - PAGE 74: REMOVED UNUSED NETWORK ON U7400 PIN 5 AND PIN 6 AS PER DAYU [R7406, C7410, R7427, R7426] -PG. 65, DELETED R6521 R - PAGE 74: STUFF R7413 AS PER DAYU -PG. 65, ADDED R6523/4 - PAGE 74: CHANGED Q7400 AND Q7402 TO 376S0772 AS PER DAYU -PG. 62, ADDED PLACEMENT COMMENT ATTR. TO XW6200/1 - PAGE 74: CHANGED Q7401 AND Q7403 TO 376S0771 AS PER DAYU -PG. 67, ADDED PLACEMENT COMMENT ATTR. TO XW6700/1/10/11 NOTICE OF PROPRIETARY PROPERTY: BRANCH - PAGE 75: CHANGED R7525 TO 107S0132 FOR COST SAVING AS PER DAYU -PG. 68, ADDED PLACEMENT COMMENT ATTR. TO XW6851/80 - PAGE 78: DELETING P5VLTS3_EN RC CIRCUIT AS IT IS NO LONGER NEEDED (SEE ABOVE). ALSO UPDATED ASSOCIATED TEXT NOTE -PG. 66, REPLACED U6610/30 WITH LM48556 CKTS THE INFORMATION CONTAINED HEREIN IS THE - PAGE 97: FIXED CONNECTION POINT (DOT) FOR LCDBKLT_VIN -PG. 67, DELETED C6760/1/2/3. PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. - PAGE 97: ADDED 0 OHMS SERIES RESISTOR ON LCD_BKLT_PWM FOR DEBUGGING PURPOSES -PG. 67, CHANGEED J6703 TO TWO PIN CONN. THE POSESSOR AGREES TO THE FOLLOWING: PAGE - PAGE 97: RENAMED LCD_BKLT_PWM TO LVDS_IG_BKL_PWM -PG. 67, ADDED J6704 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE - PAGE 97: CHANGED VOVP VALUE TO 6.9V AS PER FREESCALE FEEDBACK -PG. 62, REPLACED C6225 WITH APN: 128S0216 - PAGE 97: ADDED R9726 (22K) AND SWAPPED C9705 AND R9705 LOCATIONS FOR NOISE REDUCTION AS PER FREESCALE RECOMMENDATION II NOT TO REPRODUCE OR COPY IT - PAGE 97: DELETED C9712 AS IT IS REDUNDANT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET - PAGE 97: ADDED PLACEMENT NOTE ATTRIBUTE TO C9713 AND C9710 FOR PLACING THOSE NEAR L9710
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Revision History Apple Inc.
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4/2/2009: RELEASE 9.3.0 (MAJOR): - PAGE 4:B ADDED 5.95MM SANYO PART 128S0288 AS ALTERNATE TO 128S0271 - PAGE 4:B ADDED 5.95MM SANYO PART 128S0286 AS ALTERNATE TO 128S0248 - PAGE 4: DELETED 152S0694 ALTERNATE ENTRY FOR 152S0138 AS IT IS NOT USED - PAGE 50: REPLACED DUAL Q5032 FET WITH TWO SINGLE Q5032 & Q5033 (APN 376S0612) N-CH FETS FOR ROUTING PURPOSES (SIL ANODE SIGNAL) - PAGE 54:B CHANGED R5412 TO 118OHM (114S0127) - PAGE 72: ADDED MIN_LINE/NECK_WIDTH ATTRIBUTES TO 5V_S3_DRVL, 3V3S5_VBST, 3V3S5_DRVL (FIXED THE NET NAME- ADDED UNDERSCORE) - PAGE 75: CHANGED L7560 TO APN 152S0526 - 0.68UH, 3.5MOHM,16A - AS PER DAYU - PAGE 75: CHANGED R7569 TO 11.3K APN 114S0319 FOR SETTING THE CORRECT OCSET AS PER DAYU - PAGE 97: CHANGED MIN_NECK_WIDTH ASSOCIATED WITH PPVOUT_S0_LCDBKLT TO 0.24MM AS THAT’S THE PIN WIDTH - PAGE 97: CHANGED MIN_LINE/NECK_WIDTH ASSOCIATED WITH GND_LCDBKLT_SGND TO 0.6/0.24MM ***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 9.2.0*** - REMOVED R6725 AND =PP3V3_S3_AUDIO CONNECTION TO MAX14504 ANALOG SWITCH 4/2/2009: RELEASE: 9.4.0 (MAJOR): - PAGE 97: ADDED A 1000PF CAP (C9727) ON LCDBKLT_VIN NEAR PIN 1 - PAGE 97: REPLACED C9717 WITH 1000PF CAP APN 132S0147 AND ADDED PLACEMENT NOTE AS PER JOHN SCHEN 4/2/2009: RELEASE: 9.5.0 (MAJOR): - PAGE 9: REPLACED Z0906,Z0907,Z0910 AND Z0911 MLB MOUNTING HOLES WITH 2.7 MM DIAMETER PLATED HOLES - APN 998-1584 4/3/2009: RELEASE: 9.6.0 (MAJOR): - PAGE 4: UNDER K84_PROGPARTS BOM GROUP, REPLACED BLANK P/N WITH PROGRAMMED P/N - PAGE 8: ADDED GLOBAL DIGITAL GROUND NET WITH MIN_LINE/NECK_WIDTH AND VOLTAGE ATTRIBUTES - PAGE 9: REPLACED Z0905 AND Z0913 MLB MOUNTING HOLES WITH 2.7 MM DIAMETER PLATED HOLES - APN 998-1584 - PAGE 9: DELETED GND MIN_LINE/NECK_WIDTH AND VOLTAGE ATTRIBUTES FROM FAN STANDOFF **PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.5.0*** - REMOVED OPTIONAL STUFF-AROUND RESISTORS FOR ANALOG SWITCH - CONNECT AUDIO JACK SHIELD TO DIGITAL GROUND. 4/3/2009: RELEASE: 10.0.0 (RFA): - PAGE 9: ADDED 7 EXTRA TALL POGO PINS FOR EMI - 4 STUFFED AT THE BOTTOM, 3 UNSTUFFED ON THE TOP - PAGE 28: DELETED MAKE_BASE=TRUE ASSOCIATED WITH PCIE_RESET_L - PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH I2C_MIKEY_SCL/SDA_R - PAGE 69: REFRESHED J6955 SYMBOL - APN 516S0787 - PAGE 78: DELETED MAKE_BASE=TRUE ASSOCIATED WITH ALL_SYS_PWRGD - PAGE 78: DELETED SYNONYMS AS THEY ARE NOT NEEDED ANYMORE (DUE TO 0 OHMS) **PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.6.0*** - ADDED 100PF EMC CAP ON THREE SPEAKER CONNECTORS. - CHANGED MIN_WIDTH OF CODEC HP OUT NETS.
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4/5/2009: RELEASE 10.1.0 (MAJOR): - PAGE 4: ADDED CHGR_6258 BOM OPTION UNDER MODULE PARTS TABLE AND TO K84 MISC BOM GROUP. THIS IS TO STUFF ISL6258 PART - PAGE 9: ADDED ONE MORE TALL POGO PIN ON BOTTOM SIDE - PAGE 13: FIXED THE NOTE ON THE XDP PAGE- REPLACING 920-0620 ADAPTER BOARD WITH 920-0782 ADAPTER FLEX - PAGE 34: RENAMED P5VWLAN_SS NET TO P3V3WLAN_SS - PAGE 46: DELETED TEXT NOTE RELATED TO R4691 & R4690 AS IT IS NA TO K84 - PAGE 52: MOVED THE R5251 CONNECTION TO SENSOR ADC TO THE RIGHT SIDE TO SHOW A SEPARATE CONNECTION FOR CLARITY - PAGE 52: DELETED TEXT NOTE ON BATTERY LED DRIVER AS IT IS NA TO K84 - PAGE 69: PUT R6961 BEFORE C6955 TO GET RC FILTER. ALSO, FOR NOW, REPLACED R6961 WITH A 0 OHM RESISTOR AND NOSTUFF’ED C6955 - PAGE 70: ADDED OMIT BOM OPTION TO U7000 AS THIS PART WILL GET STUFFED WITH EITHER ISL6258 OR ISL6259 DEPENDING UPON PAGE 4 BOM TABLE - PAGE 70: FIXED Q7001 DRAIN-SOURCE ORIENTATION 4/6/2009 - RELEASE 10.1.1 (MINOR): **SCHEMATIC AND BOM CLEAN-UP** - PAGE 4: DELETED CHGR_6258 AND RENAMED 6259_NO TO CHGR_6259_NO. REPLACED CHGR_6258 WITH CHGR_6259_NO IN MODULE PARTS TABLE - PAGE 4: DELETED ENTRIES IN THE ALTERNATE BOM TABLE FOR THE FOLLOWING APN: 516-0213 AND 516S0709 - PAGE 8: DELETED =PP3V3_S3_AUDIO ALIAS AS IT IS NO LONGER APPLICABLE - PAGE 57: DELETED NO_TEST = TRUE ATTRIBUTE FROM Z2_SCLK AND Z2_MOSI AS THEY CONFLICT WITH FUNC_TEST ATTRIBUTE ON PAGE 7 - PAGE 69: RENAMED 6259_NO/YES TO CHGR_6259_NO/YES 4/6/2009 - RELEASE 11.0.0 (OK2FAB): - NO CHANGE SINCE LAST MINOR RELEASE 10.1.1
4/23/2009 - RELEASE 12.1.0 (MAJOR): - PAGE 4: ADDED METAL PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO ADDED CORRESPONDING NOTES514-0691 ALTERNATE FOR 514-0690; 514-0689 ALTERNATE FOR 514-0688 - PAGE 13: REPLACED J1300 XDP CONNECTOR WITH MORE ROBUST CONNECTOR APN 998-2515 - PAGE 39: REPLACED J3900 ETHERNET CONNECTOR WITH POR PLASTIC CONNECTOR APN 514-0692 - PAGE 46: REPLACED J4600 & J4610 USB CONNECTORS WITH POR PLASTIC CONNECTOR APN 514-0688 - PAGE 75: CHANGE Q7560 AND Q7565 TO SIS426 APN 376S0749 PER RDAR://6812904 - PAGE 75: CHANGE R7565 TO 1OHM APN 113S0023 PER RDAR://6812904 - PAGE 76: CHANGED THE CPU VTT OVER CURRENT TRIP POINT PER RDAR://6792329 BY CHANGING R7604 FROM 8.87KN) TO 6.04KN) - PAGE 94: REPLACED J9400 DP CONNECTOR WITH POR PLASTIC CONNECTOR APN 514-0690 - PAGE 75: CHANGED C7565 AND C7568 TO CASE_B4_SM PACKAGE FROM CASE_B2_SM DUE TO PACKAGING ERROR (SAME APN) 4/24/2009 - RELEASE 12.2.0 (MAJOR): **PAGES SYNCED FROM CASEY’S AUDIO_MLB SINCE LAST RELEASE 12.1.0*** - REPLACED J6700 WITH APN: 514-0694 - ADDED DZ 6702 AND L6706 - CONNECTED R6860 TO AUD_IP_PERPH_DET 4/27/2009 - RELEASE 12.3.0 (MAJOR & WEEKLY ECO): - PAGE 4: ADDED NEW BOM ENTRY 639-0254 FOR MOLEX DDR3 CONNECTOR CONFIG. ALSO, EDITED 639-0035 BOM NAME TO REFLECT FOXCONN DDR3 CONNECTOR. ADDED TWO ENTRIES (J3200 AND J3100) FOR FOXCONN AND TWO FOR MOLEX UNDER MODULE PARTS TABLE . - PAGE 74: CHANGED C7432 TO 0.001UF AS PER RDAR://6792327 - PAGE 74: UNSTUFFED C7434 AS PER RDAR://6792327 - PAGE 74: CHANGED C7428 TO 0.47UF AS PER RDAR://6792327 - PAGE 74: CHANGED R7415 TO 10.5K AS PER RDAR://6792327 - PAGE 97: CHANGED R9716 FROM 226K TO 243K TO CHANGE THE OVP POINT TO 35.3V AS PER KIRAN 4/28/2009: RELEASE 12.4.0 (MAJOR): - PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS FOR EMI PURPOSES - L6707 & L6708
APN 155S0367 ON RIGHT PIEZO SPEAKER
4/28/2009: RELEASE 12.5.0 (MAJOR): - PAGE 67: MOVED L6707 & L6708 TO J6703 (FULL RANGE SPEAKER CONNECTOR) BETWEEN CAPS AND CONNECTOR 4/29/2009: RELEASE 12.6.0 (MAJOR & WEEKLY ECO): - PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER J6704 FOR EMI PURPOSES - L6709 & L6710 - PAGE 97: CHANGED L9710 TO A BIGGER 2525 PACKAGE (LOW DCR) APN 152S0585 FOR BETTER EFFICIENCY 4/29/2009: RELEASE 12.7.0 (MAJOR & WEEKLY ECO): - PAGE 97: CHANGED L9710 BACK TO THE ORIGINAL APN 152S0826 AS 2525 PACKAGE CAN’T FIT IN
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5/01/2009: RELEASE 12.8.0 (MAJOR): - PAGE 4: ADDED A36 EEE NUMBER FOR NEW BOM CONFIGURATION 639-0254 - PAGE 60: ADDED 0 OHMS SERIES RESISTORS R6003 AND R6004 ON AVDD AND DVDD SUPPLY RAILS TO ADC CHIP - PAGE 60: CHANGED R6001 & R6002 TO 33 OHMS RESISTORS TO FIX UNDERSHOOT ON I2C BUS 05/01/2009: RELEASE 12.9.0 (MAJOR): - PAGE 4: UPDATED PLASTIC PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO ADDED CORRESPONDING NOTES514-0690 PLASTIC ALTERNATE FOR 514-0691 METAL; 514-0688 PLASTIC ALTERNATE FOR 514-0689 METAL - PAGE 46: REPLACED PLASTIC USB CONNECTORS WITH METAL APN 514-0689 PARTS - PAGE 94: REPLACED PLASTIC MINI DP CONNECTOR WITH METAL APN 514-0691 PART
05/08/2009: RELEASE 12.12.0 (MAJOR & WEEKLY ECO): - PAGE 4: DELETED SANYO 6.00MM OSCON CAPS 128S0248 & 128S0271 FROM THE ALTERNATE TABLE (MAKING ALTERNATES AS PRIMARY) - PAGE 4: TURNING ON BOM OPTION MCPSMC_DIGITEMP_YES AS POR IS TO CONNECT MIKEY TO MCP79 SMBUS 0 INSTEAD OF SMBUS 1 AND TO CONNECT SMC B SMBUS TO MCP79 SMBUS 1 - PAGE 4: ADDED A TEXT NOTE STATING THAT ADC CAN ONLY WORK IN S0 STATE AS IT HAS I2C BUS PU TO S0 POWER RAIL - PAGE 37: CHANGED C3714 AND C3715 TO 2.2UF APN 138S0642 TO FIX ETHERNET JITTER ISSUE - PAGE 50: CHANGED R5030 TO 63.4 OHMS APN 114S0102 TO INCREASE THE SIL CURRENT PER RDAR://PROBLEM/6752822 - PAGE 50: CHANGED R5714 TO 0 OHM APN 116S0004 PER RDAR://PROBLEM/6752822 - PAGE 52: CHANGED R5200, R5201, R5260 & R5261 TO 2K APN 116S0073 - PAGE 72: REPLACED C7252, C7291 & C7292 WITH 5.95MM SANYO APN 128S0288 - PAGE 72: REPLACED C7240 & C7282 WITH 5.95MM SANYO APN 128S0286 - PAGE 73: REPLACED C7331 & C7345 WITH 5.95MM SANYO APN 128S0286 - PAGE 77: CHANGED C7771 TO 47UF APN 138S0659 TO FIX ETHERNET JITTER ISSUE
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05/10/2009: RELEASE 12.13.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL): - PAGE 60: CHANGED R6003 AND R6004 TO 10 OHMS 5% RESISTOR VALUES RDAR://PROBLEM/6834630 05/11/2009: RELEASE 12.14.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL): - PAGE 57 : CHANGED R5714 TO 165 OHMS APN 114S0141 AS PER RDAR://PROBLEM/6875543 - PAGE 72 : CHANGED C7252, C7291 & C7292 BACK TO ORIGINAL APN 128S0271 05/20/2009: AGILE RELEASE PROTO 2 - FINAL PROTO 2 OK2FAB RELEASE - UPDATED PAGE BORDERS TO NEW E4 05/22/2009: AGILE RELEASE PROTO 2 ***RETRY*** - FINAL PROTO 2 OK2FAB RELEASE - UPDATED PAGE BORDERS TO NEW E4
OK2FAB 13.0.0 (FAB): DSIZE STANDARDS OK2FAB 14.0.0 (FAB)DSIZE STANDARDS
06/09/2009: RELEASE 14.1.0 (MAJOR)- PAGE 4: REMOVING CHGR_6259_NO BOM OPTION AS ISL 6259 IS NOT POR - PAGE 4: ADDED NEW ISL PART APN 353S2718 AS AN ALTERNATE TO FIX B4 DONGLE ISSUE - PAGE 9: REPLACED ALL MEDIUM POGO PINS WITH APN 870-1794 (2 MM) AND ZS0916-ZS0918 WITH THINBC APN 870-1820 (2 MM) ONES - PAGE 59: ADDED R5922 10 OHMS SERIES R ON VDD SUPPLY TO FIX SMS NOISE ISSUE - PAGE 67: CHANGED J6704 TO A THREE PIN CONNECTOR 518S0520 - PAGE 69: REFRESHED J6955 SYMBOL (HALL EFFECT CONNECTOR) - PAGE 70: REMOVED CHGR_6259_YES/NO BOM ATTRIBUTES AS ISL 6259 IS NOT POR - PAGE 70: DELETED R7051 & R7053 CHGR_6259_YES BOM OPTIONS COMPONENTS - PAGE 70: REPLACING R7052 & R7054 CHGR_6259_NO BOM OPTION COMPONENTS WITH XW SHORTS- XW7052 & XW7054 - PAGE 70: REMOVED R7050 CHGR_6259_YES COMPONENT AS IT IS NOT NEEDED WITH ISL 6258 (PM_SLP_S3_L DIRECTLY CONNECTS TO ISL 6258 PIN) - PAGE 94: STUFFED C9485 AND CHANGED IT TO 22UF (APN 138S0654),CHANGED C9400 & C9481 TO 4.7UF (APN 138S0618) & CHANGED C9480 TO 22UF (APN 138S0654): TO FIX B4 DONGLE ISSUE ***PAGES SYNCED FROM CASEY HARDY?S AUDIO_MLB SINCE LAST RELEASE 14.0.0*** - ADDED R6862 PULL-UP RESISTOR TO PERPH. DETECT CKT.
08/31/2009: RELEASE 16.1.0 (MAJOR)- PAGE 4: REMOVED 138S0606 FROM THE ALTERNATES TABLE AS IT DOESN’T PERTAIN TO K84 - PAGE 4: REPLACED CPU APN 337S3704 WITH 337S3769 IN MODULE PARTS TABLE AND REMOVED 337S3704 FROM THE ALTERNATE PART TABLE AS POR IS 337S3769 (P7550) - PAGE 4: REMOVE 870-1794, 870-1698 & 870-1820 FROM THE ALTERNATES TABLE AS POR IS LOW NOISE POGO PINS - PAGE 4: ADDED LOW NOISE POGO APNS 870-1885 (IN PLACE OF 870-1794), 870-1886 (IN PLACE OF 870-1698) & 870-1887 (IN PLACE OF 870-1820) IN MODULE PARTS TABLE - PAGE 4: ADDED NEW INTERSIL ISL6258A (WITH IMPROVED CHARGE CURRENT ACCURACY LIMITS) APN 353S2811 AS AN ALTERNATE FOR APN 353S1832 - PAGE 4: REMOVED 998S APN FROM THE ALTERNATES TABLE PERTAINING TO I/O CONNECTORS AS THEY ARE NO LONGER POR FOR DVT - PAGE 4: REMOVED 514-0706, 514-0705 AND 514-0718 FROM THE ALTERNATES TABLE AND ADDED TO MODULE PARTS TABLE AS THEY ARE NOW POR I/O CONNECTORS - PAGE 9: ADDED OMIT BOM OPTION ON ALL THE POGO PINS - PAGE 46: ADDED OMIT BOM OPTIONS TO J4600 & J4610 USB CONNECTORS - PAGE 67: ADDED OMIT BOM OPTION TO J6700 AUDIO CONNECTOR - PAGE 94: ADDED OMIT BOM OPTION TO J9400 MINI DP CONNECTOR - PAGE 97: UPDATED SCHEMATIC NOTE RELATED TO TARGET AND ACTUAL ISET & OVP NUMBERS AS PER KIRAN’S EMAIL
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09/16/2009: RELEASE 17.0.0 (FAB)- FINAL DVT OK2FAB RELEASE 09/21/2009: RELEASE A.0.0 (FAB)- FINAL PVT OK2FAB RELEASE - PAGE 4: ADDED APN 104S0033 (6.8 OHMS, 1/4W) RESISTORS IN MODULE PARTS TABLE FOR R6612, R6617, R6630 & R6633 ADDED APN 518S0774 FOR XDP CONNECTOR J1300 (TO REPLACE 998-2515) - PAGE 13: ADDED OMIT TO J1300 - PAGE 50: CHANGED R5030 SIL RESISTOR TO 80.6 OHMS APN 114S0112 AS PER ID - PAGE 53: REPLACED APN 376S0545 WITH 376S0820 @ Q5315 - PER ECO#0000737172 - PAGE 66: ADDED BOMOPTION OMIT TO RESISTORS R6612, R6617, R6630 & R6633 10/12/2009: RELEASE B.0.0 (FAB)- PROD_DEBUG (POST FIRST 5K UNTIL 1 MONTH INTO PRODUCTION) OK2FAB RELEASE - PAGE 4: ADDED 1 NEW POR BOMS 639-0554, 639-0555 AND 1 NEW DEVELOPEMENT BOM 085-1076 FOR INITIAL RAMP - PAGE 4: UPDATED BOM GROUPS TABLE TO REFLECT AFOREMENTIONED CHANGES. NEW DEVELOPMENT BOM ONLY HAS XDP CONNECTOR AND LPCPLUS COMPONENTS - PAGE 4: ADDED 2 NEW EEES TO ATTACH WITH AFOREMENTIONED NEW 639 BOMS - PAGE 4: DELETED 353S2811 ENTRY FROM THE ALTERNATES TABLE - PAGE 70: REPLACED U7000 WITH THE NEW INTERSIL SCREENED PARTS APN 353S2811 11/01/2009: RELEASE C.0.0 (FAB)- PROD (POST 1ST MONTH OF PRODUCTION) OK2FAB RELEASE - PAGE 2: UPDATED SYSTEM BLOCK DIAGRAM - PAGE 3: UPDATED POWER SYSTEM BLOCK DIAGRAM - PAGE 4: UPDATED BOM TABLES TO NOT INCLUDE ANY 085 DEVELOPMENT BOMS. AND, K84_DEBUG_PROD BOM GROUP IS TURNED ON
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06/10/2009: RELEASE 14.2.0 (MAJOR)- PAGE 4: ADDED APN 138S0661 LOW NOISE MURATA CAPS AS ALTERNATE FOR C9715 & C9716 TO FIX LCD BKLT AUDIBLE NOISE ISSUE - PAGE 49: ADDED 0.1UF CAPS ON SMS_X_AXIS, SMS_Y_AXIS & SMS_Z_AXIS NETS TO FIX NOISE ISSUE - PAGE 77: CHANGED R7780 TO 25.5K APN 114S0354 & R7781 TO 80.6K APN 114S0402 AS PER DAYU 06/11/2009: RELEASE 14.3.0 (MAJOR)- PAGE 77: ADDED 0 OHMS BOM OPTIONS R7782 BETWEEN PIN 4 OF U7750 (SKIP PIN) AND POWER RAIL AND R7783 BETWEEN PIN 4 AND GND. R7782 WILL BE NOSTUFF FOR NOW. THIS IS AS PER DAYU TO FIX ETHERNET JITTER ISSUE 06/11/2009: RELEASE 14.4.0 (MAJOR)- PAGE 49: REPLACED C4950-C4952 WITH 1UF APN 138S0640 CAPS - PAGE 78: DISCONNECTED P1V05_S5_PGOOD FROM PIN 3 OF U7840 AND CONNECTED IT TO PIN 1 (RSMRST_PWRGD) TO FIX LEAKAGE ISSUE
06/22/2009: RELEASE 14.6.0 (MAJOR)- PAGE 4: ADDED CPU APN 337S3769 AS ALTERNATE TO 337S3704 - PAGE 9: ADDED NOSTUFF BOM OPTION TO ZS0920 - PAGE 50: CHANGED R5030 TO 48.7 OHMS APN 114S0091 (SIL CURRENT TO 12MA) - PAGE 57: CHANGED R5714 TO 113 OHMS APN 114S0125 (KB LED CURRENT TO 8.5MA) - PAGE 97: ADDED CRITICAL ATTRIBUTE TO C9715 & C9716 - PAGE 97: CHANGED R9710 TO 7.68K APN 114S0304 (LCD BKLT CURRENT TO 20MA) 06/25/2009: RELEASE 14.7.0 (MAJOR)- PAGE 70: DELETED OMIT BOM OPTION FROM U7000 AS ISL6259 HAVE BEEN REMOVED 07/17/2009: AGILE EVT OK2FAB RELEASE 15.0.0 (FAB)- NO CHANGES SINCE LAST MAJOR 14.7.0. THIS IS FINAL EVT FAB RELEASE 07/21/2009: RELEASE 15.1.0 (MAJOR)- PAGE 4: DELETED MIKEY_LOAD_DET BOM OPTION FROM THE TABLE UNDER K84_MISC CATEGORY AS PER CASEY - PAGE 4: UPDATED ALTERNATES FOR MINI DP AND USB CONNECTORS WITH PG2 PLASTIC CONNECTORS- APN 514-0706 (MDP) & 514-0705 (USB). AND, UPDATED NOTE BELOW THE ALTERNATES PARTS TABLE ACCORDINGLY - PAGE 4: ADDED PG2 CONNECTOR APN 514-0704 IN THE MODULE PARTS TABLE FOR RJ45 J3900 CONNECTOR - PAGE 4: DELETED 353S2310 PART FROM THE ALTERNATES BOM TABLE AS ALL PRODUCTION HAS NOW MOVED TO ITS ALTERNATE PART 353S2718 - PAGE 4: ADDED NEW INTERSIL PART APN 353S2718 IN THE MODULE PARTS TABLE FOR U7870 TO FIX B4 DONGLE ISSUE - PAGE 21: DELETED NOSTUFF BOM ATTRIBUTE FROM R2143 AS MIKEY_LOAD_DET CIRCUIT HAS BEEN REMOVED. SO R2143 NEEDS TO BE STUFFED NOW - PAGE 39: ADDED BOMOPTION ATTRIBUTE OMIT TO J3900 AS NEW PG2 CONNECTOR PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE - PAGE 78: ADDED BOMOPTION ATTRIBUTE OMIT TO U7870 AS NEW INTERSIL PART PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE
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07/27/2009: RELEASE 15.2.0 (MAJOR)- PAGE 4: DELETED LOW NOISE MURRATA CAP ENTRY FROM THE ALTERNATES TABLE - PAGE 49: CHANGED SMS NOISE FILTERING CAPS C4950-C4952 TO 0.47UF APN 132S0178 TO FIX THE SMART TEST FAILURE - PAGE 70: DISCONNECTED PM_SLP_S3_L FROM PIN 4 (VREF) AS IT WAS INCORRECTLY CONNECTED, THEREBY CAUSING HIGHER SLEEP/SHUTDOWN POWER - PAGE 97: NOSTUFFED C9716 AND CHANGED C9715 TO APN 138S0661 AS POR IS TO HAVE SINGLE CAP LOW NOISE MURRATA CAP SOLUTION AS PER ACOUSTICS ENGINEER 08/05/2009: RELEASE 15.3.0 (MAJOR)- PAGE 4: ADDED APN 138S0606 (TAIYO-YUDEN) AS AN ALTERNATE FOR APN 138S0602 - PAGE 4: ADDED PDNI PLATED AUDIO CONNECTOR W/ CHAMFER APN 514-0718 AS AN ALTERNATE FOR J6700 APN 514-0694 - PAGE 4: ADDED GOLD PLATED AUDIO CONNECTOR W/O CHAMFER APN 998-2622 AS AN ALTERNATE FOR J6700 APN 514-0694 - PAGE 4: ADDED GOLD PLATED RJ45 CONNECTOR APN 998-2621 AS AN ALTERNATE FOR J3900 APN 514-0704 - PAGE 4: ADDED GOLD PLATED MINI DP CONNECTOR APN 998-2626 AS AN ALTERNATE FOR J9400 APN 514-0691 - PAGE 4: ADDED GOLD PLATED USB CONNECTOR APN 998-2624 AS AN ALTERNATE FOR J4600/J4610 APN 514-0689 - PAGE 4: ADDED LOW NOISE POGO PINS 870-1885 (MEDIUM), 870-1886 (TALL), AND 870-1887 (THIN) AS ALTERNATES - PAGE 49: CHANGED C4950, C4951, C4952 TO APN:132S0131 (CAP,0402,0.033UF, 16V,10%) AS THESE WOULD BE USED TO ACHIEVE CUT-OFF FREQUENCY OF ~146HZ FOR SMS (AS PER THE VENDOR) AND FILTER THE NOISE TOO AS SEEN BY SMC CHIP. CAPS ON SMS PAGE WOULD BE UNSTUFFED - PAGE 59: ADDED NOSTUFF BOM OPTION ATTRIBUTE TO C5923-C5925 AS STATED ABOVE. ALSO, EDITED THE NOTE ACCORDINGLY - PAGE 70: CHANGED R7031 FROM 10 OHM TO 2.2 OHM, 5%, APN:116S0010 TO FIX SLOW CHARGING ISSUE, PER DAYU - PAGE 70: CHANGED R7047 FROM 10 OHM TO 0 OHM, 5%, APN:116S0004 TO FIX SLOW CHARGING ISSUE, PER DAYU - PAGE 70: CHANGED C7043 FROM 0.1UF TO 1UF, 10%, APN:138S0640 TO FIX SLOW CHARGING ISSUE, PER DAYU
SYNC_MASTER=K24_MLB
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Revision History
08/27/2009: AGILE PDFC OK2FAB RELEASE 16.0.0 (FAB)- FINAL PDFC (PRE DVT) RELEASE! - PAGE 97: REFRESHED THE SYMBOL OF C9715 4.7UF APN 138S0661
DRAWING NUMBER
Apple Inc. NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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05/05/2009: RELEASE 12.11.0 (MAJOR & WEEKLY ECO): - PAGE 4: ADDED 4 QUANTITIES OF DIMM CONNECTOR SCREWS APN 452-1708 - PAGE 46: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS THOUGH POR IS PLASTIC USB CONNECTOR PART - PAGE 94: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS THOUGH POR IS PLASTIC MINI DP CONNECTOR PART
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SYNC_DATE=01/19/2009
PAGE TITLE
05/04/2009: RELEASE 12.10.0 (MAJOR): - PAGE 4: REMOVED SHORT POGO PIN ALTERNATE - PAGE 4: REVERTING MCP TO EARLIER USE APN 338S0710 - PAGE 60: CHANGED U6050 INA 211 PART TO 200X GAIN INA 210 APN 353S2073
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06/12/2009: RELEASE 14.5.0 (MAJOR)- PAGE 9: ADDED ONE MORE EXTRA TALL POGO PIN AS PER EMC RECOMMENDATION : ZS0920 - PAGE 78: ADDED 0 OHM BOM OPTION R7895 BETWEEN 1V05_S5_PGOOD AND RSMRST_PWRGD FOR DEBUG PURPOSES
4/7/2009 - RELEASE 12.0.0 OK2FAB (RFA): - NO CHANGE SINCE LAST RFA RELEASE 11.0.0. ***THIS IS A RESUBMIT AS PREVIOUS RFA DIDNT GO THROUGH***
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BRANCH
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Functional Test Points
X16 WIRELESS CONN
FAN CONNECTORS FUNC_TEST
D
I12 I15 I16
TRUE TRUE TRUE
PP5VRT_S0 FAN_RT_PWM FAN_RT_TACH
7 8
I303
43
I301
43
I302
(NEED TO ADD 1 GND TP)
I300 I299
MIC FUNC_TEST I238 I237 I239
TRUE TRUE TRUE
I298 I293
BI_MIC_LO BI_MIC_HI BI_MIC_SHIELD
53 54 I288
53 54 I292
53 54 I295
I227 I226 I228 I230 I229 I231
I290
SPEAKER FUNC_TEST SPKRAMP_L_N_OUT TRUE SPKRAMP_L_P_OUT TRUE SPKRAMP_R_N_OUT TRUE SPKRAMP_R_P_OUT TRUE SPKRAMP_SUB_N_OUT TRUE SPKRAMP_SUB_P_OUT TRUE
I271
52 53
I289
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
POWER NETS
FUNC_TEST
PP3V3_S3_BT_F 30 CONN_PCIE_MINI_D2R_P 30 72 CONN_PCIE_MINI_D2R_N 30 72 CONN_PCIE_MINI_R2D_P 30 72 CONN_PCIE_MINI_R2D_N 30 72 PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N PP3V3_WLAN 7 30 (NEED PCIE_WAKE_L 17 30 CONN_USB2_BT_P 30 73 CONN_USB2_BT_N 30 73 MINI_CLKREQ_Q_L 30 MINI_RESET_CONN_L 30
I287 I285 I284 I280 I281
30 72 I282
30 72 I376
2 TP) I396 I283 I279 I278 I270
(NEED TO ADD 2 GND TP)
I379
52 53 I273
52 53 I274
52 53 I275
52 53 I276
52 53 I272 I393
IPD_FLEX_CONN I375 I374
I259 I258
C
I260 I245 I262 I261 I256 I257 I255 I252 I253 I254 I250 I251 I313 I246 I247 I248 I249 I395
I297 I294
LVDS FUNC_TEST PP3V3_LCDVDD_SW_F PP3V3_S0_LCD_F PPVOUT_S0_LCDBKLT LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 PP5V_S3_CAMERA_F USB_CAMERA_CONN_P USB_CAMERA_CONN_N
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
I372 I370
(NEED 2 TP)
7 65 65
I371 I369
7 47 65 68
(NEED 2 TP)
I368
18 65
I361
18 65
I366
18 65 72
I365
18 65 72
I363
18 65 72
I364
18 65 72
I362
18 65 72
I360
18 65 72
I359
65 72
I357
65 72
I358
65 68
I377
65 68
I378
B
I268 I269 I267 I265 I266
KEYBOARD CONN
7 65 I354
65 73
I355
65 73
I344
I349
(NEED 2 TP)
I348
7 34 47 I350
34 36 34 72 34 72
I352 I351 I353
34 72 I327
34 72 I328
I343
FUNC_TEST
I342
I314 I315 I318 I317 I307
TRUE TRUE TRUE TRUE TRUE TRUE
I388 I387
44 45
I386
44 45 I385
44 45 I383
45
I382
44 45
I381
44 45 I380
44 45
I397
44 45 44 45
D
8 8 8 8 8 8 8 7 8 8 8 7 8 8 8 8 7 8 8 8 8 21 22 25 7 30 7 34 47 7 34 36 37 7 45 7 45 7 65 7 47 65 68
C
49 36 57 63 21 36 37 63 21 32 36 63 67 7 65
(NEED TO ADD 1 GND TP)
44 45 44 45 39 75 39 75 44 45
DC POWER CONN
FUNC_TEST
44 45
TRUE TRUE
PP18V5_DCIN_FUSE ADAPTER_SENSE
(NEED 2 TP) 55 55
FUNC_TEST
65 68
I329
I319
44 45 44 45
PPVCORE_S0_CPU PPVCORE_S0_MCP PP0V75_S0 PP1V05_S0 PP1V5_S0 PP1V8_S0 PP5VLT_S0 PP5VRT_S0 PP3V3_S0 PP1V5_S3 PP3V3_S3 PP5V_S3 PP1V1R1V05_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET_PHY PP1V2R1V05_ENET PP3V3_G3_RTC PP3V3_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP3V3_S5_AVREF_SMC PP18V5_S3 PP3V3_S3_LDO PP3V3_LCDVDD_SW_F PPVOUT_S0_LCDBKLT PP4V5_AUDIO_ANALOG SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L PP5V_S3_CAMERA_F
(NEED TO ADD 2 GND TP) 65 68
FUNC_TEST
PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SYS_LED_ANODE_R
I389
I304
(NEED TO ADD 2 GND TP)
SATA HDD/SIL
I390
7 45
65 68
I345
PP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N
I391
7 45
I312
I347
TRUE TRUE TRUE TRUE TRUE TRUE
PP3V3_S3_LDO PP18V5_S3 Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL PSOC_F_CS_L PICKB_L
(NEED TO ADD 2 GND TP)
I346
I264
I392
65 68
(NEED TO ADD 5 GND TP)
SATA ODD CONN
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
FUNC_TEST
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
FUNC_TEST
(NEED 2 TP) I341
7 34 34 72 34 72
I339 I340 I338
34 72 I336
34 72 34
I337 I333
(NEED TO ADD 3 GND TP) I335 I334 I332 I330 I331
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD
7 8 7 8 44 44 44 44 44 44 44
B
44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44
(NEED TO ADD 1 GND TP)
BATT POWER CONN I322 I321 I320
A
I305
TRUE TRUE TRUE TRUE
FUNC_TEST
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SYS_DETECT_L BATT_POS_F
39 75 39 75 55 55 56
SYNC_MASTER=K24_MLB
(NEED 2 TP) (NEED TO ADD 2 GND TP)
SYNC_DATE=02/04/2009
A
PAGE TITLE
FUNC TEST HALL EFFECT CONNECTOR I326 I308
TRUE TRUE
PP3V42_G3H SMC_LID_R
DRAWING NUMBER
FUNC_TEST
Apple Inc.
7 8
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
55
SIZE
051-7982 BRANCH
PAGE
7 OF 109 SHEET
OF
8
7
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3
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4
"S0,S0M" RAILS =PPVCORE_S0_CPU_REG
64
PPVCORE_S0_CPU
=PP5VRT_S0_FET
PP5VRT_S0
=PPVCORE_S0_CPU =PPVCORE_S0_CPU_VSENSE
11 12 40
D
=PP5V_S0_CPUVTTS0
61
=PP5V_S0_LPCPLUS
38
=PP5V_S0_FAN_RT
43
=PP5V_S0_CPU_IMVP
61
=PPCPUVTT_S0_REG
64
PP1V05_S0
=PP5VLT_S0_FET
=PP1V05_S0_CPU
10 11 12 13
=PP1V05_S0_MCP_FSB
14 22 23
23
=PP1V05_S0_MCP_SATA_DVDD
8 23
=PP1V05_S0_MCP_HDMI_VDD
18 24
=PP1V05_S0_MCP_PLL_UF_R
60
=PPMCPCORE_S0_REG
7
=PP3V3_S0_FET
62
7
22 23
7
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE
64
=PP1V5_S0_FET
=PP3V42_G3H_SMBUS_SMC_BSA
=PP1V5_S3_MEM_B
28
=PP3V42_G3H_PWRCTL
=PP1V5_S3_MEMRESET
29
PP3V3_S3
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V42_G3H_RTC_D
25
58
=PP3V42_G3H_ONEWIRE
55
=PP3V42_G3H_HALL
55
26
=PP3V3_S3_WLAN
30 21
=PP3V3_S3_TPAD
44
=PP3V3_S3_SMS
46
=PP3V3_S3_BT
30
PP5V_S3
7
55
=PP18V5_DCIN_CONN
PP18V5_G3H MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V MAKE_BASE=TRUE
13 21 22 23 24 24
57
=PP3V3_S0_ODD
34
=PP3V3_S0_SMBUS_SMC_0_S0
39
=PP3V3_S0_SMBUS_SMC_B_S0
39
=PP3V3_S0_SMBUS_MCP_0
39
=PP3V3_S0_FAN_RT
43
=PP3V3_S0_AUDIO
49 53 54
=PP3V3_S0_IMVP
59
=PP5V_S3_REG
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE
65
56
=PP5V_S3_EXTUSB
35
=PP5V_S3_CAMERA
65
=PP5V_S3_AUDIO_AMP
52
=PP5V_S3_MCPDDRFET
64
=PP5V_S3_1V5S30V75S0
58
=PP5V_S3_AUDIO
49 51 53
=PP5V_S3_P5VLTS0FET
64
=PP5V_S3_VTTCLAMP
64
=PP5V_S3_DEBUG_ISNS
47
=PP5V_S3_SYSLED
37
=PP5V_S3_TPAD
45
=PP5V_S3_ODD
34
=PP5V_S3_DEBUG_ADC_AVDD
47
=PP5V_S3_DEBUG_ADC_DVDD
47
=PP5V_S3_P5VRTS0FET
64
=PPBUS_G3H
=PP18V5_G3H_CHGR
56
PPBUS_G3H
7
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE
=PPVIN_S0_MCPCORE
=PP3V3_S0_MCP_PLL_UF
23
=PP3V3R1V5_S0_MCP_HDA
21 23 37
=PP3V3_S0_MCPTHMSNS
42
=PP3V3_S0_CPUTHMSNS
42
=PP0V75_S0_MEM_VTT_A
27
=PP3V3_S0_DPCONN
67
=PPSPD_S0_MEM_A
27
=PPSPD_S0_MEM_B
28
=PP3V3_S0_PWRCTL
63
=PP3V3_S0_VMON
63
=PP3V3_S0_CPUVTTISNS
41
=PP3V3_S0_SMBUS_MCP_1
39
=PP1V5_S0_CPU
11 12
=PP1V5_S0_VMON
63
=PP3V3_S0_P1V8S0
62
=PP3V3_S0_MCP_PLL_VLDO
62
=PP3V3_S0_MCPDDRISNS
=PP1V8R1V5_S0_MCP_MEM
16 23
=PP1V5_S0_MEM_MCP
28
41
=PP1V5_S0_MCP_PLL_VLDO
62
58 26
=PPVTT_S3_DDR_BUF
C
PP1V8_S0
=PP1V05_S0_MCP_PLL_UF
57
=PPVIN_S3_5VS3 =PPBUS_G3HRS5
41
=PPCPUVCORE_VTT_ISNS
57 40
PPBUS_G3H_CPU_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE
& CPU VTT SENSING RES.)
7
"S5" RAILS
=PP3V3R1V8_S0_MCP_IFP_VDD
18 24
=PP1V8_S0_AUDIO
49
"ENET" RAILS 32
62 23
69
PPVTT_S3_DDR_BUF MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=1.8V MAKE_BASE=TRUE
B
41
=PPBUS_S0_LCDBKLT =PPVIN_S5_3V3S5
(AFTER HIGH SIDE CPU VCORE =PP1V8_S0_REG
58
(BEFORE HIGH SIDE SENSING RES.)
7
MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V MAKE_BASE=TRUE
62
60
=PPVIN_S5_1V5S30V75S0 =PPCPUVCORE_VTT_ISNS_R
18 19 21
=PP3V3_S0_SMC
28
39
39
=PP3V3_S0_MCP_VPLL_UF
44
38
=PP3V3_S3_VREFMRGN
D
35
=PP3V42_G3H_TPAD
36 37
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S0_MCP_DAC_UF
63
=PP3V3_S5_LPCPLUS
63
=PP3V3_S0_MCP
39
56
=PP3V3_S5_SMC
60
=PP3V3_S3_PDCISENS
37
=PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX
7
=PP5V_S0_VMON
64
PP1V5_S0
=PPVIN_S5_SMCVREF
27
=PP5V_S0_MCPREG
=PPVTT_S0_VTTCLAMP =PP0V75_S0_MEM_VTT_B
64
34
7
7
=PP1V5_S3_MEM_A
66
=PP3V3_S0_MCP_GPIO
C
PP3V42_G3H
=PP1V5_S3_P1V5S0FET
=PP5V_S0_HDD
=PP3V3_S0_LCD
40
=PP3V42_G3H_REG
55
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE
=PP5V_S0_DP_AUX_MUX
=PP3V3_S0_XDP
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
PP0V75_S0
7
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_S0
63
=PPVCORE_S0_MCP_VSENSE
=PP0V75_S0_REG
=PP3V3_S3_FET
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE
=PPVCORE_S0_MCP
58
PP1V5_S3
=PP3V3_S3_MCP_GPIO 64
PPVCORE_S0_MCP
(MCP VCORE AFTER SENSE RES)
64
8 23
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_VMON
"G3H" RAILS
MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE
7
1
59
PP5VLT_S0
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
=PP1V05_S0_MCP_PEX_DVDD
=PP1V5_S3_REG
7
MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE
7
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=1.25V MAKE_BASE=TRUE
(CPU VCORE PWR)
2
"S3" RAILS 58
59
3
=PP3V3_ENET_FET
62
PP3V3_ENET_PHY
=PP1V05_S5_REG
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
=PP3V3_ENET_MCP_RMGT
18 23
=PP3V3_ENET_PHY
31
61
=PPVIN_S5_CPU_IMVP
59
B
7
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
7
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE
PP1V05_S0_MCP_PLL_UF
PP1V1R1V05_S5
=PPVIN_S0_CPUVTTS0
=PP1V05_S5_MCP_VDD_AUXC
22 23
=PP1V05_ENET_P1V05ENETFET
32
DIGITAL GROUND GND 32
=PP1V05_ENET_FET
PP1V2R1V05_ENET
7
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
57
=PP1V05_ENET_MCP_PLL_MAC
=PP3V3_S5_REG
PP3V3_S5
7
23
=PP3V3_S5_MCP_GPIO =PP1V05_ENET_MCP_RMGT =PP1V05_ENET_PHY
18 23
18 20
=PP3V3_S5_ROM
38 48
=PP3V3_S5_LCD
65
=PP3V3_S5_MCP
22 23
31
=PP3V3_S5_MCPPWRGD
PEX & SATA AVDD/DVDD aliases 23
PP1V05_S0_MCP_PEX_AVDD
=PP1V05_S0_MCP_PEX_AVDD0
17
=PP1V05_S0_MCP_PEX_AVDD1
17
=PP1V05_S0_MCP_PEX_DVDD0
17
=PP1V05_S0_MCP_PEX_DVDD1
17
=PP1V05_S0_MCP_SATA_AVDD0
20
206 mA (A01)
MAKE_BASE=TRUE
206 mA (A01)
A
23 8
=PP1V05_S0_MCP_PEX_DVDD
57 mA (A01)
25
=PP3V3_S5_PWRCTL
63
=PP3V3_S5_P1V05ENETFET
32
=PP3V3_S5_P3V3S3FET
64
=PP3V3_S5_P3V3S0FET
64
=PP3V3_S5_P1V05S5
62
=PP3V3_S5_MEMRESET
29
=PP3V3_S5_P3V3ENETFET
32
=PP3V3_S5_DP_PORT_PWR
67
206 mA (A01) 23
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=0V
MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE
SYNC_MASTER=K24_MLB
PP1V05_S0_MCP_SATA_AVDD
=PP1V05_S0_MCP_SATA_AVDD1
20
=PP1V05_S0_MCP_SATA_DVDD0
20
SYNC_DATE=02/04/2009
Power Aliases
127 mA (A01)
DRAWING NUMBER 23 8
=PP1V05_S0_MCP_SATA_DVDD 127 mA (A01)
Apple Inc.
43 mA (A01)
=PP1V05_S0_MCP_SATA_DVDD1
A
PAGE TITLE 127 mA (A01)
MAKE_BASE=TRUE
20
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
051-7982 BRANCH
PAGE
8 OF 109 SHEET
OF
8
7
6
5
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7
6
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4
3
PCI-E ALIASES
DACS ALIASES
UNUSED GPU LANES
HEATSINK STANDOFFS
17
NC_PEG_D2R_N
Z0901
STDOFF-4.5OD.98H-1.1-3.48-TH
=PEG_D2R_P
NC_PEG_D2R_P
17
=PEG_R2D_C_N
NC_PEG_R2D_C_N
NO_TEST=TRUE
1
1
NO_TEST=TRUE
ABOVE CPU
NC_PEG_R2D_C_P
17
PEG_PRSNT_L
TP_PEG_PRSNT_L
17
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
18
MCP_CLK27M_XTALIN
18
MCP_CLK27M_XTALOUT
NC_MCP_CLK27M_XTALOUT
18
CRT_IG_R_C_PR
NC_CRT_IG_R_C_PR
NO_TEST=TRUE
NO_TEST=TRUE
CRT_IG_G_Y_Y
TP_PEG_CLK100M_N MAKE_BASE=TRUE
18
CRT_IG_B_COMP_PB
NC_CRT_IG_B_COMP_PB
18
CRT_IG_HSYNC
NC_CRT_IG_HSYNC
NO_TEST=TRUE
UNUSED EXPRESS CARD LANE
NO_TEST=TRUE
17
PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_D2R_P
17
PCIE_EXCARD_D2R_N
TP_PCIE_EXCARD_D2R_N
18
CRT_IG_VSYNC
TP_MEM_A_A15
28
MEM_B_A
TP_MEM_B_A15
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ETHERNET ALIASES MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
32
=P3V3ENET_EN
32
=P1V05ENET_EN
PM_SLP_RMGT_L
31
=PP3V3_ENET_PHY_VDDREG
RTL8211_VDDREG
MAKE_BASE=TRUE
31
=RTL8211_REGOUT
NC_RTL8211_REGOUT
31
=RTL8211_ENSWREG
D
21
MAKE_BASE=TRUE
NC_CRT_IG_VSYNC
MAKE_BASE=TRUE
BELOW CPU
BELOW MCP
MEM_A_A
NC_CRT_IG_G_Y_Y NO_TEST=TRUE
1 1
27
NC_MCP_CLK27M_XTALIN
MAKE_BASE=TRUE
18
MAKE_BASE=TRUE
NC_MCP_TV_DAC_VREF
MAKE_BASE=TRUE
TP_PEG_CLK100M_P
PEG_CLK100M_N
MCP_TV_DAC_VREF
NO_TEST=TRUE
MAKE_BASE=TRUE
Z0904
Z0903
D
PEG_CLK100M_P
UNUSED ADDRESS PINS
NC_MCP_TV_DAC_RSET
NO_TEST=TRUE
MAKE_BASE=TRUE
=PEG_R2D_C_P
17
18
MAKE_BASE=TRUE
17
NO_TEST=TRUE
LEFT OF CPU
MCP_TV_DAC_RSET
NO_TEST=TRUE
17
STDOFF-4.5OD.98H-1.1-3.48-TH
18
MAKE_BASE=TRUE
1
SO-DIMM ALIASES
UNUSED CRT & TV-OUT INTERFACE
=PEG_D2R_N
NO_TEST=TRUE
Z0902
2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FAN STANDOFF
17
PCIE_EXCARD_R2D_C_P
TP_PCIE_EXCARD_R2D_C_P
17
PCIE_EXCARD_R2D_C_N
TP_PCIE_EXCARD_R2D_C_N
17
PCIE_EXCARD_PRSNT_L
TP_PCIE_EXCARD_PRSNT_L
31
1
18
18
17
TP_EXCARD_CLKREQ_L
17
PCIE_CLK100M_EXCARD_P
TP_PCIE_CLK100M_EXCARD_P
17
PCIE_CLK100M_EXCARD_N
TP_PCIE_CLK100M_EXCARD_N
LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N
NC_LVDS_IG_A_DATA_N3
18
LVDS_IG_B_CLK_P
NC_LVDS_IG_B_CLK_P
18
LVDS_IG_B_CLK_N
NC_LVDS_IG_B_CLK_N
OMIT
OMIT
72 17
Z0907
Z0906
3P2R2P7
3P2R2P7
72 17
PCIE_FW_D2R_P
LVDS_IG_B_DATA_P
NC_LVDS_IG_B_DATA_P
18
LVDS_IG_B_DATA_N
NC_LVDS_IG_B_DATA_N
NO_TEST=TRUE
TP_PCIE_FW_D2R_P
NO_TEST=TRUE
MAKE_BASE=TRUE
CPU FSB FREQUENCY STRAPS MAKE_BASE=TRUE
MAKE_BASE=TRUE
BSEL
MAKE_BASE=TRUE
0 0 0 0 1 1 1 1
PCIE_FW_R2D_C_P
TP_PCIE_FW_R2D_C_P
70 10
MISC MCP79 ALIASES
MAKE_BASE=TRUE
72 17
PCIE_FW_R2D_C_N
TP_PCIE_FW_R2D_C_N
17
PCIE_FW_PRSNT_L
TP_PCIE_FW_PRSNT_L
IN
CPU_BSEL MAKE_BASE=TRUE
=MCP_BSEL
OUT
14
MAKE_BASE=TRUE
17
FW_CLKREQ_L
TP_FW_CLKREQ_L
17
PCIE_CLK100M_FW_P
TP_PCIE_CLK100M_FW_P
17
PCIE_CLK100M_FW_N
TP_PCIE_CLK100M_FW_N
14
CPU_PECI_MCP
TP_CPU_PECI_MCP
19
FW_PME_L
TP_FW_PME_L
17
GMUX_JTAG_TCK_L
TP_GMUX_JTAG_TCK_L
17
GMUX_JTAG_TDO
TP_GMUX_JTAG_TDO
19
GMUX_JTAG_TDI
TP_GMUX_JTAG_TDI
19
GMUX_JTAG_TMS
TP_GMUX_JTAG_TMS
21
MCP_GPIO_4
MIKEY_MIC_LOAD_DET
17
CARDREADER_RESET
TP_CARDREADER_RESET
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
266 133 200 (166) 333 100 (400) (RSVD)
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
C
FSB MHZ
TP_PCIE_FW_D2R_N
PCIE_FW_D2R_N
1
1
5% 1/16W MF-LF 402
MAKE_BASE=TRUE
18
UNUSED FIREWIRE LANE
2
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
72 17
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MLB MOUNTING (TO C. BRACKET) SCREW HOLES
MAKE_BASE=TRUE
NO_TEST=TRUE MAKE_BASE=TRUE
R0931 22
NC_LVDS_IG_A_DATA_P3 NO_TEST=TRUE
MAKE_BASE=TRUE
EXCARD_CLKREQ_L
MAKE_BASE=TRUE
1
MAKE_BASE=TRUE
3P2R2P7
RTL8211_CLK125
LVDS ALIASES
MAKE_BASE=TRUE
OMIT
Z0905
TP_RTL8211_CLK125
C
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
LVDS CONNECTOR HOLE
20
USB_EXTD_P
TP_USB_EXTD_P
20
USB_EXTD_N
TP_USB_EXTD_N
20
USB_EXCARD_P
20
TP_USB_EXCARD_P
USB_EXCARD_N
TP_USB_EXCARD_N
MAKE_BASE=TRUE MAKE_BASE=TRUE
18
=MCP_MII_RXER
18
=MCP_MII_COL
18
=MCP_MII_CRS
MCP_MII_PD MAKE_BASE=TRUE
1
USB_MINI_P
TP_USB_MINI_P
2
MAKE_BASE=TRUE
20
OMIT
USB_MINI_N
20
USB_EXTC_P
TP_USB_EXTC_P
20
USB_EXTC_N
TP_USB_EXTC_N
73 20
USB_CARDREADER_P
TP_USB_CARDREADER_P
73 20
USB_CARDREADER_N
TP_USB_CARDREADER_N
73 20
USB_IR_N
TP_USB_IR_N
73 20
USB_IR_P
TP_USB_IR_P
3P2R2P7 1
59
SM
TP_IMVP6_NTC MAKE_BASE=TRUE
18
MAKE_BASE=TRUE
=DVI_HPD_GMUX_INT
HPLUG_DET2 MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
MAKE_BASE=TRUE
R0940 20K
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
OMIT
ZS0902 2.0DIA-MED-EMI-MLB-K84
ZS0903 2.0DIA-MED-EMI-MLB-K84
SM
1
IMVP6_NTC
MAKE_BASE=TRUE
2
SM
1
TP_IMVP6_VR_TT MAKE_BASE=TRUE
59
EMI IO MEDIUM POGO PINS (870-1794 ) OMIT
IMVP6_VR_TT
DP HOTPLUG PULL-DOWN
MAKE_BASE=TRUE
OMIT
CPU VCORE ALIASES
5% 1/16W MF-LF 402
TP_USB_MINI_N MAKE_BASE=TRUE
Z0913
R0930 47K
MAKE_BASE=TRUE MAKE_BASE=TRUE
20
ZS0901 2.0DIA-MED-EMI-MLB-K84
TP_SMC_SYS_KBDLED MAKE_BASE=TRUE
1
OMIT
SMC_SYS_KBDLED
LAN ALIASES
UNUSED USB PORTS
1
ZS0900 2.0DIA-MED-EMI-MLB-K84
36
USB ALIASES
Z0910 3P2R2P7
3P2R2P7
54 MAKE_BASE=TRUE
OMIT
OMIT
Z0911
SMC ALIASES
MAKE_BASE=TRUE
MLB MOUNTING (TO TOPCASE) SCREW HOLES
SM
1
1
B
B OMIT
OMIT
ZS0908 2.0DIA-MED-EMI-MLB-K84
ZS0909 2.0DIA-MED-EMI-MLB-K84
SM
OMIT
ZS0911 2.0DIA-MED-EMI-MLB-K84
SM
1
SM
1
1
EMI TALL POGO PINS (870-1698 ) OMIT ZS0904
OMIT ZS0905
OMIT ZS0906
OMIT ZS0907
OMIT ZS0910
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
SM
SM
1
SM
1
SM
1
SM
1
1
OMIT ZS0912
OMIT ZS0913
OMIT ZS0914
OMIT ZS0915
OMIT ZS0919
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
SM
SM
1
SM
1
SM
1
SM
1
1
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/04/2009
A
PAGE TITLE
SIGNAL ALIAS
EMI THINBC POGO PINS (870-1820 ) OMIT ZS0917 2.0DIA-MLB-THIN-BC-K84 SM
DRAWING NUMBER
Apple Inc. OMIT ZS0918
OMIT ZS0916
2.0DIA-MLB-THIN-BC-K84
2.0DIA-MLB-THIN-BC-K84
SM
SM
NOSTUFF
NOTICE OF PROPRIETARY PROPERTY:
SM
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
1 1
C.0.0
ZS0920
1 1
D
REVISION
R
2.0DIA-MLB-THIN-BC-K84
SIZE
051-7982 BRANCH
PAGE
9 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
K5
70 14
BI
FSB_A_L
M3
70 14
BI
FSB_A_L
N2
70 14
BI
FSB_A_L
J1
70 14
BI
FSB_A_L
N3
70 14
BI
70 14
FSB_A_L
P5
BI
FSB_A_L
P2
70 14
BI
FSB_A_L
L2
70 14
BI
FSB_A_L
P4
70 14
BI
FSB_A_L
P1
70 14
BI
FSB_A_L
R1
70 14
BI
FSB_ADSTB_L
M1
70 14
BI
FSB_REQ_L
K3
BI
FSB_REQ_L
H2
70 14
BI
FSB_REQ_L
K2
70 14
BI
FSB_REQ_L
J3
70 14
BI
FSB_REQ_L
L1
70 14
BI
FSB_A_L
Y2
70 14
BI
FSB_A_L
U5
70 14
BI
FSB_A_L
R3 W6
BI
FSB_A_L
70 14
BI
FSB_A_L
U4
70 14
BI
FSB_A_L
Y5
70 14
BI
FSB_A_L
U1
70 14
BI
FSB_A_L
R4
70 14
BI
FSB_A_L
T5
70 14
BI
FSB_A_L
T3
70 14
BI
FSB_A_L
W2
70 14
BI
FSB_A_L
W5
70 14
BI
FSB_A_L
Y4
70 14
BI
FSB_A_L
U2 V4
70 14
BI
FSB_A_L
70 14
BI
FSB_A_L
W3
70 14
BI
FSB_A_L
AA4
70 14
BI
FSB_A_L
AB2
70 14
BI
FSB_A_L
AA3
70 14
BI
FSB_ADSTB_L
70 14
V1
70 14
IN
CPU_A20M_L
A6
70 14
OUT
CPU_FERR_L
A5
70 14
IN
CPU_IGNNE_L
C4
70 14
IN
CPU_STPCLK_L
70 14
IN
CPU_INTR
C6
70 14
IN
CPU_NMI
B4
IN
CPU_SMI_L
A3
70 14
D5
TP_CPU_RSVD_M4
M4
TP_CPU_RSVD_N5
N5
TP_CPU_RSVD_T2
T2
TP_CPU_RSVD_V3
V3
TP_CPU_RSVD_B2
B2
TP_CPU_RSVD_F6
F6
TP_CPU_RSVD_D2
D2
TP_CPU_RSVD_D22 TP_CPU_RSVD_D3
D22 D3
1 OF 4
DEFER* DRDY* DBSY* BR0*
REQ0* REQ1* REQ2* REQ3* REQ4*
A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1*
BI
14 70
FSB_BNR_L
BI
14 70
FSB_BPRI_L
BI
14 70
H5
FSB_DEFER_L
BI
14 70
F21
FSB_DRDY_L
BI
14 70
E1
FSB_DBSY_L
BI
14 70
FSB_BREQ0_L
F1
BI
=PP1V05_S0_CPU
R1000 1% 1/16W MF-LF 402
14 70
1
2
D
IERR* INIT*
B3
CPU_INIT_L
IN
LOCK*
H4
FSB_LOCK_L
BI
RESET* RS0* RS1* RS2* TRDY*
C1
FSB_CPURST_L
IN
13 14 70
F3
FSB_RS_L
IN
14 70
F4
FSB_RS_L
IN
14 70
G3
FSB_RS_L
IN
14 70
G2
FSB_TRDY_L
IN
14 70
G6
FSB_HIT_L
BI
14 70
E4
FSB_HITM_L
BI
14 70
BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR*
8 11 12 13
54.9
D20
HIT* HITM*
70 CPU_IERR_L 14 70
14 70
OMIT
AD4
XDP_BPM_L
AD3
XDP_BPM_L
BI
13 70
AD1
XDP_BPM_L
BI
13 70
AC4
XDP_BPM_L
BI
13 70
AC2
XDP_BPM_L
AC1
XDP_BPM_L
AC5
XDP_TCK
AA6
BI
BI
13 70
1
R1001
70 14
BI
FSB_D_L
E22
70 14
BI
FSB_D_L
F24 E26
BI
FSB_D_L
70 14
BI
FSB_D_L
G22
70 14
BI
FSB_D_L
F23
70 14
BI
FSB_D_L
G25
70 14
BI
FSB_D_L
E25
BI
FSB_D_L
E23 K24 G24
70 14
54.9 1% 1/16W MF-LF 402
13 70
2
BI
13 70
IN
10 13 70
70 14
XDP_TDI
IN
10 13 70
70 14
BI
FSB_D_L
AB3
XDP_TDO
OUT
10 13 70
70 14
BI
FSB_D_L
AB5
XDP_TMS
AB6
XDP_TRST_L
C20
XDP_DBRESET_L
IN
10 13 70
70 14
BI
FSB_D_L
J24
IN
10 13 70
70 14
BI
FSB_D_L
J23
70 14
BI
FSB_D_L
H22 F26
OUT
13 25
R1002
1
BI
FSB_D_L
70 14
BI
FSB_D_L
K22
70 14
BI
FSB_D_L
H23
70 14
BI
FSB_DSTB_L_N
J26
70 14
BI
FSB_DSTB_L_P
H26
70 14
BI
FSB_DINV_L
H25
70 14
BI
FSB_D_L
N22
70 14
BI
FSB_D_L
K25
70 14
BI
FSB_D_L
P26
70 14
BI
FSB_D_L
R23
70 14
BI
FSB_D_L
L23
70 14
BI
FSB_D_L
M24
70 14
BI
FSB_D_L
L22
70 14
BI
FSB_D_L
M23
70 14
BI
FSB_D_L
P25
70 14
BI
FSB_D_L
P23
70 14
BI
FSB_D_L
P22 T24
70 14
68 5% 1/16W MF-LF 402
THERMAL PROCHOT* THERMDA THERMDC
A20M* FERR* IGNNE* STPCLK* LINT0 LINT1 SMI*
FSB_ADS_L
G5
THERMTRIP*
CPU_PROCHOT_L
A24
CPU_THERMD_P
B25
C7
2
OUT OUT
42 76
CPU_THERMD_N
OUT
42 76
PM_THRMTRIP_L
OUT
14 37 70
14 37 70
H CLK
BCLK0 BCLK1
RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8
D21
A22
FSB_CLK_CPU_P
A21
FSB_CLK_CPU_N
IN IN
14 70 14 70
BI
FSB_D_L
70 14
BI
FSB_D_L
R24
70 14
BI
FSB_D_L
L25
70 14
BI
FSB_D_L
T25
70 14
BI
FSB_D_L
N25
70 14
BI
FSB_DSTB_L_N
L26
70 14
BI
FSB_DSTB_L_P
M26
70 14
BI
FSB_DINV_L
N24
70 14
1
R1005 1K
CPU JTAG Support
B
R1090
2
1% 1/16W MF-LF 402
D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0*
D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1*
U1000 PENRYN FCBGA
2 OF 4
DATA GRP 2
FSB_A_L
H1 E2
DATA GRP 3
BI
FCBGA
DATA GRP 0
70 14
ADS* BNR* BPRI*
PENRYN
DATA GRP 1
BI
L4
CONTROL
L5
U1000
XDP/ITP SIGNALS
FSB_A_L FSB_A_L
A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0*
ADDR GROUP0
BI
70 14
70 14
C
J4
ADDR GROUP1
70 14
FSB_A_L
ICH
BI
RESERVED
D
70 14
D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2*
D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3*
Y22
FSB_D_L
BI
14 70
AB24
FSB_D_L
BI
14 70
V24
FSB_D_L
BI
14 70
V26
FSB_D_L
BI
14 70
V23
FSB_D_L
BI
14 70
T22
FSB_D_L
BI
14 70
U25
FSB_D_L
BI
14 70
U23
FSB_D_L
BI
14 70
Y25
FSB_D_L
BI
14 70
W22
FSB_D_L
BI
14 70
Y23
FSB_D_L
BI
14 70
W24
FSB_D_L
BI
14 70
W25
FSB_D_L
BI
14 70
AA23
FSB_D_L
BI
14 70
AA24
FSB_D_L
BI
14 70
AB25
FSB_D_L
BI
14 70
Y26
FSB_DSTB_L_N
BI
14 70
AA26
FSB_DSTB_L_P
BI
14 70
U22
FSB_DINV_L
BI
14 70
AE24
FSB_D_L
BI
14 70
AD24
FSB_D_L
BI
14 70
AA21
FSB_D_L
BI
14 70
AB22
FSB_D_L
BI
14 70
AB21
FSB_D_L
BI
14 70
AC26
FSB_D_L
BI
14 70
AD20
FSB_D_L
BI
14 70
AE22
FSB_D_L
BI
14 70
AF23
FSB_D_L
BI
14 70
AC25
FSB_D_L
BI
14 70
AE21
FSB_D_L
BI
14 70
AD21
FSB_D_L
BI
14 70
AC22
FSB_D_L
BI
14 70
AD23
FSB_D_L
BI
14 70
AF22
FSB_D_L
BI
14 70
AC23
FSB_D_L
BI
14 70
AE25
FSB_DSTB_L_N
BI
14 70
AF24
FSB_DSTB_L_P
BI
14 70
AC20
FSB_DINV_L
BI
14 70
C
B
54.9 70 13 10
XDP_TMS
70 13 10
XDP_TDI
1
70 26 CPU_GTLREF
2
CPU_TEST1
C23
R1006
CPU_TEST2
D25
2.0K
TP_CPU_TEST3
1% 1/16W
R1091
1
MF-LF 402
54.9 1
2 1% 1/16W MF-LF
R1092 2
54.9
402
70 13 10
XDP_TDO
1
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)
1% 1/16W MF-LF 402
CPU_TEST4 NO STUFF
C1014
2 1% 1/16W
NO STUFF
MF-LF
R1010
402 1
NO STUFF
R1011
R1093
10% 16V X5R 402
1
2 1% 1/16W
R1094
MF-LF 402
649 70 13 10
XDP_TRST_L
1
NO STUFF 1
402
1K
54.9
XDP_TCK
1/16W MF-LF
5% 1/16W MF-LF 402
2
AF26 AF1
TP_CPU_TEST6
A26 C3
70 9
OUT CPU_BSEL
B22
70 9
OUT CPU_BSEL
B23
70 9
OUT CPU_BSEL
C21
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2
COMP0 COMP1 COMP2 COMP3
MISC
DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*
R26
70 CPU_COMP
U26
70 CPU_COMP
AA1
70 CPU_COMP
Y1
70 CPU_COMP
1
E5
CPU_DPRSTP_L
IN
14 59 70
B5
CPU_DPSLP_L
IN
14 70
54.9
54.9
1% 1/16W
1% 1/16W
D24
FSB_DPWR_L
IN
14 70
D6
CPU_PWRGD
IN
13 14 70
D7
FSB_CPUSLP_L
IN
14 70
AE6
CPU_PSI_L
R1023
MF-LF
OUT
402
59
5% 1/16W MF-LF 402
1
R1021
MF-LF 402
2
1
2
1
R1022 27.4
R1012 1K
2
C24
TP_CPU_TEST5
TP_CPU_TEST7 2
2 5%
1
1
0.1uF
0
70 13 10
AD26
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.
1% 1/16W
PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.
MF-LF 402
2
R1020 27.4 1% 1/16W
2
MF-LF 402
PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
2
PLACEMENT_NOTE (all 4 resistors):
1%
Place within 12.7mm of CPU
1/16W MF-LF 402
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
CPU FSB DRAWING NUMBER
SYNC FROM T18
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
CHANGE CPU FROM SOCKET TO BGA SYMBOL
SIZE
BRANCH
PAGE
10 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
A4
P6
A8
(CPU CORE POWER)
1
P21
OMIT A11
=PPVCORE_S0_CPU
P24
U1000
8 11 12 A14
R2
PENRYN
44 A (SV Design Target)
A16
41 A (SV HFM)
A19
30.4 A (SV LFM)
A23
R25
AF2
T1
B6
T4
R5
FCBGA
D
AB20
A7 A9
AB7
OMIT
A10
23 A (LV Design Target)
AC7
U1000
AC9
A12
R22
4 OF 4
B8
T23
AC12
B11
T26
AC13
B13
U3
PENRYN A13
FCBGA
A15
3 OF 4
A17
AC15
B16
U6
A18
AC17
B19
U21
A20
AC18
B21
U24
B7
AD7
B24
V2
B9
AD9
C5
V5
B10
AD10
C8
V22
B12
AD12
C11
V25
B14
AD14
C14
W1
B15
AD15
C16
W4
B17
AD17
C19
W23
B18
AD18
C2
W26
B20
VCC
C22
Y3 Y6
C9
AE10
C25
C10
AE12
D1
Y21
C12
AE13
D4
Y24
C13
AE15
D8
AA2
C15
AE17
D11
AA5
C17
AE18
D13
AA8
C18
AE20
D16
AA11
AF9
D19
AA14
D10
AF10
D23
AA16
D12
AF12
D26
AA19
D14
AF14
E3
AA22
D9
C
AE9
D15
VCC
AF15
E6
AA25
D17
AF17
E8
AB1
D18
AF18
E11
E7
AF20
(CPU IO POWER 1.05V) E14
=PP1V05_S0_CPU
E9
8 10 12 13
D
C
AB4
VSS
VSS
AB8
E16
AB11
E19
AB13
E21
AB16
E10
G21
E12
V6
E13
J6
E24
AB19
E15
K6
F5
AB23
E17
M6
F8
AB26
E18
J21
F11
AC3
E20
K21
F13
AC6
F7
M21
F16
AC8
N21
F19
AC11
F2
AC14
4500 mA (before VCC stable) 2500 mA (after VCC stable)
VCCP
F9 F10
N6
F12
R21
F22
AC16
F14
R6
F25
AC19
F15
T21
G4
AC21
F17
T6
G1
AC24
F18
V21
F20
W21
G23
AD2
G26
AD5
H3
AD8
H6
AD11
H21
AD13
H24
AD16 AD19
(CPU INTERNAL PLL POWER 1.5V) AA7
=PP1V5_S0_CPU
(BR1#)
AA9
B26
VCCA
AA10
B
8 12
130 mA C26
AA12
VID0 VID1 VID2 VID3 VID4 VID5 VID6
AA13 AA15 AA17 AA18 AA20 AB9 AC10
AD6
CPU_VID
OUT
59 70
J2
AF5
CPU_VID
OUT
59 70
J5
AD22
AE5
CPU_VID
OUT
59 70
J22
AD25
AF4
CPU_VID
OUT
59 70
J25
AE1
AE3
CPU_VID
OUT
59 70
K1
AE4
K4
AE8
AF3
CPU_VID
AE2
CPU_VID
=PPVCORE_S0_CPU
OUT
59 70
OUT
59 70
1
2
VCCSENSE
AB14
AF7
8 11 12
R1100 100
AB10 AB12
CPU_VCCSENSE_P
1% 1/16W MF-LF 402
OUT
59 70
AB15 PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs. PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.
AB17
VSSSENSE
AB18
AE7
B
CPU_VCCSENSE_N
OUT 1
2
59 70
K23
AE11
K26
AE14
L3
AE16
L6
AE19
L21
AE23
L24
AE26
M2
A2
M5
AF6
R1101
M22
AF8
100
M25
AF11
N1
AF13
N4
AF16
N23
AF19
N26
AF21
1% 1/16W MF-LF 402
P3 B1
A25
(Socket-P KEY)
A
AF25
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
CPU Power & Ground DRAWING NUMBER
SYNC FROM T18 Apple Inc.
CHANGE CPU FROM SOCKET TO BGA SYMBOL
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
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C.0.0
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BRANCH
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11 OF 109 SHEET
OF
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
8
051-7982
7
6
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CPU VCore HF and Bulk Decoupling 4X 330UF. 20X 22UF 0805 PLACEMENT_NOTE (C1200-C1219): 11 8 =PPVCORE_S0_CPU
Place inside socket cavity on secondary side.
D
CRITICAL 1
CRITICAL 1
C1200 22UF
2
22UF
20% 6.3V CERM-X5R 805
2
CRITICAL 1
2
CRITICAL 1
C1201
C1203
22UF
20% 6.3V CERM-X5R 805
2
CRITICAL 1
C1210
CRITICAL 1
C1202
22UF
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
2
CRITICAL 1
C1211
CRITICAL 1
22UF 2
CRITICAL 1
C1212
C1213
CRITICAL 1
C1204
22UF
20% 6.3V CERM-X5R 805
2
CRITICAL 1
CRITICAL 1
C1205
CRITICAL 1
22UF
20% 6.3V CERM-X5R 805
2
CRITICAL 1
C1214
C1206
C1216
CRITICAL 1
22UF 2
CRITICAL 1
C1215
20% 6.3V CERM-X5R 805
C1207 20% 6.3V CERM-X5R 805
22UF 2
CRITICAL 1
C1217
22UF
22UF
22UF
22UF
22UF
22UF
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
20% 6.3V CERM-X5R 805
2
2
2
2
2
2
2
20% 6.3V CERM-X5R 805
CRITICAL 1
C1218
22UF
20% 6.3V CERM-X5R 805
2
2
CRITICAL 1
22UF
20% 6.3V CERM-X5R 805
C1209 22UF
20% 6.3V CERM-X5R 805
22UF
D
CRITICAL 1
C1208
C1219 22UF
2
20% 6.3V CERM-X5R 805
C
C PLACEMENT_NOTE (C1240-C1243): Place on secondary side. CRITICAL
NOSTUFF
1
1
C1240 470UF-4MOHM
2
CRITICAL 1
C1241 470UF-4MOHM
20% 3
Place on secondary side.
CRITICAL
470UF-4MOHM
20%
2.0V POLY-TANT
3
D2T-SM
2
C1243 470UF-4MOHM 20%
20%
2.0V POLY-TANT
3
D2T-SM
Place on secondary side.
CRITICAL 1
C1242
2
2.0V POLY-TANT
3
2.0V POLY-TANT
2
D2T-SM
D2T-SM
Place on secondary side.
VCCA (CPU AVdd) DECOUPLING 1x 10uF, 1x 0.01uF 11 8 =PP1V5_S0_CPU
PLACEMENT_NOTE=Place C1281 near CPU pin B26.
C1250
1
1
2
2
C1251
10uF 20% 6.3V X5R 603
0.01UF 10% 16V CERM 402
B
B VCCP (CPU I/O) DECOUPLING 1x 330uF, 6x 0.1uF 0402 13 11 10 8 =PP1V05_S0_CPU
1 CRITICAL
C1260
1
330UF 2
20% 2.5V TANT CASE-B2-SM
2
C1261
1
C1262
1
C1263
1
C1264
1
C1265
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
2
2
2
2
1
C1266 0.1UF
2
20% 10V CERM 402
A
SYNC_MASTER=K24_MLB
SYNC_DATE=03/30/2009
A
PAGE TITLE
CPU Decoupling DRAWING NUMBER
Apple Inc.
SYNC FROM T18 REMOVE NO STUFF CAPS C1220 TO C1231 REMOVE C1244 & C1245 CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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SIZE
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12 OF 109 SHEET
OF
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1
Mini-XDP Connector NOTE: This is not the standard XDP pinout.
D
USE WITH 920-0782 ADAPTER FLEX TO SUPPORT CPU, MCP DEBUGGING.
D
MCP79-specific pinout
8 12 11 10 8
=PP3V3_S0_XDP =PP1V05_S0_CPU
XDP
R1315
OMIT CRITICAL
1
J1300
54.9 1% 1/16W MF-LF 402
70 10 70 10
70 10 70 10
DF40C-60DS-0.4V F-ST-SM 2
XDP_BPM_L
OBSFN_A0
4
OBSFN_C0
JTAG_MCP_TDO
BI
XDP_BPM_L
OBSFN_A1
5
6
OBSFN_C1
JTAG_MCP_TRST_L
7
8 10
OBSDATA_C0
MCP_DEBUG
BI
19 73
OBSDATA_C1
MCP_DEBUG
BI
19 73
BI
19 73
BI
BI IN
XDP_BPM_L
OBSDATA_A0
9
XDP_BPM_L
OBSDATA_A1
11
12
13
14 16
OBSDATA_C2
MCP_DEBUG
OBSDATA_C3
MCP_DEBUG
70 10
IN
XDP_BPM_L
70 10
IN
XDP_BPM_L
XDP
OBSDATA_A2
15
OBSDATA_A3
17
18
19
20
1
21
19 73
21
22
OBSFN_D0
JTAG_MCP_TDI
OUT
21
TP_XDP_OBSFN_B1
OBSFN_B1
23
24
OBSFN_D1
JTAG_MCP_TMS
OUT
21
25
26
TP_XDP_OBSDATA_B0
OBSDATA_B0
27
28
OBSDATA_D0
MCP_DEBUG
BI
19 73
TP_XDP_OBSDATA_B1
OBSDATA_B1
29
30
OBSDATA_D1
MCP_DEBUG
BI
19 73
31
32 19 73
TP_XDP_OBSDATA_B2
OBSDATA_B2
33
34
OBSDATA_D2
MCP_DEBUG
BI
TP_XDP_OBSDATA_B3
OBSDATA_B3
35
36
OBSDATA_D3
MCP_DEBUG
BI
37
38
PWRGD/HOOK0
39
40
ITPCLK/HOOK4
FSB_CLK_ITP_P
IN
14 70
FSB_CLK_ITP_N
IN
14 70
XDP_PWRGD
2
21
OBSFN_B0
1K
CPU_PWRGD
IN OUT
TP_XDP_OBSFN_B0
R1399 IN
2
BI
3
C
70 14 10
1
HOOK1
41
42
ITPCLK#/HOOK5
VCC_OBS_AB
43
44
VCC_OBS_CD
XDP_OBS20
5% 1/16W MF-LF 402
19 73
XDP
R1303 1K
19
IN
PM_LATRIGGER_L
HOOK2
45
46
RESET#/HOOK6
21
OUT
JTAG_MCP_TCK
HOOK3
47
48
DBR#/HOOK7
70 XDP_CPURST_L
XDP_DBRESET_L
49
50
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
1
OUT
10 25
SMBUS_MCP_0_DATA
SDA
51
52
TDO
XDP_TDO
IN
10 70
BI
SMBUS_MCP_0_CLK
SCL
53
54
TRSTn
XDP_TRST_L
OUT
10 70
55
56
TDI
XDP_TDI
OUT
10 70
OUT
XDP_TCK
57
58
TMS
XDP_TMS
OUT
10 70
59
60
XDP_PRESENT#
NC
TCK0
1
1
2
2
0.1uF
B
10 14 70
C1301 0.1uF
10% 16V X5R 402
IN
XDP
XDP
C1300
FSB_CPURST_L
PLACEMENT_NOTE=Place close to CPU to minimize stub.
402
BI
73 39 21
TCK1
2 5% 1/16W MF-LF
73 39 21
70 10
C
10% 16V X5R 402
B
(998-2515) 518S0774
Direction of XDP module Please avoid any obstructions ON ODD-NUMBERED SIDE OF J1300
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/25/2009
A
PAGE TITLE
eXtended Debug Port(MiniXDP) DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
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13 OF 109 SHEET
OF
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OMIT
U1400 MCP79-TOPO-B BGA (1 OF 11)
BI
FSB_DSTB_L_P
70 10
BI
FSB_DSTB_L_N
U40
BI
FSB_DINV_L
V41
70 10
70 10 70 10 70 10
D
L36
70 10
BI
FSB_DINV_L
N35
70 10
BI
FSB_DSTB_L_P
M39
70 10
BI
FSB_DSTB_L_N
M41
70 10
BI
FSB_DINV_L
BI
FSB_A_L
BI
FSB_A_L
70 10 70 10 70 10 70 10 70 10 70 10 70 10
FSB_A_L
AE37
BI
FSB_A_L
AE35
BI
FSB_A_L
AB35
BI
FSB_A_L
AF35
BI
FSB_A_L
BI
FSB_A_L
BI
FSB_A_L
AE33
BI
FSB_A_L
AG37
BI
FSB_A_L
AG35 AG39
AG38
FSB_A_L
70 10
BI
FSB_A_L
70 10
BI
FSB_A_L
BI
FSB_A_L
AL39 AG33 AL33 AJ33
BI
FSB_A_L
BI
FSB_A_L
BI
FSB_A_L
AJ37
70 10
BI
FSB_A_L
AJ36
70 10
BI
FSB_A_L
AJ38
70 10
BI
FSB_A_L
AL37
BI
FSB_A_L
BI
FSB_A_L
70 10
BI
FSB_A_L
70 10
BI
FSB_A_L
BI
FSB_A_L
70 10 70 10
BI
FSB_A_L
BI
FSB_A_L
70 10
BI
70 10
BI
FSB_ADSTB_L
70 10 70 10
AN36 AJ35
AL34 AN37 AJ34 AL38 AL35 AN34 AR39
FSB_A_L
BI
FSB_ADSTB_L
AN35
AE36 AK35
BI
FSB_REQ_L
AC38
BI
FSB_REQ_L
AA33 AC39
BI
FSB_REQ_L
70 10
BI
FSB_REQ_L
AC33
70 10
BI
FSB_REQ_L
AC35
70 10
5% 1/16W
70 10
BI
FSB_ADS_L
AD42
MF-LF
MF-LF
MF-LF
70 10
BI
FSB_BNR_L
AD43
BI
FSB_BREQ0_L
AE40
70 FSB_BREQ1_L
AL32
402
2
2
402
70 10
IN
PM_THRMTRIP_L
70 10
BI
FSB_DBSY_L
AD39
IN
CPU_FERR_L
70 10
BI
FSB_DRDY_L
AD41
70 10
BI
70 10
NO STUFF
R1420
NO STUFF 1
R1421
1K
402
1
1
1K
2
402
AB42
FSB_HITM_L
AD40
IN
FSB_LOCK_L
AC43
70 10
OUT
FSB_TRDY_L
AE41
9
OUT
CPU_PECI_MCP
R1422
70 37 10
OUT
CPU_PROCHOT_L
1K
E41 AJ41 AG43
5% 1/16W
MF-LF
MF-LF
FSB_HIT_L
BI
70 10
NO STUFF
5% 1/16W
5% 1/16W
CPU_DSTBP1# CPU_DSTBN1# CPU_DBI1# CPU_DSTBP2# CPU_DSTBN2# CPU_DBI2# CPU_DSTBP3# CPU_DSTBN3# CPU_DBI3# CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32# CPU_A33# CPU_A34# CPU_A35# CPU_ADSTB0# CPU_ADSTB1# CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4#
62
5% 1/16W
2
CPU_DSTBP0# CPU_DSTBN0# CPU_DBI0#
R1416
1% 1/16W 402
9
BI
BI
70 10
9
BI
AC37
70 10
70 10
9
AE34
FSB_A_L
BI
70 10
70 10
FSB_A_L
70 10
70 10
70 37 10
BI
AN38
70 10
B
AE38
AG34
70 10
62
AC34
FSB_A_L
70 10
54.9
J41
FSB_A_L
70 10
R1415
N37
BI
70 10
R1410
V35
FSB_DSTB_L_N
70 10
1
FSB_DINV_L
BI
70 10
1
BI
W37
BI
70 10
1
FSB_DSTB_L_N
70 10
70 10
=PP1V05_S0_MCP_FSB
BI
W39
70 10
70 10
23 22 14 8
FSB_DSTB_L_P
FSB_DSTB_L_P
70 10
C
BI
T40
FSB
70 10
AH40
MF-LF 2
2
CPU_ADS# CPU_BNR# CPU_BR0# CPU_BR1# CPU_DBSY# CPU_DRDY# CPU_HIT# CPU_HITM# CPU_LOCK# CPU_TRDY# CPU_PECI CPU_PROCHOT# CPU_THERMTRIP# CPU_FERR#
402
IN
=MCP_BSEL
(MCP_BSEL)
F42
IN
=MCP_BSEL
(MCP_BSEL)
D42
IN
=MCP_BSEL
(MCP_BSEL)
F41
CPU_BSEL2 CPU_BSEL1 CPU_BSEL0
CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63#
Y43
FSB_D_L
BI
10 70
W42
FSB_D_L
BI
10 70
Y40
FSB_D_L
BI
10 70
W41
FSB_D_L
BI
10 70
Y39
FSB_D_L
BI
10 70
V42
FSB_D_L
BI
10 70
Y41
FSB_D_L
BI
10 70
Y42
FSB_D_L
BI
10 70
P42
FSB_D_L
BI
10 70
U41
FSB_D_L
BI
10 70
R42
FSB_D_L
BI
10 70
T39
FSB_D_L
BI
10 70
T42
FSB_D_L
BI
10 70
T41
FSB_D_L
BI
10 70
R41
FSB_D_L
BI
10 70
T43
FSB_D_L
BI
10 70
W35
FSB_D_L
BI
10 70
AA37
FSB_D_L
BI
10 70
W33
FSB_D_L
BI
10 70
W34
FSB_D_L
BI
10 70
AA36
FSB_D_L
BI
10 70
AA34
FSB_D_L
BI
10 70
AA38
FSB_D_L
BI
10 70
AA35
FSB_D_L
BI
10 70
U38
FSB_D_L
BI
10 70
U36
FSB_D_L
BI
10 70
U35
FSB_D_L
BI
10 70
U33
FSB_D_L
BI
10 70
U34
FSB_D_L
BI
10 70
W38
FSB_D_L
BI
10 70
R33
FSB_D_L
BI
10 70
U37
FSB_D_L
BI
10 70
N34
FSB_D_L
BI
10 70
N33
FSB_D_L
BI
10 70
R34
FSB_D_L
BI
10 70
R35
FSB_D_L
BI
10 70
P35
FSB_D_L
BI
10 70
R39
FSB_D_L
BI
10 70
R37
FSB_D_L
BI
10 70
R38
FSB_D_L
BI
10 70
L37
FSB_D_L
BI
10 70
L39
FSB_D_L
BI
10 70
L38
FSB_D_L
BI
10 70
N36
FSB_D_L
BI
10 70
N38
FSB_D_L
BI
10 70
J39
FSB_D_L
BI
10 70
J38
FSB_D_L
BI
10 70
J37
FSB_D_L
BI
10 70
L42
FSB_D_L
BI
10 70
M42
FSB_D_L
BI
10 70
P41
FSB_D_L
BI
10 70
N41
FSB_D_L
BI
10 70
N40
FSB_D_L
BI
10 70
M40
FSB_D_L
BI
10 70
H40
FSB_D_L
BI
10 70
K42
FSB_D_L
BI
10 70
H41
FSB_D_L
BI
10 70
L41
FSB_D_L
BI
10 70
H43
FSB_D_L
BI
10 70
H42
FSB_D_L
BI
10 70
K41
FSB_D_L
BI
10 70
J40
FSB_D_L
BI
10 70
H39
FSB_D_L
BI
10 70
M43
FSB_D_L
BI
AA41
FSB_BPRI_L
OUT
10 70
AA40
FSB_DEFER_L
OUT
10 70
BCLK_OUT_CPU_P BCLK_OUT_CPU_N
G42
FSB_CLK_CPU_P
OUT
10 70
G41
FSB_CLK_CPU_N
OUT
10 70
BCLK_OUT_ITP_P BCLK_OUT_ITP_N
AL43
FSB_CLK_ITP_P
OUT
13 70
AL42
FSB_CLK_ITP_N
OUT
13 70
BCLK_OUT_NB_P BCLK_OUT_NB_N
AL41
70 FSB_CLK_MCP_P
AK42
70 FSB_CLK_MCP_N
BCLK_IN_N BCLK_IN_P
AK41
CPU_A20M# CPU_IGNNE# CPU_INIT# CPU_INTR CPU_NMI CPU_SMI#
AF41
CPU_A20M_L
OUT
10 70
AH39
CPU_IGNNE_L
OUT
10 70
CPU_BPRI# CPU_DEFER#
D
C
B
10 70
Loop-back clock for delay matching.
OUT
FSB_RS_L
AC41
70 10
OUT
FSB_RS_L
AB41
70 10
OUT
FSB_RS_L
AC42
70 10
R1430
1
1
49.9
49.9
1%
270 mA (A01)
2
2
1
1
49.9
AG27
20 mA
AH27
MF-LF 402
29 mA
AG28
15 mA
AH28
70 MCP_BCLK_VML_COMP_VDD
AM39
70 MCP_BCLK_VML_COMP_GND
AM40
70 MCP_CPU_COMP_VCC
AM43
70 MCP_CPU_COMP_GND
AM42
R1436 49.9
1%
1%
1/16W MF-LF 402
206 mA
1/16W
A R1431
PP1V05_S0_MCP_PLL_FSB
1%
1/16W MF-LF 402
23
R1435
1/16W
2
2
CPU_RS0# CPU_RS1# CPU_RS2#
MF-LF 402
+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU BCLK_VML_COMP_VDD BCLK_VML_COMP_GND CPU_COMP_VCC CPU_COMP_GND
CPU_PWRGD CPU_RESET# CPU_SLP# CPU_DPSLP# CPU_DPWR# CPU_STPCLK# CPU_DPRSTP#
AJ40
AH42
CPU_INIT_L
OUT
10 70
AF42
CPU_INTR
OUT
10 70
AG41
CPU_NMI
OUT
10 70
AH41
CPU_SMI_L
OUT
10 70
=PP1V05_S0_MCP_FSB
R1440 150 5% 1/16W MF-LF 2
7
402
SYNC_MASTER=K24_MLB
AH43
CPU_PWRGD
H38
FSB_CPURST_L
OUT
10 13 70
AM33
FSB_CPUSLP_L
OUT
10 70
AN33
CPU_DPSLP_L
OUT
10 70
AM32
FSB_DPWR_L
OUT
10 70
AG42
CPU_STPCLK_L
OUT
10 70
AN32
CPU_DPRSTP_L
OUT
10 59 70
OUT
10 13 70
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP CPU Interface DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
REVISION
C.0.0
R
BRANCH
PAGE
14 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
8 14 22 23
NO STUFF 1
6
5
4
3
2
1
7
6
5
4
3
2
OMIT
U1400
MCP79-TOPO-B
MCP79-TOPO-B
BGA
BGA
(2 OF 11)
BI
MEM_A_DQ
AL8
71 27
BI
MEM_A_DQ
AL9
71 27
BI
MEM_A_DQ
AP9
71 27
BI
MEM_A_DQ
AN9
71 27
BI
MEM_A_DQ
AL6
71 27
BI
MEM_A_DQ
AL7
71 27
BI
MEM_A_DQ
AN6
71 27
BI
MEM_A_DQ
AN7
71 27
BI
MEM_A_DQ
AR6 AR7
BI
MEM_A_DQ
71 27
BI
MEM_A_DQ
AV6
71 27
BI
MEM_A_DQ
AW5
71 27
BI
MEM_A_DQ
AN10
71 27
BI
MEM_A_DQ
AR5
71 27
BI
MEM_A_DQ
AU6
71 27
BI
MEM_A_DQ
AV5
71 27
BI
MEM_A_DQ
AU7
71 27
BI
MEM_A_DQ
AU8
71 27
BI
MEM_A_DQ
AW9
71 27
BI
MEM_A_DQ
AP11 AW6
71 27
BI
MEM_A_DQ
71 27
BI
MEM_A_DQ
AY5
71 27
BI
MEM_A_DQ
AU9
71 27
BI
MEM_A_DQ
AV9
71 27
BI
MEM_A_DQ
AU11
71 27
BI
MEM_A_DQ
AV11
71 27
BI
MEM_A_DQ
AV13
71 27
BI
MEM_A_DQ
AW13
71 27
BI
MEM_A_DQ
AR11
71 27
BI
MEM_A_DQ
AT11
71 27
BI
MEM_A_DQ
AR14 AU13
71 27
C
BI
MEM_A_DQ
71 27
BI
MEM_A_DQ
AR26
71 27
BI
MEM_A_DQ
AU25
71 27
BI
MEM_A_DQ
AT27
71 27
BI
MEM_A_DQ
AU27
71 27
71 27
BI
MEM_A_DQ
AP25
71 27
BI
MEM_A_DQ
AR25
71 27
BI
MEM_A_DQ
AP27
BI
MEM_A_DQ
AR27
BI
MEM_A_DQ
71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27
BI
MEM_A_DQ
AR29
BI
MEM_A_DQ
AP31
BI
MEM_A_DQ
BI
MEM_A_DQ
BI
MEM_A_DQ
BI
MEM_A_DQ
BI
MEM_A_DQ
BI
MEM_A_DQ
AR31 AV27 AN29 AV29 AN31 AU31
BI
MEM_A_DQ
AR33
BI
MEM_A_DQ
AV37
71 27
BI
MEM_A_DQ
AW37
71 27
BI
MEM_A_DQ
AT31
71 27
BI
MEM_A_DQ
AV31
71 27
BI
MEM_A_DQ
AT37
71 27
BI
MEM_A_DQ
AU37
71 27
BI
MEM_A_DQ
AW39
71 27
BI
MEM_A_DQ
AV39
71 27
BI
MEM_A_DQ
AR37
71 27
BI
MEM_A_DQ
AR38
71 27
BI
71 27
71 27 71 27
B
AP29
MEM_A_DQ
AV38
BI
MEM_A_DQ
AW38
71 27
BI
MEM_A_DQ
AR35
71 27
BI
MEM_A_DQ
AP35
71 27
OUT
MEM_A_DM
AN5
71 27
OUT
MEM_A_DM
AU5
71 27
OUT
MEM_A_DM
AR10
71 27
OUT
MEM_A_DM
AN13
71 27
OUT
MEM_A_DM
AN27
71 27
OUT
MEM_A_DM
AW29
71 27
OUT
MEM_A_DM
AV35
71 27
OUT
MEM_A_DM
AR34
MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0 MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0
(3 OF 11)
MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N
MEMORY PARTITION 0
D
71 27
1
OMIT
U1400
AL10
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AT4
AL11
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AT3
AR8
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AV2
AR9
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AV3
AW7
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AR4
AW8
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AR3
AP13
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AU2
AR13
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AU3
AV25
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AY4
AW25
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AY3
AU30
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
BB3
AU29
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
BC3
AT35
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
AW4
AU35
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
AW3
AU39
MEM_A_DQS_P
BI
27 71
71 28
BI
MEM_B_DQ
BA3
AT39
MEM_A_DQS_N
BI
27 71
71 28
BI
MEM_B_DQ
BB2
71 28
BI
MEM_B_DQ
BB5
71 28
BI
MEM_B_DQ
BA5
71 28
BI
MEM_B_DQ
BA8
71 28
BI
MEM_B_DQ
BC8 BB4
BI
MEM_B_DQ
OUT
27 71
71 28
BI
MEM_B_DQ
BC4
OUT
27 71
71 28
BI
MEM_B_DQ
BA7
71 28
BI
MEM_B_DQ
AY8
71 28
BI
MEM_B_DQ
BA9
71 28
BI
MEM_B_DQ
BB10
71 28
BI
MEM_B_DQ
BB12
71 28
BI
MEM_B_DQ
AW12
71 28
71 28
MRAS0# MCAS0# MWE0#
MBA0_2 MBA0_1 MBA0_0
MA0_14 MA0_13 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0
AV17
MEM_A_RAS_L
AP17
MEM_A_CAS_L
AR17
MEM_A_WE_L
AP23
MEM_A_BA
AP19
MEM_A_BA
AW17
MEM_A_BA
MEM_A_A
AR23
MEM_A_A
AU15
MEM_A_A
AN23
OUT
27 71
BI
MEM_B_DQ
OUT
27 71
71 28
BI
MEM_B_DQ
BB9
OUT
27 71
71 28
BI
MEM_B_DQ
AY12 BA12
OUT
27 71
OUT
27 71
OUT
27 71
OUT OUT
27 71
AN19
MEM_A_A
OUT
27 71
AV21
MEM_A_A
OUT
27 71
OUT
27 71
AU21
MEM_A_A
OUT
27 71
AP21
MEM_A_A
OUT
27 71
AR21
MEM_A_A
OUT
27 71
AN21
MEM_A_A
OUT
27 71
AV19
MEM_A_A
OUT
27 71
AU19
MEM_A_A
OUT
27 71
AT19
MEM_A_A
OUT
27 71
OUT
27 71
TP_MEM_A_CLK2P
AV33
TP_MEM_A_CLK2N
71 28
BI
MEM_B_DQ
AW32
71 28
BI
MEM_B_DQ
BA35
71 28
BI
MEM_B_DQ
AY36
71 28
BI
MEM_B_DQ
BA32
71 28
BI
MEM_B_DQ
BB32
71 28
BI
MEM_B_DQ
BA34
BI
MEM_B_DQ
AY35
BI
MEM_B_DQ
71 28
MEM_A_A
AW33
BC32
71 28
71 28 71 28 71 28 71 28 71 28 71 28
BC36
BI
MEM_B_DQ
AW36
BI
MEM_B_DQ
BA39
BI
MEM_B_DQ
BI
MEM_B_DQ
BI
MEM_B_DQ
BI
MEM_B_DQ
BI
MEM_B_DQ
BI
MEM_B_DQ
AY40 BA36 BB36 BA38 AY39 BB40
BI
MEM_B_DQ
AW40
BI
MEM_B_DQ
AV42
71 28
BI
MEM_B_DQ
AV41
71 28
BI
MEM_B_DQ
BA40
71 28
BI
MEM_B_DQ
BC40
71 28
BI
MEM_B_DQ
AW42
71 28
BI
MEM_B_DQ
AW41
71 28
BI
MEM_B_DQ
AT40
71 28
BI
MEM_B_DQ
AT41
71 28
BI
MEM_B_DQ
AP41
71 28 71 28
MEMORY CONTROL 0A MCLK0A_2_P MCLK0A_2_N
BI
MEM_B_DQ
71 28
AR22
MEM_A_A
71 28
71 28
71 28
MEM_A_A
AR19
BI
MEM_B_DQ
27 71
AW21
BB8
MCLK0A_1_P MCLK0A_1_N
BA24
MEM_A_CLK_P
OUT
27 71
71 28
BI
MEM_B_DQ
AN40
AY24
MEM_A_CLK_N
OUT
27 71
71 28
BI
71 28
MCLK0A_0_P MCLK0A_0_N
BB20
MEM_A_CLK_P
OUT
27 71
OUT
27 71
MCS0A_1# MCS0A_0# MODT0A_1 MODT0A_0 MCKE0A_1 MCKE0A_0
MEM_A_CLK_N
BC20
AT15
MEM_A_CS_L
AR18
MEM_A_CS_L
MEM_B_DQ
AU40
BI
MEM_B_DQ
AU41
71 28
BI
MEM_B_DQ
AR41
71 28
BI
MEM_B_DQ
AP42
AT5
OUT
27 71
71 28
OUT
MEM_B_DM
OUT
27 71
71 28
OUT
MEM_B_DM
BA2 AY7
71 28
OUT
MEM_B_DM
AP15
MEM_A_ODT
OUT
27 71
71 28
OUT
MEM_B_DM
BA11
AV15
MEM_A_ODT
OUT
27 71
71 28
OUT
MEM_B_DM
BB34 BB38
71 28
OUT
MEM_B_DM
AU23
MEM_A_CKE
OUT
27 71
71 28
OUT
MEM_B_DM
AY43
AT23
MEM_A_CKE
OUT
27 71
71 28
OUT
MEM_B_DM
AR42
A
MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0 MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0
MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N
AT2
MEM_B_DQS_P
BI
28 71
AT1
MEM_B_DQS_N
BI
28 71
AY2
MEM_B_DQS_P
BI
28 71
AY1
MEM_B_DQS_N
BI
28 71
BB6
MEM_B_DQS_P
BI
28 71
BA6
MEM_B_DQS_N
BI
28 71
BA10
MEM_B_DQS_P
BI
28 71
AY11
MEM_B_DQS_N
BI
28 71
BB33
MEM_B_DQS_P
BI
28 71
BA33
MEM_B_DQS_N
BI
28 71
BB37
MEM_B_DQS_P
BI
28 71
BA37
MEM_B_DQS_N
BI
28 71
BA43
MEM_B_DQS_P
BI
28 71
AY42
MEM_B_DQS_N
BI
28 71
AT42
MEM_B_DQS_P
BI
28 71
AT43
MEM_B_DQS_N
BI
28 71
MRAS1# MCAS1# MWE1#
AW16
MEM_B_RAS_L
OUT
28 71
BA15
MEM_B_CAS_L
OUT
28 71
BA16
MEM_B_WE_L
OUT
28 71
MBA1_2 MBA1_1 MBA1_0
BB29
MEM_B_BA
OUT
28 71
BB18
MEM_B_BA
OUT
28 71
BB17
MEM_B_BA
OUT
28 71
MA1_14 MA1_13 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0
BA29
MEM_B_A
OUT
28 71
BA14
MEM_B_A
OUT
28 71
AW28
MEM_B_A
OUT
28 71
BC28
MEM_B_A
OUT
28 71
BA17
MEM_B_A
OUT
28 71
BB28
MEM_B_A
OUT
28 71
AY28
MEM_B_A
OUT
28 71
BA28
MEM_B_A
OUT
28 71
AY27
MEM_B_A
OUT
28 71
BA27
MEM_B_A
OUT
28 71
BA26
MEM_B_A
OUT
28 71
BB26
MEM_B_A
OUT
28 71
BA25
MEM_B_A
OUT
28 71
BB25
MEM_B_A
OUT
28 71
BA18
MEM_B_A
OUT
28 71
MCLK1A_2_P MCLK1A_2_N
BA42
TP_MEM_B_CLK2P
BB42
TP_MEM_B_CLK2N
MCLK1A_1_P MCLK1A_1_N
BB22
MEM_B_CLK_P
OUT
28 71
BA22
MEM_B_CLK_N
OUT
28 71
MCLK1A_0_P MCLK1A_0_N
BA19
MEM_B_CLK_P
OUT
28 71
AY19
MEM_B_CLK_N
OUT
28 71
MCS1A_1# MCS1A_0#
BB14
MEM_B_CS_L
OUT
28 71
BB16
MEM_B_CS_L
OUT
28 71
MODT1A_1 MODT1A_0
BB13
MEM_B_ODT
OUT
28 71
AY15
MEM_B_ODT
OUT
28 71
MCKE1A_1 MCKE1A_0
AY31
MEM_B_CKE
OUT
28 71
BB30
MEM_B_CKE
OUT
28 71
MEMORY PARTITION 1
8
D
C
MEMORY CONTROL 1A
B
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP Memory Interface DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
15 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400 MCP79-TOPO-B BGA
23 23 16 8
TP_MEM_A_CLK5N
AU34
TP_MEM_A_CLK4P
BB24
TP_MEM_A_CLK4N
BC24
TP_MEM_A_CLK3P
BA21
TP_MEM_A_CLK3N
BB21
TP_MEM_A_CS_L
AU17
TP_MEM_A_CS_L
AR15
TP_MEM_A_ODT
AN17
TP_MEM_A_ODT
AN15
TP_MEM_A_CKE
AV23
TP_MEM_A_CKE
AN25
MCLK0B_2_P MCLK0B_2_N MCLK0B_1_P MCLK0B_1_N MCLK0B_0_P MCLK0B_0_N MCS0B_0# MCS0B_1# MODT0B_0 MODT0B_1 MCKE0B_0 MCKE0B_1
MEMORY CONTROL 1B
D
AU33
MEMORY CONTROL 0B
(4 OF 11)
TP_MEM_A_CLK5P
MCLK1B_2_P MCLK1B_2_N
BA41
TP_MEM_B_CLK5P
BB41
TP_MEM_B_CLK5N
MCLK1B_1_P MCLK1B_1_N
AY23
TP_MEM_B_CLK4P
BA23
TP_MEM_B_CLK4N
MCLK1B_0_P MCLK1B_0_N
BA20
TP_MEM_B_CLK3P
AY20
TP_MEM_B_CLK3N
MCS1B_0# MCS1B_1#
BC16
TP_MEM_B_CS_L
BA13
TP_MEM_B_CS_L
MODT1B_0 MODT1B_1
AY16
TP_MEM_B_ODT
BC13
TP_MEM_B_ODT
MCKE1B_0 MCKE1B_1
BA30
TP_MEM_B_CKE
BA31
TP_MEM_B_CKE
MRESET0#
AY32
D
PP1V05_S0_MCP_PLL_CORE
=PP1V8R1V5_S0_MCP_MEM 87 mA (A01)
R1610
1
17 mA
T27
12 mA
U28
19 mA
U27
39 mA
T28
40.2 1% 1/16W
+V_PLL_XREF_XS +V_PLL_DP +V_PLL_CORE +V_VPLL
MCP_MEM_RESET_L
OUT
29
TP or NC for DDR2.
MF-LF 402
R1611
C
2
71 MCP_MEM_COMP_VDD
AN41
71 MCP_MEM_COMP_GND
AM41
MEM_COMP_VDD MEM_COMP_GND
1
40.2 AA22
1% 1/16W MF-LF 402
AP12 2
G30 P10 T10 T6 V10 V34 W5 AA39 AB22 AB7 AD22 AE20 AF24 AG24 AH35 AK7 AM28 AT25 AP30 AR36 AU10 F28 BC21 AY9
B
BC9 D34 F24 G32 H31 K7 M38 M5 M6 M7 M9 N39 N8 P33 P34 P37 P4 P40 P7 R36 R40 R43 R5 T18 T20 AK11
A
T24 T26
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54
=PP1V8R1V5_S0_MCP_MEM
+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8 +VDD_MEM9 +VDD_MEM10 +VDD_MEM11 +VDD_MEM12 +VDD_MEM13 +VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20 +VDD_MEM21 +VDD_MEM22 +VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26 +VDD_MEM27 +VDD_MEM28 +VDD_MEM29 +VDD_MEM30 +VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34 +VDD_MEM35 +VDD_MEM36 +VDD_MEM37 +VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41 +VDD_MEM42 +VDD_MEM43 +VDD_MEM44 +VDD_MEM45 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64
AM17
8 16 23
4771 mA (A01, DDR3)
AM19
C
AM21 AM23 AM25 AM27 AM29 AN16 BC29 AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29
B
AV24 AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AY26 AW19 AW24 BC25 AL30 AM31
T33 T34 T35 T37 T38 T7 T9 U18 U20
SYNC_MASTER=K24_MLB U22
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP Memory Misc DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
C.0.0
7
BRANCH
PAGE
16 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400 MCP79-TOPO-B BGA (5 OF 11)
IN
=PEG_D2R_P
F7
9
IN
=PEG_D2R_N
E7
9
IN
=PEG_D2R_P
D7
9
IN
=PEG_D2R_N
C7
9
IN
=PEG_D2R_P
E6
9
IN
=PEG_D2R_N
F6
IN
=PEG_D2R_P
E5
9
IN
=PEG_D2R_N
F5
9
IN
=PEG_D2R_P
E4
9
IN
=PEG_D2R_N
E3
9
IN
=PEG_D2R_P
C3
9
IN
=PEG_D2R_N
D3
9
IN
=PEG_D2R_P
G5
9
IN
=PEG_D2R_N
H5
9
IN
=PEG_D2R_P
J7
9
IN
=PEG_D2R_N
J6
9
IN
=PEG_D2R_P
J5 J4
9
D
IN
=PEG_D2R_N
9
IN
=PEG_D2R_P
L11
9
IN
=PEG_D2R_N
L10
9
IN
=PEG_D2R_P
L9
9
IN
=PEG_D2R_N
L8
9
IN
=PEG_D2R_P
L7
9
IN
=PEG_D2R_N
L6
9
IN
=PEG_D2R_P
N11
9
9
IN
=PEG_D2R_N
N10
9
IN
=PEG_D2R_P
N9
9
IN
=PEG_D2R_N
P9 N7
IN
=PEG_D2R_P
9
IN
=PEG_D2R_N
N6
9
IN
=PEG_D2R_P
N5
IN
=PEG_D2R_N
N4
9
9
C
PE0_RX0_P PE0_RX0_N PE0_RX1_P PE0_RX1_N PE0_RX2_P PE0_RX2_N PE0_RX3_P PE0_RX3_N PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE0_RX6_P PE0_RX6_N PE0_RX7_P PE0_RX7_N PE0_RX8_P PE0_RX8_N PE0_RX9_P PE0_RX9_N PE0_RX10_P PE0_RX10_N PE0_RX11_P PE0_RX11_N PE0_RX12_P PE0_RX12_N PE0_RX13_P PE0_RX13_N PE0_RX14_P PE0_RX14_N PE0_RX15_P PE0_RX15_N
=PEG_R2D_C_P
OUT
9
D4
=PEG_R2D_C_N
OUT
9
C4
=PEG_R2D_C_P
OUT
9
B4
=PEG_R2D_C_N
OUT
9
A4
=PEG_R2D_C_P
OUT
9
A3
=PEG_R2D_C_N
OUT
9
B3
=PEG_R2D_C_P
OUT
9
B2
=PEG_R2D_C_N
OUT
9
C1
=PEG_R2D_C_P
OUT
9
D1
=PEG_R2D_C_N
OUT
9
D2
=PEG_R2D_C_P
OUT
9
E1
=PEG_R2D_C_N
OUT
9
E2
=PEG_R2D_C_P
OUT
9
F2
=PEG_R2D_C_N
OUT
9
F3
=PEG_R2D_C_P
OUT
9
F4
=PEG_R2D_C_N
OUT
9
G3
=PEG_R2D_C_P
OUT
9
H4
=PEG_R2D_C_N
OUT
9
H3
=PEG_R2D_C_P
OUT
9
H2
=PEG_R2D_C_N
OUT
9
H1
=PEG_R2D_C_P
OUT
9
J1
=PEG_R2D_C_N
OUT
9
J2
=PEG_R2D_C_P
OUT
9
J3
=PEG_R2D_C_N
OUT
9
K2
=PEG_R2D_C_P
OUT
9
K3
=PEG_R2D_C_N
OUT
9
L4
=PEG_R2D_C_P
OUT
9
L3
=PEG_R2D_C_N
OUT
9
M4
=PEG_R2D_C_P
OUT
9
M3
=PEG_R2D_C_N
OUT
9
M2
=PEG_R2D_C_P
OUT
9
M1
=PEG_R2D_C_N
OUT
9
PE0_REFCLK_P PE0_REFCLK_N
E11
PEG_CLK100M_P
OUT
9
D11
PEG_CLK100M_N
OUT
9
PE1_REFCLK_P PE1_REFCLK_N
G11
PCIE_CLK100M_MINI_P
OUT
30 72
F11
PCIE_CLK100M_MINI_N
OUT
30 72
PE2_REFCLK_P PE2_REFCLK_N
J11
PCIE_CLK100M_FW_P
OUT
9
J10
PCIE_CLK100M_FW_N
OUT
9
PE3_REFCLK_P PE3_REFCLK_N
G13
PCIE_CLK100M_EXCARD_P
OUT
9
F13
PCIE_CLK100M_EXCARD_N
OUT
9
PE4_REFCLK_P PE4_REFCLK_N
J13
TP_PCIE_CLK100M_PE4P
H13
TP_PCIE_CLK100M_PE4N
PE5_REFCLK_P PE5_REFCLK_N
L14
TP_PCIE_CLK100M_PE5P
K14
TP_PCIE_CLK100M_PE5N
PE6_REFCLK_P PE6_REFCLK_N
N14
TP_PCIE_CLK100M_PE6P
M14
TP_PCIE_CLK100M_PE6N
PEX_RST0#
K11
PCIE_RESET_L
OUT
25
PE1_RX0_P PE1_RX0_N
PE1_TX0_P PE1_TX0_N
D8
PCIE_MINI_R2D_C_P
OUT
30 72
C8
PCIE_MINI_R2D_C_N
OUT
30 72
PE1_RX1_P PE1_RX1_N
PE1_TX1_P PE1_TX1_N
B8
PCIE_FW_R2D_C_P
OUT
9 72
A8
PCIE_FW_R2D_C_N
OUT
9 72
PE1_RX2_P PE1_RX2_N
PE1_TX2_P PE1_TX2_N
A7
PCIE_EXCARD_R2D_C_P
OUT
9
B7
PCIE_EXCARD_R2D_C_N
OUT
9
PE1_RX3_P PE1_RX3_N
PE1_TX3_P PE1_TX3_N
B6
TP_PCIE_PE4_R2D_CP
Int PU
PE0_PRSNT_16#
IN
PEG_PRSNT_L
C9
30
IN
MINI_CLKREQ_L
D5
PEB_CLKREQ#/GPIO_49
30
IN
PCIE_MINI_PRSNT_L
D9
PEB_PRSNT#
9
IN
FW_CLKREQ_L
E8
9
IN
PCIE_FW_PRSNT_L
C10
9
IN
EXCARD_CLKREQ_L
M15
PED_CLKREQ#/GPIO_51
9
IN
PCIE_EXCARD_PRSNT_L
B10
PED_PRSNT#
TP_PE4_CLKREQ_L
L16
PEE_CLKREQ#/GPIO_16
TP_PE4_PRSNT_L
L18
PEE_PRSNT#/GPIO_46
AUD_IP_PERIPHERAL_DET
M16
PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47
9
PE0_TX0_P PE0_TX0_N PE0_TX1_P PE0_TX1_N PE0_TX2_P PE0_TX2_N PE0_TX3_P PE0_TX3_N PE0_TX4_P PE0_TX4_N PE0_TX5_P PE0_TX5_N PE0_TX6_P PE0_TX6_N PE0_TX7_P PE0_TX7_N PE0_TX8_P PE0_TX8_N PE0_TX9_P PE0_TX9_N PE0_TX10_P PE0_TX10_N PE0_TX11_P PE0_TX11_N PE0_TX12_P PE0_TX12_N PE0_TX13_P PE0_TX13_N PE0_TX14_P PE0_TX14_N PE0_TX15_P PE0_TX15_N
C5
PCI EXPRESS
9
Int PU
Int PU
Int PU
PEC_CLKREQ#/GPIO_50
PEC_PRSNT#
Int PU
Int PU Int PU
Int PU
D
C
Int PU 54
Int PU
9
OUT
GMUX_JTAG_TCK_L
M18
9
OUT
CARDREADER_RESET
M17
9
IN
GMUX_JTAG_TDO
M19
Int PU Int PU
PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48 Int PU
IN
PCIE_WAKE_L
72 30
IN
PCIE_MINI_D2R_P
K9
72 30
30 7
B
F17
IN
PCIE_MINI_D2R_N
J9
72 9
IN
PCIE_FW_D2R_P
H9
72 9
IN
PCIE_FW_D2R_N
G9
9
IN
PCIE_EXCARD_D2R_P
F9
9
IN
PCIE_EXCARD_D2R_N
E9
TP_PCIE_PE4_D2RP
H7
TP_PCIE_PE4_D2RN
G7
PE_WAKE# Int
PU (S5)
TP_PCIE_PE4_R2D_CN
C6
=PP1V05_S0_MCP_PEX_DVDD0
8
=PP1V05_S0_MCP_PEX_AVDD0 T17
57 mA (A01, DVDD0 & 1)
W19 U17 V19 W16 W17 W18 U16
+DVDD0_PEX1 +DVDD0_PEX2 +DVDD0_PEX3 +DVDD0_PEX4 +DVDD0_PEX5 +DVDD0_PEX6 +DVDD0_PEX7 +DVDD0_PEX8
=PP1V05_S0_MCP_PEX_DVDD1
8
T19 U19
PP1V05_S0_MCP_PLL_PEX
23
T16
+DVDD1_PEX1 +DVDD1_PEX2
A11
Y12
+AVDD1_PEX1 +AVDD1_PEX2 +AVDD1_PEX3
M13
PEX_CLK_COMP
8
206 mA (A01, AVDD0 & 1)
AA12 AB12 M12 P12 R12 N12 T12 U12 AC12 AD12 V12 W12
+V_PLL_PEX
84 mA (A01)
72 MCP_PEX_CLK_COMP
+AVDD0_PEX1 +AVDD0_PEX2 +AVDD0_PEX3 +AVDD0_PEX4 +AVDD0_PEX5 +AVDD0_PEX6 +AVDD0_PEX7 +AVDD0_PEX8 +AVDD0_PEX9 +AVDD0_PEX10 +AVDD0_PEX11 +AVDD0_PEX12 +AVDD0_PEX13
B
=PP1V05_S0_MCP_PEX_AVDD1
8
N13 P13
NO STUFF
A
1
R1710
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
SYNC_MASTER=K24_MLB
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
PAGE TITLE
2.37K 1%
2
SYNC_DATE=04/06/2009
402
DRAWING NUMBER PLACEMENT_NOTE=Place within 12.7mm of U1400
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
C.0.0 BRANCH
PAGE
17 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
7
SIZE
REVISION
R
8
A
MCP PCIe Interfaces
1/16W MF-LF
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400 MCP79-TOPO-B BGA (6 OF 11)
IN
ENET_RXD
C23
74 31
IN
ENET_RXD
B23
74 31
IN
ENET_RXD
E24
74 31
IN
ENET_RXD
A24
74 31
IN
ENET_CLK125M_RXCLK
A23
RGMII_RXC/MII_RXCLK
74 31
IN
ENET_RX_CTRL
C22
RGMII_RXCTL/MII_RXDV
IN
=MCP_MII_RXER
F23
9
IN
=MCP_MII_COL
B26
9
IN
=MCP_MII_CRS
B22
TP_ENET_INTR_L
J22
9
23 18 8
RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3
74 31
=PP3V3_ENET_MCP_RMGT
1
R1810
8 18 23
J24
+3.3V_DUAL_RMGT2
K24
+V_DUAL_RMGT1 +V_DUAL_RMGT2
U23
MII_VREF
E28
MCP_MII_VREF
RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3
B24
ENET_TXD
OUT
31 74
C24
ENET_TXD
OUT
31 74
C25
ENET_TXD
OUT
31 74
D25
ENET_TXD
OUT
31 74
RGMII_TXC/MII_TXCLK RGMII_TXCTL/MII_TXEN
D24
ENET_CLK125M_TXCLK
OUT
31 74
C26
ENET_TX_CTRL
OUT
31 74
RGMII_MDC RGMII_MDIO
D21
ENET_MDC
OUT
31 74
C21
ENET_MDIO
LAN
D
=PP3V3_ENET_MCP_RMGT
+3.3V_DUAL_RMGT1
83 mA (A01)
=PP1V05_ENET_MCP_RMGT
D
8 23
131 mA (A01)
V23
Network Interface Select
MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK RGMII_INTR/GPIO_35
IN
23
Interface
ENET_TXD
RGMII
1
MII
0
NOTE: All Apple products set strap to MII, RGMII products will enable
BI
feature via software.
This
31 74
avoids a leakage issue since
49.9 1/16W MF-LF 402
PP1V05_ENET_MCP_PLL_MAC
23
1%
T23
+V_DUAL_MACPLL
74 MCP_MII_COMP_VDD
C27
74 MCP_MII_COMP_GND
B27
MII_COMP_VDD MII_COMP_GND
5 mA (A01)
RGMII_PWRDWN/GPIO_37
G23
TP_ENET_PWRDWN_L
2
BUF_25MHZ
E23
MCP_CLK25M_BUF0_R
MII_RESET#
J23
ENET_RESET_L
+V_RGB_DAC +V_TV_DAC
J32
103 mA
PP3V3_S0_MCP_DAC
R1811
1
1% MF-LF 402
TP_MCP_RGB_DAC_VREF
C39 B38
2
RGB_DAC_RSET RGB_DAC_VREF
C 9
OUT
MCP_TV_DAC_RSET
E36
9
OUT
MCP_TV_DAC_VREF
A35
TV_DAC_RSET TV_DAC_VREF
=PP3V3_S5_MCP_GPIO
1
9 9
47K
IN
MCP_CLK27M_XTALIN
C38
OUT
MCP_CLK27M_XTALOUT
D38
B
IN
LPCPLUS_GPIO
E16
DP_IG_CA_DET
B15
(See below)
69 68
OUT
LVDS_IG_BKL_PWM
69
OUT
LVDS_IG_BKL_ON
E37
G39
65
TMDS/HDMI
DisplayPort
OUT
LVDS_IG_PANEL_PWR
MCP Signal =MCP_HDMI_TXC_P/N
TMDS_IG_TXC_P/N
DP_IG_ML_P/N
66
OUT
=MCP_HDMI_TXC_P
D35
=MCP_HDMI_TXD_P/N
TMDS_IG_TXD_P/N
DP_IG_ML_P/N
66
OUT
=MCP_HDMI_TXC_N
E35
=MCP_HDMI_TXD_P/N
TMDS_IG_TXD_P/N
DP_IG_ML_P/N 66
OUT
=MCP_HDMI_TXD_P
G35
66
OUT
=MCP_HDMI_TXD_N
F35
66
OUT
=MCP_HDMI_TXD_P
F33
66
OUT
=MCP_HDMI_TXD_N
G33
66
OUT
=MCP_HDMI_TXD_P
J33
66
OUT
=MCP_HDMI_TXD_N
H33
NOTE: 20K pull-down required on DP_HPD_DET.
72 66
OUT
DP_IG_AUX_CH_P
D43
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
72 66
OUT
DP_IG_AUX_CH_N
C43
TMDS_IG_TXD_P/N
DP_IG_ML_P/N
=MCP_HDMI_DDC_CLK
TMDS_IG_DDC_CLK
DP_IG_DDC_CLK
=MCP_HDMI_DDC_DATA
TMDS_IG_DDC_DATA
DP_IG_DDC_DATA
=MCP_HDMI_HPD
TMDS_IG_HPD
DP_IG_HPD
DP_IG_AUX_CH_P/N
TP_DP_IG_AUX_CHP/N
DP_IG_AUX_CH_P/N
XTALIN_TV XTALOUT_TV
IFP interface can 9
IN
=DVI_HPD_GMUX_INT
66
IN
=MCP_HDMI_HPD
be used to provide HDMI or dual-channel TMDS without level-shifters. LVDS:
1
K32
103 mA
2
2
R1861 100K 5% 1/16W MF-LF 402
A31
MCP_DDC_DATA0
RGB_DAC_RED RGB_DAC_GREEN RGB_DAC_BLUE
B39
TP_MCP_RGB_RED
A39
TP_MCP_RGB_GREEN
Okay to float all RGB_DAC signals.
B40
TP_MCP_RGB_BLUE
DDC_CLK0/DDC_DATA0 pull-ups still required.
RGB_DAC_HSYNC RGB_DAC_VSYNC
A40
TP_MCP_RGB_HSYNC
A41
TP_MCP_RGB_VSYNC
TV_DAC_RED TV_DAC_GREEN TV_DAC_BLUE
A36
CRT_IG_R_C_PR
OUT
9
B36
CRT_IG_G_Y_Y
OUT
9
Okay to float all TV_DAC signals.
C36
CRT_IG_B_COMP_PB
OUT
9
Okay to float XTALIN_TV and XTALOUT_TV.
TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45
D36
CRT_IG_HSYNC
OUT
9
C37
CRT_IG_VSYNC
OUT
9
IFPA_TXC_P IFPA_TXC_N
B35
LVDS_IG_A_CLK_P
OUT
65 72
C35
LVDS_IG_A_CLK_N
OUT
65 72
IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N
B32
LVDS_IG_A_DATA_P
OUT
A32
LVDS_IG_A_DATA_N
OUT
7 65 72
D32
LVDS_IG_A_DATA_P
OUT
7 65 72
C32
LVDS_IG_A_DATA_N
OUT
7 65 72
D33
LVDS_IG_A_DATA_P
OUT
7 65 72
C33
LVDS_IG_A_DATA_N
OUT
7 65 72
B34
LVDS_IG_A_DATA_P
OUT
9
C34
LVDS_IG_A_DATA_N
OUT
9
IFPB_TXC_P IFPB_TXC_N
L31
LVDS_IG_B_CLK_P
OUT
9
K31
LVDS_IG_B_CLK_N
OUT
9
IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N
J29
LVDS_IG_B_DATA_P
OUT
9
H29
LVDS_IG_B_DATA_N
OUT
9
L29
LVDS_IG_B_DATA_P
OUT
9
K29
LVDS_IG_B_DATA_N
OUT
9
L30
LVDS_IG_B_DATA_P
OUT
9
K30
LVDS_IG_B_DATA_N
OUT
9
N30
LVDS_IG_B_DATA_P
OUT
9
M30
LVDS_IG_B_DATA_N
OUT
9
DDC_CLK2/GPIO_23 DDC_DATA2/GPIO_24
C30
LVDS_IG_DDC_CLK
OUT
7 65
B30
LVDS_IG_DDC_DATA
DDC_CLK3 DDC_DATA3
D31
=MCP_HDMI_DDC_CLK
E31
=MCP_HDMI_DDC_DATA
IFPAB_RSET IFPAB_VPROBE
E32
MCP_IFPAB_RSET
OUT
24 72
G31
MCP_IFPAB_VPROBE
OUT
24 72
/ Component / Pr
Y
/ Y
Comp / Pb
GPIO_6/FERR*/IGPU_GPIO_6 GPIO_7/NFERR*/IGPU_GPIO_7
LCD_BKL_CTL/GPIO_57 LCD_BKL_ON/GPIO_59 LCD_PANEL_PWR/GPIO_58 HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
NOTE: HDMI port requires level-shifting.
1
5% 1/16W MF-LF
MCP_DDC_CLK0
Power +VDD_IFPx at 1.8V
C31 F31
HPLUG_DET2/GPIO_22 HPLUG_DET3
=PP3V3R1V8_S0_MCP_IFP_VDD
24 8
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
(See below)
DP_AUX_CH0_P DP_AUX_CH0_N
M27
190 mA (A01, 1.8V)
M26
PP3V3_S0_MCP_VPLL
24
16 mA (A01)
8 mA
M28
8 mA
M29
=PP1V05_S0_MCP_HDMI_VDD
24 8
+VDD_IFPA +VDD_IFPB +V_PLL_IFPAB +V_PLL_HDMI
T25
+VDD_HDMI
J31 J30
HDMI_RSET HDMI_VPROBE
FLAT PANEL
BI
F40
=MCP_HDMI_TXD_P/N
R1860
24
206 mA (A01)
8 19 21
C
RGB DAC Disable:
TV DAC Disable:
DDC_CLK0/DDC_DATA0 pull-ups still required.
2
66
Interface Mode
=PP3V3_S0_MCP_GPIO
B31
C
MF-LF
38
OUT
31 74
DDC_CLK0 DDC_DATA0
TV
5% 1/16W 402
32 74
402
RGB ONLY
TP_MCP_RGB_DAC_RSET
DACS
1/16W
R1820
OUT
100K
49.9
20 8
MCP79 requires a S5 pull-up.
7 65 72
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
BI
OUT BI
B
7 65
66 66
95 mA (A01) 72 24
OUT
MCP_HDMI_RSET
72 24
OUT
MCP_HDMI_VPROBE
1
R1850 10K
GPIOs 57-59 (if LCD panel is used):
5% 1/16W MF-LF
In MCP79 these pins have undocumented internal pull-ups (~10K to 3.3V S0).
A
2
402
To ensure pins are low
by default, pull-downs (1K or stronger) must be used.
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP Ethernet & Graphics
=DVI_HPD_GMUX_INT:
DRAWING NUMBER Alias to DVI_HPD for systems using IFP for DVI.
Apple Inc.
Alias to GMUX_INT for systems with GMUX.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
C.0.0
7
BRANCH
PAGE
18 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
D
REVISION
R
Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.
SIZE
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400
21 18 8
=PP3V3_S0_MCP_GPIO
MCP79-TOPO-B BGA
19
(7 OF 11)
73 19
PCI_REQ1_L
V9
OUT
FW_PWR_EN
T3
OUT
AUD_IPHS_SWITCH_EN
U9
19
IN
MCP_RS232_SIN_L
T4
73 13
BI
MCP_DEBUG
AC3
73 13
BI
MCP_DEBUG
AE10
73 13
BI
MCP_DEBUG
AC4
73 13
BI
MCP_DEBUG
AE11 AB3
BI
MCP_DEBUG
73 13
BI
MCP_DEBUG
AC6
73 13
BI
MCP_DEBUG
AB2
BI
MCP_DEBUG
AC7
TP_PCI_AD
AC8
TP_PCI_AD
AA2
TP_PCI_AD
AC9
TP_PCI_AD
AC10
TP_PCI_AD
AC11
TP_PCI_AD
AA1
TP_PCI_AD
AA5
TP_PCI_AD
Y5
TP_PCI_AD
W3
TP_PCI_AD
W6
TP_PCI_AD
W4
TP_PCI_AD
W7
TP_PCI_AD
V3
TP_PCI_AD
W8
TP_PCI_AD
V2
TP_PCI_AD
W9
73 13
73 13
C
TP_PCI_AD
U3
TP_PCI_AD
W11
TP_PCI_AD
U2
TP_PCI_AD
U5
TP_PCI_AD
U1
TP_PCI_AD
U6
TP_PCI_AD
T5
TP_PCI_AD
U7
TP_PCI_INTW_L
P2
TP_PCI_INTX_L
N3
TP_PCI_INTY_L
N2
TP_PCI_INTZ_L
N1
TP_PCI_TRDY_L
38 36
9
38 36
IN
IN
BI
Y3
PM_CLKRUN_L
AD11
FW_PME_L
AE2
TP_LPC_DRQ0_L
AE1
LPC_SERIRQ
AE6
PCI_REQ0# PCI_REQ1#/FANRPM2 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
PCI_GNT0# PCI_GNT1#/FANCTL2 PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS# PCI_GNT4#/GPIO_53/RS232_SOUT# PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_PAR PCI_PERR#/GPIO_43/RS232_DCD# PCI_SERR# PCI_STOP#
PCI
T2
54
19
D
PCI_REQ0_L
73 19 R4
GMUX_JTAG_TMS
OUT
9
U11
GMUX_JTAG_TDI
OUT
9
P3
MCP_RS232_SOUT_L
OUT
19
AA3
TP_PCI_C_BE_L
AA6
TP_PCI_C_BE_L
U39 U4 U8 V16
B
V17 V18 V20 V22 V24 V26 V27 V28 V33 V37 V4 V40 V7 W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22
A
Y24 Y25
8.2K
1
2
R1990
8.2K
1
2
PCI_REQ1_L
R1991 R1992
8.2K
AA11
TP_PCI_C_BE_L
W10
TP_PCI_C_BE_L
AA9
TP_PCI_DEVSEL_L
Y4
TP_PCI_FRAME_L
AA10
TP_PCI_IRDY_L
Y1
TP_PCI_PAR
AB9
TP_PCI_PERR_L
AA7
TP_PCI_SERR_L
Y2
TP_PCI_STOP_L
T1
PM_LATRIGGER_L
OUT
13
R10
MEM_VTT_EN_R
OUT
25
R11
TP_PCI_RESET1_L
R6
TP_PCI_CLK0
19
1
2
8.2K
1
2
19
FW_PWR_EN
R1994
MCP_RS232_SIN_L
8.2K
1
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 402
5%
1/16W
MF-LF
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
Int PU (S5)
PCI_RESET0# PCI_RESET1#
TP_PCI_CLK1
R7
73 PCI_CLK33M_MCP_R
R8
R1910
C
22 5% 1/16W MF-LF 402
PLACEMENT_NOTE=Place close to pin R8
PCI_CLKIN
LPC_FRAME# LPC_PWRDWN#/GPIO_54/EXT_NMI#
PCI_TRDY# PCI_CLKRUN#/GPIO_42
GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 GND81 GND82 GND83 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97
R1989
PCI_REQ0_L
D
2
Int PU
GND
U26
73 19
TP_PCI_GNT1_L
U10
73 PCI_CLK33M_MCP
R9
R1960
22
AD4
LPC_FRAME_R_L
OUT
36 38 73
AE12
LPC_PWRDWN_L
OUT
36 38
LPC_RESET0#
AE5
LPC_RESET_L
OUT
25 73
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
AD3
LPC_AD_R
AD2
LPC_AD_R
AD1
LPC_AD_R
AD5
LPC_AD_R
1
LPC_FRAME_L
2 5%
LPC_CLK0
AE9
GND98 GND99 GND100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND111 GND112 GND113 GND114 GND115 GND116 GND117 GND118 GND119 GND120 GND121 GND122 GND123 GND124 GND125 GND126 GND127 GND128 GND129 GND130
Y26
R1950 R1951
22
1
2
22
1
2
R1952 R1953
22
1
2
22
1
2
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
LPC_AD
BI
LPC_AD
BI
36 38 73
LPC_AD
BI
36 38 73
LPC_AD
BI
LPC_CLK33M_SMC_R
1
U24
MCP_RS232_SOUT_L
TP_PCI_GNT0_L
R3
1
PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#
LPC_DRQ1#/GPIO_19 LPC_DRQ0# Int PU LPC_SERIRQ Int PU
PCI_PME#/GPIO_30
PCI_CLK0 PCI_CLK1 PCI_CLK2
LPC
73 19
OUT
36 38 73
36 38 73
25 73
R1961 10K
Y27
5% 1/16W
AB18
MF-LF 2
H34 AB20
402
Strap for Boot ROM Selection (See HDA_SDOUT)
AB21
B
AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4 AB40 AC22 AC36 AC40 AB33 AC5 AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27 AD28 AD33
SYNC_MASTER=K24_MLB
AD34
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP PCI & LPC DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
19 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400 MCP79-TOPO-B BGA (8 OF 11)
OUT
SATA_HDD_R2D_C_P
AJ7
OUT
SATA_HDD_R2D_C_N
AJ6
72 34
IN
SATA_HDD_D2R_N
AJ5
72 34
IN
SATA_HDD_D2R_P
AJ4
72 34 72 34
External A
SATA_A0_TX_P SATA_A0_TX_N
USB0_P USB0_N
C29
USB_EXTA_P
BI
35 73
D29
USB_EXTA_N
BI
35 73
SATA_A0_RX_N SATA_A0_RX_P
USB1_P USB1_N
C28
USB_MINI_P
BI
9
D28
USB_MINI_N
BI
9
USB2_P USB2_N
A28
USB_EXTD_P
BI
9
B28
USB_EXTD_N
BI
9
USB3_P USB3_N
F29
USB_CAMERA_P
BI
65 73
G29
USB_CAMERA_N
BI
65 73
USB4_P USB4_N
K27
USB_IR_P
BI
9 73
USB_IR_N
BI
9 73
USB_TPAD_P
BI
44 73
USB_TPAD_N
BI
44 73
USB_BT_P
BI
30 73
USB_BT_N
BI
30 73
USB_EXTB_P
BI
35 73
USB_EXTB_N
BI
35 73
USB_EXCARD_P
BI
9
USB_EXCARD_N
BI
9
H25
USB_EXTC_P
BI
9
J25
USB_EXTC_N
BI
9
AirPort (PCIe Mini-Card)
External D
D 72 34
OUT
SATA_ODD_R2D_C_P
72 34
OUT
SATA_ODD_R2D_C_N
72 34 72 34
AJ11 AJ10
IN
SATA_ODD_D2R_N
AJ9
IN
SATA_ODD_D2R_P
AK9
SATA_A1_TX_P SATA_A1_TX_N
D
Camera
SATA_A1_RX_N SATA_A1_RX_P
IR
L27
Geyser Trackpad/Keyboard
AK2
TP_SATA_C_R2D_CN
AJ3
TP_SATA_C_D2RN
AJ2
TP_SATA_C_D2RP
AJ1
TP_SATA_D_R2D_CP
AM4
TP_SATA_D_R2D_CN
AL3
TP_SATA_D_D2RN
AL4
TP_SATA_D_D2RP
AK3
SATA_B0_TX_P SATA_B0_TX_N SATA_B0_RX_N SATA_B0_RX_P
SATA_B1_TX_P SATA_B1_TX_N
J26 J27
Bluetooth
USB6_P USB6_N
SATA USB
TP_SATA_C_R2D_CP
USB5_P USB5_N
SATA_B1_RX_N SATA_B1_RX_P
F27 G27
External B
USB7_P USB7_N
D27 E27
ExpressCard
USB8_P USB8_N
K25 L25
=PP3V3_S5_MCP_GPIO
USB9_P USB9_N
1
1
R2051 8.2K
5%
1/16W
TP_SATA_E_R2D_CP
AN1
TP_SATA_E_R2D_CN
AM1
TP_SATA_E_D2RN
AM2
TP_SATA_E_D2RP
AM3
TP_SATA_F_R2D_CP
AP3
TP_SATA_F_R2D_CN
AP2
TP_SATA_F_D2RN
AN3
TP_SATA_F_D2RP
AN2
SATA_C0_TX_P SATA_C0_TX_N
USB10_P USB10_N
F25 G25
TP_USB_10N
USB11_P USB11_N
K23
USB_CARDREADER_P
BI
9 73
L23
USB_CARDREADER_N
BI
9 73
TP_USB_10P 2
SATA_C1_RX_N SATA_C1_RX_P
1
8.2K
SATA_C0_RX_N SATA_C0_RX_P
SATA_C1_TX_P SATA_C1_TX_N
R2050
1/16W
MF-LF 402
2
R2052
MF-LF 402
C
1
8.2K
5%
5%
1/16W MF-LF
1/16W MF-LF
402
R2053 8.2K
5%
C
8 18
External C
2
402
2
USB_OC0#/GPIO_25 USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO
L21
USB_EXTA_OC_L
IN
35
K21
USB_EXTB_OC_L
IN
35
J21
USB_EXTC_OC_L
IN
H21
EXCARD_OC_L
IN
+V_PLL_USB
L28
PP3V3_S0_MCP_PLL_USB
37
23
19 mA (A01)
USB_RBIAS_GND
A27
73 MCP_USB_RBIAS_GND
1
R2060 TP_MCP_SATALED_L
E12
PP1V05_S0_MCP_PLL_SATA
23
AE16
SATA_LED#
+V_PLL_SATA
84 mA (A01) =PP1V05_S0_MCP_SATA_DVDD0
8
43 mA (A01, DVDD0 & 1)
AF19 AG16 AG17 AG19
+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4
=PP1V05_S0_MCP_SATA_DVDD1
8
B
AH17 AH19
+DVDD1_SATA1 +DVDD1_SATA2
=PP1V05_S0_MCP_SATA_AVDD0
8
127 mA (A01, AVDD0 & 1)
AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13
+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9
=PP1V05_S0_MCP_SATA_AVDD1
8
AN14 AL14 AM13 AM14
72 MCP_SATA_TERMP
1
AE3
+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4 SATA_TERMP
GND131 GND132 GND133 GND134 GND135 GND136 GND137 GND138 GND139 GND140 GND141 GND142 GND143 GND144 GND145 GND146 GND147 GND148 GND149 GND150 GND151 GND152 GND153 GND154 GND155 GND156 GND157 GND158 GND159 GND160
AD35
806 1%
AD37 AD38
1/16W MF-LF 402
2
AE22 AE24 AE39 AE4 AD6 AF16 AF17 AF18
B
AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24
R2010 2.49K 1%
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
1/16W
2
MF-LF 402
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP SATA & USB DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
C.0.0
7
BRANCH
PAGE
20 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
6
5
4
3
2
1
8
7
6
5
4
3
2
1
OMIT
U1400
=PP3V3R1V5_S0_MCP_HDA
MCP79-TOPO-B
8 21 23
7 mA (A01)
BGA (9 OF 11)
+V_DUAL_HDA1 +V_DUAL_HDA2
73 49
HDA_SDIN0
IN
G15
HDA_SDATA_IN0 Int PD
1
K16
R2160 8.2K 5% 1/16W
HDA
D
J16
D
MF-LF 2
402
R2170 22
HDA_SDATA_OUT
73 21 HDA_SDOUT_R
F15
1
2
HDA_SDOUT
OUT
49 73
5%
BIOS Boot Select
1/16W MF-LF
R2171
402
22
TP_MLB_RAM_SIZE
J14
HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK
HDA_BITCLK
73 21 HDA_BIT_CLK_R
E15
1
Int PD
HDA_BIT_CLK
2
OUT
49 73
I/F
HDA_SDOUT
LPC_FRAME#
LPC
0
0
PCI
0
1
SPI0
1
0
SPI1
1
1
5% 1/16W MF-LF 402
R2172 22
TP_MLB_RAM_VENDOR
J15
=PP3V3R1V5_S0_MCP_HDA
23 21 8
HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA
(MXM_OK for MXM systems)
HDA_RESET*
73 21 HDA_RST_R_L
K15
1
2
Int PD
HDA_RST_L
OUT
49 73
5% 1/16W MF-LF
R2173
1
R2110
402
22
HDA_SYNC
49.9
73 21 HDA_SYNC_R
L15
1
HDA_SYNC
2
OUT
49 73
1% 5%
1/16W MF-LF 2
1/16W MF-LF
402
402
73 MCP_HDA_PULLDN_COMP
A15
HDA_PULLDN_COMP
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA
K17
MCP_GPIO_4
L17
AUD_I2C_INT_L
SLP_S3* SLP_RMGT* SLP_S5*
G17
PM_SLP_S3_L
OUT
7 32 36 63 67
J17
PM_SLP_RMGT_L
OUT
9
H17
PM_SLP_S4_L
OUT
7 36 37 63
THERM_DIODE_P THERM_DIODE_N
B11
MCP_THMDIODE_P
OUT
42 76
C11
MCP_THMDIODE_N
OUT
42 76
9 21
IN
R1961 and R2160 selects SPI0 ROM by
21 54
PP1V05_S0_MCP_PLL_NV
23
default, LPC+ debug card pulls
37 mA (A01)
20 mA
AE18
17 mA
AE17
+V_PLL_NV_H +V_PLL_SP_SPREF
LPC_FRAME# high for SPI1 ROM override. NOTE: MCP79 does not support FWH, only LPC ROMs.
PP3V3_G3_RTC
25 22 7
38 37 36 32
R2120
C
1
1
49.9K
IN
R2121
=SPI_CS1_R_L_USE_MLB
L24
1%
1%
L26
GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L
TP_SB_A20GATE
K13
TP_MCP_KBDRSTIN_L
L13
Int PU A20GATE KBRDRSTIN* Int PU SIO_PME* Int PU (S5) EXT_SMI/GPIO_32* Int
1/16W
2
2
MF-LF 402
36
IN
SMC_WAKE_SCI_L
C19
36
IN
SMC_RUNTIME_SCI_L
C18
SM_INTRUDER_L
B20
NOTE: MCP79 rev A01 does not support =PP3V3_S0_MCP
MCP_VID0/GPIO_13 MCP_VID1/GPIO_14 MCP_VID2/GPIO_15
L20
MCP_VID
OUT
21 60
M20
MCP_VID
OUT
21 60
M21
MCP_VID
OUT
21 60
SPKR
C13
MCP_SPKR
SMB_CLK0 SMB_DATA0 SMB_CLK1/MSMB_CLK SMB_DATA1/MSMB_DATA SMB_ALERT*/GPIO_64
L19
SMBUS_MCP_0_CLK
K19
SMBUS_MCP_0_DATA
G21
SMBUS_MCP_1_CLK
F21
SMBUS_MCP_1_DATA
M23
AP_PWR_EN
PU (S5)
1
M25
PM_BATLOW_L
M24
70 59
IN
PM_DPRSLPVR
M22
CPU_DPRSLPVR
36
IN
PM_PWRBTN_L
C16
25
IN
PM_SYSRST_DEBOUNCE_L
D16
PWRBTN* RSTBTN*
Int PU (S5) Int PU
RTC_RST*
1/16W MF-LF
(MGPIO2)
(MGPIO3)
D20
IN
MCP_PS_PWRGD
E20
25
IN
MCP_CPU_VLD
C17
CPU_VLD
13
IN
JTAG_MCP_TDI
E19
13
OUT
JTAG_MCP_TDO
F19
13
IN
JTAG_MCP_TMS
J19
13
IN
JTAG_MCP_TRST_L
J18
13
IN
JTAG_MCP_TCK
G19
JTAG_TDI Int JTAG_TDO JTAG_TMS Int JTAG_TRST* JTAG_TCK
25
IN
MCP_CLK25M_XTALIN
A16
25
OUT
MCP_CLK25M_XTALOUT
B16
25
IN
RTC_CLK32K_XTALIN
A19
25
OUT
RTC_CLK32K_XTALOUT
B19
PU
PU
XTALIN XTALOUT XTALIN_RTC XTALOUT_RTC
FANRPM0/GPIO_60 FANCTL0/GPIO_61 FANRPM1/GPIO_63 FANCTL1/GPIO_62
B12
MEM_EVENT_L
A12
ODD_PWR_EN_L
CPUVDD_EN
D17
D12
SMC_IG_THROTTLE_L
C12
ARB_DETECT
1
1
10K 5% 1/16W MF-LF 402
2
13 39 73
OUT
37
R2181
HDA_SYNC 24 MHz
1
14.31818 MHz
0
10K 13 39 73
BI
39 73
OUT
2
39 73
BI
5%
USER mode: Normal
1/16W MF-LF
SAFE mode: For ROMSIP
402
recovery
SPI Frequency Select
21 30 32
OUT
Connects to SMC for
IN
Frequency
SPI_DO
SPI_CLK
31 MHz
0
0
42 MHz
0
1
25 MHz
1
0
1 MHz
1
1
21 27 28 36 34
OUT
21 37
IN 21
25
OUT
SPI_CS0/GPIO_10 SPI_CLK/GPIO_11 SPI_DI/GPIO_8 SPI_DO/GPIO_9
C14
SPI_CS0_R_L
OUT
38 73
D13
SPI_CLK_R
OUT
38 48 73
NOTE: Straps not provided on this page.
C15
SPI_MISO
IN
38 48 73
B14
SPI_MOSI_R
OUT
38 48 73
SUS_CLK/GPIO_34 BUF_SIO_CLK
B18
PM_CLK32K_SUSCLK_R
OUT
25 73
AE7
TP_MCP_BUF_SIO_CLK
TEST_MODE_EN PKG_TEST
K22
B
MCP_TEST_MODE_EN
L22 1
R2163 10K
R2151
5% 1/16W
5% 1/16W
MF-LF 402
2
R2190 1K
100K
MF-LF 2
OUT
MCP_CPUVDD_EN
1
R2150
Frequency
402
automatic recovery.
PWRGD_SB PS_PWRGD
PM_RSMRST_L
25
BUF_SIO_CLK Frequency
5%
1
Int PU (S5)
IN
36
C
R2180 10K
Int PU (S5)
MISC
C20
Rev B01 will.
BOOT_MODE_USER
TP_MCP_LID_L
IN
RTC_RST_L
B
INTRUDER* LID* LLB*
SPI1 option.
8 22 23
BOOT_MODE_SAFE
2
36
So Apple designs will
not use LPC for BootROM override.
GPIO_1/PWRDN_OK/SPI_CS1
SMC_ADAPTER_EN
49.9K
1/16W MF-LF 402
OUT
1% 1/16W
2
MF-LF 402
402
=PP3V3_S0_MCP_GPIO
8 18 19
=PP3V3_S3_MCP_GPIO
8
HDA Output Caps 1
For EMI Reduction on HDA interface
R2140
1
10K
HDA_SDOUT_R HDA_BIT_CLK_R
A
C2170
1
C2172
10PF 5% 50V CERM
21 73
2
R2141
1
10K
1
R2142 10K
10K
5% 1/16W
5% 1/16W
5% 1/16W
MF-LF
MF-LF
MF-LF
MF-LF
2
402
2
402
2
5% 50V CERM
402
2
C2171
5% 1/16W MF-LF
402
2
MCP_GPIO_4
9 21
21 73
AUD_I2C_INT_L
21 54
HDA_SYNC_R
21 73
MEM_EVENT_L
21 27 28 36
402
SMC_IG_THROTTLE_L
21 37
ARB_DETECT
21
AP_PWR_EN
1
21 30 32
MCP_VID
21 60
MCP_VID
21 60
MCP_VID
21 60
1
1
C2173 10PF
5% 50V CERM
5% 50V CERM
2
2
1
1
R2156
R2157
22K
22K
22K
5%
5%
5%
5%
1/16W MF-LF
1/16W MF-LF
1/16W MF-LF
1/16W MF-LF
2
402
2
402
2
DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
REVISION
C.0.0
R
402
402
7
A
MCP HDA & MISC
R2155
100K
402
SYNC_DATE=03/24/2009
PAGE TITLE
1
R2147
BRANCH
PAGE
21 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
SYNC_MASTER=K24_MLB
2
10PF
402
100K
HDA_RST_R_L
402
1
R2154
21 73
10PF 2
R2143
5% 1/16W 402
1
6
5
4
3
2
1
8
7
6
5
4
OMIT
MCP79-TOPO-B
BGA
BGA
AH37 AH38 AJ39
D
AJ8 AK10 AK33 AK34 AK37 AK4 AK40 AL36 AL40 AL5 AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38 AM5 AM6 AM7 AM9
C
AP26 AN28 AN30 AN39 AN4 Y7 AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37 AP4 AP40 AP7 AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29 AT33
B
AT6 AT7 AT9 AY21 AY22 L12 AU12 AU28 AP33 AU32 AR30 AU36 AU38 AU4 G28 F20 AV28 AV32 AV36 AV4 AV7 AW11 G20 AR43 AW43
A
AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41
23 8
GND253 GND254 GND255 GND256 GND257 GND258 GND259 GND260 GND261 GND262 GND263 GND264 GND265 GND266 GND267 GND268 GND269 GND270 GND271 GND272 GND273 GND274 GND275 GND276 GND277 GND278 GND279 GND280 GND281 GND282 GND283 GND284 GND285 GND286 GND287 GND288 GND289 GND290 GND291 GND292 GND293 GND294 GND295 GND296 GND297 GND298 GND299 GND300 GND301 GND302 GND303 GND304 GND305 GND306 GND307 GND308 GND309 GND310 GND311 GND312 GND313 GND314 GND315 GND316 GND317 GND318 GND319 GND320 GND321 GND322 GND323 GND324 GND325 GND326 GND327 GND328 GND329 GND330 GND331 GND332 GND333 GND334 GND335 GND336 GND337 GND338 GND339 GND340 GND341 GND342 GND343
(10 OF 11)
=PPVCORE_S0_MCP
AV40
23065 mA (A01, 1.2V)
AA25
BA1
16996 mA (A01, 1.0V)
AC23 U25
BA4 AW31
AH12
AY6
AG10
L35
AG5
BC33
Y21
BC37
Y23
BC41
AA16
AY14
AA26
BC5
AA27
C2
AA28
D10
AC16
D14
AC17
D15
AC18
D18
AC19
D19
AC20
D22
AC21
D23
AA17
D26
AC24
D30
AC25
D37
AC26
D6
AC27
E13
AC28
E17
AD21
E21
AD23
E25
W27
E29
V25
E33
AA18
F12
AE19
F16
AE21
F32
AE23
F8
AE25
G10
AE26
G12
AE27
G14
AE28
G16
AF10
BC12
AF11
G22
AA19
G24
AF2
AW20
AF21
G34
AF23
G4
AF25
G43
AF3
G6
AF4
G8
AF7
H11
AH23
H15
AF9
AW35
AA20
H23
AG11
AN8
AG12
G40
AG21
J12
AG23
J8
AG25
K10
AG3
K12
AG4
K18
AA21
K26
AG6
K37
AG7
K4
AG8
K40
AG9
K8
AH1
AU1
AH10
L40
AH11
L43
W26
L5
AH2
M10
AA23
M34
W28
M35
AH25
M37
AH21
Y28
AH3
Y33
AH4
Y34
AH5
Y35
AH6
Y37
AH7
Y38
AH9
AB17
AA24
AB16
W21
AN26
W23
AD7
W25 AF12
M11
+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6 +VDD_CORE7 +VDD_CORE8 +VDD_CORE9 +VDD_CORE10 +VDD_CORE11 +VDD_CORE12 +VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19 +VDD_CORE20 +VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30 +VDD_CORE31 +VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37 +VDD_CORE38 +VDD_CORE39 +VDD_CORE40 +VDD_CORE41 +VDD_CORE42 +VDD_CORE43 +VDD_CORE44 +VDD_CORE45 +VDD_CORE46 +VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54 +VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81
POWER
AH34
GND
(11 OF 11)
GND161 GND162 GND163 GND164 GND165 GND166 GND167 GND168 GND169 GND170 GND171 GND172 GND173 GND174 GND175 GND176 GND177 GND178 GND179 GND180 GND181 GND182 GND183 GND184 GND185 GND186 GND187 GND188 GND189 GND190 GND191 GND192 GND193 GND194 GND195 GND196 GND197 GND198 GND199 GND200 GND201 GND202 GND203 GND204 GND205 GND206 GND207 GND208 GND209 GND210 GND211 GND212 GND213 GND214 GND215 GND216 GND217 GND218 GND219 GND220 GND221 GND222 GND223 GND224 GND225 GND226 GND227 GND228 GND229 GND230 GND231 GND232 GND233 GND234 GND235 GND236 GND237 GND238 GND239 GND240 GND241 GND242 GND243 GND244 GND245 GND246 GND247 GND248 GND249 GND250 GND251 GND252
1
U1400
MCP79-TOPO-B
AH33
2
OMIT
U1400
AH26
3
=PP1V05_S0_MCP_FSB
+VTT_CPU1 +VTT_CPU2 +VTT_CPU3 +VTT_CPU4 +VTT_CPU5 +VTT_CPU6 +VTT_CPU7 +VTT_CPU8 +VTT_CPU9 +VTT_CPU10 +VTT_CPU11 +VTT_CPU12 +VTT_CPU13 +VTT_CPU14 +VTT_CPU15 +VTT_CPU16 +VTT_CPU17 +VTT_CPU18 +VTT_CPU19 +VTT_CPU20 +VTT_CPU21 +VTT_CPU22 +VTT_CPU23 +VTT_CPU24 +VTT_CPU25 +VTT_CPU26 +VTT_CPU27 +VTT_CPU28 +VTT_CPU29 +VTT_CPU30 +VTT_CPU31 +VTT_CPU32 +VTT_CPU33 +VTT_CPU34 +VTT_CPU35 +VTT_CPU36 +VTT_CPU37 +VTT_CPU38 +VTT_CPU39 +VTT_CPU40 +VTT_CPU41 +VTT_CPU42 +VTT_CPU43 +VTT_CPU44 +VTT_CPU45 +VTT_CPU46 +VTT_CPU47 +VTT_CPU48 +VTT_CPU49 +VTT_CPU50 +VTT_CPU51 +VTT_CPU52
R32
1139 mA
8 14 23
1182 mA (A01)
AC32 E40 J36 N32 T32
D
U32 V32 W32 P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32 B41 B42 C40 C41 C42 D39 D40 D41 E38 E39 F37 F38 F39
C
G36 G37 G38 H35 H37 J34 J35 K33 K34 K35 L32 L33 L34 M31 M32 M33 N31 P32 Y32 AA32
+VTT_CPUCLK
AG32
+3.3V_1 +3.3V_2 +3.3V_3 +3.3V_4 +3.3V_5 +3.3V_6 +3.3V_7 +3.3V_8
AD10
43 mA
=PP3V3_S0_MCP
8 21 23
450 mA (A01)
B
AE8 AB10 AD9 Y10 AB11 AA8 Y9
=PP3V3_S5_MCP
+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4
G18
+3.3V_DUAL_USB1 +3.3V_DUAL_USB2 +3.3V_DUAL_USB3 +3.3V_DUAL_USB4
G26
+VDD_AUXC1 +VDD_AUXC2 +VDD_AUXC3
T21
16 mA
8 23
266 mA (A01)
H19 J20 K20
250 mA
H27 J28 K28
=PP1V05_S5_MCP_VDD_AUXC
8 23
AA4 AB19
25 21 7
PP3V3_G3_RTC
AY13
10 uA (G3)
P11
80 uA (S0)
A20
+VBAT
105 mA (A01)
U21 V21
Y6
SYNC_MASTER=K24_MLB
T11
PAGE TITLE
SYNC_DATE=04/06/2009
Y11
DRAWING NUMBER
AH16
Apple Inc.
T22
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
C.0.0 BRANCH
PAGE
22 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
7
SIZE
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
8
A
MCP Power & Ground
V11
6
5
4
3
2
1
8
7
MCP Core Power 22 8
6
5
4
3
2
1
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
=PPVCORE_S0_MCP 23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
C2500 (No IG vs. EG data)
D
1
C2501
1
C2502
1
C2503
4.7UF
4.7UF
4.7UF
4.7UF
20% 4V X5R-1 402
20% 4V X5R-1 402
20% 4V X5R-1 402
20% 4V X5R-1 402
2
2
2
1
1
2
2
1
C2504
1
C2506
1
C2507
1
C2508
C2509
1
1
C2510
1
C2511
C2512
1UF
1UF
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10% 10V X5R 402-1
10% 10V X5R 402-1
10% 10V X5R 402-1
10% 10V X5R 402-1
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
2
MCP PCIE (DVDD) Power 8
1
C2505
1UF
2
2
2
2
2
2
2
1
C2513 0.1UF
2
20% 10V CERM 402
MCP SATA (DVDD) Power
=PP1V05_S0_MCP_PEX_DVDD 57 mA (A01)
8
43 mA (A01)
333 mA (A01)
Apple: 5x 2.2uF 0402 (11 uF)
30-OHM-5A
=PP1V05_S0_MCP_AVDD_UF
D
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
L2570
=PP1V05_S0_MCP_SATA_DVDD
8
1
PP1V05_S0_MCP_PEX_AVDD
8
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
206 mA (A01)
0603
C2515
1
1
2
2
C2516
4.7UF 20% 4V X5R-1 402
1
1UF
1
C2517 1UF
10% 10V X5R 402-1
2
1
C2518 0.1uF
10% 10V X5R 402-1
2
C2519
C2520
0.1uF
20% 10V CERM 402
2
1
1
2
2
4.7UF
20% 10V CERM 402
20% 4V X5R-1 402
1
C2521 0.1uF
1
C2570
C2571
2.2UF
20% 10V CERM 402
2
1
2.2UF
20% 6.3V CERM 402-LF
C2572 2.2UF
20% 6.3V CERM 402-LF
2
1
2
1
C2573 2.2UF
20% 6.3V CERM 402-LF
2
C2574 2.2UF
20% 6.3V CERM 402-LF
2
20% 6.3V CERM 402-LF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) MCP 1.05V AUX Power 22 8
MCP 1.05V RMGT Power
=PP1V05_S5_MCP_VDD_AUXC
18 8
105 mA (A01)
L2575
Apple: 2x 2.2uF 0402 (4.4 uF)
30-OHM-5A
=PP1V05_ENET_MCP_RMGT
PP1V05_S0_MCP_SATA_AVDD
1
131 mA (A01)
8
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
127 mA (A01)
0603
1
2
MCP FSB (VTT) Power 22 14 8
1
C2525
C2526
0.1uF
0.1uF
20% 10V CERM 402
20% 10V CERM 402
2
C2528
1
1
4.7UF 20% 4V X5R-1 402
2
2
1
C2529
2.2UF
20% 10V CERM 402
20% 6.3V CERM 402-LF
2
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
C2576 2.2UF 20% 6.3V CERM 402-LF
2
L2580
Apple: 7x 2.2uF 0402 (15.4 uF)
=PP1V05_S0_MCP_FSB
1
C2575
0.1uF
62 8
1182 mA (A01)
30-OHM-1.7A
=PP1V05_S0_MCP_PLL_UF 562 mA (A01)
PP1V05_S0_MCP_PLL_FSB
1
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
14
270 mA (A01)
0402
C
1
2
1
C2530
1
C2531
C2532
1
C2533
1
C2534
1
1
C2535
C2536
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
2
2
2
2
2
2
C2580
1
1
2
2
4.7UF
10UF 20% 6.3V X5R
2
603
MCP Memory Power 16 8
1
C2592
20% 4V X5R-1 402
C
C2581 0.1UF 20% 10V CERM 402
L2582 30-OHM-1.7A
=PP1V8R1V5_S0_MCP_MEM 1
4771 mA (A01, DDR3)
PP1V05_S0_MCP_PLL_PEX
17
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
84 mA (A01)
0402
C2540
1
1
20% 4V X5R-1 402
2
1
C2541
4.7UF 2
1
C2545
1
C2549
C2582
0.1UF
0.1UF
0.1UF
0.1UF
4.7UF
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
2
2
C2547
1
0.1UF
20% 10V CERM 402
2
C2546
1
0.1UF
20% 10V CERM 402
2
C2544
1
0.1UF
20% 10V CERM 402
2
C2543
1
0.1UF
20% 10V CERM 402
2
C2542
1
0.1UF
C2548
2
2
20% 4V X5R-1 402
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) MCP 3.3V Power 22 21 8
=PP3V3_S0_MCP
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
L2555
Apple: 4x 2.2uF 0402 (8.8 uF)
450 mA (A01)
1
19 mA (A01)
2
2
C2583 0.1UF
30-OHM-1.7A
PP3V3_S0_MCP_PLL_USB
20
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
2
1
20% 10V CERM 402
L2584
Apple: 1x 2.2uF 0402 (2.2 uF)
30-OHM-1.7A
=PP3V3_S0_MCP_PLL_UF
8
1
1
PP1V05_S0_MCP_PLL_SATA
20
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
19 mA (A01)
84 mA (A01)
0402
0402
1
2
1
C2550
1
C2551
C2552
1
1
C2553
2.2UF
2.2UF
2.2UF
2.2UF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
2
2
2
2
C2584
C2555
2.2UF
1
1
2
2
4.7UF 20% 4V X5R-1 402
C2585 0.1UF 20% 10V CERM 402
B
B L2586 MCP 3.3V AUX/USB Power 22 8
=PP3V3_S5_MCP
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
MCP 3.3V Ethernet Power
Apple: 1x 2.2uF 0402 (2.2 uF) 23 18 8
266 mA (A01)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
30-OHM-1.7A
Apple: 1x 2.2uF 0402 (2.2 uF)
=PP3V3_ENET_MCP_RMGT
1
1
2
PP1V05_S0_MCP_PLL_CORE
16
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
87 mA (A01)
0402
83 mA (A01) 1
C2560
C2564
C2586
2.2UF
2.2UF
4.7UF
20% 6.3V CERM 402-LF
20% 6.3V CERM 402-LF
2
20% 4V X5R-1 402
1
1
2
2
C2587 0.1UF 20% 10V CERM 402
L2588 MCP 3.3V/1.5V HDA Power 21 8
=PP3V3R1V5_S0_MCP_HDA
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
30-OHM-1.7A
Apple: 1x 2.2uF 0402 (2.2 uF)
1
PP1V05_S0_MCP_PLL_NV
21
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
37 mA (A01)
0402
7 mA (A01) 1
C2562
C2588
2.2UF 2
1
1
4.7UF
MCP79 Ethernet VRef
20% 6.3V CERM 402-LF
23 18 8
20% 4V X5R-1 402
C2589
1
0.1UF 2
2
20% 10V CERM 402
C2590 0.1UF
2
20% 10V CERM 402
=PP3V3_ENET_MCP_RMGT
R2591
1
1.47K 1% 1/16W MF-LF 402
A L2595 8
5 mA (A01)
SYNC_MASTER=K24_MLB
2
PP1V05_ENET_MCP_PLL_MAC
1
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
MCP_MII_VREF
18
R2590 C2595
1
1
4.7UF 20% 4V X5R-1 402
C2596
A
2
MCP Standard Decoupling
18
DRAWING NUMBER
1 1
1.47K 1% 1/16W MF-LF 402
0.1UF 2
OUT
5 mA (A01)
0402
20% 10V CERM 402
C2591
Apple Inc.
0.1UF 20% 10V 2
2
7
051-7982
CERM 402
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
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REVISION
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Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
SYNC_DATE=04/06/2009
PAGE TITLE
30-OHM-1.7A
=PP1V05_ENET_MCP_PLL_MAC
6
5
4
3
2
1
8
7
6
5
4
3
2
1
WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) NO STUFF Apple: 1x 2.2uF 0402 (2.2 uF) 18 8
8
190 mA (A01, 1.8V)
C2610
1
D
PP3V3_S0_MCP_DAC
0402
NO STUFF 1
20% 6.3V CERM 402-LF
1
C2650 20% 6.3V CERM 402-LF
206 mA (A01)
R2651 0
2.2UF 2
18 8
18
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
2
2.2UF 2
Apple: 2x 2.2uF 0402 (4.4 uF)
30-OHM-1.7A
=PP3V3_S0_MCP_DAC_UF 206 mA (A01)
1
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
L2650
=PP3V3R1V8_S0_MCP_IFP_VDD
5% 1/16W
D
MF-LF
2
402
=PP1V05_S0_MCP_HDMI_VDD 95 mA (A01)
C2615
1
1
2
2
C2616
4.7UF 20% 4V X5R-1 402
72 18
MCP_HDMI_RSET
72 18
MCP_HDMI_VPROBE
C
1
NO STUFF
C2620
0.1UF
1
72 18
MCP_IFPAB_RSET
72 18
MCP_IFPAB_VPROBE
20% 10V 2
2
NO STUFF
R2620
NO STUFF
1K
C2630
1% 1/16W
0.1UF CERM 402
20% 10V CERM 402
1 1
CERM 402
C
1% 1/16W
20% 10V
MF-LF 402
R2630 1K
0.1UF 2
2
MF-LF 402
WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640 8
16 mA (A01)
Apple: ???
30-OHM-1.7A
=PP3V3_S0_MCP_VPLL_UF 1
PP3V3_S0_MCP_VPLL MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
2
18
16 mA (A01)
0402
C2640
1
1
2
2
4.7UF 20% 6.3V CERM 603
C2641 0.1uF 20% 10V CERM 402
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
MCP Graphics Support
SYNC FROM T18 REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672 NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650) CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC REMOVE HDCP ROMS
DRAWING NUMBER
Apple Inc. NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
7
SIZE
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26 OF 109 SHEET
OF
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
051-7982
6
5
4
3
2
1
8
7
6
5
4
3
2
1
Platform Reset Connections LPC Reset (Unbuffered) R2820 0 8 =PP3V42_G3H_RTC_D
1
D
PP3V3_G3_RTC
2 5% 1/16W MF-LF 402
R2881
7 21 22
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
33
PLACEMENT_NOTE=Place close to U1400
73 19
LPC_RESET_L
IN
1
1
10%
38
2
SMC_LRESET_L
OUT
36
2
BKLT_PLT_RST_L
OUT
69
MINI_RESET_L
OUT
30
PCA9557D_RESET_L
OUT
26
D
33 1 5% 1/16W MF-LF 402
PLACEMENT_NOTE=Place close to U1400
2
CERM 402
OUT
R2883
1UF 6.3V
DEBUG_RESET_L
2 5% 1/16W MF-LF 402
C2819
PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79
PLACE C2819 CLOSE TO MCP79
PCIE Reset (Unbuffered) R2892 0 17
PCIE_RESET_L
IN
1 5% 1/16W MF-LF 402
R2891 0 1
RTC Crystal
2 5% 1/16W MF-LF 402
C2810
R2871 0 1
12pF 21
IN
1
RTC_CLK32K_XTALOUT
R2810
1
C
C
2
RTC_CLK32K_XTALOUT_R
NO STUFF 1
4
CRITICAL
10M 5% 1/16W MF-LF 402
21
OUT
Y2810 32.768K 2
C2811 1
R2811
5% 1/16W MF-LF 402
5% 50V CERM 402
0 5% 1/16W MF-LF 402
7X1.5X1.4-SM
12pF 1
RTC_CLK32K_XTALIN
2
5% 50V CERM 402
MCP 25MHz Crystal
C2815
R2870
12pF 21
IN
1
MCP_CLK25M_XTALOUT
R2815
1
1
R2816
MEM_VTT_EN_R
1
4
2
2
Y2815
OUT
58 64
LPC_CLK33M_SMC
OUT
36 73
LPC_CLK33M_LPCPLUS
OUT
38 73
PM_CLK32K_SUSCLK
OUT
36 73
33
PLACEMENT_NOTE=Place close to U1400
LPC_CLK33M_SMC_R
1
2 5% 1/16W MF-LF 402
NC NC
R2826 33 1
1
C2816
PLACEMENT_NOTE=Place close to U1400
12pF 1
MCP_CLK25M_XTALIN
2
5% 50V CERM 402
MCP S0 PWRGD & CPU_VLD
2 5% 1/16W MF-LF 402
B
R2829 22 73 21
IN
PM_CLK32K_SUSCLK_R
1 PLACEMENT_NOTE=Place close to U1400
8
=DDRVTT_EN
R2825 IN
3
CRITICAL
MEM_VTT_EN MAKE_BASE=TRUE
2 5% 1/16W MF-LF 402
73 19
25.0000M
B
IN
MCP_CLK25M_XTALOUT_R
SM-3.2X2.5MM
OUT
19
2
1M
21
33
2
5% 50V CERM 402
0 5% 1/16W MF-LF 402
NO STUFF
5% 1/16W MF-LF 402
2
2
=PP3V3_S5_MCPPWRGD
2 5% 1/16W MF-LF 402
MCPSEQ_SMC 1
C2850 0.1UF
2
20% 10V CERM 402
Reset Button 36
IN
PM_SYSRST_L
MCPSEQ_SMC 5 TC7SZ08AFEAPE 63 36
IN
ALL_SYS_PWRGD
2
U2850 59
IN
VR_PWRGOOD_DELAY
1
Y
4
XDP
R2853
SOT665
A
R2898
0 S0_AND_IMVP_PGOOD
1
OUT
21
13 10
IN
XDP_DBRESET_L
1
5% 1/16W MF-LF 402
B 3
33 2
5% 1/16W MF-LF 402
1
R2890
R2852
1
NO STUFF
PM_SYSRST_DEBOUNCE_L
2
OUT
21
NO STUFF
5% 1/16W MF-LF
0 5% 1/16W MF-LF 402
MCPSEQ_MIX
10K pull-up to 3.3V S0 inside MCP
R2899
0 MCP_PS_PWRGD
2
1
402
C2899 1UF 10% 10V
SILK_PART=SYS RST
2
2
X5R 402
0 1
2
5% 1/16W MF-LF 402
MCPSEQ_MIX
R2851 0 1
A
MCP_CPU_VLD
2
5% 1/16W MF-LF 402
OUT
21
MCPSEQ_SMC
R2850 0
21
IN
MCP_CPUVDD_EN
1
2
SYNC_MASTER=K24_MLB PLACEMENT_NOTE=Place close to U1400
5% 1/16W MF-LF 402
SYNC FROM T18 CHANGE RESET BUTTOM TO RESET PADS REMOVE UNUSED PCIE RESET SIGNALS REMOVE R2824 AND NET PCI_CLK33M_SLOT_A CHANGE RTC COIN CELL TO LDO & SUPERCAP ALIAS MEM_VTT_EN TO =DDRVTT_EN CHANGE Y2810 AND U2850 TO SMALLER PARTS
MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections, but results in MCP79 ROMSIP sequence happening after CPU powers up. MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization. SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).
7
A
SB Misc DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
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28 OF 109 SHEET
OF
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
8
SYNC_DATE=02/15/2009
PAGE TITLE
6
5
4
3
2
1
8
7
6
5
4
3
2
1
Page Notes MEM A VREF DQ
Power aliases required by this page:
MEM A VREF CA
MEM B VREF DQ
MEM B VREF CA
CPU FSB VREF
- =PP3V3_S3_VREFMRGN
DAC channel
A
B
A
B
C
- =PP3V3_S5_VREFMRGN
Min DAC code
0x00
0x00
0x00
0x00
0x00
- =PPVTT_S3_DDR_BUF
Max DAC code Signal aliases required by this page:
Max sink I
- =I2C_VREFDACS_SCL
0x87
0x87
0x87
0x87
0x55
-3.75 mA
-3.75 mA
-3.75 mA
-3.75 mA
-0.91 mA
Max source I
5 mA
5 mA
5 mA
5 mA
- =I2C_VREFDACS_SDA
Nominal Vref
0.75 V
0.75 V
0.75 V
0.75 V
0.70 V
- =I2C_PCA9557D_SCL
Min Vref
0.375 V
0.375 V
0.375 V
0.375 V
0.091 V
- =I2C_PCA9557D_SDA
Max Vref
1.250 V
1.250 V
1.250 V
1.250 V
Vref Stepping
6.5 mV
6.5 mV
6.5 mV
6.5 mV
SO-DIMM A and SO-DIMM B Vref settings should be margined separately
0.52 mA
(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
1.044 V
=PPVTT_S3_DDR_BUF 58 8
D
D
11.2 mV
BOM options provided by this page:
10mA max load
(per DAC LSB) VREFMRGN NO_VREFMRGN
R2903
VREFMRGN
200 1
B1
VREFMRGN 1
A2
C2903
V+
0.1UF 2
=PP3V3_S3_VREFMRGN 8
U2902
A3
UCSP A1
1
VREFMRGN_DQ_SODIMMA_BUF
26 VREFMRGN_DQ_SODIMMA_EN
0.1UF 20% 10V CERM 402 B1 C2
V+
VREFMRGN C3
VDD
39
IN
=I2C_VREFDACS_SCL
6 SCL
BI
=I2C_VREFDACS_SDA
7 SDA 9 A0
ADDR=0x98(WR)/0x99(RD)
C
VOUTA
1
VREFMRGN_DQ_SODIMM
VOUTB
2
VREFMRGN_CA_SODIMM
VOUTC
4
VREFMRGN_CPUFSB
VOUTD
5
1
VREFMRGN_DQ_SODIMMB_BUF
5% 1/16W MF-LF 402 B1
VREFMRGN 1
GND 3
A2
C2904
V+
0.1UF 2
A3
1
1
VREFMRGN_CA_SODIMMA_BUF
U2903
2 1
UCSP C1
1
VREFMRGN_CA_SODIMMB_BUF
26 VREFMRGN_CA_SODIMMB_EN
B1
2
U2904
A3
2
Place close to J3200.126
1
VREFMRGN
MAX4253 UCSP A1
VREFMRGN
20% 10V CERM 402
5% 1/16W MF-LF 402
2 1% 1/16W MF-LF 402
C4
V+
28 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
100
V-
A2
0.1UF
PP0V75_S3_MEM_VREFCA_B
R2912
100K
C2905
2
1% 1/16W MF-LF 402
MAX4253
R2908
VREFMRGN
200
VREFMRGN
VREFMRGN
B4
1
Place close to J3100.126
R2911 1
100K 5% 1/16W MF-LF 402
2 1% 1/16W MF-LF 402
26 VREFMRGN_CA_SODIMMA_EN
VREFMRGN
27 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
100
A1
R2907
C3
C
PP0V75_S3_MEM_VREFCA_A
R2910
UCSP
B4
B1
2 1% 1/16W MF-LF 402
A4
V+
VREFMRGN
200
MAX4253
V-
C2
Place close to J3200.1
R2909 VREFMRGN
U2903
VREFMRGN
20% 10V CERM 402
2 1% 1/16W MF-LF 402
26 VREFMRGN_DQ_SODIMMB_EN
R2902
NC
28 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
100
C1 C4
V-
100K
10 A1
PP0V75_S3_MEM_VREFDQ_B
R2906
UCSP
B4
MSOP
DAC5574
39
1% 1/16W MF-LF 402
MAX4253
VREFMRGN
U2900
8
5% 1/16W MF-LF 402
U2902
2
VREFMRGN
1
2
VREFMRGN
200 1
100K
2
20% 6.3V CERM 402-LF
Place close to J3100.1
R2905
2
R2901
C2901
1
1
2.2UF
2 1% 1/16W MF-LF 402
A4
V-
VREFMRGN
C2900
27 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
100
B4
VREFMRGN
PP0V75_S3_MEM_VREFDQ_A
R2904
MAX4253
VREFMRGN
20% 10V CERM 402
2 1% 1/16W MF-LF 402
NC
A4
VB4
B
B B1 C2
VREFMRGN
V+
2
C3
U2901 QFN
4 5
39 39
IN BI
=I2C_PCA9557D_SCL
1
=I2C_PCA9557D_SDA
2
A0 A1 A2
SCL SDA THRM 17
PAD
26 VREFMRGN_CPUFSB_EN
RESET*
6
NC
7
R2913
VREFMRGN_CPUFSB_EN 26
100K
VREFMRGN_CA_SODIMMA_EN
9
5% 1/16W MF-LF 402
26 VREFMRGN_DQ_SODIMMA_EN
10
26 VREFMRGN_CA_SODIMMB_EN
11
14
OUT
10 70
VREFMRGN
26 VREFMRGN_DQ_SODIMMB_EN
12 13
CPU_GTLREF
Place close to U1000.AD26
26
NC NC PCA9557D_RESET_L
15
IN
25
GND 8
3
P0 P1 P2 P3 P4 P5 P6 P7
2 1% 1/16W MF-LF 402
C4
V-
VREFMRGN
100 1
VREFMRGN_CPUFSB_BUF
B4
PCA9557
ADDR=0x30(WR)/0x31(RD)
C1
VREFMRGN
VCC
20% 10V CERM 402
R2914
UCSP
2
0.1UF
U2904 MAX4253
VREFMRGN
1
C2902
16
1
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
FSB/DDR3 Vref Margining
Required zero ohm resistors when no VREF margining circuit stuffed
DRAWING NUMBER
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2903
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2905
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2909
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2911
CRITICAL
NO_VREFMRGN
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
29 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
Page Notes
3
2
1
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE) 8 =PP1V5_S3_MEM_A
Power aliases required by this page: - =PP1V5_S0_MEM_A 1
- =PP1V5_S3_MEM_A
C3100
1
10UF
- =PP0V75_S0_MEM_VTT_A - =PPSPD_S0_MEM_A (2.5 - 3.3V)
2
C3101
1
2
20% 6.3V X5R
2
603
603
1
C3110
1
C3111
0.1UF
10UF
20% 6.3V X5R
0.1UF
20% 10V CERM 402
1
C3112 0.1UF
20% 10V CERM 402
2
2
1
C3113 0.1UF
20% 10V CERM 402
2
1
C3114 0.1UF
20% 10V CERM 402
2
1
C3115 0.1UF
20% 10V CERM 402
2
1
C3116 0.1UF
20% 10V CERM 402
2
C3117 0.1UF
20% 10V CERM 402
2
20% 10V CERM 402
Signal aliases required by this page: - =I2C_SODIMMA_SCL - =I2C_SODIMMA_SDA
D
BOM options provided by this page:
26 PP0V75_S3_MEM_VREFDQ_A (NONE)
1
C3130
C3131
2.2UF
0.1UF
20% 6.3V 2
20% 10V 2
CERM 402-LF
CERM 402
1 3
75
NC 71 15
IN
77 79
MEM_A_BA
81 71 15
IN
MEM_A_A
71 15
IN
MEM_A_A
83 85 87
71 15
IN
MEM_A_A
71 15
IN
MEM_A_A
89 91 93
71 15
IN
MEM_A_A
71 15
IN
MEM_A_A
95 97 99
C
71 15 71 15
IN
MEM_A_CLK_P
101
IN
MEM_A_CLK_N
103 105
71 15 71 15
71 15
IN
MEM_A_A
107
IN
MEM_A_BA
109
IN
MEM_A_WE_L
113
MEM_A_CAS_L
115
111
71 15
IN
117 71 15 71 15
IN IN
MEM_A_A
119
MEM_A_CS_L
121 123
NC
125 127
71 15
BI
MEM_A_DQ
129
71 15
BI
MEM_A_DQ
131 133
71 15
BI
MEM_A_DQS_N
135
71 15
BI
MEM_A_DQS_P
137 139
71 15
BI
MEM_A_DQ
141
71 15
BI
MEM_A_DQ
143 145
BI
MEM_A_DQ
147
71 15
BI
MEM_A_DQ
149
71 15
IN
MEM_A_DM
153
71 15
151
155
B
71 15
BI
MEM_A_DQ
157
71 15
BI
MEM_A_DQ
159 161
71 15
BI
MEM_A_DQ
163
71 15
BI
MEM_A_DQ
165 167
71 15
BI
MEM_A_DQS_N
169
71 15
BI
MEM_A_DQS_P
171
BI
MEM_A_DQ
175
BI
MEM_A_DQ
177
173 71 15 71 15
179 71 15
BI
MEM_A_DQ
181
71 15
BI
MEM_A_DQ
183 185
71 15
IN
MEM_A_DM
187 189
71 15
BI
MEM_A_DQ
191
71 15
BI
MEM_A_DQ
193 195
MEM_A_SA
197
MEM_A_SA
201
199
8 =PPSPD_S0_MEM_A
203
1 1
A
C3140
10K
2.2UF
402-LF
2
MEM_A_CKE
IN
15 71
76
MEM_A_A
IN
9
2
71 15
BI
MEM_A_DQ
5
BI
MEM_A_DQ
7
80
MEM_A_A
IN
15 71
71 15
IN
11
MEM_A_DM
13
82 84
MEM_A_A
IN
15 71
71 15
86
MEM_A_A
IN
15 71
71 15
BI
MEM_A_DQ
15
BI
MEM_A_DQ
17 19
88 90
MEM_A_A
IN
15 71
71 15
BI
MEM_A_DQ
92
MEM_A_A
IN
15 71
71 15
BI
MEM_A_DQ
21 23 25
94 96
MEM_A_A
98
MEM_A_A
IN
15 71
71 15
BI
MEM_A_DQS_N
IN
15 71
71 15
BI
MEM_A_DQS_P
27 29 31
100 102
MEM_A_CLK_P
104
MEM_A_CLK_N
IN
15 71
71 15
IN
15 71
71 15
BI
MEM_A_DQ
33
BI
MEM_A_DQ
35 37
106 108
MEM_A_BA
110
MEM_A_RAS_L
MEM_A_CS_L
IN
15 71
71 15
IN
15 71
71 15
IN
15 71
71 15
BI
MEM_A_DQ
39
BI
MEM_A_DQ
41
BI
MEM_A_DQS_N
45
MEM_A_DQS_P
47
43
112 114 116
MEM_A_ODT
IN
71 15
15 71
BI
49
118 120 122
MEM_A_ODT
IN
15 71
71 15 71 15
NC
BI BI
MEM_A_DQ
51
MEM_A_DQ
53 55
124 126
71 15
128
71 15
130
MEM_A_DQ
BI
15 71
132
MEM_A_DQ
BI
15 71
BI
MEM_A_DQ
57
BI
MEM_A_DQ
59 61
71 15
IN
63
MEM_A_DM
65
134 136
MEM_A_DM
IN
15 71
138 140
MEM_A_DQ
BI
15 71
142
MEM_A_DQ
BI
15 71
146
MEM_A_DQ
BI
15 71
148
MEM_A_DQ
BI
15 71
152
MEM_A_DQS_N
BI
15 71
154
MEM_A_DQS_P
BI
15 71
158
MEM_A_DQ
BI
15 71
160
MEM_A_DQ
BI
15 71
164
MEM_A_DQ
BI
15 71
166
MEM_A_DQ
BI
MEM_A_DM
IN
174
MEM_A_DQ
BI
15 71
176
MEM_A_DQ
BI
15 71
180
MEM_A_DQ
BI
15 71
182
MEM_A_DQ
BI
15 71
71 15
BI
MEM_A_DQ
67
71 15
BI
MEM_A_DQ
69 71
VREFDQ VSS VSS OMIT DQ4 DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* J3100 DQS0 DM0 F-RT-THB VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 RESET* DQS1 VSS VSS DQ14 DQ10 DQ15 DQ11 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 VSS DQS2 DQ22 VSS DQ23 DQ18 VSS DQ19 DQ28 VSS DQ24 DQ29 VSS DQ25 VSS DQS3* DQS3 DM3 VSS VSS DQ30 DQ26 DQ31 DQ27 VSS VSS
2 4
MEM_A_DQ
BI
15 71
6
MEM_A_DQ
BI
15 71
10
MEM_A_DQS_N
BI
15 71
12
MEM_A_DQS_P
BI
15 71
16
MEM_A_DQ
BI
15 71
18
MEM_A_DQ
BI
15 71
22
MEM_A_DQ
BI
15 71
24
MEM_A_DQ
BI
8
14
20
15 71
26 28
MEM_A_DM
IN
15 71
30
MEM_RESET_L
IN
28 29
34
MEM_A_DQ
BI
36
MEM_A_DQ
BI
15 71
32 15 71
C
38 40
MEM_A_DQ
BI
15 71
42
MEM_A_DQ
BI
15 71
44 46
MEM_A_DM
IN
50
MEM_A_DQ
BI
15 71
52
MEM_A_DQ
BI
15 71
56
MEM_A_DQ
BI
15 71
58
MEM_A_DQ
BI
15 71
62
MEM_A_DQS_N
BI
15 71
64
MEM_A_DQS_P
BI
15 71
68
MEM_A_DQ
BI
15 71
70
MEM_A_DQ
BI
15 71
15 71
48
54
60
66
72
KEY
144
516-0201
150
156
B
162
15 71
168 170
15 71
172
PP0V75_S3_MEM_VREFCA_A
26
178
1
C3135
184
2.2UF
186
20% 6.3V
188
MEM_A_DQS_N
BI
15 71
MEM_A_DQS_P
BI
15 71
192
MEM_A_DQ
BI
15 71
194
MEM_A_DQ
BI
2
1
C3136 0.1UF 20% 10V
2
CERM 402-LF
CERM 402
190
15 71
196 198
MEM_EVENT_L
OUT
21 28 36
200
=I2C_SODIMMA_SDA
BI
202
=I2C_SODIMMA_SCL
IN
"Factory" (top) slot
39 39
204
=PP0V75_S0_MEM_VTT_A
8
R3141 1
C3150
1
2.2UF
1/16W
MF-LF 402
71 15
9
78
5%
1/16W
CERM
CKE0 CKE1 VDD OMIT VDD NC J3100 A15 A14 BA2 F-RT-THB VDD VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK0 CK1 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD ODT1 A13 NC S1* VDD VDD VREFCA TEST VSS VSS DQ36 DQ32 DQ33 DQ37 VSS VSS DQS4* DM4 DQS4 VSS DQ38 VSS DQ34 DQ39 DQ35 VSS VSS DQ44 DQ40 DQ45 DQ41 VSS VSS DQS5* DQS5 DM5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ55 DQ50 VSS DQ51 VSS DQ60 DQ61 DQ56 DQ57 VSS VSS DQS7* DM7 DQS7 VSS VSS DQ62 DQ58 DQ63 DQ59 VSS VSS SA0 EVENT* VDDSPD SDA SA1 SCL VTT VTT
74
10K
5%
20% 6.3V 2
1
R3140
KEY
(SYMBOL 2 OF 2)
IN
73
MEM_A_CKE
DDR3-SODIMM-DUAL-M97-3
71 15
(SYMBOL 1 OF 2)
1
DDR3-SODIMM-DUAL-M97-3
D
2
CERM 402-LF
C3151 2.2UF
20% 6.3V
MF-LF 402
SYNC_MASTER=K24_MLB
20% 6.3V 2
SYNC_DATE=02/05/2009
A
PAGE TITLE
DDR3 SO-DIMM Connector A
CERM 402-LF
DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
516-0201 SPD ADDR=0xA0(WR)/0xA1(RD)
SIZE
BRANCH
PAGE
31 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
Page Notes
3
2
1
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE) 8 =PP1V5_S3_MEM_B
Power aliases required by this page: - =PP1V5_S0_MEM_B 1
- =PP1V5_S3_MEM_B
C3200
1
10UF
- =PP0V75_S0_MEM_VTT_B - =PPSPD_S0_MEM_B (2.5 - 3.3V)
2
20% 6.3V X5R 603
C3201
1
20% 6.3V X5R
1
C3210
2
603
1
C3211
0.1UF
10UF 2
0.1UF
20% 10V CERM 402
1
C3212 0.1UF
20% 10V CERM 402
2
2
1
C3213 0.1UF
20% 10V CERM 402
2
C3214
1
0.1UF
20% 10V CERM 402
2
20% 10V CERM 402
1
C3215 0.1UF
2
1
C3216 0.1UF
20% 10V CERM 402
2
C3217 0.1UF
20% 10V CERM 402
2
20% 10V CERM 402
Signal aliases required by this page: - =I2C_SODIMMB_SCL - =I2C_SODIMMB_SDA
D
BOM options provided by this page:
26 PP0V75_S3_MEM_VREFDQ_B (NONE)
1
C3230
C3231
2.2UF
0.1UF
20% 6.3V 2
20% 10V 2
CERM 402-LF
CERM 402
1 3
75 77 71 15
MEM_B_BA
IN
79 81
71 15
IN
MEM_B_A
71 15
IN
MEM_B_A
83 85 87
71 15
IN
MEM_B_A
71 15
IN
MEM_B_A
89 91 93
71 15
IN
MEM_B_A
71 15
IN
MEM_B_A
95 97 99
C
71 15 71 15
IN
MEM_B_CLK_P
101
IN
MEM_B_CLK_N
103 105
71 15 71 15
71 15
IN
MEM_B_A
107
IN
MEM_B_BA
109
IN
MEM_B_WE_L
113
MEM_B_CAS_L
115
111
71 15
IN
117 71 15 71 15
IN IN
MEM_B_A
119
MEM_B_CS_L
121 123 125 127
71 15
BI
MEM_B_DQ
129
71 15
BI
MEM_B_DQ
131 133
71 15
BI
MEM_B_DQS_N
135
71 15
BI
MEM_B_DQS_P
137 139
71 15
BI
MEM_B_DQ
141
71 15
BI
MEM_B_DQ
143 145
BI
MEM_B_DQ
147
71 15
BI
MEM_B_DQ
149
71 15
IN
MEM_B_DM
153
71 15
151
155
B
71 15
BI
MEM_B_DQ
157
71 15
BI
MEM_B_DQ
159 161
71 15
BI
MEM_B_DQ
163
71 15
BI
MEM_B_DQ
165 167
71 15
BI
MEM_B_DQS_N
169
71 15
BI
MEM_B_DQS_P
171 173
71 15
BI
MEM_B_DQ
175
71 15
BI
MEM_B_DQ
177
BI
MEM_B_DQ
181
BI
MEM_B_DQ
183
179 71 15 71 15
185 1
R3240
71 15
MEM_B_DM
IN
189
10K 5% 1/16W
71 15
BI
MEM_B_DQ
191
71 15
BI
MEM_B_DQ
193
MF-LF 2
187
402
195
MEM_B_SA
197
MEM_B_SA
201
199
8 =PPSPD_S0_MEM_B
203
1 1
A
C3240
5%
20% 6.3V 2
R3241 10K
2.2UF
1/16W
CERM 402-LF
2
MF-LF 402
205 207 209 211
KEY
CKE0 CKE1 VDD VDD OMIT NC A15 BA2 A14 J3200 VDD VDD F-RT-BGA3 A11 A12/BC* A9 A7 VDD VDD A6 A8 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK1 CK0 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD A13 ODT1 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DQS4* DM4 VSS DQS4 VSS DQ38 DQ34 DQ39 DQ35 VSS VSS DQ44 DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ47 DQ43 VSS VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DM6 DQS6* DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS DQ60 VSS DQ56 DQ61 DQ57 VSS DQS7* VSS DQS7 DM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS SA0 EVENT* VDDSPD SDA SCL SA1 VTT VTT (2 OF 2)
IN
73
DDR3-SODIMM
71 15
MEM_B_CKE
MTG PINS
MTG PIN MTG PIN MTG PIN MTG PIN
74
MEM_B_CKE
IN
15 71
76
71 15
BI
MEM_B_DQ
71 15
BI
MEM_B_DQ
MEM_B_A
IN
9
80
MEM_B_A
IN
15 71
71 15
IN
11
MEM_B_DM
13
82 84
MEM_B_A
IN
15 71
71 15
86
MEM_B_A
IN
15 71
71 15
BI
MEM_B_DQ
15
BI
MEM_B_DQ
17 19
88 90
MEM_B_A
IN
15 71
71 15
BI
MEM_B_DQ
92
MEM_B_A
IN
15 71
71 15
BI
MEM_B_DQ
21 23 25
94 96
MEM_B_A
98
MEM_B_A
IN
15 71
71 15
BI
MEM_B_DQS_N
IN
15 71
71 15
BI
MEM_B_DQS_P
27 29 31
100 102
MEM_B_CLK_P
104
MEM_B_CLK_N
IN
15 71
71 15
IN
15 71
71 15
BI
MEM_B_DQ
33
BI
MEM_B_DQ
35 37
106 108
MEM_B_BA
110
MEM_B_RAS_L
MEM_B_CS_L
IN
15 71
71 15
IN
15 71
71 15
IN
15 71
71 15
BI
MEM_B_DQ
39
BI
MEM_B_DQ
41
BI
MEM_B_DQS_N
45
MEM_B_DQS_P
47
43
112
116
MEM_B_ODT
IN
71 15
15 71
BI
49
118 120
MEM_B_ODT
IN
71 15
15 71
122
71 15
BI BI
51
MEM_B_DQ
53
MEM_B_DQ
55
124 126
71 15
128
71 15
130
MEM_B_DQ
BI
15 71
132
MEM_B_DQ
BI
15 71
BI
MEM_B_DQ
57
BI
MEM_B_DQ
59 61
71 15
IN
63
MEM_B_DM
65
134 136
7 9
78
114
5
MEM_B_DM
15 71
IN
138 140
MEM_B_DQ
BI
15 71
142
MEM_B_DQ
BI
15 71
146
MEM_B_DQ
BI
15 71
148
MEM_B_DQ
BI
15 71
152
MEM_B_DQS_N
BI
15 71
154
MEM_B_DQS_P
BI
15 71
158
MEM_B_DQ
BI
15 71
160
MEM_B_DQ
BI
15 71
71 15
BI
MEM_B_DQ
67
71 15
BI
MEM_B_DQ
69 71
VREFDQ VSS OMIT DQ4 VSS DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* J3200 DQS0 DM0 F-RT-BGA3 VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ10 DQ14 DQ11 DQ15 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ18 DQ23 DQ19 VSS VSS DQ28 DQ24 DQ29 DQ25 VSS DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS (1 OF 2)
1
DDR3-SODIMM
D
2 4
MEM_B_DQ
BI
15 71
6
MEM_B_DQ
BI
15 71
10
MEM_B_DQS_N
BI
15 71
12
MEM_B_DQS_P
BI
15 71
16
MEM_B_DQ
BI
15 71
18
MEM_B_DQ
BI
15 71
22
MEM_B_DQ
BI
15 71
24
MEM_B_DQ
BI
8
14
20
15 71
26 28
MEM_B_DM
IN
15 71
30
MEM_RESET_L
IN
27 29
34
MEM_B_DQ
BI
36
MEM_B_DQ
BI
15 71
32 15 71
C
38 40
MEM_B_DQ
BI
15 71
42
MEM_B_DQ
BI
15 71
44 46
MEM_B_DM
IN
50
MEM_B_DQ
BI
15 71
52
MEM_B_DQ
BI
15 71
56
MEM_B_DQ
BI
15 71
58
MEM_B_DQ
BI
15 71
62
MEM_B_DQS_N
BI
15 71
64
MEM_B_DQS_P
BI
15 71
68
MEM_B_DQ
BI
15 71
70
MEM_B_DQ
BI
15 71
15 71
48
54
60
66
72
KEY
144
516S0706
150
156
B
162
DDR3 GROUND RETURN CAPS (MCP SIDE)
164
MEM_B_DQ
BI
15 71
166
MEM_B_DQ
BI
15 71
8 =PP1V5_S0_MEM_MCP
168 170
MEM_B_DM
IN
174
MEM_B_DQ
BI
15 71
176
MEM_B_DQ
BI
15 71
180
MEM_B_DQ
BI
15 71
182
MEM_B_DQ
BI
15 71
1
15 71
C3222
1
0.1UF
172 2
PP0V75_S3_MEM_VREFCA_B
26
20% 10V CERM 402
C3223
1
0.1UF 2
20% 10V CERM 402
C3224
1
0.1UF 2
20% 10V CERM 402
C3225
1
0.1UF 2
20% 10V CERM 402
C3226
1
0.1UF 2
20% 10V CERM 402
C3227
1
0.1UF 2
20% 10V CERM 402
1
C3228 0.1UF
2
C3229 0.1UF
20% 10V CERM 402
2
20% 10V CERM 402
178
1
C3235
184
2.2UF
186
20% 6.3V
188
MEM_B_DQS_N
BI
15 71
MEM_B_DQS_P
BI
15 71
192
MEM_B_DQ
BI
15 71
194
MEM_B_DQ
BI
2
1
C3236 0.1UF 20% 10V
2
CERM 402-LF
CERM 402
190
15 71
196 198
MEM_EVENT_L
OUT
200
=I2C_SODIMMB_SDA
BI
202
=I2C_SODIMMB_SCL
IN
21 27 36 39
"Expansion" (bottom) slot 39
204
=PP0V75_S0_MEM_VTT_B
MTG PIN
206
MTG PIN
208
MTG PIN
210
2.2UF
MTG PIN
212
20% 6.3V
1
2
C3250
CERM 402-LF
1
8
C3251 2.2UF
SYNC_MASTER=K24_MLB
20% 6.3V 2
SYNC_DATE=02/05/2009
A
PAGE TITLE
DDR3 SO-DIMM Connector B
CERM 402-LF
DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY:
516S0706
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
SPD ADDR=0xA2(WR)/0xA3(RD)
SIZE
BRANCH
PAGE
32 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
D
D
DDR3 RESET Support Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.
R3309 0
MCP_MEM_RESET_L
2
1
MEM_RESET_L
27 28
R3310 1
Q3305
1K
1 2
B
R3305
3
5
C3300
Q1
6
D
MEM_RESET_RC_L
E
1
20K 5% 1/16W MF-LF 402
2
5% 1/16W MF-LF 402
C
1
3.3V S5 is used because MEM_RESET must be high before 1.5V starts to rise to avoid glitch on MEM_RESET_L.
100K
2
R3301 1
8
SOT-363
4
10K 5% 1/16W MF-LF 402
=PP3V3_S5_MEMRESET
DMB53D0UDW
S
R3300
5% 1/16W MF-LF 402
1
G
=PP1V5_S3_MEMRESET
C
OUT
5% 1/16W MF-LF 402
Q2
8
IN
C
16
2
MEM_RESET
0.1UF 2 2
20% 10V CERM 402
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
DDR3 Support DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
33 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6 17
5
4
3
2
1
OUT PCIE_MINI_PRSNT_L
3
D
Q3401 SSM6N15FEAPE SOT563
4
S
G
5
AP_PWR_EN
IN
21 32
3V S3 WLAN FET
D 17
MINI_CLKREQ_L
OUT
6
D
D
MOSFET
TPCP8102
CHANNEL
P-TYPE
Q3401 20-30 MOHM @2.5V
RDS(ON)
SSM6N15FEAPE SOT563
LOADING
0.727 A (EDP)
2
MINI_CLKREQ_Q_L
PCIE_MINI_R2D_P
72
PCIE_MINI_R2D_N
1 1
2
10%
PLACEMENT_NOTE=Place close to J3401.
CRITICAL
0.1uF 16V
X5R
402
PCIE_MINI_R2D_C_P
IN
17 72
PCIE_MINI_R2D_C_N
IN
17 72
7
C3422
PLACEMENT_NOTE=Place close to J3401.
72 7
CONN_PCIE_MINI_D2R_P 4
3
PCIE_MINI_D2R_P
J3401
OUT
17 72
C
72 7
CONN_PCIE_MINI_D2R_N 1
2
PCIE_MINI_D2R_N
PLACEMENT_NOTE=Place close to J3401.
OUT
47 30
PP3V3_WLAN_F
1 3
2 4
3
8
PP3V3_WLAN_R
C3421 0.1uF 20% 10V CERM 402
2
1
1
C3420
2
2
10% 16V X5R 402
C3450 0.1UF 1
90-OHM-100MA DLP11S
C3451
1
2
2
R3450 1
2
5% 1/16W MF-LF 402
PM_WLAN_EN_L
2
IN
30 32
5% 1/16W MF-LF 402
10% 16V X5R 402
PLACEMENT_NOTE=Place close to J3401.
R3451
100K
P3V3WLAN_SS
8 30
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
10K
0.033UF
20% 10V X5R 805
L3401
17 72
=PP3V3_S3_WLAN 1
10UF
AIRPORT
CRITICAL
F-ST-SM 32 31
1
20% 10V CERM 402
SYM_VER-1
500913-0302
2 0603
0.1uF
90-OHM-100MA DLP11S
CRITICAL
1
PP3V3_WLAN MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=3.3V
402
C3430
L3402
516S0582
X5R
2
10%
0.1uF 16V
1
72
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=3.3V
D
2
23V1K-SM
1% 1/4W MF 1206
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=3.3V
4 G
CONN_PCIE_MINI_R2D_N 1
FERR-120-OHM-3A
C3431
5
72 7
L3404
727 MA PEAK 606 MA NOMINAL MAX
PLACEMENT_NOTE=Place close to J3401.
3
TPCP8102
0.002
7
SYM_VER-1
CONN_PCIE_MINI_R2D_P 4
Q3450
R3452
155S0367
L3405 90-OHM-100MA DLP11S
72 7
CRITICAL
CRITICAL
CRITICAL
2
G
6
7
S
S
1
C
SYM_VER-1
NC NC
2
1
4
3
72 7
PCIE_CLK100M_MINI_CONN_P
6
5
72 7
PCIE_CLK100M_MINI_CONN_N
8
7
10
9
12
11
14
13
16
15
18
17
20
19
4
1
PLACEMENT_NOTE=Place close to Q3450.
PCIE_CLK100M_MINI_P
3
17 72
IN
17 72
PLACEMENT_NOTE=Place close to Q3450.
ISNS_AIRPORT_P
PCIE_CLK100M_MINI_N
2
IN
ISNS_AIRPORT_N
OUT OUT
47 76 47 76
PLACEMENT_NOTE=Place close to J3401.
BLUETOOTH
22
21
73 7
CONN_USB2_BT_P
24
23
73 7
CONN_USB2_BT_N
26
25
28
27
30
29
1 C3432
34
33
2
7
L3403 90-OHM DLP0NS
CRITICAL
SYM_VER-1
4
3
USB_BT_P
BI
20 73
1
2
USB_BT_N
BI
20 73
PP3V3_S3_BT_F
PLACEMENT_NOTE=Place close to J3401.
L3406
0.01UF 10% 16V CERM 402
2
1
=PP3V3_S3_BT
8
FERR-120-OHM-1.5A 0402-LF
PLACEMENT_NOTE=PLACE L3406 NEAR J3401.
PLACEMENT_NOTE=PLACE C3432 NEAR J3401
B
B
RC VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN 3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET
PP3V3_WLAN_F =PP3V3_S3_WLAN PCIE_WAKE_L
OUT
8 30
1
7 17
30 47
R3453 110K
U3402
5% 1/16W MF-LF
5
74LVC1G17 TC7SZ08AFEAPE 5 SOT665 7
2
A
2
SOT353-1 4
WLAN_SMIT_BUF
402
R3455
2
1
4
MINI_RESET_CONN_L
Y
U3401
WLAN_SMIT_RC
NC B
1
3
1
NC
3
1
C3453 MINI_RESET_L
A
IN
1
10% 6.3V CERM 402
2 5% 1/16W MF-LF 402
WLAN_SMIT_DISCHRG
Q3455 3
D
SSM3K15FV SOD-VESM-HF
62K
1UF
25
R3454
1
5%
NOSTUFF
1/16W MF-LF
2 2
SYNC_MASTER=K24_MLB
402
2
S
G
SYNC_DATE=01/27/2009
A
PAGE TITLE
1
PM_WLAN_EN_L
X16 WIRELESS CONNECTOR
30 32
DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
34 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
=PP1V05_ENET_PHY
1
8
(221mA typ - 1000base-T)
D
(
C3710
1
C3711
0.1UF
8
10% 16V X5R 402
=PP3V3_ENET_PHY
1
1
0.1UF 10% 16V X5R 402
2
D
7mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
CRITICAL
L3715
2
FERR-120-OHM-1.5A 0402-LF
(43mA typ - 1000base-T) (19mA typ - Energy Detect) 1
1
WF: Marvell numbers, update for Realtek
1
C3700 0.1UF
CRITICAL
L3705 FERR-120-OHM-1.5A
1
C3701 0.1UF
10% 16V X5R 402
2
2
C3702
2
0.1UF
10% 16V X5R 402
2
10% 16V X5R 402
PP1V05_ENET_PHYAVDD
1
C3714
0402-LF
C3715
1
C3716
2.2UF
2.2UF
0.1UF
10% 6.3V X5R 402
10% 6.3V X5R 402
10% 16V X5R 402
2
2
2
1
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
PP3V3_ENET_PHYAVDD MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
1
C3705 0.1UF
2
C3706 0.1UF
10% 16V X5R 402
2
10% 16V X5R 402
=PP3V3_ENET_PHY_VDDREG
9
If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45. NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
9
=RTL8211_ENSWREG
IN
2
2
40
10
28
3
45
44
37
21
36
AVDD10
5% 1/16W MF-LF 402
DVDD10
4.7K
FB10
10K 5% 1/16W MF-LF 402
15
6
R3725
VDDREG
Alias to =PP3V3_ENET_PHY for internal switcher. Alias to GND for external 1.05V supply.
1
DVDD33
C
1
AVDD33
NO STUFF
R3720
41
R3750
1
1
R3751
R3752
4.7K
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
1
=RTL8211_REGOUT
9
If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
2
C
If internal switcher is not used, VDDREG and REGOUT can float.
CRITICAL 39
U3700 ENSWREG
RTL8251CA-VB-GR
REGOUT
48
RXC
19
TQFP
R3796 74 18
IN
ENET_CLK125M_TXCLK
1
0
22
74 ENET_CLK125M_TXCLK_R
2
5% 1/16W 402 MF-LF
PLACE R3796 CLOSE TO U1400, PIN D24
74 18
IN
ENET_TXD
23
74 18
ENET_TXD
24
IN
74 18
ENET_TXD
25
IN IN
ENET_TXD
26
74 18
74 18
ENET_TX_CTRL
IN
27
74 18
ENET_MDC
30
IN
74 18
BI
ENET_MDIO
31
TXC
TXD[0] TXD[1] TXD[2] TXD[3]
RGMII/MII
RXD[0] RXD[1]/TXDLY RXD[2]/AN0 RXD[3]/AN1
TXCTL
MDC MDIO
RXCTL
0
IN
ENET_RESET_L
1
RTL8211_PHYRST_L
2
5% 1/16W MF-LF 402
1
2
HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.
NO STUFF
PHYRSTB*
RTL8211_RSET
46
20% 10V CERM 402
B
9
TP_RTL8211_CLK125
32
RSET
REFERENCE
74
ENET_RXD_R
16
74
ENET_RXD_R
17
74
ENET_RXD_R
74
ENET_RXD_R
18
13
74
ENET_RXCTL_R
ENET_MDI_P
BI
33 74
2
ENET_MDI_N
BI
33 74
MDI+[1] MDI-[1]
4
ENET_MDI_P
BI
33 74
5
ENET_MDI_N
BI
33 74
MDI+[2] MDI-[2]
8
ENET_MDI_P
BI
33 74
9
ENET_MDI_N
BI
33 74
MDI+[3] MDI-[3]
11
ENET_MDI_P
BI
33 74
12
ENET_MDI_N
BI
33 74
LED0/PHYAD0 LED1/PHYAD1 LED2/RXDLY
34
RTL8211_PHYAD0
35
RTL8211_PHYAD1
22
1
2
R3791 R3792
22
1
2
22
1
2
R3793 R3794
22
1
2
22
1
2
R3795
1
RESET MEDIA DEPENDENT
C3725 0.1UF
ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.
29
14
MDI+[0] MDI-[0]
MANAGEMENT
R3724 74 18
R3790
74 ENET_CLK125M_RXCLK_R
22
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1
1/16W
MF-LF
ENET_CLK125M_RXCLK
OUT
18 74
ENET_RXD
OUT
18 74
ENET_RXD
OUT
18 74
ENET_RXD
OUT
18 74
ENET_RXD
OUT
18 74
ENET_RX_CTRL
OUT
18 74
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
B
CLK125
1
R3730
CLOCK
2.49K
IN
RTL8211_CLK25M_CKXTAL1
42
TP_RTL8211_CKXTAL2
43
CKXTAL1 CKXTAL2
LED
38
RTL8211_RXDLY NO STUFF
C3790
47
33
GND 20
74 32
2
7
1% 1/16W MF-LF 402
1
10PF 5% 50V CERM 402
2
R3755
1
R3756
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
1
1
R3757 4.7K
2
2
5% 1/16W MF-LF 402
Reserved for EMI per RealTek request.
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
Ethernet PHY (RTL8211CL) DRAWING NUMBER
Apple Inc.
051-7982
PHYAD
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
= 01 (PHY Address 00001)
AN[1:0] = 11 (Full auto-negotiation) RXDLY
= 0
(RXCLK transitions with data)
TXDLY
= 0
(No TXCLK Delay)
8
D
REVISION
C.0.0
R
Configuration Settings:
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2
1
3.3V ENET FET @ 2.5V Vgs:
CRITICAL
Rds(on) = 90mOhm max I(max)
Q3810
= 1.7A (85C)
NTR4101P SOT-23-HF
=PP3V3_S5_P3V3ENETFET
8
=PP3V3_ENET_FET
S
2
D R3800
1
1
D
C3811
8
3
D
G
0.033UF
10K 5% 1/16W
10% 16V X5R 402
2
MF-LF 402
1
C3810
R3810
2
0.01UF
100K P3V3ENET_EN_L
D
Q3801
1
2
P3V3ENET_SS
2 5% 1/16W MF-LF 402
3
1
10% 16V CERM 402
SSM6N15FEAPE SOT563
5
9
IN
G
S
4
=P3V3ENET_EN
MOBILE: Recommend aliasing PM_SLP_RMGT_L and =P3V3ENET_EN.
Nets separated on
ARB for alternate power options.
WLAN Enable Generation "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L
C
30
OUT
Q3805
D
C
1.05V ENET FET
Pull-up is with power FET. 6
SSM6N15FEAPE SOT563
8
=PP1V05_ENET_P1V05ENETFET
1.8V Vgs 2
30 21
IN
G
S
1
AP_PWR_EN
C3840
Q3805
D
3
6
D
8
Q3801
CRITICAL
SOT563
R3842
G
D
2
Q3840
100K 1
5
CERM 402
R3840
=PP3V3_S5_P1V05ENETFET
1
P1V05ENET_SS
2
G
SSM6N15FEAPE
SOT563
IN
3
20% 10V
SSM6N15FEAPE
37 36 21
1
0.1UF
AC_OR_S0_L
S
4
1
S
G
1
Q3841
6
SOT23
2
=PP1V05_ENET_FET
2 2
R3841
G
S
1 1
IN
1
10% 16V
2
PM_SLP_S3_L
2 1%
D
Q3841
1/16W MF-LF
3
C3841 0.01UF
10K
P1V05ENET_EN_L 67 63 36 21 7
8
SOT563
1% 1/16W MF-LF 402
D
SSM6N15FEAPE
69.8K
2
SMC_ADAPTER_EN
SI2312BDS
S
5% 1/16W MF-LF 402
CERM 402
P1V05ENET_EN_L_RC
402
SSM6N15FEAPE SOT563
5
B
9
IN
G
S
4
B
=P1V05ENET_EN
Non-ARB: Recommend aliasing PM_SLP_RMGT_L and =P1V05ENET_EN.
Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
A
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
Ethernet & AirPort Support
R3895 22 74 18
IN
MCP_CLK25M_BUF0_R
1
2
RTL8211_CLK25M_CKXTAL1
OUT
DRAWING NUMBER
31 74
5% 1/16W MF-LF 402
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
PLACEMENT_NOTE=Place close to U1400
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
38 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
- COPY THIS PAGE FROM K36 CSA.39
D
D
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902
ENET_CONN_CTAP
1
2
C3900
1
1
C3901 0.1UF
0.1UF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
2
2
1
C3902
0.1UF
C3903 0.1UF
2
10% 16V X5R 402
ETHERNET CONNECTOR CRITICAL
T3901 SM
OMIT CRITICAL
74 31
BI
ENET_MDI_P
1
12
74 31
BI
ENET_MDI_N
2
11
3
10
74
J3900
ENET_MDI_TRAN_P
RJ45-10/100TX-K83 74
TX
1 1%
1/16W
1%
1/16W
TLA-6T213HF
74 31
BI
5
ENET_MDI_P
75
2
MF-LF
1
ENET_CENTER_TAP
2 3
402
4
R3902
9
4
C
1
R3903 ENET_CENTER_TAP
75
2 MF-LF
5 6
402
8
74 74
74 31
BI
6
ENET_MDI_N
F-R-TH
ENET_MDI_TRAN_N
ENET_MDI_TRAN_P
7
ENET_MDI_TRAN_N
8
ENET_MDI TRAN_P0 TRAN_N0 TRAN_P1 TRAN_P2 TRAN_N2 TRAN_N1 TRAN_P3 TRAN_N3
C
7
RX
9 10
CRITICAL
74 31
74 31
BI
BI
ENET_MDI_N
1
ENET_MDI_P
2
T3902 SM
3
11
12
74
ENET_MDI_TRAN_N
11
74
ENET_MDI_TRAN_P
74
ENET_MDI_TRAN_N
10
R3901 1
ENET_CENTER_TAP
TX
1%
TLA-6T213HF 4
9
74 31
BI
ENET_MDI_N
5
8
BI
ENET_MDI_P
6
7
1/16W
2
1/16W
2
514-0692
75
MF-LF
R3900 1
ENET_CENTER_TAP 1%
74 31
SHIELD PINS
12
402
75
MF-LF
402
74 ENET_MDI_TRAN_P
RX ENET_BOB_SMITH_CAP MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1 1
B
2
1
C3911
C3913
10PF
10PF
5% 50V CERM 402-1
5% 50V CERM 402-1
2
1
10PF 2
CRITICAL
CRITICAL
C3915
2
CRITICAL CRITICAL
CRITICAL
1
1
C3912 10PF
2
2
1
C3910
B
1000PF
5% 50V CERM 402-1
2
CRITICAL
10% 2KV CERM 1206
CRITICAL
C3914
1
10PF
5% 50V CERM 402-1
CRITICAL
C3917 10PF
5% 50V CERM 402-1
5% 50V CERM 402-1
CRITICAL
C3916
1
10PF 2
5% 50V CERM 402-1
C3918 10PF
2
5% 50V CERM 402-1
PLACEMENT_NOTE=PLACE C3911-C3918 ON MDI LINES WITHOUT ANY STUBS
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
ETHERNET CONNECTOR DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
39 OF 109 SHEET
OF
8
7
6
5
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8
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1
CRITICAL
Q4590
ODD Power Control
TPCP8102 23V1K-SM
PP5V_SW_ODD_R 8
=PP5V_S3_ODD
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
1
100K 2
R4595 ODD_PWR_EN_LS5V_L
D
1
R4597 D
Q4596
6
D
10% 10V CERM 402
C4596 0.01UF 1
ODD_PWR_SS
2
6
10% 16V CERM 402
R4598 1
SOT563
Q4596
D
3
S
4
G
S
3
ISNS_ODD_P
1% 1/4W MF 1206 2 4
ISNS_ODD_N
47 76
OUT
0.002
SSM6N15FEAPE ODD_PWR_EN 2
D
2
CRITICAL
5% 1/16W MF-LF 402
100K 5% 1/16W MF-LF 402
100K
4
0.068UF
5% 1/16W MF-LF 402
=PP3V3_S0_ODD
C4595
G
R4596
NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5. 34 8
5
1
2
S
7
3
8
OUT
47 76
1
SSM6N15FEAPE SOT563
5 21
IN
G
ODD_PWR_EN_L
47 7
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
CRITICAL
SATA ODD
PP5V_SW_ODD
FL4520
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79
90-OHM-100MA DLP11S
PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
SYM_VER-1
34 8
3
=PP3V3_S0_ODD
4
72
R4590
OUT
1
72
Indicates disc presence
C4521
2
CERM
CERM
SATA_ODD_R2D_C_P
IN
20 72
SATA_ODD_R2D_C_N
IN
20 72
402
C4520
10% 16V
0.01UF
F-ST-SM
SMC_ODD_DETECT
1
SATA_ODD_R2D_UF_N
54722-0164
5% 1/16W MF-LF 402 2
36 7
2
J4500
1
33K
2
10% 16V
0.01UF
CRITICAL
C
1
SATA_ODD_R2D_UF_P
402
C
PLACEMENT_NOTE=Place FL4520 close to J4500
1
2
3
4
72 7
5
6
72 7
7
8
9
10
11
12
13
14
15
16
SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P
FL4525
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500
90-OHM-100MA DLP11S
PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
SYM_VER-1
C4526
1
2
C4525
1
2
72
CERM
CERM
OUT
20 72
OUT
20 72
402 1
SATA_ODD_D2R_UF_P
10% 16V
0.01UF
CRITICAL 3 SATA_ODD_D2R_N
4
SATA_ODD_D2R_UF_N
10% 16V
0.01UF
516S0616
72
2
SATA_ODD_D2R_P
402
PLACEMENT_NOTE=Place FL4525 close to J4500
CRITICAL
J4502 78171-0002 M-RT-SM
3 PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
R4531
B
4.7 37
SYS_LED_ANODE
2
1 5% MF-LF
PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
1
7 SYS_LED_ANODE_R
402
B
2
1/16W
4
SIL
1
1
1
C4501 0.1UF
518S0519 2
C4531
2
CRITICAL
CRITICAL
20% 10V CERM 402
R4599 0.002
L4500
0.001UF 2
C4502 0.1UF
20% 10V CERM 402
10% 50V CERM
1% 1/4W MF 1206
FERR-70-OHM-4A
402
7
1
PP5V_S0_HDD_FLT
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2MM VOLTAGE=5V
2
1 3
PP5V_S0_HDD_R MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
0603 PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
2 4
=PP5V_S0_HDD
8
ISNS_HDD_P CRITICAL
FL4502
ISNS_HDD_N
90-OHM-100MA
OUT OUT
47 76
47 76
DLP11S SYM_VER-1
72 7
C4515
SATA_HDD_D2R_C_N
CRITICAL
54722-0164
72 7
F-ST-SM
1
4
5
6
7
SATA HDD
A
NC
C4516
SATA_HDD_D2R_C_P
2
72
10% 16V 1
CERM
2 CERM
SATA_HDD_D2R_UF_N
4
3
SATA_HDD_D2R_N
OUT
20 72
2
SATA_HDD_D2R_P
OUT
20 72
402
72
10% 16V
0.01UF
2
3
1
0.01UF
J4501
SATA_HDD_D2R_UF_P
1
402 PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
PLACEMENT_NOTE=Place C4515 next to C4516 PLACEMENT_NOTE=Place C4516 close to J4501
8
9
10
11
12
13
14
15
16
CRITICAL
FL4501
90-OHM-100MA
PLACEMENT_NOTE=Place C4511 next to C4510 PLACEMENT_NOTE=Place C4510 close to MCP79
DLP11S
SYNC_MASTER=K24_MLB
SYM_VER-1
72 7
3
SATA_HDD_R2D_N
4
72
SATA_HDD_R2D_UF_N
C4511
1
10% 16V
0.01UF
516S0616 72 7
2
SATA_HDD_R2D_P
1
72
SATA_HDD_R2D_UF_P
C4510 0.01UF
PLACEMENT_NOTE=Place FL4501 close to J4501
2
1
2 10% 16V
SATA_HDD_R2D_C_N CERM
SATA_HDD_R2D_C_P CERM
SYNC_DATE=01/19/2009
SATA Connectors DRAWING NUMBER
IN
A
PAGE TITLE
IN
402
20 72
Apple Inc.
402
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
45 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
D
D
POR IS PLASTIC USB CONNECTOR PARTS BUT METAL PART’S SCHEMATIC AND CAD SYMBOLS HAVE BEEN USED AS ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES
Port Power Switch
USB PORT A (FRONT PORT) PLACEMENT_NOTE=NEAR J4600
CRITICAL
CRITICAL
U4690
FERR-220-OHM-2.5A
L4605
TPS2064DGN 8
IN
OUT1
7
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
MSOP 20
20
8
USB_EXTA_OC_L
OUT
USB_EXTB_OC_L
OUT
OC1*
3
EN1
5
OC2*
4
EN2
OUT2
1
PP5V_S3_RTUSB_A_ILIM
6
2
C4605
PP5V_S3_RTUSB_B_ILIM
20% 16V CERM 402
PLACEMENT_NOTE=NEAR J4600 CRITICAL 2
1
C4690
1
1
10UF 20% 6.3V X5R 603
2
2
CRITICAL
C4695
0.1UF
1
1
10UF
20% 10V CERM 402
F-RT-TH 5
90-OHM DLP0NS
6
SYM_VER-1
9
C4691
USB-K83
L4600
GND TPAD NOSTUFF
OMIT CRITICAL
J4600
0.01uF
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
C
PP5V_S3_RTUSB_A_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
0603 1
20% 6.3V X5R 603
C4696 100UF
2
2
20% 6.3V POLY-TANT CASE-B2-SM
CRITICAL 1
C4617
1
10UF 2
2
3
73 CONN_USB_EXTA_N 1 2
C4616 100UF
20% 6.3V X5R 603
4
73 USB_EXTA_MUXED_N
1
73 USB_EXTA_MUXED_P
2
3
73 CONN_USB_EXTA_P
20% 6.3V POLY-TANT CASE-B2-SM
4
2 5 3 4
We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.
6 VBUS
NC IO NC IO
C
2
=PP5V_S3_EXTUSB
7 8
1 GND 63
CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION
=USB_PWR_EN
IN
514-0689
D4600 RCLAMP0502N SLP1210N6 CRITICAL NOSTUFF PLACEMENT_NOTE=NEAR J4610 CRITICAL We can add protection to 5V if we want, but leaving NC for now
L4615 FERR-220-OHM-2.5A 1
2
1
USB/SMC Debug Mux 8
B
C4615 0.01uF
2
20% 16V CERM 402
OMIT CRITICAL
=PP3V42_G3H_SMCUSBMUX
J4610 USB-K83
SMC_DEBUG_YES
1
C4650
1
0.1UF 2 2
10K
CRITICAL
5% 1/16W MF-LF 402
L4610
6
90-OHM DLP0NS
1
SYM_VER-1
9
20% 10V CERM 402
F-RT-TH 5
PLACEMENT_NOTE=NEAR J4610
R4650
73 20
BI
USB_EXTB_N
4
3
IN
SMC_RX_L
5
M+
38 37 36
OUT
SMC_TX_L
4
M-
73 20
BI
USB_EXTA_P
7
73 20
BI
USB_EXTA_N
6
D+ D-
2
CONN_USB_EXTB_P
3
73
VCC 38 37 36
73 CONN_USB_EXTB_N
4
SMC_DEBUG_YES
U4650
Y+
1
Y-
2
73 20
BI
USB_EXTB_P
1
2
7
PI3USB102ZLE
2 5 3 4
TQFN
6 VBUS
8
NC IO NC IO
B
Place L4600 and L4605 at connector pin
PP5V_S3_RTUSB_B_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
0603
CRITICAL
514-0689 1 GND
OE*
8
SEL
10
USB_DEBUGPRT_EN_L
IN
36
SEL=0 Choose SMC SEL=1 Choose USB
D4610
3
GND
RCLAMP0502N SLP1210N6 CRITICAL NOSTUFF SMC_DEBUG_NO
A
R4651
SYNC_MASTER=K24_MLB
0 1
2 5%
SYNC_DATE=02/05/2009
A
PAGE TITLE
1/16W MF-LF
External USB Connectors
USB PORT B (BACK PORT)
SMC_DEBUG_NO
R4652
402
DRAWING NUMBER
0 1
2
Apple Inc.
5% 1/16W
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
MF-LF 402
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
46 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
NOTE: Unused pins have "SMC_Pxx" names.
6
5
4
3
2
1
Unused
pins designed as outputs can be left floating, those designated as inputs require pull-ups.
37 7
PP3V3_S5_AVREF_SMC
37 8
=PP3V3_S5_SMC
D
D C4902
1
1
2
2
22UF 20% 6.3V CERM 805
U4900
21 59 21
37
OUT
PM_RSMRST_L
C13
OUT
IMVP_VR_ON
C12
OUT
PM_PWRBTN_L
D10
OUT
ESTARLDO_EN
D13
37
D12 F11
SMC_P24
E13 E12
NC 37
SMC_P26
F13 E10
NC BI
LPC_AD
A9
73 38 19
BI
LPC_AD
D9
73 38 19
BI
LPC_AD
C8
73 38 19
BI
LPC_AD
B7 A8
73 38 19
C
73 38 19
IN
LPC_FRAME_L
25
IN
SMC_LRESET_L
IN
LPC_CLK33M_SMC
D7
LPC_SERIRQ
D6
73 25 38 19
BI
SMB_MGMT_DATA
46
OUT
SMS_ONOFF_L
A5 B4
(OC)
A1 C2
NC NC 37
OUT
SMC_GFX_THROTTLE_L
9
OUT
SMC_SYS_KBDLED
38 37 36 35
OUT
SMC_TX_L
IN
SMC_RX_L
38 37 36 35 39
BI
P40 P41 P42 P43 P44 P45 P46 P47
D4
SMC_P41
BI
P30 P31 P32 P33 P34 P35 P36 P37
D8
NC 37 39
P20 P21 P22 P23 P24 P25 P26 P27
E11
NC NC NC
B2 C1 C3
F3 E4
(OC)
P70 P71 P72 P73 P74 P75 P76 P77
J12
7 57 63
4.7
OUT
NC SMC_PROCHOT_3_3_L
IN
37
H12
SMC_BIL_BUTTON_L
IN
37
N10
SMC_CPU_ISENSE
IN
41
M11
SMC_CPU_VSENSE SMC_GPU_ISENSE
IN
40
IN
37
SMC_GPU_VSENSE
IN
37
N12
SMC_DCIN_ISENSE
IN
41
M13
SMC_PBUS_VSENSE
IN
40
N13
SMC_BATT_ISENSE
IN
41
L12
SMC_NB_MISC_ISENSE
IN
37
SMC_WAKE_SCI_L
OUT
21
C7
PM_CLKRUN_L
OUT
19 38
D5
LPC_PWRDWN_L
IN
19 38
A6
SMC_TX_L
B5
SMC_RX_L
A7
P90 P91 P92 P93 P94 P95 P96 P97
J4
B6
C6
C4907
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
C4920
1
10% 6.3V CERM-X5R 402
0.1UF 20% 10V CERM 402
VCC
AVCC
1
0.47UF
VCL AVREF
2
2
1
H8S2117
PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PIN M12
LGA-HF
NC
E5
MD1 MD2
D1
NMI
E3
ETRST
H3
AVSS
L9
OMIT 38 37
SMC_RESET_L
D3
RES*
37
SMC_XTAL
A3
37
SMC_EXTAL
A2
XTAL EXTAL
IN
1
R4909
U4900
PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PIN M12
R4901
10K
NC
5% 1/16W MF-LF 402
(3 OF 3)
N11
P80 P81 P82 P83 P84 P85 P86
PP3V3_S5_SMC_AVCC
2 5% 1/16W MF-LF 402
21 32 37
J11
L10
SMC_VCL
R4999 1
SMC_ADAPTER_EN
K13 J10
OUT
10K
2
2
5% 1/16W MF-LF 402
SMC_MD1
IN
38
SMC_NMI
IN
38
SMC_TRST_L
IN
38
SMC_KBC_MDE
H1
NC
(OC)
OUT
35 36 37 38
IN
35 36 37 38
SMB_MGMT_CLK
BI
SMC_ONOFF_L
IN
VSS
39
G3
SMC_BC_ACOK
IN
H2
SMC_BS_ALRT_L
IN
37
G1
PM_SLP_S3_L
IN
7 21 32 63 67
H4
PM_SLP_S4_L
IN
7 21 37 63
G4
PM_SLP_S5_L
IN
37
F4
PM_CLK32K_SUSCLK
IN
25 73
F1
SMB_0_S0_DATA
BI
(OC)
1
R4902 10K
37 44
XW4900 SM 2
37 55
NOTE: P94 and P95 are shorted, P95 could be spare.
C
NO STUFF 1
2
1
R4998 10K
5% 1/16W MF-LF 402
2
R4903 0
5% 1/16W MF-LF 402
2
5% 1/16W MF-LF 402
1
GND_SMC_AVSS
37 40 41
39
P50 P51 P52
G2
SMB_0_S0_CLK
OMIT
K11
PLACEMENT_NOTE=PLACE C4907 CLOSE TO U4900 PIN E1
SMC_PM_G2_EN
NC NC NC
L11
D11
NC
(1 OF 3)
K12
E1
B13
L13
H10
A12
RSMRST_PWRGD
P60 P61 P62 P63 P64 P65 P66 P67
20% 10V CERM 402
M1
ALL_SYS_PWRGD
IN
LGA-HF
2
B1
IN
63
H8S2117
C4906 0.1UF
20% 10V CERM 402
C5
63 25
P10 P11 P12 P13 P14 P15 P16 P17
C4905 0.1UF
2
B11
A13
20% 10V CERM 402
2
F10
B12
SMC_RSTGATE_L
C4904 0.1UF
20% 10V CERM 402
M12
SMC_EXCARD_PWR_EN
OUT
0.1UF
1
L3
OUT
37
C4903
1
D2
37
1
U4900 (DEBUG_SW_1)
37
SMC_PA0
N3
(DEBUG_SW_2)
37
SMC_PA1
N1
25
OUT
PM_SYSRST_L
(OC)
M3
35
OUT
USB_DEBUGPRT_EN_L
(OC)
M2
BI
MEM_EVENT_L
(OC)
N2
(OC)
L1
28 27 21
B
37
SMC_PA5
55
BI
SYS_ONEWIRE
(OC)
K3
21
OUT
PM_BATLOW_L
(OC)
L2 B8
NC 21
OUT
SMC_RUNTIME_SCI_L
C9
IN
SMC_ODD_DETECT
B9
34 7
37
SMC_PB3
A10
(See below)
37
IN
SMC_EXCARD_CP
37
IN
SMC_EXCARD_OC_L
C11
37
IN
SMC_GFX_OVERTEMP_L
A11
C10 B10
NC
OUT
SMC_FAN_0_CTL
G11
37
OUT
SMC_FAN_1_CTL
G13
37
OUT
SMC_FAN_2_CTL
F12
37
OUT
SMC_FAN_3_CTL
H13
43
IN
SMC_FAN_0_TACH
G10
37
IN
SMC_FAN_1_TACH
G12
37
IN
SMC_FAN_2_TACH
H11
37
IN
SMC_FAN_3_TACH
J13
46
IN
SMS_X_AXIS
M10
46
IN
SMS_Y_AXIS
N9
46
IN
SMS_Z_AXIS
K10
43
A
37
IN
SMC_ANALOG_ID
L8
37
IN
SMC_NB_CORE_ISENSE
M9
37
IN
SMC_NB_DDR_ISENSE
N8
37
IN
ALS_LEFT
K9
37
IN
ALS_RIGHT
L7
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
H8S2117 LGA-HF
(2 OF 3) OMIT
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
PE0 PE1 PE2 PE3 PE4 PF0
K1
SMC_CASE_OPEN
IN
37
J3
SMC_TCK
IN
37 38
K2
SMC_TDI
IN
37 38
J1
SMC_TDO
OUT
37 38
K4
SMC_TMS
IN
37 38
PF1 PF2 PF3 PF4 PF5 PF6 PF7
N5
SMC_SYS_LED
M6
SMC_LID
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
M8
PH0 PH1 PH2 PH3 PH4 PH5
E2
SMC_PROCHOT
F2
SMC_THRMTRIP
J2
SMC_PH2
A4
ALS_GAIN
K5
L5 M5
M4
OUT IN
37 37 44 55
NC NC SMC_MCP_SAFE_MODE
N4 L4
B
NC
OUT
37
37
NC NC NC =SMC_SMS_INT
IN
K8
(OC)
SMB_BSA_DATA
BI
39
K7
(OC)
SMB_BSA_CLK
BI
39
K6
(OC)
SMB_A_S3_DATA
BI
39
N6
(OC)
SMB_A_S3_CLK
BI
39
M7
(OC)
SMB_B_S0_DATA
BI
39
L6
(OC)
SMB_B_S0_CLK
BI
N7
B3 C4
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
39
OUT
37
OUT
37
OUT
37
37
NC NC
SYNC_MASTER=K24_MLB
SYNC_DATE=04/02/2009
SMC
1 C4950
DRAWING NUMBER
0.033UF
2 PLACEMENT_NOTE=PLACE C4950 CLOSE TO U4900 PIN M10 PLACEMENT_NOTE=PLACE C4951 CLOSE TO U4900 PIN N9 PLACEMENT_NOTE=PLACE C4952 CLOSE TO U4900 PIN K10
10% 16V
1
C4951
Apple Inc.
0.033UF
X5R 402
10%
2
16V X5R
10% 16V
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
X5R 402
SMC_PB3: SMC_IG_THROTTLE_L for MG systems. Otherwise, TP/NC okay (was ISENSE_CAL_EN)
8
7
SIZE
D
REVISION
C.0.0
NOTICE OF PROPRIETARY PROPERTY:
0.033UF
2
051-7982
R
1 C4952
402
A
PAGE TITLE
BRANCH
PAGE
49 OF 109 SHEET
OF
6
5
4
3
2
.
1
8
7
6
5
4
3
2
1
SMC FSB to 3.3V Level Shifting 36
SMC_BIL_BUTTON_L
36
SMC_FAN_1_CTL
36
SMC_FAN_2_CTL
36
SMC_FAN_3_CTL
NC_SMC_BIL_BUTTON_L
37 8
=PP3V3_S0_SMC
MAKE_BASE=TRUE
NC_SMC_FAN_1_CTL MAKE_BASE=TRUE
1
NC_SMC_FAN_2_CTL MAKE_BASE=TRUE
SMC Reset "Button" / Brownout Detect 36
SMC_GFX_THROTTLE_L
1
R5061
R5060 10K
100K
NC_SMC_FAN_3_CTL MAKE_BASE=TRUE
SMC_IG_THROTTLE_L
21
2
5% 1/16W MF-LF 402
2
5% 1/16W MF-LF 402 TO SMC
MAKE_BASE=TRUE
36
ESTARLDO_EN
SMC_PROCHOT_3_3_L
NC_ESTARLDO_EN
37 36 8 =PP3V3_S5_SMC 55 37 36
SMC_BC_ACOK
=CHGR_ACOK
36
CPU_PROCHOT_BUF
56
6
MAKE_BASE=TRUE
D
C5000
1
36
1
1K
CRITICAL 2
5
SMC_MANUAL_RST_L NOSTUFF
4
NC
CD NC GND
36
SMC_P41
36
SMC_NB_CORE_ISENSE
36
SMC_NB_DDR_ISENSE
OUT IN
1
SMC_RESET_L
OUT
SMC_MCP_DDR_ISENSE
70 14 10
BI
36
ALS_LEFT
SMC_CPU_FSB_ISENSE
Q5032
10%
36
16V 2
SSM3K15FV
402
D
41
SMC_MCP_VSENSE
SMC_GPU_VSENSE
6
D
SOD-VESM-HF
36
SMC_EXCARD_PWR_EN
36
SMC_RSTGATE_L
36
SMC_PB3
SOT-563
S
4
1
Q5059 SSM6N15FEAPE
40
SOT563
MAKE_BASE=TRUE
3
G
Q5060
5
CPU_PROCHOT_L_R
DMB53D0UV
MAKE_BASE=TRUE
CERM
2
5% 1/16W MF-LF 402
41
MAKE_BASE=TRUE
3
MF-LF
3.3K
1
MAKE_BASE=TRUE
0.01UF
603
41
CPU_PROCHOT_L
2
3
R5062
TO CPU
SMC_MCP_CORE_ISENSE
36 38
2
5%
2
SOT-563
TP_SMC_P41
0 1/10W
DMB53D0UV
MAKE_BASE=TRUE
402
D
Q5060
TP_SMC_P26
2
1
C5001
SMC_P26
MAKE_BASE=TRUE
MF-LF
SOT23-5-HF
1
D
1/16W
NCP303LSN
402
36
5%
U5000
10V
R5001
TP_SMC_P24 MAKE_BASE=TRUE
20%
CERM
SMC_P24
R5000
0.1uF
SILK_PART=SMC_RST
OUT
MAKE_BASE=TRUE
TP_SMC_EXCARD_PWR_EN MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
1
MAKE_BASE=TRUE
1
37 36 8 =PP3V3_S5_SMC
G
S
2 36
ALS_GAIN
36
SMC_ANALOG_ID
36
ALS_RIGHT
SMC_PROCHOT
36
IN
NC_SMC_ANALOG_ID 70 14 10
MAKE_BASE=TRUE
SOT553-5
SMC_TPAD_RST
OUT
PM_THRMTRIP_L
NC_ALS_RIGHT MAKE_BASE=TRUE
2
44 37 36 SMC_ONOFF_L
2
MAKE_BASE=TRUE
SN74LVC1G02 4
G
NC_ALS_GAIN
U5001
5 1
44 SMC_TPAD_RST_L
S
NC_SMC_PB3 MAKE_BASE=TRUE
02
3
=PP3V3_S5_SMC
D
8 36 37
3
Q5059 SSM6N15FEAPE SOT563
R5095
1
R5010
0
36
OUT
SMC_EXCARD_OC_L
1
2
EXCARD_OC_L
IN
10K
20
5% 5%
SMC AVREF Supply
S
G
5
MF-LF
MF-LF
2
402
C
4
1/16W
1/16W
SMC_THRMTRIP
402
IN
36
C
CRITICAL
36
OUT
=SMC_SMS_INT
SMS_INT_L
IN
MAKE_BASE=TRUE
VR5020 8
REF3333
=PPVIN_S5_SMCVREF
PP3V3_S5_AVREF_SMC
37 36 8
7 36
SOT23-3
=PP3V3_S5_SMC
MIN_LINE_WIDTH=0.4 mm 1
OUT
IN
2
MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
GND 1
0.01UF 10%
SMC_PA0
R5091
100K
1
2
36
SMC_PA1
R5092
100K
1
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE
16V 2
36
C5026
3
CERM 402
1
C5020
C5025
0.47UF
1
RADAR 5925345
10uF
10%
20% 6.3V
6.3V 2
44 37 36
SMC_ONOFF_L
R5070
10K
1
2
55 44 36
SMC_LID
R5071
100K
1
2
36
SMC_PH2
R5072
10K
1
2
2 CERM-X5R
X5R
402
603
R5011 0 21 GND_SMC_AVSS
MCP_SPKR
38 36 35
1
2
SMC_MCP_SAFE_MODE
IN
36 40 41
R5073
SMC_TX_L
36 38 36 35
10K
R5074
SMC_RX_L
1
100K
1
2
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
402
2
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
353S1381
353S1912
BOM OPTION
REF DES
COMMENTS:
38 36
SMC_TMS
R5077
10K
1
2
38 36
SMC_TDO
R5078
10K
1
2
38 36
SMC_TDI
R5079
10K
1
2
5%
1/16W
MF-LF
402
TABLE_ALT_ITEM
ALL
ISL60002-33, INTERSIL
38 36 55 37 36 36
B System (Sleep) LED Circuit
R5080
10K
1
2
SMC_BC_ACOK
R5087
470K
1
2
SMC_GFX_OVERTEMP_L
R5050
10K
1
2
SMC_BS_ALRT_L
R5076
100K
1
2
SMC_FAN_1_TACH
R5051
10K
1
2
36
SMC_FAN_2_TACH
R5052
10K
1
2
36
SMC_FAN_3_TACH
R5053
10K
1
2
36
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
B
36
36
36
8
SMC_TCK
5%
SMC_GPU_ISENSE
R5054
10K
1
2
SMC_NB_MISC_ISENSE
R5055
10K
1
2
SMC_ADAPTER_EN
R5085
10K
1
2
SMC_CASE_OPEN
R5086
10K
1
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
=PP5V_S3_SYSLED 36 32 21
SMC Crystal Circuit
Debug Power "Button" 36
1
R5031
R5030
523
80.6
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
2
2
C5010 2
1
SILK_PART=PWR_BTN
5X3.2-SM 2
SOD
MF-LF
402
MF-LF
402
15pF
1
Q5030
36
1
SMC_EXTAL
36 37 44
36
SMC_EXCARD_CP
R5088
10K
1
2
36
PM_SLP_S5_L
R5090
100K
1
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
63 36 21 7
NOSTUFF
402
R5016
0
0 1/10W MF-LF
MF-LF
603
603 2
2
SILK_PART=PWR_BTN
1.47K
OUT
R5089
SMC_PA5
10K
1
2
5%
5% 50V CERM 402
3
SYS_LED_ANODE
=PP3V3_S0_SMC
37 8
5%
1/10W
2
PLACE R5015,R5001 ON BOTTOM SIDE PLACE R5016 ON TOP SIDE
36 1
PM_SLP_S4_L
1
R5015 5%
C5011
2SA2154MFV-YAE
SYS_LED_L_VDIV
OUT
NOSTUFF 1
20.00MHZ 2
SMC_ONOFF_L
5% 50V CERM 402
CRITICAL
Y5010
1% 1/16W MF-LF 402
1/16W
1/16W
15pF 1
36 SMC_XTAL
SYS_LED_ILIM
R5032
5%
5%
1
34
1/16W
MF-LF
402
2
SYS_LED_L
A
SYNC_MASTER=K24_MLB
Q5033 SSM3K15FV
D
IN
DRAWING NUMBER
SMC_SYS_LED
Apple Inc. 1
G
S
A
SMC Support
SOD-VESM-HF
36
SYNC_DATE=02/04/2009
PAGE TITLE 3
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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1
LPC+SPI Connector CRITICAL LPCPLUS
J5100 55909-0374 M-ST-SM
D
=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS
38 8 8
73 36 19
BI
73 36 19
BI
73 38
IN
73 38
OUT
73 36 19
Alternate SPI ROM Support
36 19
OUT
37 36
OUT
25
IN
36 37 36
OUT
36 37 36 35
48 38 8
IN
IN OUT IN
31
LPC_AD LPC_AD SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS DEBUG_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L
D
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
LPC_CLK33M_LPCPLUS LPC_AD LPC_AD SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
IN BI BI
OUT IN IN BI
25 73 19 36 73 19 36 73
38 38 73 38 19 36
IN
19 36
OUT
36 37
OUT
36 37
OUT
36 37
OUT
36
OUT
35 36 37
OUT
18
=PP3V3_S5_ROM
R5190 1
516S0573
10K 5% 1/16W MF-LF 402 2 73 48 38 21
IN
SPI_CLK_R
C
73 48 38 21
R5191
IN
C
SPI_MOSI_R
1
10K 5% 1/16W MF-LF 402 2
LPCPLUS_NOT
R5146 0 1
SPI_MLB_CS_L
2
5% 1/16W MF-LF 402
PLACEMENT_NOTE=PLACE NEXT TO U5110
=PP3V3_S5_LPCPLUS
38 8
=PP3V3_S5_ROM
R5144
LPCPLUS 1
20K 5% 1/16W MF-LF 402 2
C5124 0.1UF
1
LPCPLUS SEL HIGH OUTPUTS TO B1(ON BOARD ROM) SEL LOW OUTPUTS TO B0 (FRANKCARD ROM)
100K 5% 1/16W MF-LF 402
21
VCC
38
U5110 SPIROM_USE_MLB MAKE_BASE=TRUE
73 21
IN
20% 10V CERM 402
NC7SB3157P6XG 6 S SC70 B1 1
2
=SPI_CS1_R_L_USE_MLB
BI
2
5
R5140
8 38 48
1
SPI_MLB_CS_L
OUT
38 4838 48
OUT
38
CRITICAL
SPI_CS0_R_L
4 A
SPI_ALT_CS_L
B0 3
Pull-up on debug card
2
GND
B
B
PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO
LPCPLUS R5156 0 73 38
OUT
SPI_ALT_CLK
1
2 5% 1/16W MF-LF 402
SPI_CLK_R
IN
21 38 48 73
SPI_MOSI_R
IN
21 38 48 73
LPCPLUS R5157 0
73 38
OUT
SPI_ALT_MOSI
1
LPCPLUS R5158
2 5% 1/16W MF-LF 402
PLACEMENT_NOT=PLACENEXT TO WHERE IT BRANCHES INTO TWO
0 73 38
IN
SPI_ALT_MISO
1
SPI_MISO
2
OUT
21 48 73
5% 1/16W MF-LF 402
A
SYNC_MASTER=K24_MLB
PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO
SYNC_DATE=02/15/2009
A
PAGE TITLE
LPC+SPI Debug Connector DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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7
6
5
MCP79 SMBUS "0" CONNECTIONS
4
3
2
SMC "0" SMBus Connections
1
SMC "A" SMBus Connections
D
NOTE: SMC RMT bus remains powered and may be active in S3 state
D
8 =PP3V3_S0_SMBUS_MCP_0
8 =PP3V3_S0_SMBUS_SMC_0_S0
R5200
MCP79 U1400 (MASTER)
1
1
R5201
2.0K
2.0K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
73 21 13 SMBUS_MCP_0_CLK
SO-DIMM "A"
SMC
J3100
U4900
(Write: 0xA0 Read: 0xA1)
(MASTER)
8 =PP3V3_S3_SMBUS_SMC_A_S3
R5250
=I2C_SODIMMA_SCL
27
36 SMB_0_S0_CLK
75 SMBUS_SMC_0_S0_SCL
=I2C_SODIMMA_SDA
27
36 SMB_0_S0_DATA
75 SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
1
1
R5251
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
MCP Temp
SMC
EMC1403-5: U5535
U4900
(Write: 0x98 Read: 0x99)
(MASTER)
=I2C_MCPTHMSNS_SCL
42
36 SMB_A_S3_CLK
=I2C_MCPTHMSNS_SDA
42
36 SMB_A_S3_DATA
MAKE_BASE=TRUE
73 21 13 SMBUS_MCP_0_DATA
1
1
1K 5% 1/16W MF-LF 402
R5271
TRACKPAD
1K
2
2
J5800
5% 1/16W MF-LF 402
SMBUS_SMC_A_S3_SCL
(Write: 0x90 Read: 0x91)
=I2C_TPAD_SCL
45
=I2C_TPAD_SDA
45
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R5270
SMBUS_SMC_A_S3_SDA MAKE_BASE=TRUE
SO-DIMM "B"
SENSOR ADC
J3200
U6000
(Write: 0xA2 Read: 0xA3)
(WRITE: 0X10 READ: 0X11)
1
R5203
0 MCPSMC_DIGITEMP_YES
5% 1/16W MF-LF 2 402
=I2C_SODIMMB_SCL
28
=I2C_SMC_ADCS_SCL
47
=I2C_SODIMMB_SDA
28
=I2C_SMC_ADCS_SDA
47
SENSOR ADC CAN ONLY WORK IN S0 AS IT HAS I2C BUS PULLED UP TO S0 POWER RAIL
1MCPSMC_DIGITEMP_YES
R5204
0
Mikey
5% 1/16W MF-LF 2 402
C
39 I2C_MIKEY_SCL_R
U6880
=I2C_MIKEY_SCL
39 54
=I2C_MIKEY_SDA
39 54
C 8 =PP3V42_G3H_SMBUS_SMC_BSA
MAKE_BASE=TRUE
39 I2C_MIKEY_SDA_R
SMC "B" SMBus Connections
SMC "Battery A" SMBus Connections
(WRITE: 0X72 READ: 0X73)
8 =PP3V3_S0_SMBUS_SMC_B_S0
MAKE_BASE=TRUE
1
1
R5280
SMC
5% 1/16W MF-LF 402
(MASTER)
MCP79 SMBUS "1" CONNECTIONS 36 SMB_BSA_CLK
1
R5281
1K
U4900
1K
2
2
5% 1/16W MF-LF 402
SMBUS_SMC_BSA_SCL
BATTERY
SMC
J6950
U4900
(See Table)
(MASTER)
=SMBUS_BATT_SCL
39 36 SMB_B_S0_CLK
55
MAKE_BASE=TRUE
36 SMB_BSA_DATA
R5261
2.0K
2.0K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
75 SMBUS_SMC_B_S0_SCL
CPU Temp EMC1403-5: U5515 (Write: 0x98 Read: 0x99)
=I2C_CPUTHMSNS_SCL
42
=I2C_CPUTHMSNS_SDA
42
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
8 =PP3V3_S0_SMBUS_MCP_1
1
R5260
=SMBUS_BATT_SDA
39 36 SMB_B_S0_DATA
55
MAKE_BASE=TRUE
75 SMBUS_SMC_B_S0_SDA MAKE_BASE=TRUE
MCPSMC_DIGITEMP_NO 1
MCP79
R5230
U1400
2.0K
(MASTER) (SLAVE: WRITE:0XE0 READ:0XE1)
5% 1/16W MF-LF 402
1
MCPSMC_DIGITEMP_NO
Mikey
R5231 2.0K
2
Battery Charger
U6880
5% 1/16W MF-LF 402
SMC "B" SMBUS SIGNALS ALSO GET CONNECTED TO MCP SMBUS 1 CONNECTIONS(SEE LEFT SIDE)
ISL6258A - U7000
MCPSMC_DIGITEMP_NO
R5232 0 2 1
2
73 21 SMBUS_MCP_1_CLK
5%39 I2C_MIKEY_SCL_R 1/16W MF-LF 402
73 21 SMBUS_MCP_1_DATA
(WRITE: 0X72 READ: 0X73)
Battery
=I2C_MIKEY_SCL
39 54
=I2C_MIKEY_SDA
39 54
(Write: 0x12 Read: 0x13)
Battery Manager - (Write: 0x16 Read: 0x17)
=SMBUS_CHGR_SCL
56
=SMBUS_CHGR_SDA
56
Battery Temp - (Write: 0x90 Read: 0x91)
R5233 0 2 1
39 I2C_MIKEY_SDA_R
5% 1/16W MF-LF 402 MCPSMC_DIGITEMP_NO
B
B
SMC "Management" SMBus Connections 1MCPSMC_DIGITEMP_YES
The bus formerly known as "Battery B"
R5235
0
8 =PP3V3_S3_SMBUS_SMC_MGMT
5% 1/16W MF-LF 2 402
R5234
U4900
0 MCPSMC_DIGITEMP_YES
R5290
SMC
1
5% 1/16W MF-LF 2 402
(MASTER)
SMC
36 SMB_MGMT_CLK
75 SMBUS_SMC_MGMT_SCL
36 SMB_MGMT_DATA
75 SMBUS_SMC_MGMT_SDA
1
1
R5291
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
Vref DACs U2900 (Write: 0x98 Read: 0x99)
=I2C_VREFDACS_SCL
26
=I2C_VREFDACS_SDA
26
MAKE_BASE=TRUE
U4900
MAKE_BASE=TRUE
(MASTER)
SMC "B" SMBUS SMB_B_S0_CLK
36 39
SMB_B_S0_DATA
36 39
Margin Control U2901 (Write: 0x30 Read: 0x31)
=I2C_PCA9557D_SCL
26
=I2C_PCA9557D_SDA
26
MCP SMBUS1 ACTS AS SLAVE DEVICE FOR MCPSMC_DIGITEMP_YES STUFFED
A
SYNC_MASTER=K24_MLB
SYNC_DATE=01/19/2009
A
PAGE TITLE
K84 SMBUS CONNECTIONS DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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8
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6
5
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7
6
5
4
3
2
1
CPU Voltage Sense / Filter XW5309 8
=PPVCORE_S0_CPU_VSENSE
R5309
SM
4.53K 1
2
CPUVSENSE_IN
1
SMC_CPU_VSENSE
2
PLACEMENT_NOTE=Place near U1000 center
OUT
36
1% 1/16W 1
MF-LF 402
C5309 0.22UF 20% 6.3V
2
D
X5R 402
GND_SMC_AVSS
D
36 37 40 41
Place RC close to SMC
MCP Voltage Sense / Filter XW5359 8
=PPVCORE_S0_MCP_VSENSE
R5359
SM
4.53K 1
2
MCPVSENSE_IN
1
SMC_MCP_VSENSE
2
PLACEMENT_NOTE=Place near U1400 center
OUT
37
1% 1/16W MF-LF
1
402
C5359 0.22UF 20% 6.3V
2
X5R 402
GND_SMC_AVSS
36 37 40 41
Place RC close to SMC
C
C PBUS VOLTAGE SENSE ENABLE & FILTER
Q5315 NTUD3169CZ SOT-963
N-CHANNEL
6
PBUSVSENS_EN_L
D 1
R5316 63
IN
2
=PBUSVSENS_EN
100K
G
1%
S
Enables PBUS VSense
1/16W MF-LF 402
1
divider when high.
3
2
PPBUS_G3HRS5_VSENSE MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=18.5V
D
1
R5385 5 8
27.4K
G
1%
S
=PPBUS_G3HRS5
1/16W MF-LF 402
4
2
RTHEVENIN = 4573 OHMS
P-CHANNEL
B
R5315
SMC_PBUS_VSENSE
36
B
1
R5386
1% 1/16W
1
5.49K
MF-LF 402
OUT
1
100K
0.22UF
1%
20% 6.3V
1/16W MF-LF
2
402
PBUSVSENS_EN_L_DIV
C5385
2 2
X5R 402
GND_SMC_AVSS
36 37 40 41
Place RC close to SMC
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
VOLTAGE SENSING DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
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53 OF 109 SHEET
OF
8
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6
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6
5
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3
2
1
MCP VCore Current Sense Filter R5416 4.53K 60
1
MCPCORES0_IMON
2
SMC_MCP_CORE_ISENSE
OUT
37
1% 1/16W MF-LF
1
C5472
402
0.22UF 20% 6.3V 2
D
X5R
D
402
GND_SMC_AVSS
36 37 40 41
Place RC close to SMC
MCP MEM VDD Current Sense
=PP3V3_S0_MCPDDRISNS
8
64
IN
64
IN
P1V5_S0_KELVIN
MEM_SENSE P1V5_S0_SENSE
MEM_SENSE
U5400 5
1 1
R5410
2
5% 1/16W MF-LF 402
Gain: 50x
R5417 4.53K 1
MEM_SENSE R5411
2SA2154MFV-YAE SOD
1
SMC_MCP_DDR_ISENSE
1
37
C5435
402
0.22UF
C
20% 6.3V 2
X5R 402
P1V5_S0_SENSE_C GND_SMC_AVSS
1
OUT
MEM_SENSE
1/16W MF-LF
P1V5_S0_SENSE_AMP
2 5% 1/16W MF-LF 402
3
2 1%
0
P1V5_S0_SENSE_B
1
C
MCP MEM VDD Current Sense Filter MEM_SENSE
Q5401 MEM_SENSE
20% 10V CERM 402
2
2
10% 16V X5R 402
P1V5_S0_SENSE_E
2
2
3
0.1UF 1
C5400 0.1uF
4
MEM_SENSE C5434
0
MEM_SENSE
1
OPA348 SC70-5
36 37 40 41
Place RC close to SMC
R5412 118
2
1% 1/16W MF-LF 402
MEM_SENSE
CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE =PP3V3_S0_CPUVTTISNS 1
R5492 0.01 1W
2
MF 0612-1
8
IN
=PPCPUVCORE_VTT_ISNS_R
1
2
3
4
=PPCPUVCORE_VTT_ISNS
OUT
CPU VCore Load Side Current Sense / Filter
C5417 0.1uF
1P05_HIGH_SIDE_SENSE
0.5%
1P05_HIGH_SIDE_SENSE
20% 10V CERM 402
Place RC close to SMC
3
8
1P05_HIGH_SIDE_SENSE
R5471
V+
8
6.19K
1P05_HIGH_SIDE_SENSE
U5402 5
IN-
76 ISNS_CPUVTT_P
4
IN+
SC70
59
IN
IMVP6_IMON
R5418
INA213 76 ISNS_CPUVTT_N
OUT
CPUVTT_IOUT
1
1
SMC_CPU_FSB_ISENSE
OUT
37
MF-LF 402
1P05_HIGH_SIDE_SENSE
R5480
1
1
36
C5470 0.22UF
17.4K
20%
1/16W MF-LF
1
OUT
1/16W
2 1%
REF
SMC_CPU_ISENSE
2
1%
4.53K
6
1
C5436
1% 1/16W
0.22UF
MF-LF 402
X5R
402 20% 6.3V
GND 2
2
6.3V 2 402
2
GND_SMC_AVSS
36 37 40 41
X5R 402
GND_SMC_AVSS
B
36 37 40 41
B
Place RC close to SMC
DC-IN (AMON) CURRENT SENSE
DC-IN (BMON) CURRENT SENSE R5401
R5481
4.53K 56
IN
CHGR_BMON
1
4.53K
SMC_BATT_ISENSE
2
OUT
36
56
IN
CHGR_AMON
1% 1/16W MF-LF
SMC_DCIN_ISENSE
2
OUT
36
1% 1/16W
1
402
C5490
MF-LF
1
402
0.22UF 2
20% 6.3V
C5487 0.22UF
2
X5R 402
GND_SMC_AVSS 36 37 40 41
A
1
20% 6.3V X5R 402
GND_SMC_AVSS
PLACE R5401 AND C5490 CLOSE TO SMC
36 37 40 41
SYNC_MASTER=K24_MLB
SYNC_DATE=01/27/2009
A
PAGE TITLE
Current Sensing DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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CPU T-Diode Thermal Sensor INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE 8
R5515
=PP3V3_S0_CPUTHMSNS
47 1
PP3V3_S0_CPUTHMSNS_R
2
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
5% 1/16W MF-LF 402
D 76 10
BI
APN 353S2571
C5521 0.0022uF
3 DN1
10% 50V CERM 402
BI
2
DFN 2 DP1
1
R5516
C5515
THERM*/ADDR
CRITICAL
1
1
10K
0.1uF
EMC1413 SIGNAL_MODOL=EMPTY
76 10
1
U5515
CPU_THERMD_P
DETECT CPU DIE TEMPERATURE
1 VDD
1% 1/16W MF-LF 402
20% 10V CERM 402
7
CPUTHMSNS_THERM_L
D
R5517 10K
2
2
5% 1/16W MF-LF 402
ALERT*
8
CPUTHMSNS_ALERT_L
4 DP2/DN3
SMDATA
9
=I2C_CPUTHMSNS_SDA
BI
39
5 DN2/DP3 GND 6
SMCLK
10
=I2C_CPUTHMSNS_SCL
BI
39
2
CPU_THERMD_N
THRM_PAD 11
76 CPUTHMSNS_D2_P 3
SIGNAL_MODOL=EMPTY
Q5501 DETECT FIN-STACK TEMPERATURE
PLACEMENT NOTE: PLACE U5515 NEAR CPU
1
C5520
1
0.0022uF
BC846BMXXH
10% 50V CERM 402
SOT732-3 2
2
76 CPUTHMSNS_D2_N
C
C
MCP T-Diode Thermal Sensor INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
MCP_T_DIODE_SENSOR 8
R5535
=PP3V3_S0_MCPTHMSNS
MCP_T_DIODE_SENSOR
47 1
2 5% 1/16W MF-LF 402
PP3V3_S0_MCPTHMSNS_R MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
MCP_T_DIODE_SENSOR
MCP_T_DIODE_SENSOR
APN 353S2571 1
1
VDD 76 21
C5522
B
76 21
DFN
1
0.0022uF 10% 50V CERM 402
2 DP1 3 DN1
THERM*/ADDR
CRITICALALERT*
20% 10V CERM 402
7
MCPTHMSNS_THERM_L
8
MCPTHMSNS_ALERT_L
1
1
R5536
R5537
10K 1% 1/16W MF-LF 402
10K
2
2
5% 1/16W MF-LF 402
MCP_T_DIODE_SENSOR
2
MCP_THMDIODE_N
BI
2
EMC1413 SIGNAL_MODOL=EMPTY
DETECT MCP DIE TEMPERATURE
0.1uF
U5535
MCP_THMDIODE_P
BI
C5535
MCP_T_DIODE_SENSOR
4 DP2/DN3
SMDATA
9
=I2C_MCPTHMSNS_SDA
BI
39
5 DN2/DP3 GND 6
SMCLK
10
=I2C_MCPTHMSNS_SCL
BI
39
B
THRM_PAD 11
MCP_T_DIODE_SENSOR 76 MCPTHMSNS_D2_P SIGNAL_MODOL=EMPTY
3
C5540
1
PLACEMENT NOTE: PLACE U5535 NEAR MCP
0.0022uF
1
Q5502
10% 50V CERM 402
DETECT HEAT-PIPE TEMPERATURE
BC846BMXXH SOT732-3
2
2
76 MCPTHMSNS_D2_N
MCP_T_DIODE_SENSOR
PLACEMENT_NOTE=PLACE CLOSE TO J4501 IN A CONVENIENT LOCATION
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/04/2009
A
PAGE TITLE
Thermal Sensors DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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D
D
8
=PP5V_S0_FAN_RT
8
=PP3V3_S0_FAN_RT CRITICAL
R5660 1
C
47K 5% 1/16W MF-LF 402
R5665 36
1
SMC_FAN_0_TACH
47K 2
7
J5601
C
78171-0004 NC
M-RT-SM 5
2 1
FAN_RT_TACH
2
5V DC TACH
3
5% 1/16W MF-LF 402
4
NC
MOTOR CONTROL GND
6
R5661 1
36
518S0521
G
SSM3K15FV 7
FAN_RT_PWM
3
D
SOD-VESM-HF 2
SMC_FAN_0_CTL
Q5660
2 S
1/16W MF-LF 402
1
100K 5%
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
Fan DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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KEYBOARD CONNECTOR PIN NAME
CURRENT
R_SNS
V_SNS
POWER
10UA
2.55 KOHM
0.0255 V
0.255E-6 W
0.204 V
16.32E-6 W
TMP102
V+
3V3 LDO
VDD
60MA MAX
VOUT
60MA MAX
80UA
USB INTERFACES TO MLB
TRACKPAD PICK BUTTONS
SPI HOST TO Z2
KEYBOARD SCANNER
D
PSOC
VDD
18V BOOSTER
VIN
10 OHM
8MA (TYP)
0.6 V
0.2 OHM
0.012 V
1.5 OHM
0.012 V
14MA (MAX)
PP3V3_S3_PSOC
45 7 45 7
PSOC_F_CS_L
45 7
PSOC_MOSI
45 7
PSOC_SCLK
45 7
Z2_MISO
45 7
Z2_CS_L
45 7
Z2_MOSI
45 7
Z2_SCLK
44
44
44
44
44
44
7
7
7
7
7
7
4MA (MAX)
4.7 OHM
WS_KBD18
U5701 CY8C24794 MLF
(SYM-VER2) APN 337S2983 OMIT
113
P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 THRML PAD
WS_KBD17
7 44
41
WS_KBD16N
44
44 WS_KBD15_C
1
2
WS_KBD1
44 7
WS_KBD2
44 7
WS_KBD3
44 7
WS_KBD4
44 7
WS_KBD5
44 7
WS_KBD6
44 7
WS_KBD7
44 7
WS_KBD8
44 7
WS_KBD9
44 7
WS_KBD10
44 7
WS_KBD11
44 7
WS_KBD12
44 7
WS_KBD13
44 7
WS_KBD14
40
WS_KBD15_C
39
WS_KBD14
7 44
WS_KBD13
7 44
38 37
WS_KBD12
36
WS_KBD11
35
26 25 24 23 22 21 20 19 18 17 16 15
7 WS_KBD15_CAP
402
14
7 WS_KBD16_NUM 13
44 7
WS_KBD17
R5715
44 7
WS_KBD18
10K
44 7
WS_KBD19
44 7
WS_KBD20
44 7
WS_KBD21
44 7
WS_KBD22
44 7
WS_KBD23
7 44 7 44
WS_KBD10
44 WS_KBD16N
7 44
WS_KBD9
7 44
33
WS_KBD8
7 44
1
WS_KBD7 WS_KBD1
7 44
WS_KBD2
7 44
R5710
37 36
OUT
9 8 7 6
1K
SMC_ONOFF_L
1
7 WS_KBD_ONOFF_L
2
5
44 8 =PP3V42_G3H_TPAD
5%
WS_KBD3
10
MF-LF
7 44
30
11
2
402
31
12
1% 1/16W
29
27
MF-LF
44
34
32
28
1% 1/16W
4
1/16W
7 44
44 7 WS_LEFT_SHIFT_KBD
MF-LF
1
57
2
C5710
44 7 WS_LEFT_OPTION_KBD
0.1UF
44 7 WS_CONTROL_KBD
20% 10V CERM
2 1
402
WS_KBD4
7 44
WS_KBD5
7 44
WS_KBD6
7 44
31 F-RT-SM
FF14-30A-R11B-B-3H C5725 0.1UF
=PP3V42_G3H_TPAD
2
44 8
1
SMC_MANUAL_RESET LOGIC
TP_PSOC_SDA TP_ISSP_SDATA_P1_0
20%
CRITICAL
5
ISSP SDATA/I2C SDA 44 8
=PP3V3_S3_TPAD
2
WS_LEFT_SHIFT_KBD
1
10V CERM
TC7SZ08AFEAPE SOT665
402
A
44 8
WS_LEFT_SHIFT_KEY
4
TP_PSOC_P1_3 Z2_CLKIN
NC
PLACEMENT_NOTE=NEAR J5713
ISOLATION CIRCUIT
C
3
402
TP_PSOC_SCL
D
29
44 7 75.2E-6 W
R5714 42
32
30
294E-6 W
0.0188 V
43
WS_KBD19 44
WS_KBD20 45
WS_KBD21
WS_KBD22
46
47
49
50
51
CRITICAL
15
C
Z2_DEBUG3
PSOC_MISO
48
WS_KBD23 NC
Z2_RESET
52
2
Z2_KEY_ACT_L
45 7
P2_5 P2_7 P0_1 P0_3 P0_5 P0_7 VSS VDD P0_6 P0_4 P0_2 P0_0 P2_6 P2_4
P2_3 P2_1 3 P4_7 4 P4_5 5 P4_3 6 P4_1 7 P3_7 8 P3_5 9 P3_3 10 P3_1 11 P5_7 12 P5_5 13 P5_3 14 P5_1
WS_CONTROL_KEY
TP_P4_5 45 7
0.021 V
44
P1_7 P1_5 P1_3 18 P1_1 19 VSS 20 D+ 21 D22 VDD 23 P7_7 24 P7_0 25 P1_0 26 P1_2 27 P1_4 28 P1_6
44
1
55
44
WS_LEFT_OPTION_KEY
56
WS_LEFT_SHIFT_KEY
53
Z2_HOST_INTN
44
45 7
NC =PP3V3_S3_TPAD
IN
96E-6 W
BUTTON_DISABLE
54
45 7
APN 518S0637
36E-3 W 0.72E-3 W
17
44
PICKB_L
16
45 7
CRITICAL
J5713
44 8
IC
PSOC USB CONTROLLER
U5725
7 45 44 7
=PP3V42_G3H_TPAD 1
44
Y
C5758 0.1UF
B 2
3
10% 16V X7R-CERM 402
TP_P7_7 TP_ISSP_SCLK_P1_1 ISSP SCLK/I2C SCL
C5726 0.1UF
=PP3V42_G3H_TPAD
2
44 8
1
APN 311S0406 5
R5701 44 8
24 USB_TPAD_P
73 20
1
=PP3V3_S3_TPAD
CRITICAL
10V
TC7SZ08AFEAPE
2
5
CERM 402
SOT665
A
2 73 USB_TPAD_R_P
WS_LEFT_OPTION_KEY
4 44
44 7
1/16W MF-LF 402
WS_LEFT_OPTION_KBD
1
44
Y
U5726
PP3V3_S3_PSOC
5%
B
20%
CRITICAL
DIFFERENTIAL_PAIR=USB2_TPAD
B
44 7 WS_LEFT_SHIFT_KBD
1
44 7 WS_LEFT_OPTION_KBD
3
WS_CONTROL_KBD
6
44 7
B
SN74LVC1G10 SC70
A
4 U5703
37
Y SMC_TPAD_RST_L
C
3
B
2
TO MLB CONNECTOR
R5702 24 USB_TPAD_N
73 20
1
2 73 USB_TPAD_R_N
C5727 5%
1
R5769
0.1UF
1/16W MF-LF 402
=PP3V42_G3H_TPAD
2
44 8
20%
CRITICAL
5
=PP3V3_S3_TPAD
2
10V CERM
TC7SZ08AFEAPE SOT665
A
1
R5771
33K
33K
WS_CONTROL_KEY
Y
U5727
WS_CONTROL_KBD
1
2
5%
1/16W MF-LF 402 2
5%
1/16W MF-LF 402
1/16W MF-LF 402 2
402
4 44 7
R5770
5%
DIFFERENTIAL_PAIR=USB2_TPAD
44 8
1
33K
1
44
B 3
U5701 CHIP DECOUPLING
Alternate Parts
PLACE C5701, C5702 & C5703
PLACE C5704, C5705 & C5706
CLOSE TO U5701
CLOSE TO U5701
TABLE_ALT_HEAD
VDD PIN 22
VDD PIN 49
PART NUMBER
ALTERNATE FOR PART NUMBER
311S0406
311S0447
TPAD BUTTONS DISABLE
BOM OPTION
REF DES
COMMENTS: TABLE_ALT_ITEM
ALL
NXP PART AS ALTERNATE
R5704 =PP3V3_S3_TPAD
1.5 44
PP3V3_S3_PSOC
1
MIN_LINE_WIDTH=0.50MM
2
44
BUTTON_DISABLE
PLACE THESE COMPONENTS CLOSE TO J5800
8 44
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
MIN_NECK_WIDTH=0.20MM
1
C5701
1
4.7UF 2
C5702
1
100PF
20% 6.3V X5R 603
2
5% 50V CERM 402
C5703
1
0.1UF 2
10% 16V X7R-CERM 402
C5704
1
100PF 2
5% 50V CERM 402
C5705
1
0.1UF 2
10% 16V X7R-CERM 402
C5706
5% 1/16W MF-LF 402
4.7UF 2
Q5701
20% 6.3V X5R 603
SSM3K15FV
D
3
SOD-VESM-HF
A
SYNC_MASTER=K24_MLB PLACEMENT_NOTE=PLACE C5702 CLOSE TO U5701 VDD PIN 22
PLACEMENT_NOTE=PLACE C5704 CLOSE TO U5701 VDD PIN 49
SMC_LID 55 37 36
G
S
2
SYNC_DATE=03/04/2009
A
PAGE TITLE
THE TPAD BUTTONS WILL BE DISABLE 1
WELLSPRING 1
WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V
DRAWING NUMBER
IN LID CLOSE => SMC_LID_LC < 0.50V
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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57 OF 109 SHEET
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5
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7
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1
BOOSTER +18.5VDC FOR SENSORS BOOSTER DESIGN CONSIDERATION: - POWER CONSUMPTION - DROOP LINE REGULATION - RIPPLE TO MEET ERS - 100-300 KHZ CLEAN SPECTRUM - STARTUP TIME LESS THAN 2MS
D
45 8
=PP5V_S3_TPAD
D
- R5812,R5813,C5818 MODIFIED
APN 152S0504
CRITICAL CRITICAL
L5801
D5802
3.3UH-870MA
R5806
0
5% 1/16W MF-LF 402
R5805
2
SOD-323
INPUT_SW
1
MIN_LINE_WIDTH=0.50MM
2
PP18V5_S3
IPD FLEX CONNECTOR
7 45
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
5%
MIN_NECK_WIDTH=0.20MM
0.20MM
0
PP18V5_S3_SW
BOOST_SW VLF3010AT-SM-HF
0.50MM
1/16W
B0520WSXG
MF-LF
SWITCH_NODE=TRUE
1
APN 371S0313
402
1 1
PP5V_S3_BOOSTER
MIN_LINE_WIDTH=0.50MM
R5812
C5818 39PF
MIN_NECK_WIDTH=0.20MM 5% 50V
2
2
CERM
APN 353S1401
APN 516S0689
1M
2
402
1% 1/16W MF-LF 402
CRITICAL
J5800 55560-0228
VIN
0.50MM
1
U5805
L
1 1
FB
10%
TPS61045
C5800
2
QFN
3
0.1UF
DO
CTRL
C5819
5
Z2_BOOST_EN
44 7
25V
10V
2
CRITICAL
CERM
2.2UF 10%
PGND
GND
C5817
10%
6
1
0.1UF
9
C5816
7
PAD 1
1
4
3
6
5
8
7
Z2_KEY_ACT_L
7 44
Z2_RESET
7 44
PSOC_F_CS_L
7 44
1
SW
402
THRML
2
44 7 Z2_MOSI
44 7 Z2_DEBUG3
603-1
7 45
Z2_CS_L
X5R
20%
PLACEMENT_NOTE=NEAR J5800
M-ST-SM
1UF
BOOST_FB
4
0.20MM
R5813
8
1% 1/16W
1
MF-LF
R5811
402
10
9
12
11
PSOC_MISO
45 7 Z2_BOOST_EN
14
13
PSOC_MOSI
16
15
PSOC_SCLK
18
17
=I2C_TPAD_SDA
20
19
22
21
44 7 Z2_HOST_INTN
2
100K
Z2_MISO
44 7 Z2_SCLK
44 7
71.5K
1%
NC
PICKB_L
7 44 7 44 7 44 7 44 39
1/16W
2
16V X7R-CERM 402
2
16V MF-LF
X5R
2
603
402
44 7
Z2_CLKIN
45 7
PP3V3_S3_LDO
=I2C_TPAD_SCL
0.50MM
0.50MM
0.20MM
0.20MM
39
PP18V5_S3
7 45
C
C
3V3 LDO FOR IPD
R5873 =PP5V_S3_TPAD 45 8
10 1
2
PP5V_S3_VR
1% 1/16W MF-LF 402
PP3V3_S3_LDO
45 7
VR5802
2.2UF
MM3243DRRE
10% 16V
2
MF
402-HF
1%
1/6W
1
0.1UF
1
CE
VOUT
3
PP3V3_S3_LDO_R
C5854 4.7UF
10%
2
MLF
1
C5838
20%
16V
6.3V
2
X7R-CERM 402
X5R 603
GND
B
4
B
X5R 603
0.2
2
C5853
1
1
R5836
2
CRITICAL
APN 353S1364
VDD
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/25/2009
A
PAGE TITLE
WELLSPRING 2 DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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D
D
C
C
Analog SMS
R5921 PULLS UP SEL PINS TO ENTER STANDBY MODE WHEN PIN IS NOT BEING DRIVEN BY SMC
R5922 1
2
PP3V3_S3_SMS_FILT
5% 1/16W MF-LF 402
=PP3V3_S3_SMS
1 2
8
10
1
VDD R5921 5% 1/16W MF-LF 402
B 36
IN
SMS_ONOFF_L
2
BMA141
10K
LGA 2
NC
7
AMUX
11
AX
10
10% 16V X5R 402
1 C5926 0.01UF
2
10% 16V CERM 402
Desired orientation when placed on board top-side:
NC
B
DNC CRITICAL
12 6
SMS_PWRDN MAKE_BASE=TRUE
C5922 0.1UF
U5920
1
SMS_X_AXIS
OUT
36
SEL0 SEL1
AY
9
SMS_Y_AXIS
OUT
36
ST
AZ
8
SMS_Z_AXIS
OUT
36
+Y Front of system
5
+X +Z (up)
3 4
GND
1
NOSTUFF C5923
NOSTUFF 1 C5924
0.033UF 2
10% 16V X5R 402
NOSTUFF 1 C5925 0.033UF
0.033UF
2
10% 16V X5R 402
2
Circle indicates pin 1 location when placed
10% 16V X5R 402
in correct orientation
C4950-C4952 CAP VALUES WILL BE USED TO GET CUT-OFF FREQUENCY OF ~146HZ
A
A PAGE TITLE
SMS DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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REVISION
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DEBUG_ADC
DEBUG_ADC
R6003
PP3V3_WLAN_F_XW
34 7
1
PP5V_SW_ODD
2
D
R6020
1% 1/16W MF-LF 2 402
R6012
PP3V3_WLAN_F_DIV DEBUG_ADC
226K
1
ADC_CH0
2
1% 1/16W MF-LF 402
1
R6011
DEBUG_ADC 1
2
47
DEBUG_ADC 1
47
C6022
47
2.2UF
1% 1/16W MF-LF 402
2
10% 6.3V X5R 402
47 47
47
DVDD
ADC_CH0 ADC_CH1 ADC_CH2 ADC_CH3 ADC_CH4 ADC_CH5 ADC_CH6 ADC_CH7
22
5
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
6
COM
23 24 1 2 3 4
R6001
QFN
DEBUG_ADC
AD0 AD1
14
I2C ADDRESS: 0X10 / 0X11
SDA SCL
17 16
VREF
7
REFCOMP
8
ADC_SDA ADC_SCL
DEBUG_ADC
ISNS_AIRPORT_P
243 1
2
76
3
+IN
10UF
20% 10V CERM 402
20% 6.3V X5R 603
ISNS_AIRPORT_N
243 1
2
76
76 34
ISNS_AIRPORT_IOUT
1
226K
2
ADC_CH2
47
DEBUG_ADC 1
2
R6032
76 34
2
1
1
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
47 8
DEBUG_ADC
OPA330 4
ISNS_ODD_IOUT
2
76
2
ADC_CH4
10% 50V CERM 402
R6052 280K
2 2
10% 6.3V X5R 402
DEBUG_ADC
DEBUG_ADC 1 1
470PF
C6033
C6054 2.2UF
2
DEBUG_ADC
47
DEBUG_ADC 1
1% 1/16W MF-LF 402
2
R6053 1
1% 1/16W MF-LF 402
280K
2
DEBUG_ADC
1% 1/16W MF-LF 402
C6053
470PF
470PF
1
1
2
2 10% 50V CERM 402
=PP5V_S3_DEBUG_ISNS DEBUG_ADC 1
3.65K 1
2
76
20% 10V 2 CERM 402
DEBUG_ADC
ISNS_1V5_S3_R_P 5
1
DEBUG_ADC
3
R6041
0.1UF 20% 10V
V+
-IN
V-
76
DEBUG_ADC
SC70-5
R6044
R6060
4
226K
412
ISNS_1V5_S3_IOUT
1
2
ADC_CH3
1% 1/16W MF-LF 402
GAIN: 273X
ISNS_1V5_S3_R_N
1
IN
ISNS_HDD_P
1
2
76
ISNS_HDD_R_P
DEBUG_ADC
5
1
R6043
1M 2 2
1M
1
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
3
R6061 76 34
R6042
470PF
DEBUG_ADC
DEBUG_ADC
DEBUG_ADC 1 1
10% 6.3V X5R 402
IN
+IN
V+
1
2
DEBUG_ADC
OPA330
R6064
SC70-5
4
ISNS_HDD_IOUT
76
1
GAIN: 845X
ISNS_HDD_R_N
226K
2
ADC_CH5
1% 1/16W MF-LF 402
V-
-IN
2
412
ISNS_HDD_N
PLACEMENT_NOTE=PLACE RC NEAR U6000
U6041
1% 1/16W MF-LF 402
C6044
B
DEBUG_ADC
2.2UF 2
10% 50V CERM 402
76 34
47
DEBUG_ADC
1% 1/16W MF-LF 402
C6042
402
DEBUG_ADC
OPA330
2
3.65K 2
+IN
C6041
2 CERM
PLACEMENT_NOTE=PLACE RC NEAR U6000
U6031
1% 1/16W MF-LF 402
1
DEBUG_ADC 1
C6031 0.1UF
R6040
ISNS_1V5_S3_N
226K 1% 1/16W MF-LF 402
GAIN: 561X
ISNS_ODD_R_N
C6052
DEBUG_ADC
ISNS_1V5_S3_P
1
V-
-IN
C
R6054
SC70-5
V+ 2
499
ISNS_ODD_N
IN
10% 6.3V X5R 402
DEBUG_ADC
301K
+IN
3
R6033
301K 2
1
R6051
C6034
PLACEMENT_NOTE=PLACE RC NEAR U6000
U6040 5
10% 50V CERM 402
2
DEBUG_ADC
1
2.2UF
DEBUG_ADC
DEBUG_ADC 1
C6062
2
10% 50V CERM 402
R6063
348K 2 2
10% 6.3V X5R 402
DEBUG_ADC
R6062
1
470PF
10% 50V CERM 402
C6064
2
C6043
47
DEBUG_ADC 1
1% 1/16W MF-LF 402
470PF
1
1% 1/16W MF-LF 402
348K 1% 1/16W MF-LF 402
PLACEMENT_NOTE=PLACE NEAR D9710
2
DEBUG_ADC
C6063 470PF
OMIT
1
2
XW6080
=PP5V_S3_DEBUG_ISNS 1
SM
PPVOUT_S0_LCDBKLT
DEBUG_ADC
1
68 65 7
C6050 0.1UF
2
3
A IN-
SC70
ISNS_LCDBKLT_IOUT
6
ISNS_LCDBKLT_P
4
IN+
REF
1
GAIN: 200X
1
226K
ADC_CH6
2
1% 1/16W MF-LF 402
47
1
C6074 2.2UF
GND 2
2
SYNC_MASTER=K19_IMLB
R6082 1
226K
2
1% 1/16W MF-LF 402
R6081
10% 6.3V X5R 402
2
2
DIVIDER: 1/22
A
DEBUG SENSORS AND ADC
DEBUG_ADC 1
DRAWING NUMBER
C6082
Apple Inc.
2.2UF
1% 1/16W MF-LF 402
SYNC_DATE=02/25/2009
PAGE TITLE
ADC_CH7
47.0K
DEBUG_ADC 1
DEBUG_ADC
PPVOUT_S0_LCDBKLT_DIV DEBUG_ADC
R6074
DEBUG_ADC
PLACEMENT_NOTE=PLACE RC NEAR U6000
1% 1/16W MF-LF 2 402
DEBUG_ADC
OUT
R6080 1M
PLACEMENT_NOTE=PLACE RC NEAR U6000
INA210 5
10% 50V CERM 402
PPVOUT_S0_LCDBKLT_XW
1
U6050 ISNS_LCDBKLT_N
2
DEBUG_ADC
20% 10V CERM 402
V+
IN
20% 6.3V CERM 402-LF
20% 10V CERM 402
DEBUG_ADC
ISNS_ODD_R_P
DEBUG_ADC
DEBUG_ADC 1 10% 50V CERM 402
76
DEBUG_ADC
2.2UF
470PF
2 1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
GAIN: 1239X
1
1
R6034
ISNS_AIRPORT_R_N
C6032
499
ISNS_ODD_P
IN
DEBUG_ADC
4
V-
-IN
PLACEMENT_NOTE=PLACE RC NEAR U6000
2
DEBUG_ADC
76 68
2.2UF 2
0.1UF
R6050
1% 1/16W MF-LF 402
IN
2
C6006
C6040
2
SC70-5
V+
R6031
76 68
39
DEBUG_ADC 1
C6005
0.1UF
DEBUG_ADC
OPA330
5
1
DEBUG_ADC
47 8
DEBUG_ADC 1
C6004
25
20
19
18
9
11
10
1
20% 10V CERM 402
U6030
ISNS_AIRPORT_R_P
1% 1/16W MF-LF 402
C
2
DEBUG_ADC
R6030
IN
IN
DEBUG_ADC
C6030 0.1UF
76 58
=I2C_SMC_ADCS_SCL
5% 1/16W MF-LF 402
ADC_REFCOMP DEBUG_ADC
DEBUG_ADC
IN
PLACEMENT_NOTE=PLACE CLOSE TO U4900
2
=PP5V_S3_DEBUG_ISNS 1
B
R6002 33
2
39
BI
DEBUG_ADC
ADC_VREF
LSB: 0.001V
76 58
=I2C_SMC_ADCS_SDA
1
1
D
PLACEMENT_NOTE=PLACE CLOSE TO U4900
2
5% 1/16W MF-LF 402
THRM PAD
GND
ADC RANGE: 0V TO 4.096V
IN
20% 6.3V X5R 603
33 1
15
DIVIDER: ~ 2/5
76 30
8
DEBUG_ADC
LTC2309
DIVIDER: ~ 2/3
IN
C6003
=PP5V_S3_DEBUG_ADC_DVDD
10UF 2
U6000
47
76 30
1
20% 10V CERM 402
2
47
47
47 8
C6002 0.1UF
20% 6.3V X5R 603
AVDD ADC_CH1
2
681K
10% 6.3V X5R 402
2
226K 1% 1/16W MF-LF 402
R6021
2.2UF
1% 1/16W MF-LF 402
1
10UF
R6022 1
1
C6012
1M
C6001
2
DEBUG_ADC
2
5% 1/16W MF-LF 402
DEBUG_ADC
PP5V_SW_ODD_DIV DEBUG_ADC
47
1
20% 10V CERM 402
PLACEMENT_NOTE=PLACE RC NEAR U6000
1M
DEBUG_ADC
C6000
10
1
DEBUG_ADC
12
PLACEMENT_NOTE=PLACE RC NEAR U6000
1% 1/16W MF-LF 402
2
2
1
R6010
DEBUG_ADC
0.1UF
DEBUG_ADC
1
2
1
PP5V_SW_ODD_XW
DEBUG_ADC 634K
DEBUG_ADC
PP5V_S3_DEBUG_ADC_DVDD_FILT
21
SM 2
R6004 PP5V_S3_DEBUG_ADC_AVDD_FILT
2
5% 1/16W MF-LF 402
XW6020
SM 1
10
1
OMIT
XW6010 PP3V3_WLAN_F
8
13
OMIT
30
=PP5V_S3_DEBUG_ADC_AVDD
PLACEMENT_NOTE=PLACE NEAR Q4590
PLACEMENT_NOTE=PLACE NEAR Q3450
10% 6.3V X5R 402
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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1
D
D
38 8
=PP3V3_S5_ROM
R61901
R6100 1
10K
R6150 73 38 21
IN
IN
5% 1/16W MF-LF 402 2
R6101 3.3K
1
20% 10V CERM 402
1
C
CRITICAL
VCC
U6100
2
32MBIT
R6152
SOP
2
73
SPI_CLK
5% 1/16W MF-LF 402
SPI_MLB_CS_L
C6100 0.1UF
5% 1/16W MF-LF 2 402
0
SPI_CLK_R
PLACEMENT_NOTE=PLACE CLOSE TO U6100 38
1
3.3K
5% 1/16W MF-LF 402 2
8
NO STUFF
C
6
SCLK
SI/SIO0
5
73
0
SPI_MOSI
1
MX25L3205DM2I-12G 1
SPI_WP_L SPI_HOLD_L
3 7
CE* WP*/ACC HOLD*
R6105
OMIT SO/SIO1
2
73
SPI_MISO_R NO STUFF
1
GND
R6191
1
0 5% 1/16W MF-LF 402
2
2 5% 1/16W MF-LF 402
SPI_MOSI_R
IN
21 38 73
PLACEMENT_NOTE=PLACE CLOSE TO U6100
SPI_MISO
OUT
21 38 73
PLACEMENT_NOTE=PLACE CLOSE TO U6100
4
10K
2
5% 1/16W MF-LF 402
MCP79 SPI Frequency Select Frequency
B
SPI_MOSI
SPI_CLK
31 MHz
0
0
42 MHz
0
1
25 MHz
1
0
1 MHz
1
1
B
25MHz is selected with R5190 and R5191 Any of the 4 frequencies can be selected with R6190, R6191, R5190 and R5191
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/15/2009
A
PAGE TITLE
SPI ROM DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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REVISION
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1
AUDIO CODEC APPLE P/N 353S2355
L6201
U6201 CONSUMES 33MA MAX. FROM 1.8V RAIL
FERR-220-OHM 8
1
=PP1V8_S0_AUDIO
IN
2
VOLTAGE=1.8V MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM
C6210
D
1
1
C6211
4.7UF
0.1UF
20% 4V X5R 402
10% 16V X5R 402
2
2
C6216
C6221 R6210 2.67K
2
GPIO1 = HP AMP CONTROL GPIO3 = SPKR AMP SHDN CONTROL
1
10UF
20% 6.3V X5R 603-1
20% 6.3V X5R 603-1
2
2
VBIAS_DAC CS4206_FP CS4206_FN
CRITICAL
1% 1/16W MF-LF 402
29 44 41
OUT AUD_GPIO_0
2
51
OUT AUD_GPIO_1
12
TP_AUD_GPIO_2 NC AUD_GPIO_3 OUT
54
25
46
VD VA_REF VA_HP VA VBIAS_DAC HPOUT_L VHP_FILT+ VHP_FILTU6201 HPOUT_R CS4206ACNZC HPREF
C6222
1
1
2.2UF 20% 6.3V CERM 402-LF
73 21
73 21
IN
73 21
IN
1
HDA_SDIN0
OUT
NC
2
2
2
20% 16V TANT-POLY 2012-LLP
1
2
2
10UF 20% 6.3V X5R 603-1
CRITICAL
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM
AUD_HP_PORT_L AUD_HP_PORT_R
OUT
40
OUT
51
39
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM
AUD_HP_PORT_REF
IN
53
LINEIN_L+ LINEIN_CLINEIN_R+
21
MICIN_L+ MICIN_LMICIN_R+ MICIN_R-
18
VREF+_ADC
27
CS4206_VREF_ADC
NC
4
TP_AUD_DMIC_CLK
NC
1
VL_IF
6
BITCLK
8 5 11
47
AUD_SPDIF_OUT_CHIP
22
1
48
34 36 37
NC NC
AUD_LO2_P_L AUD_LO2_N_L AUD_LO2_P_R AUD_LO2_N_R
30 32 33
51
AUD_CODEC_MICBIAS
OUT
52
OUT
52
OUT
FR SPKR AMP. SIG. SOURCE
52
OUT
52
OUT
52
OUT
52
OUT
54
LFT. SPKR AMP. SIG. SOURCE RT. SPKR AMP. SIG. SOURCE
C
CS4206_VCOM
AUD_LI_P_L AUD_LI_REF AUD_LI_P_R
22
23
IN
50
IN
50
IN
50
IN
54
IN
54
IN
54
IN
54
SYNC SDI SDO RESET*
SPDIF_IN SPDIF_OUT
2
DMIC_SCL
5% 1/16W MF-LF 402
TP_AUD_LO1_P_L TP_AUD_LO1_N_L AUD_LO1_P_R AUD_LO1_N_R
28
VL_HD
49 51 53 49 50 53 54
38
VCOM
3
7 49
C6213
GND_AUDIO_HP_AMP
16
FLYP FLYC FLYN CRITICAL
AUD_SDI_R
AUD_SPDIF_OUT
OUT
10% 16V X5R 402
MICBIAS
42
10
R6212 53
1
0.1UF
31
43
20% 6.3V CERM 402-LF
5% 1/16W MF-LF 402
HDA_SDOUT HDA_RST_L TP_AUD_SPDIF_IN
C6214 2
LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+ LINEOUT_R2-
2.2UF
R6211 22
D IN
AUD_MIC_INP_L AUD_MIC_INN_L AUD_MIC_INP_R AUD_MIC_INN_R
17 19 20
EXT MIC CODEC INPUT BI MIC CODEC INPUT
7
DGND THRM_PAD AGND 26
HDA_SYNC
2
10% 16V X5R 402
SENSE_A
49
IN
2
2
13
C 73 21
10UF
C6215 0.1UF
10% 10V X5R 402-1
15
C6223
CS4206_FLYN
HDA_BIT_CLK
C6217
35
45
IN
1
LINEOUT_L1+ LINEOUT_L1LINEOUT_R1+ LINEOUT_R1-
CS4206_FLYP CS4206_FLYC
73 21
8 49 53 54
1
GPIO0/DMIC_SDA1 GPIO1/DMIC_SDA2 /SPDIF_OUT2 GPIO2 GPIO3
14
AUD_SENSE_A
IN
=PP3V3_S0_AUDIO
QFN
53
52
10% 16V X5R 402
C6220
1
10UF
1
0.1UF
2
9
CRITICAL
PP4V5_AUDIO_ANALOG
IN
C6218 24
GND_AUDIO_HP_AMP
1
GPIO0 = ANALOG SW CONTROL
20% 16V TANT-POLY 2012-LLP
1
1UF
1
10UF
49 7
8 49 51 53
PP4V5_AUDIO_ANALOG
C6219 53 51 49
=PP5V_S3_AUDIO PP1V8_S0_AUDIO_DIG
0402
CRITICAL
C6224
1
20% 16V TANT 0603-SM
1
C6225
NOSTUFF
10UF
1UF 2
1
20% 2 16V POLY-TANT CASE-B2-SM
100K
B
2
54 53 50 49
R6213 5% 1/16W MF-LF 402
B
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
GND_AUDIO_CODEC
4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2456 NOTES ON CODEC I/O L6200
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM VOLTAGE=5V
FERR-220-OHM 53 51 49 8
IN
=PP5V_S3_AUDIO
1
2
TPS71745
4V5_REG_IN
6
IN
4V5_REG_EN
4
EN
0402
IN
=PP3V3_S0_AUDIO
2.21K 1
SON
OUT
1
PP4V5_AUDIO_ANALOG
OUT
DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS
7 49
CRITICAL
R6200 54 53 49 8
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM VOLTAGE=4.5V
U6200 NR/FB
3
NC
5
4V5_NR
2 1% 1/16W MF-LF 402
GND 1
C6200
1
1UF 2
10% 10V X5R 402
C6201
2
1
C6202
1UF
PLACE NEAR U6200
XW6200
2
10% 16V X7R-CERM 402
SM 1
1
2 2
C6203 1UF
0.1UF
10% 10V X5R 402
10% 10V X5R 402
GND_AUDIO_CODEC
2
49 50 53 54
NOSTUFF
A
R6201
SYNC_MASTER=AUDIO
0 1
SYNC_DATE=06/09/2009
AUDIO: CODEC/REGULATOR
5% 1/16W MF-LF 402
DRAWING NUMBER
Apple Inc.
XW6201 SM 1
A
PAGE TITLE
2
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
2
PLACE NEAR C6220 AND C6221
051-7982 C.0.0
49 51 53
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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GND_AUDIO_HP_AMP
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1
D
D LINE INPUT VOLTAGE DIVIDER CODEC RIN = 20K OHMS NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS) FC_HP = 3.6 HZ FC_LP = 43KHZ VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
C6301
R6301 53
IN
AUD_LI_L MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
2.2UF
7.87K2
AUD_LI_L_DIV
1
1
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1% 1/16W MF-LF 402
2
20% 10V X5R-CERM 402
C NOSTUFF 1
C6303 820PF
10% 50V 2 CERM 402
AUD_LI_P_L
49
OUT
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
C
1
R6302 21.5K
1% 1/16W MF-LF 2 402
CRITICAL
C6302 2.2UF 1
2
20% 10V X5R-CERM 402
53
IN
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
AUD_LI_GND
AUD_LI_REF MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
OUT
49
1
R6300 10
CRITICAL
1% 1/16W MF-LF 2 402
C6312 2.2UF 1
54 53 49
IN
GND_AUDIO_CODEC 1
2
20% 10V X5R-CERM 402
NOSTUFF
C6313 820PF
10% 50V 2 CERM 402
B
1
R6312
B
21.5K 1% 1/16W MF-LF 2 402
CRITICAL
C6311
R6311 53
IN
AUD_LI_R MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
7.87K2
1
1% 1/16W MF-LF 402
2.2UF
AUD_LI_R_DIV MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1
2
20% 10V X5R-CERM 402
AUD_LI_P_R MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
OUT
49
A
A PAGE TITLE
AUDIO: LINE INPUT FILTER DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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D
D L6520
53 49 8
FERR-120-OHM-1.5A =PP5V_S3_AUDIO 1 2
HP/LO AMP APN: 353S1637
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_PP5V_F
0402-LF 1
C6520
1
0.1UF
C6521 10UF
20% 2 6.3V X5R 603
MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM 12
10% 2 16V X7R-CERM 402
AUD_LO_AMP_INL_M
AUD_LO_AMP_INR_M
6 INL 8 INR
AUD_GPIO_1_R
5 SHDN*
51 51
U6500 MAX9724A
2
5% 1/16W MF-LF 402
AUD_HP_PORT_L CRITICAL
C6500
1 1
R6522
0.1UF
NC
10% 16V X7R-CERM 402
IN
C6522 1UF
39
53 51 49
OUT
51 53
R6523 2.21K
C6524
1
R6524
1% 1/16W MF-LF 2 402
1UF
CRITICAL 1
10% 10V 2 X5R 402
GND_AUDIO_HP_AMP 53 51 49
2
51 53
10% 2 10V X5R 402
2.21K
1% 1/16W MF-LF 2 402
MAX9724_SVSS
5% 1/16W MF-LF 2 402
R65001 5% 1/16W MF-LF 402
1
MAX9724_C1N
AUD_LO_AMP_OUTR
OUT
1
CRITICAL
C1P 1 C1N 3
100K 2
AUD_HP_ZOBEL_L
C
MAX9724_C1P
4 PVSS
0
9 SVSS
1
7 SGND
IN
AUD_GPIO_1
13 THRM PAD
51 49
IN
OUTL 11 OUTR 10
TQFN
R6520 49
2 PGND
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
VDD CRITICAL
AUD_LO_AMP_OUTL
MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM
CRITICAL 1
C6523
C
1UF
10% 10V 2 X5R 402
GND_AUDIO_HP_AMP
R65101 39 5% 1/16W MF-LF 402
NC
MAX9724 GAIN/FILTER COMPONENTS
2
AUD_HP_ZOBEL_R
AV_PB = -1V/V, FC_LPF = 35.2KHZ CRITICAL
C6510
CRITICAL 1
C6530
0.1UF 10% 16V X7R-CERM 402 51 49
IN
330PF 1
2
AUD_HP_PORT_R
2 5% 50V COG 402
R6531 13.7K2
1
1% 1/16W MF-LF 402
B
AUD_HP_PORT_L 51 49
IN
R6530 13.7K2
AUD_LO_AMP_INL_M
1
B
AUD_LO_AMP_OUTL
51
OUT
51 53
OUT
51 53
1% 1/16W MF-LF 402
AUD_HP_PORT_R 51 49
IN
R6532 13.7K2
AUD_LO_AMP_INR_M
1
AUD_LO_AMP_OUTR
51
1% 1/16W MF-LF 402
R6533 13.7K2
1
1% 1/16W MF-LF 402
CRITICAL
C6531 330PF 1
2 5% 50V COG 402
A
SYNC_MASTER=AUDIO
SYNC_DATE=06/09/2009
A
PAGE TITLE
AUDIO: HEADPHONE FILTER DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
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1
DYNAMIC (SUB) AND PIEZO (SATELLITE) SPKR AMPLIFIERS NO STUFF
C6612 180PF
SATELLITE
HPF FC = 775 HZ
SUB SUB GAIN SAT GAIN
80 HZ < HPF FC < 132 HZ 6DB (2V/V) 5.6DB (1.91V/V)
1
2
5% 50V CERM 402
R6615 26.1K2
1
NO STUFF
1% 1/16W MF-LF 402
C6613 180PF 1
D
D
2
5% 50V CERM 402
R6616 26.1K2
1
ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
=PP5V_S3_AUDIO_AMP
D3
CRITICAL
C6607 1
1
A2
52 8
1% 1/16W MF-LF 402
APN:353S2630 10% 10V X5R 2 402
CRITICAL
IN
0.015UF 1
0402 CRITICAL
L6611
49
IN
52
C
IN
R6613
10% 16V X7R 402
1% 1/16W MF-LF 402
10% 16V X7R 402
AUD_GPIO_3
BGA
C3
C2 D1
C1P C1N
100K
R6610 0
5% 1/16W MF-LF 2 402
2
5% 1/16W MF-LF 402
R6617 SPKRAMP_R_N_OUT_R LM48556_C1P_R
6.8
2
6.8
5% 1/8W MF-LF 805
2
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_P_OUT 7 53 MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_N_OUT 7 53
5% 1/8W MF-LF 805
C6604 4.7UF
10% 10V 2 X5R 805
SVSS
LM48556_VSS_R
1
CRITICAL 1
C1
CPVSS PGND
R6611
1
OMIT
OUT+ B2 OUT- A1
CRITICAL
SD*
1
1
SPKRAMP_SHDN
A3 IN+ B3 IN-
LM48311_R_P LM48311_R_N
1% 1/16W MF-LF 402
R6612
SPKRAMP_R_P_OUT_R
LM48556TL
LM48311_R_P_C 113.7K2
C6611 FERR-1000-OHM R6614 0.015UF 2 SPKRAMP_INR_N 1 2 LM48311_R_N_C 113.7K2 AUD_LO2_N_R 1 0402
49
2
OMIT
10% 16V 2 X5R-CERM 0805
SVDD
U6610
D2
49
C6610
FERR-1000-OHM 1 2 SPKRAMP_INR_P AUD_LO2_P_R
PVDD
B1
L6610
C6601 10UF
1UF
LM48556_C1N_R
CRITICAL 1
C6602 10UF
10% 16V 2 X5R-CERM 0805
C
ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM 52 8
=PP5V_S3_AUDIO_AMP CRITICAL
APN:353S2621 C6608 L6620
49
IN
AUD_LO1_P_R
1
2
0.1UF
SPKRAMP_INSUB_P
0402
IN
1
AUD_LO1_N_R
2
SPKRAMP_INSUB_N
0402
52
CRITICAL
C6621
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_P_OUT 7 53
20% 2 6.3V TANT1 2012-LLP
U6620 LM48311 BGA
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_N_OUT 7 53
OUTA A3 OUTB C3
A2 SD*
0.1UF 1
C6603 47UF
B2 B1 PVDD VDD CRITICAL
A1 IN+ C1 IN-
LM48311_SUB_P LM48311_SUB_N
2
10% 16V X5R 402
L6621
FERR-1000-OHM 49
10% 10V X5R 2 402
C6620 1
1
1UF
CRITICAL
FERR-1000-OHM
1
2
PGND GND 10% 16V X5R 402
B3
C2
SPKRAMP_SHDN NO STUFF
C6634 180PF 1
R6634
B
2
5% 50V CERM 402
26.1K2
B
1
1% 1/16W MF-LF 402
NO STUFF
C6635 180PF 1
2
5% 50V CERM 402
R6635 26.1K2
1
ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM 52 8
1% 1/16W MF-LF 402
APN:353S2630
=PP5V_S3_AUDIO_AMP
C6609 1
L6630
IN
AUD_LO2_P_L
1
2
SPKRAMP_INL_P
0402
L6631
49
IN
AUD_LO2_N_L
A
1UF
C6630
FERR-1000-OHM 49
R6631
0.015UF 1
2 10% 16V X7R 402
LM48311_L_P_C
13.7K2
1
1% 1/16W MF-LF 402
CRITICAL
LM48311_L_P
LM48311_L_N
BGA
C3
1/16W MF-LF 402
SPKRAMP_L_P_OUT_R
CRITICAL
D2
OMIT
R6630 1
OMIT
OUT+ B2 OUT- A1 C1P C1N
C2 D1
CPVSS
C1
SD*
PGND
SPKRAMP_SHDN
10UF
LM48556TL A3 IN+ B3 IN-
C6605
10% 16V 2 X5R-CERM 0805
SVDD
U6630
10% 10V X5R 2 402
C6631 FERR-1000-OHM R6632 0.015UF 13.7K2 1 2 SPKRAMP_INL_N 1 2 1 0402 LM48311_L_N_C 1% 10% 16V X7R 402
52
PVDD
R6633 SPKRAMP_L_N_OUT_R LM48556_C1P_L CRITICAL 1
C6633
1
6.8
6.8
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_P_OUT 7 53
2
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_N_OUT
5% 1/8W MF-LF 805
2
7 53
5% 1/8W MF-LF 805
4.7UF
SVSS
LM48556_C1N_L
B1
CRITICAL
A2
D3
CRITICAL 1
10% 10V 2 X5R 805
SYNC_MASTER=AUDIO
SYNC_DATE=06/09/2009
AUDI0: SPEAKER AMP
CRITICAL 1
A
PAGE TITLE
LM48556_VSS_L
DRAWING NUMBER
C6632
Apple Inc.
10UF
10% 16V 2 X5R-CERM 0805
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX 54 49 8
=PP3V3_S0_AUDIO
AUD_SPDIF_OUT
IN
49
HS_MIC_HI
OUT
54
HS_MIC_LO
OUT
54
L6701 FERR-1000-OHM 1
2
0402
AUD_CONNJ1_MIC
L6702
PLACE NEAR J6700
FERR-1000-OHM 1
D
2
L6703
MIN_LINE_WIDTH=0.4MM
FERR-120-OHM-1.5A
APN:514-0694
1
AUDIO-JACK-TRANS-K83
SM 1
8
1
AUD_CONNJ1_SLEEVEDET AUD_CONNJ1_TIP AUD_CONNJ1_RING
7
AUD_LI_GND 2
50
AUD_CONN_GND
L6705
5353
FERR-220-OHM
AUDIO
AUD_CONN_R
2
BI
53
0402
5
AUD_IP_PERPH_DET_JACK
3 4
AUD_CONNJ1_TIPDET
L6706 FERR-1000-OHM
HP DETECT
1
9
MIC CONNECTOR
AUD_IP_PERPH_DET
2
OUT
54
10 11
CRITICAL
J6701
APN:518S0520
0402
78171-0003 M-RT-SM
R6700 CRITICAL
OPERATING VOLTAGE 3.3 1
12
2
2
10% 2
14
2
CRITICAL
CERM 402
4
AUD_J1_SLEEVEDET_R 2
OUT
54
402
54 7 54 7
CRITICAL
2
6.3V
10K 5% 1/16W MF-LF 402
6.8V-100PF
402
1UF
13
DZ6703
6.8V-100PF
C6700
1
CRITICAL
DZ6705
POF
SHIELD PINS
1
53
BI
CRITICAL
1
A - VIN B - VCC C - GND
SM
AUD_CONN_L
2 0402
6
PHS DETECT GND
49 51
XW6701
FERR-220-OHM
F-RT-TH
GND_AUDIO_HP_AMP 2
PLACE NEAR J6700
L6704
1
49
XW6700
0402-LF
2
OUT
PLACE NEAR J6700 AUD_CONN_GND
CRITICAL
CRITICAL
D
AUD_HP_PORT_REF
2
MIN_NECK_WIDTH=0.2MM
2
OMIT
J6700
C
SM
1
CRITICAL
AUD_CONNJ1_SLEEVE
SHELL
XW6702
0402
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
54 7
2
CRITICAL
DZ6704
CRITICAL
1
DZ6702
DZ6701
6.8V-100PF
6.8V-100PF
402
402
DZ6700
1
6.8V-100PF
402 1
2
1
1 1
4.7
3
AUD_J1_TIPDET_R 2
OUT
C
5
54
5% 1/16W MF-LF 402
402
1
1
R6701
2
1
6.8V-100PF
BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI
C6701 100PF 5%
2
50V
CERM 402
SPEAKER CONNECTORS
APN:518S0519 CRITICAL
J6702 78171-0002 M-RT-SM 3
R6724 51 49 8
=PP5V_S3_AUDIO
1
0
AUD_LO_AMP_OUTL
1
2
AUD_LO_AMP_OUTL_SWITCH
2
10% 10V X5R 402
2
R6718 1
NC1
C1
NC2
A4
NO1 NO2
C2 5% 1/16W MF-LF 402
WLP
A2
CB
COM2
B1
EN*
C6711
1
0.0033UF
5% 1/16W MF-LF 402
10% 50V CERM 402
B2
24K
52 7
IN
5% 1/16W MF-LF 2 402
52 7
IN
0
1
IN
2
54 50 49
0 1
2 5% 1/16W MF-LF 402
GND STUFFING OPTIONS FOR CMOS SWITCH GND_AUDIO_CODEC
1
2 CERM
B DYN. FULL RANGE
4
2
402
0603
CRITICAL
53
J6704
78171-0003 M-RT-SM 4
CRITICAL
L6709
FERR-120-OHM-3A
1
R6713
2
24K
52 7
IN
5% 1/16W MF-LF 2 402
52 7
IN
1
SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT
2
SPKRAMP_R_P_OUT_CONN
1 2
0603
SPKRAMP_R_N_OUT_CONN
RT. PIEZO
3
CRITICAL
1
1
L6710
C6706
FERR-120-OHM-3A
5
100PF
5%
5%
50V
2 50V CERM
402
R6715 AUD_CONN_GND
5% 50V
CERM 2
402
1
2 0603
R6721 100K
53
L6708
FERR-120-OHM-3A
100PF
100PF
2
2
CRITICAL
1C6704
5% 50V
C6707
1
1
SPKRAMP_SUB_N_OUT_CONN
AUD_CONN_R
AUD_SWITCH_CTRL
5% 1/16W MF-LF 402
A
1
2 SPKRAMP_SUB_P_OUT_CONN 0603
100PF CERM 2 402
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
1
SPKRAMP_SUB_P_OUT SPKRAMP_SUB_N_OUT
C6705
R6720 AUD_GPIO_0 49
3
L6707
GND AUD_LI_R_SWITCH
2
CRITICAL
NEG
B3
1
B4
BI
SWITCH_CP
0
AUD_LI_R IN
402
CRITICAL 53
R6712
COM1
CRITICAL
R6719 50
5%
FERR-120-OHM-3A
AUD_LI_L_SWITCH
2
100PF
M-RT-SM
AUD_CONN_L BI
MAX14504
C4
A1
0
AUD_LI_L IN
C6702
J6703
U6700 AUD_LO_AMP_OUTR_SWITCH
5% 1/16W MF-LF 402
50
2 50V CERM
1
C3
1
2
4
78171-0002
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
A3
0
AUD_LO_AMP_OUTR
1
APN: 353S2536
VCC OUT
LEFT PIEZO
2
1
5% 50V
CERM 402
R6717 51
1
100PF
C6710
5% 1/16W MF-LF 402
B
SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT
1UF
0
OUT
IN
C6703 1
R6716 51
IN
52 7
PP_MAX14504_VCC
2
5% 1/16W MF-LF 402
52 7
5% 1/16W MF-LF 402
ANALOG AUDIO IO SWITCH GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED
AUD_SWITCH_GND
SYNC_MASTER=AUDIO 0 1
0 1
5% 1/16W MF-LF 402
A
AUDIO: JACK
R6727
2
SYNC_DATE=06/09/2009
PAGE TITLE
NOSTUFF
R6714
DRAWING NUMBER
2
Apple Inc.
5% 1/16W MF-LF 402
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
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PAGE
67 OF 109 SHEET
OF
8
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8
7
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1
PORT B LEFT(HEADSET MIC) HP=80HZ, LP=8.82KHZ
CODEC OUTPUT SIGNAL PATHS
MIKEY
FUNCTION
VOLUME
CONVERTER
PIN COMPLEX
MUTE CONTROL
DET ASSIGNMENT
HP/LINE OUT
0X02 (2)
0X02 (2)
0X09 (9,A)
GPIO_0 AND GPIO_1
0X09 (A)
LINE IN
0X05 (5)
0X05 (5)
0X0C (12)
GPIO_0 AND GPIO_1
0X09 (A) AND UI ELEMENT
L6880 54 53 49 8
SATELLITES
0X04 (4)
0X04 (4)
0X0B (11)
GPIO_3
N/A
SUB
0X03 (3)
0X03 (03)
0X0A (10)
GPIO_3
N/A
N/A
0X08 (8)
0X10 (16)
1
=PP3V3_S0_AUDIO
2
DRC MIKEY APN:353S2256
CRITICAL MIKEY
0X0D (B)
N/A
PP3V3_S0_HS_RX
0402
C6880
CODEC INPUT SIGNAL PATHS
1
3
SPDIF OUT
MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V
FERR-1000-OHM
1UF
MIKEY
10%
FUNCTION
D
CONVERTER
PIN COMPLEX
VREF/ENABLE
AVDD
6.3V
DET ASSIGNMENT
2
CERM 402
BUILT-IN MIC
0X06 (6)
0X0D (13,B,RIGHT)
MIC_BIAS (80%)
N/A
HEADSET MIC
0X06 (6)
0X0D (13,V22,B,LEFT)
MCP79 GPIO_38
MCP79 GPIO_17 (PERIPH DETECT) MCP79 GPIO_4 (LOAD DETECT)
U6880
PORT A DETECT (HEADPHONES)
D
CD3275
PULLUPS ON MCP PAGE
DRC 39
PORT B DETECT(SPDIF DELEGATE)
IN
=I2C_MIKEY_SCL
6
SCL
1
54 MICBIAS
HS_MIC_BIAS MIKEY
39
BI
=I2C_MIKEY_SDA
5
SDA
DETECT
2
21
OUT
AUD_I2C_INT_L
7
INT*
BYPASS
10
19
IN
AUD_IPHS_SWITCH_EN
HS_SW_DET
CRITICAL 1
1
APN:376S0613
R6801 300K
2
AUD_OUTJACK_INSERT_L 2
5% 1/16W MF-LF 402
R6806
R6805
39.2K
20.0K
1% 1/16W MF-LF 402
2
AUD_PORTA_DET_L
Q6800
D
8
1
MIKEY
R6880
Q6801
SOT563
3
D
Q6801
SSM6N15FEAPE
R6802 53
IN
5% 1/16W MF-LF 402
G
S
54 53 50 49
G
S
2 4
G
S
1
OUT AUD_MIC_INP_L
1
MIKEY CRITICAL 0.1UF 1
OUT AUD_MIC_INN_L
C 2
54 53
IN
AUD_J1_SLEEVEDET_INV
5% 1/16W MF-LF 402
Q6800
5% 1/16W MF-LF 402
6
1/16W MF-LF 402
2
2
HS_MIC_HI_RC
1
HS_MIC_HI
2
MIKEY 1
IN
53 54
IN
53
5% 1/16W
R6883
MIKEY
1
MF-LF 402
5% 1/16W MF-LF 402
C6885
0.0082UF 10% X7R
2
MIKEY
1
C6884
100K
27PF
25V 402 2
CRITICAL
50V 402
5% CERM
CRITICAL
XW6880 SM
54 53 50 49 GND_AUDIO_CODEC
D
5%
2
2.2K
2
10% 25V X5R 402
220K
220K
2.2K
R6884
2
R6803
R6804
MIKEY
10% 25V X5R 402
C6886
10V 402
49
1
402
C6883 49
5
2
R6882
1/16W MF-LF
MIKEY CRITICAL
54 53 50 49 GND_AUDIO_CODEC
1
1
1%
0.1UF
54 PP3V3_S0_AUDIO_F
1
R6881
SOT563
49 50 53 54
MIKEY
2
GND_AUDIO_CODEC
4
C6801 20% CERM
MIKEY
10% CERM
0.1UF
1
2
16V 402
2
NC
6
AUD_J1_DET_RC 5
GND_AUDIO_CODEC
0.01UF
402
SSM6N15FEAPE
SOT563 2
1
C6881
MF-LF
47K 1
MIKEY
5% 1/16W
1K
D
20% 6.3V TANT 402
2
THM
3
SSM6N15FEAPE
AUD_J1_TIPDET_R
1
2.2UF
100K
1% 1/16W MF-LF 402
AUD_PORTB_DET_L
NC
ENABLE GND
C6882
11
1
4
54 PP3V3_S0_AUDIO_F
9
OUT AUD_SENSE_A
49
HS_RX_BP
1
HS_MIC_LO
2
PLACE NEAR C6886
54 53 AUD_J1_SLEEVEDET_R
C
SSM6N15FEAPE SOT563
PORT B RIGHT(BUILT-IN MIC)
AUD_J1_SLEEVEDET_R 1
C6802
2
G
S
R6850 1
2
54 53 50 49 GND_AUDIO_CODEC
R6851
100
0.01UF
49
10% 16V CERM 402
IN
AUD_CODEC_MICBIAS
2.4K
1
2 1% 1/16W MF-LF 402
MIC_BIAS_FILT
1
1
2 1% 1/16W MF 402-1
CRITICAL
C6852 2.2UF 20% 6.3V TANT 402
2
MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM
54 53 50 49 GND_AUDIO_CODEC
54 PP3V3_S0_AUDIO_F
VOLTAGE=3.3V
CRITICAL
IN
=PP3V3_S0_AUDIO
1
1
OUT AUD_MIC_INP_R
2
MIKEY
1 1
0.1UF 10V 402
20% CERM
0.1UF
R6864
49
220K
C6861 2
2
5% 1/16W MF-LF 402
1
R6865
MIKEY
300K
2
Q6802
5% 1/16W MF-LF 402
D
2
54 53 50 49 GND_AUDIO_CODEC
5% 1/16W MF-LF 402
AUD_PERPH_DET_R
AUD_IP_PERIPHERAL_DET
OUT
2
G
S
Q6802 1
15K
3
S
4
BI_MIC_HI
IN
7 53
5% 1/16W MF-LF 402
2
2
IN
7 53
IN
7 53
C6854
0.001UF 50V 402
10% CERM
CRITICAL
27PF 5% CERM
50V 402
L6851 FERR-1000-OHM 1
BI_MIC_LO_F
2
BI_MIC_LO
2 1% 1/16W MF 402-1
BI_MIC_SHIELD
2
PLACE NEAR J6701
HP=80HZ
B
SSM6N15FEAPE SOT563
R6860 1
D
1
C6853
100K
5% 1/16W MF-LF 402
MIKEY MIKEY
17
1
0402
1
SOT563
CRITICAL
R6852
2.4K
SM
0
2
R6853
XW6851
MIKEY
1
2
1
R6861
6
SSM6N15FEAPE
1
BI_MIC_HI_F
2
10% 25V X5R 402
100K
R6862
1
OUT AUD_MIC_INN_R
MIKEY
1MIKEY
53 AUD_IP_PERPH_DET
10% 25V X5R 402
C6851
PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA
2
0402
CRITICAL
0402
B
FERR-1000-OHM
0.1UF 49
54 53 49 8
L6850
C6850
EXTRACTION NOTIFICATION CKT
L6862 FERR-1000-OHM
PERPH_DET_FILT 2
5% 1/16W MF-LF 402
MIKEY 1
0.1UF 2
5
G
C6860 AUD_J1_TIPDET_INV
20% 10V CERM 402
54 53 50 49 GND_AUDIO_CODEC
MIKEY MIC LOAD DET CKT PP3V3_S0_AUDIO_F 54 54
HS_MIC_BIAS
MIKEY_LOAD_DET
MIKEY_LOAD_DET CRITICAL
1
R6870
B1
HS_MIC_BIAS_COMP
COMP. TRIP PT. = 2.64V
A
MIKEY_LOAD_DET 1
R6871 100K
1% 1/16W MF-LF 2 402
VCC
B3
HS_MIC_HI
UCSP
A2
VEE1
54 53
MAX9028EBT+
A1
VEE0
1% 1/16W MF-LF 2 402
1
C6870 27PF
5% 2 50V CERM 402
R6872 100K
1% 1/16W MF-LF 2 402
MIKEY_LOAD_DET
R6873 0 5% 1/16W MF-LF 402
B2 OUTPUT HIGH WHEN MIC BIAS LOADED OUTPUT LOW WHEN MIC BIAS UNLOADED
MIKEY_LOAD_DET 1
10% 16V 2 X5R 402
MIKEY_LOAD_DET 1
MIC_LOAD_COMP_OUT 1
A3 MIKEY_LOAD_DET
C6872 0.1UF
U6870
2.21K
MIKEY_LOAD_DET 1
C6871
2 MIKEY_MIC_LOAD_DET
OUT
9
SYNC_MASTER=AUDIO
SYNC_DATE=06/09/2009
A
PAGE TITLE
AUDIO: JACK TRANSLATORS
27PF
DRAWING NUMBER
5% 2 50V CERM 402
Apple Inc.
051-7982
GND_AUDIO_CODEC
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
54 53 50 49
SIZE
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68 OF 109 SHEET
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8
7
6
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7
6
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1
MagSafe DC Power Jack CRITICAL
J6900
CRITICAL
78048-0573
F6905
M-RT-SM
6AMP-24V
1
1
7 PP18V5_DCIN_FUSE MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V
2 3
1
R6928 1
2 5% 1/16W MF-LF 402
518S0656
=PP3V42_G3H_ONEWIRE
20% 50V CERM 603
2
SMC_BC_ACOK_VCC
R6929 2.0K
5
402 MF-LF 1/16W 5%
U6901
U6900
1
36 37
4
Y
B
1 1
MAX9940 SC70-5
SYS_ONEWIRE
BI
SMC_BC_ACOK
2
A
VCC ONEWIRE_PU
EXT 5
NC
2
2
GND
C6908 0.1UF
3
4 INT
3
36
D
8
SOT665 TC7SZ08AFEAPE
1
7 ADAPTER_SENSE
8 55
C6905 0.01UF
0 5
=PP18V5_DCIN_CONN
2
4
D
2
1206-1
20% 10V CERM 402
PLACEMENT_NOTE=PLACE NEAR U6901
NC
1-Wire OverVoltage Protection ADAPTER_SENSE_R
C
C 516S0787
J6955 ASP-146700-03 F-ST-SM 8
1
2 5% 1/8W MF-LF 805
SOT665
PPDCIN_S5_P3V42G3H MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V
4
5
6
3.425V "G3Hot" Supply R6961
5
1
0
Supply needs to guarantee 3.31V delivered to SMC VRef generator
7 SMC_LID_R
1
2
1/16W
4
3
SMC_LID
NOSTUFF
PPVIN_G3H_P3V42G3H
NC
C6990
P3V42G3H_BOOST
1
C6994
VIN
BOOST
20% 6.3V X5R 402
LT3470A
NC
7
SHDN* NC
SW
4
BIAS
2
DFN CRITICAL
5
GND
FB THRM PAD
10% 50V CERM 402
1
0.22uF
U6990
2
8
B
2
DIDT=TRUE
10UF 10% 25V X5R 805
C6955 0.001UF
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V
3
2
CRITICAL
L6995
2
33UH-20%-0.44A-0.455OHM
1
P3V42G3H_SW MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE
=PP3V42_G3H_REG
8
HALL EFFECT CONNECTOR
2
Vout = 3.425V
D52LC-SM
250MA MAX OUTPUT
1
1
9
NC
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 mm VOLTAGE=12.6V
6
BATT_POS_F
36 37 44
402 5% MF-LF
1 56 55 7
2
3
HN2D01JEAPE
47 =PP18V5_DCIN_CONN
1
D6905
R6905 55 8
=PP3V42_G3H_HALL
C6995 22pF
2
5% 50V CERM 402
R6995
B
(Switcher limit)
1
348K 1% 1/16W MF-LF 402
CRITICAL 2
1
C6999 22UF
P3V42G3H_FB
R6996
1
2
20% 6.3V CERM 805
200K 1% 1/16W MF-LF 402
2
Vout = 1.25V * (1 + Ra / Rb) CRITICAL
J6950
BATTERY CONNECTOR
BAT-K24 M-RT-TH
56 55 7 BATT_POS_F 7 SYS_DETECT_L
=SMBUS_BATT_SDA
5 6
39
7
=SMBUS_BATT_SCL
39
CRITICAL
8
1
2
D6950
9
RCLAMP2402B 11 12 13
R6950
1
5% 1/16W MF-LF 402
C6950
SYNC_MASTER=K24_MLB
1
10% 25V X5R 402
SYNC_DATE=02/05/2009
A
PAGE TITLE
DC-In & Battery Connectors
0.1UF
10K
SC-75
10
2
DRAWING NUMBER
2
Apple Inc.
3
SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
1 2 3 4
NOSTUFF
A
P1 P2 P3 P4 P5 P6 P7 P8 P9
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
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R
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1
PBUS SUPPLY / BATTERY CHARGER Q7001 HAT1128R01 SOI
Q7000 8
PPVDCIN_G3H_PRE2
CRITICAL
3 2
D
D7010
1
2
1SS418
R7098
SOD-723-HF
C7063
1
1
10% 25V X5R 402
5% 1/16W MF-LF 402
2
6
7
5
D2 D1
1% 1/16W MF-LF 402
56
3
PPVDCIN_G3H_PRE
2
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM
1
S1
D
GATE
5
4
=PP3V42_G3H_CHGR GATE
R7099
56 8
4
R7060 1
CHGR_SGATE
2
1% 1/16W MF-LF 402 2
2 5% 1/16W MF-LF 402
R7062
10% 25V X5R 402
57.6K
62K
1
0.1UF
1
62K
2
5% 1/16W MF-LF 402
1
5% 1/16W MF-LF 402
5 1
CHGR_AMON
56 41
100K
1
CHGR_LOWCURRENT_GATE_R
C7060
1
2
30.1K
CHGR_DCIN
D2 D1
6
R7001 R7010
S3 S2
D3
MIN_NECK_WIDTH=0.3 MM
1
100K
0.1UF
MIN_LINE_WIDTH=0.6 MM
8
D3
S1
D4
7
D4
S3 S2
CRITICAL
8
HAT1128R01 SOI
=PP18V5_G3H_CHGR
2
VCC 4
2
1
R7061
GND
CHGR_LOWCURRENT_REF3
1.82K
CHGR_LOWCURRENT_GATE
CRITICAL
U7060
2
1% 1/16W MF-LF 402
TL331 SOT23-5 2
R7023 (CHGR_ACIN)
56 1
1
1
CHGR_VDD
2
R7011
1
C7047
9.31K 1% 1/16W MF-LF 402
5% 1/16W MF-LF 402
1UF
=PP3V42_G3H_CHGR
10% 10V X5R 402-1
1
1
5% 1/16W MF-LF 402 1 2
C7040 1UF
2
10% 10V X5R 402-1
C7024
1UF
0.047UF
10% 10V X5R 402-1
10% 10V CERM 402
2
VDD
2 12 39 39
=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA
11 10
AGATE CSIP CSIN
1
BGATE DCIN
16
28 27
56.2K 1
0.01UF 2
10% 16V CERM 402
C7045 56
1UF
1% 1/16W MF-LF 402 2 CHGR_VCOMP_R
C7044
17
C7043 1
2 10% 16V X5R 402
1
10% 50V CERM 402
25 24 23
LGATE
21
TRKL*
13
AMON BMON ACOK
CHGR_AGATE CHGR_CSIP CHGR_CSIN
9 15 14
2
1
MIN_LINE_WIDTH=0.6 MM
PP18V5_S5_CHGR_SW_R CRITICAL
2
1
C7061
1
2
0.1UF 10% 25V X5R 402
C7062
1
2
2
0.1UF 10% 25V X5R 402 GND_CHGR_SGND
CHGR_BOOT CHGR_UGATE CHGR_PHASE
C7023 1UF
2
2
10% 25V X5R 603-1
1
C7027 0.001UF
2
C
20% 50V CERM 402
CRITICAL 1
LFPAK-HF
C7025 0.1UF 10% 25V X5R 402
1
2
3
L7000
PPVBAT_G3H_CHGR_REG
2
1206
0.5% 1W MF 0612-1
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM
4.7UH-9.5A
1
2
3
4
PPVBAT_G3H_CHGR_OUT 1
IHLP4040DZ-SM
C7028
1
0.001UF 20% 50V CERM 402
2
CRITICAL 1
2
2
20% 16V POLY-TANT CASED2E-SM
10% 25V X5R 603-1
CRITICAL
2
PWM FREQ. = 400 kHz MAX CURRENT = 7A
Q7021
C7026
RJK0305DPB
0.001UF
1
LFPAK-HF
2
3
10% 50V 2 X7R 402
PLACEMENT_NOT=PLACE XW7000 CLOSE TO U7000
56
C7011 1UF
C7008 33UF
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
1
8
7AMP
0.01
CRITICAL 2
56
SM
=PPBUS_G3H
F7000
R7008
1
56
TO SYSTEM 2
CRITICAL
1
5
XW7000
56
1
RJK0305DPB
4
2
C7022 1UF 10% 25V X5R 603-1
Q7020
(??? limited)
GND_CHGR_SGND
R7031
CHGR_VNEG_R
2.2
(CHGR_CSOP)
1
2
1 5% 1/16W MF-LF 402
470PF 10% 50V CERM 402
2
1
CRITICAL
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE 1
C7021 22UF 20% 25V POLY-TANT CASE-D2-SM
5 56
4
CHGR_LGATE TP_CHGR_TRKL CHGR_AMON 41 56 CHGR_BMON 41 =CHGR_ACOK 37
CHGR_PIN26
3.01K
C7046
1
22UF 20% 25V POLY-TANT CASE-D2-SM
DIDT=TRUE
DIDT=TRUE
2
PLACEMENT_NOTE=PLACE C7027 ACROSS PIN 5 OF Q7020 AND PINS 1/2/3 OF Q7021
CRITICAL
C7020
CHGR_CSIN_XW7021
56 CHGR_BGATE CHGR_DCIN 56
CHGR_PIN6
R7046 1
B
0.5% 1W MF 2 0612-1
SM
OMIT
1% 1/16W MF-LF 402
MIN_NECK_WIDTH=0.3 MM
0.02
XW7021
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
0.001UF
GND_CHGR_SGND
2
R7020
5% 1/16W MF-LF 402
2
DIDT=TRUE
PGND
R7045 1
18
BOOT UGATE PHASE
AGND
2
8
29
10% 16V X5R 402
7
ICOMP VCOMP VNEG CSOP CSON THRM_PAD
1
0.033UF
5
ISL6258AHRTZ
CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSOP CHGR_CSON
QFN
VREF ACIN
6
3
26
C7042
4
CRITICAL
1
OMIT
22
NC
2
R7021
U7000 CHGR_ACIN
1
10
VDDP
VHST SCL CRITICAL SDA
XW7020
CHGR_CSIP_XW7020
1
1
C
PLACEMENT_NOT=PLACE XW7020 ON PAD OF R7020 PLACEMENT_NOT=PLACE XW7021 ON PAD OF R7020 SM OMIT
10
CHGR_VDDP
4.7
C7041 56 8
2
19
10% 25V X5R 402
2
R7040
0.1UF
20
C7010
2
CHGR_CSO_R_P
76
CHGR_CSO_R_N
B
R7047 0 1
(CHGR_CSON)
76
2 5% 1/16W MF-LF 402
(CHGR_CSO_R_N)
AMON PULLDOWN LOGIC CHGR_AMON
56 41
=PP3V42_G3H_CHGR
1
56
2
G
S
OMIT 1
Q7050 2
GND_CHGR_SGND
56
SI7137DP SO-8
2
XW7052
1
56
Q7070
D
CHGR_PIN6 2
3
OMIT
SSM6N15FEAPE
A
PPVBAT_G3H_CHGR_OUT 1
CHGR_VDD_L 56
1
SOT563 56 CHGR_VDD
CRITICAL
PLACEMENT_NOT=PLACE XW7052 CLOSE TO U7000
SM
2
GND_CHGR_SGND
C7050
C7051
0.01uF
0.1UF
10% 16V CERM 402
10% 16V X5R 402
1
2
D
5% 1/16W MF-LF 402
BATT_POS_F
7 55
5
5% 1/16W MF-LF 402 2
BATTERY CHARGE LIMITING FETS
CHGR_PIN26
1M
S
R7075
3
NOSTUFF
2
6
SOT563
1
SSM6N15FEAPE D
1
1M
G
Q7070 R7074
4
56 8
56
SYNC_MASTER=K24_MLB
SM
5
R7073
G
S
4
CHGR_BGATE
A
PBUS Supply/Battery Charger
56
PLACEMENT_NOT=PLACE XW7054 CLOSE TO U7000
1
SYNC_DATE=02/05/2009
PAGE TITLE
XW7054
DRAWING NUMBER
Apple Inc.
1K 5% 1/16W MF-LF 402 2
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
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SIZE
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- COPY THIS PAGE FROM K36 CSA.76
5V S3/3.3V S5 POWER SUPPLY D
D VOUT = (2 * RA / RB) + 2
R7267 R7268 R7269 R7270 15.0K 10K 10K 6.49K
OMIT
ROUTING NOTE:
XW7203
Place XW7203 by Pin1 OF L7260.
1% 1/16W MF-LF 402
SM 2
VOUT = (2 * RC / RD) + 2
1
1% 1/16W MF-LF 402
1
5V_S3_VFB_XW7203
2
1
1% 1/16W MF-LF 402
2
OMIT
XW7204
1% 1/16W MF-LF 402
1
2
1
SM 2
2
3V3S5_VFB_R7270
PLACEMENT_NOT=PLACE XW7203 BY PIN 1 OF L7260
ROUTING NOTE: Place XW7204 by Pin 2 of L7220.
1
PLACEMENT_NOT=PLACE XW7204 BY PIN 2 OF L7220 57
GND_5V3V3S5_SGND OMIT
ROUTING NOTE:
XW7205 SM 2
C
Place XW7205 by C7252. 1
C
PLACEMENT_NOT=PLACE XW7205 BY C7252
=PPVIN_S3_5VS3 57 8
OMIT
ROUTING NOTE:
XW7202
Place XW7202 by C7292.
1
C7272 1UF
SM 2
10% 25V 2 X5R 603-1
1
PLACEMENT_NOT=PLACE XW7202 BY C7292
PLACEMENT_NOTE=PLACE C7230 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7220
C7260 0.1UF 10% 16V X5R 402
D
CRITICAL
2
Q7260 PWRPK-12128
B
EMI request
1
C7233 0.001UF
20% 2 50V CERM 402
CRITICAL 1
C7290 10UF 20%
2 6.3V X5R
C7291 1
150UF-.025-OHM 20% 6.3V TANT 2 CASE-B2-SM
CRITICAL
C7292 1
U7200 QFN
19 DRVL1
NO STUFF
24 VO1
1
5V_S3_VFB
2.2 2
150UF-.025-OHM
603
VREG5 17 5V3V3S5_REG5
20 LL1
5V_S3_DRVL
R7294 D
CRITICAL
5% 1/16W MF-LF 402
2 VFB1
MIN_LINE_WIDTH=0.6 MM
10% 16V X5R 402
2
3V3S5_VBST
DIDT=TRUE
2
2
VO2 7
Q7220
1
S
1
R7271 75K
100PF 5% 50V
2
2 CERM
1
NO STUFF
3V3S5_ENTRIP 4
NC
5
2
1
C7273
1
=PP3V3_S5_REG
2 6.3V X5R
603
R7272
2
1
1% 1/16W MF-LF 402
C7231 C7252
1
1 150UF-.025-OHM 0.001UF 20% 20%
C7295
2
100PF
50V CERM 402
8
VOLTAGE=3.3V MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm
CRITICAL
EMI request 1
EMI request NO STUFF
75K
10UF 20%
B
CRITICAL
5% 1/16W MF-LF 402
3V3S5_LL_SNUBBER
EN0 13 GND THRM_PAD
2 PCMC063T-SM
R7295 2.2
PGOOD 23
1% 1/16W MF-LF 402
4.7UH-10A EMI request
6
PWM FREQ. = 375 KHZ MAX CURRENT = 4A
L7220
8
DIDT=TRUE
3V3S5V02VO2
VCLK 18
C7294
20% 2 16V POLY B1A-SM
SIZ700DT
3V3S5_VFB
ENTRIP2 6
1
10% 2 25V X5R 603-1
3V3S5_DRVL
MIN_LINE_WIDTH=0.6 MM
VFB2 5
1
POWERPAK-6X3.7
1
PWRPK-12128
G
50V CERM 402
CRITICAL
MIN_LINE_WIDTH=0.6 MM 3V3S5_LL MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 DIDT=TRUE
LL2 11
CRITICAL C7230 C7241 C7240 0.001UF 20% 1UF 39UF-0.027OHM
7
MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 3V3S5_DRVH
DRVH2 10
DRVL2 12
1 ENTRIP1
3
1 DIDT=TRUE
SIS426DN
EMI request NO STUFF 1
5V_S3_ENTRIP
Q7261
VREG3 8
4 TONSEL
21 DRVH1
C7220 0.1UF
VREF
22 VBST1 CRITICAL VBST2 9
5V_S3_VBST
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 5V_S3_VO1
5V_S3_LL_SNUBBER
20% 6.3V TANT 2 CASE-B2-SM
DIDT=TRUE
DIDT=TRUE
=PP5V_S3_REG VOLTAGE=5V
402
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
2
CRITICAL
VIN 14 SKIPSEL
MIN_LINE_WIDTH=0.6 MM DIDT=TRUE MIN_NECK_WIDTH=0.2 MM 5V_S3_LL
S
L7260
PCMB104E4R7-SM
8
G
4.7UH-13A-15MOHM 1
0.22UF 10%
2 10V CERM
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 5V_S3_DRVH
SIS426DN
PWM FREQ. = 300 KHZ MAX CURRENT = 10A
1
C7271
3
1
20% 2 16V POLY B1A-SM
EMI request 1
20% 2 6.3V X5R 603
25
10% 2 25V X5R 603-1
20% 2 16V ELEC C6-SM
50V CERM 402
C7282 39UF-0.027OHM
8
C7270 10UF
1
CRITICAL 1
16
2
C7281 1UF
TPS51125
0.001UF 20%
1
15
C7232
=PPVIN_S5_3V3S5
5VS3_3V3S5_VREF
CRITICAL 1 C7280 68UF
EMI request 1
5V3V3S5_REG3
=PPVIN_S3_5VS3
57 8
6.3V TANT 2 CASE-B2-SM
C7250 10UF 20%
2 6.3V X5R
603
5% 50V
2 CERM 402
402
OMIT 57
D
6
63 36 7
SMC_PM_G2_EN
=P5VS3_EN_L
2
G
S
IN
1
100K 2
2
XW7201 SM PLACEMENT_NOT=PLACE XW7201 BETWEEN PIN 15 AND PIN 25 OF U7200 5V3V3_REG_EN
P5V3V3_PGOOD
5% 1/16W MF-LF 402
SOT563
63
1
R7273
Q7221 SSM6N15FEAPE
GND_5V3V3S5_SGND
63
ROUTING NOTE:
Q7221
1
D
3
Place XW7201 between Pin 15 and Pin 25 of U7200.
SSM6N15FEAPE SOT563
A
=P3V3S5_EN_L 5 63
IN
G
S
A
4
PAGE TITLE
5V/3.3V SUPPLY DRAWING NUMBER
Apple Inc. SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
72 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
1.5V/0.75V(DDR3) POWER SUPPLY D
D
VOUT = 0.75V * (1 + RA / RB) NO STUFF 1 2 1 2 1V5S3_VDDQSET R7322 C7303 20K 0.1% 100PF 1/16W MF 402
26 8
5% 50V CERM 402
R7321
=PPVTT_S3_DDR_BUF
20.0K
1
1% 1/16W MF-LF 402
2
C7340
1
0.033UF 10% 16V X5R 402
PLACEMENT_NOT=PLACE XW7304 BY C7300
C7301 10UF
20% 6.3V 2 X5R 603
XW7304 1
OMIT
2
1V5S3_V5FILT_XW 1
2
1
1V5S3_V5FILT
C7300
SM
=PP5V_S3_1V5S30V75S0
2
R7307
1
5% 1/16W MF-LF 402
2
C7302 10UF
4.7
1UF
10% 10V X5R 402-1
20% 6.3V X5R 603
PLACEMENT_NOTE=PLACE XW7301 BY L7320 OMIT
=PP0V75_S0_REG
1V5S3_VDDQSNS
1
ISNS_1V5_S3_P OUT ISNS_1V5_S3_N OUT
Place XW7301 by L7320.
2
8
1
1V5S3_VBST
2
1
R7310 10.7K
VDDQSET VTTREF VLDOIN VTT V5FILT
R7300
2
8
15
22
14
24
23
5
9
DIDT=TRUE
0
5% 1/16W MF-LF 402
VBST V5IN VDDQSNS VTTSNS
1% 1/16W MF-LF 2 402
PGOOD DRVH LL
2
1V5S3_CS
1
5
QFN
DRVL
19 1V5S3_DRVL
MODE
4
D 4
G
ROUTING NOTE:
ROUTING NOTE: CONNECT CS_GND TO Q7321 PIN1,2.3 USING KEVIN CONNECTION.
NC0 NC1
2 6.3V X5R-CERM-1 603
THRM_PAD
CS_GND
GND
PGND
VTTGND
1
22UF 20%
18
C7308
3
2 6.3V X5R-CERM-1 603
1
17
22UF 20%
25
C7307
C
20% 50V CERM 402
PLACEMENT_NOTE=PLACE C7333 ACROSS Q7320 PWR AND Q7321 GND
1 2 3
1 NO STUFF
2 PP1V5_S3_REG_R
R7390
CRITICAL Q7321
2
5% 1/16W MF-LF 402
2 4
C7343 330UF
1
MF-1 0612
1V5S3_LL_SNUBBER
2
3.3X3.3-QFN
1
8
MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm
0.001
PLACE NEXT TO L73201% 1W
CSD58858Q3 S
=PP1V5_S3_REG CRITICAL
VOLTAGE=1.5V
1 3
R7350
2.2 EMI request
G
C7333 0.001UF
L7320
1
4
2
CRITICAL
NO STUFF
1
47 76
1.0UH-13A-5.6M-OHM SM-IHLP-1
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm 5
7 NC 12 NC
20% 2 16V POLY B1A-SM
CRITICAL
S
D
1
39UF-0.027OHM
10% 2 25V X5R 603-1
CSD58858Q3 3.3X3.3-QFN
2
20% 2 16V POLY B1A-SM
CRITICAL Q7320
DIDT=TRUE
Place XW7303 by C7308.
1
39UF-0.027OHM
DIDT=TRUE
DIDT=TRUE
16 CS
=PPVIN_S5_1V5S30V75S0 CRITICAL CRITICAL 1 C7332 C7331 C7345 1UF
47 76
8
DIDT=TRUE MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm
21 1V5S3_DRVH 20 1V5S3_LL
TPS51116
6 COMP
OMIT
16V 10% X5R 402
13
CRITICAL
U7300 SYM (1 OF 2)
SM
=DDRREG_EN
PLACEMENT_NOT=PLACE XW7303 BY C7308
1 C7309 0.1uF
10 S3 11 S5
1
63
=DDRVTT_EN
XW7303
64 25
1V5S3_VBST_RC
C
ROUTING NOTE:
XW7301 SM
1V5S3_VTTSNS
C7344 C7342 0.001UF 330UF 20% 50V CERM 402
20% 2.5V TANT CASE-B2-SM
PLACE CLOSE TO L7320
C7390
1
C7341 10UF
20% 2 6.3V X5R 603
20% 2.5V TANT CASE-B2-SM
MAX CURRENT = 13A PWM FREQ. = 400 KHZ
CRITICAL
100PF 5%
2 50V CERM
1 2 3
402
EMI request
B
B
OMIT
GND_1V5S3_SGND
1
XW7300 SM
ROUTING NOTE: PUT 6 VIAS UNDER THE THERMAL PAD
OMIT GND_1V5S3_CSGND
1
DDRREG_PGOOD
2
R7399 100K
ROUTING NOTE: Place XW7300 between Pin 3 and Pin 25 of U7300. 1
2
XW7302 SM
63
5% 1/16W MF-LF 402 2
=PP3V3_S3_PDCISENS
8
ROUTING NOTE: Place XW7302 by Q7321.
PLACEMENT_NOT=PLACE XW7300 BETWEEN PIN 3 AND PIN 25 OF U7300
STATE
PM_SLP_S4_L
PM_SLP_S3_L
PP1V5_S3
PP0V75_S0
PLACEMENT_NOT=PLACE XW7302 BY Q7321
S0
HIGH
HIGH
1.5V
0.75V
S3
HIGH
LOW
1.5V
0.0V
S5/G3HOT
LOW
LOW
0.0V
0.0V
A
A PAGE TITLE
1.5V/0.75V DDR3 SUPPLY DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
73 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
7
6
4
=PP5V_S0_CPU_IMVP
8
1
R7412
1UF
10
59 8
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
C7426
2
10% 6.3V CERM 402
1
R7420
DPRSTP*
2
1
1
2-PHASE CCM
0
1
0
1-PHASE CCM
1
0
1
1-PHASE DCM
0 1
R7421
0.1uF
10
10% 16V X5R 402
1
1
1
R7447
VID6
42
VID5
70 11 70 11
CPU_VID
70 11
1% 1/16W MF-LF 2 402
22
IN CPU_DPRSTP_L IMVP_DPRSLPVR
C
10
(NC) 36
FROM SMC
25
2
0.015uF
VR_PWRGOOD_DELAY
OUT
IMVP6_VR_TT IMVP6_NTC
9
147K
IMVP_VR_ON
IN
9
C7405
1% 1/16W MF-LF 402
10% 16V X7R 402
1
1
2
1K
2
1% 1/16W MF-LF 402
1
VID2
38
VID1
37
VID0
46
DPRSTP*
45
DPRSLPVR
3V3 CLK_EN*
44
VR_ON
1
4
IMVP6_VDIFF
13
2
59
1K
59 59 59
IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
PHASE1 LGATE1
35
59
IMVP6_UGATE1
34
59
IMVP6_PHASE1
32
59
IMVP6_LGATE1
24
59
IMVP6_ISEN1
27
59
IMVP6_UGATE2
PHASE2
59
IMVP6_PHASE2
LGATE2
30
59
IMVP6_LGATE2
PGND2
29
23
VO
18
DROOP
16
RBIAS
12
X5R 402
R7400
C7407
59
IRF6710 S1
IMVP6_ISEN2
4
59
IMVP6_VSUM
59
IMVP6_OCSET
59
IMVP6_VO
NO STUFF
59
IMVP6_DROOP
C7416
59
IMVP6_DFB
1
C7408
2
R7404 1
0.22uF
5% 1/16W MF-LF 402
10% 6.3V CERM-X5R 402
2
C74111
1
10% 25V X5R 603-1
20% 16V 2 POLY-TANT CASED2E-SM
2
C7422 0.001UF
1UF
33UF
20% 16V POLY-TANT CASED2E-SM
20% 50V CERM 402
2
1
C7431 0.001UF 1 2
VW
NC TPAD 49
2
20% 50V CERM 402
59
R7418
R7417
1K
5.36K
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
1
3.65K
180pF 2
1
5% 50V
2
2
6
5
1
DIRECTFET-MX
S 4
R7430
NOSTUFF 1
C7434
1
C7428
0.12UF
0.47UF
2
10% 10.0V CERM-X5R 402
2
10% 6.3V CERM-X5R 402
1
R7415
2
2
2
20% 50V CERM 402
1
2 PPVCORE_S0_CPU_XW_2
R7405
C7404
10K
0.22uF
1% 1/16W MF-LF 402
R7407 1 5% 1/16W MF-LF 402
10% 6.3V CERM-X5R 402
1% 1/16W MF-LF 402
B 1
IMVP6_VO_R
10.5K 1% 1/16W MF-LF 402
C7423 0.001UF
1 1
2
3.92K
2
1
2
SM
1
IRF6795
G
3
XW7404
SM PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7401
Q7403
(IMVP6_VO)
2
OMIT
XW7403
7
CRITICAL
D
DIDT=TRUE
PLACEMENT_NOTE=PLACE C7423 CLOSE TO PIN 2 OF L7401
PLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7401
PIMA104E-R36MN0R755 DCR=0.75MOHM
2
1% 1/16W MF-LF 402
2 PIMA104E-SM
OMIT
R7416
1
1
DIDT=TRUE
R7443 3.65K
1
CRITICAL
R7431
2
1% 1/16W MF-LF 402
10KOHM-5% (IMVP6_ISEN2)
0603-LF
1% 1/16W MF-LF 402
CRITICAL
(IMVP6_PHASE2)
1
0.001UF 1 2
R7410
L7401
0.36UH-20%-40A-0.00075OHM
1
13.7K
CERM 402
1% 1/16W MF-LF 402
6 S
CERM 402
C7429
R7401
2
2
10% 50V
2
6.81K
2
1
C7401 33UF
2
G
3
14
RTN 15
COMP
9
1
1
D
DIDT=TRUE
1
VSEN
FB
10
=PPVIN_S5_CPU_IMVP CRITICAL CRITICAL
Q7402
20% 50V CERM 402
1
C7403
10K 1% 1/16W MF-LF 402
CRITICAL
C7432
10% 50V CERM 402
1
IMVP6_PHASE1_XW
X5R 402
GND_IMVP6_SGND
0.001UF
R7414
0.1UF 10% 16V
2
2
C
C7433
2
0.1UF 10% 16V
2
PPVCORE_S0_CPU_XW
1
2
PLACEMENT_NOTE=PLACE C7422 ACROSS PINS 1/2/5/6 OF Q7402 AND PINS 3/4 OF Q7403
FB2
11
(IMVP6_VW)
1
1
4
(IMVP6_ISEN1)
0.001UF
220PF
2
SM
PLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7400
1
0.001UF
1
5% 25V CERM 402
1
0
1
VDIFF
VOLTAGE=0V
2
3
20% 50V CERM 402
XW7402
SM
C7415
C7427
(GND)
59
1
OMIT
XW7401 1
IMVP6_BOOT2_RC
0.001UF
2
OMIT
DIRECTFET-MX
59 8
28
21
IMVP6_COMP_RC
2
IRF6795
G
C7420
1
PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7400
(GND)
PGND1 33
VSUM 19 OCSET 8
SOFT
1% 1/16W MF-LF 402
C7413
7
CRITICAL
5
GND
10% 50V CERM 402
6
NTC
C7414
1
UGATE1
ISEN2
25
470PF
2
5% 1/16W MF-LF 402
DIDT=TRUE
R7411
59
2
IMVP6_BOOT2
VR_TT*
6
7
1% 1/16W MF-LF 402
B
2
D
PGOOD
5
IMVP6_RBIAS
IMVP6_BOOT1
59
UGATE2
47
IMVP6_SOFT
59
26
ISEN1
IMON
48
59
DIDT=TRUE
36
BOOT2
DFB 17
(IMVP6_FB)
1
8
PSI*
255
2
=PPVCORE_S0_CPU_REG
2
DIDT=TRUE
IMVP6_VDIFF_RC 1
1
S
R7425
BOOT1
R7413
C7406 0.001UF 10% 50V CERM 402
R7409
VID3
39
59
2
59
1
1 PIMA104E-SM
5
QFN
40
3
IMVP6_IMON OUT 41
R7408
D
CRITICALL7400 0.36UH-20%-40A-0.00075OHM
Q7401
31
PVCC
U7400
VID4
2
CPU_PSI_L
IN
VDD
CRITICAL
41
70 14 10
70
MAX CURRENT = 44A
1-PHASE DCM
IMVP6_BOOT1_RC
2
1 20
43
70 11
R7445
PWM FREQ. = 300 KHZ
2
(IMVP6_PHASE1)
5% 1/16W MF-LF 402
CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID
499
2
20% 50V CERM 402
S
0
CPU_VID
70 11
0.001UF
1UF 10% 25V X5R 603-1
LOAD LINE SLOPE = -2.1 MV/A
DIDT=TRUE
5% 1/16W MF-LF 2 402
2
70 11
2
C7419
1
C7418
1
20% 16V POLY-TANT CASED2E-SM
6
G
3
DIDT=TRUE
2.0K
70 11
2
2 5
R7424
VIN
1
0
PP3V3_S0_IMVP6_3V3
IMVP6_RTN
GND_IMVP6_SGND
C7417 33UF
20% 16V POLY-TANT CASED2E-SM
PIMA104E-R36MN0R755 DCR=0.75MOHM
C7430
59
1
C7409
CRITICAL
1
2
5% 1/16W MF-LF 402
CRITICAL
33UF
DIDT=TRUE
IMVP6_VSEN
1
1 1
D
0.01UF 10% 16V CERM 402
ISL9504BCRZ
=PP3V3_S0_IMVP
OPERATION MODE
0
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM 8
PSI*
4
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
C7496
1
5% 1/16W MF-LF 402
CRITICAL
DIDT=TRUE
20% 6.3V X5R 603
PPVIN_S5_IMVP6_VIN
2
10
IN
C7435 10UF
1
PM_DPRSLPVR
DPRSLPVR
1
PLACEMENT_NOTE=PLACE C7419 ACROSS PINS 1/2/5/6 OF Q7400 AND PINS 3/4 OF Q7401
S1
2
=PPVIN_S5_CPU_IMVP
2
Q7400 IRF6710
PP5V_S0_IMVP6_VDD
2
5% 1/16W MF-LF 402
D
3
=PPVIN_S5_CPU_IMVP
59 8
1
70 21
5
IMVP6_PHASE2_XW
8
20% 50V CERM 402
2
(IMVP6_VSUM)
ERT-J1VR103J
97.6K
2
1% 1/16W MF-LF 402
(IMVP6_VO) (IMVP6_COMP) 1
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
2
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY. PLACEMENT_NOTE=PLACE CLOSE TO PIN 21 OF U7400
2
OMIT
C7421 0.22uF
XW7400 SM 1
10% 6.3V CERM-X5R 402
1
R7423
1
0
R7422 0
5% 1/16W MF-LF 2 402
2
5% 1/16W MF-LF 402
CPU_VCCSENSE_P CPU_VCCSENSE_N
MIN_LINE_WIDTH
11 70 11 70
59 59 59
IMVP6 CPU VCORE REGULATOR
59 59 59
A
59 59
MIN_LINE_WIDTH 59 59 59 59 59
IMVP6_PHASE1 IMVP6_BOOT1 IMVP6_UGATE1 IMVP6_LGATE1 IMVP6_ISEN1
MIN_NECK_WIDTH
MIN_LINE_WIDTH
1.5 MM
0.25 MM
59
0.25 MM
0.25 MM
59
1.5 MM
0.25 MM
59
1.5 MM
0.25 MM
59
0.25 MM
0.25 MM
59
IMVP6_PHASE2 IMVP6_BOOT2 IMVP6_UGATE2 IMVP6_LGATE2 IMVP6_ISEN2
MIN_NECK_WIDTH
59
0.25 MM
0.25 MM
59
0.25 MM
0.25 MM
59
0.25 MM
0.25 MM
59
0.25 MM
0.25 MM
59
0.25 MM
0.25 MM
IMVP6_OCSET IMVP6_VSUM GND_IMVP6_SGND IMVP6_VO IMVP6_DROOP IMVP6_DFB IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
0.25 MM
IMVP6_RTN IMVP6_VSEN
MIN_NECK_WIDTH 0.20 MM
0.25 MM
0.20 MM
0.50 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
SYNC_MASTER=K24_MLB
SYNC_DATE=03/03/2009
IMVP6 CPU VCore Regulator DRAWING NUMBER
Apple Inc.
59
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
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PLACEMENT_NOTE=PLACE C7563 ACROSS PIN 5 OF Q7560 AND PINS 1/2/3 OF Q7565
=PPVIN_S0_MCPCORE
R7560
D
5V_S0_MCPREG_VIN
2.2
1
VOLTAGE=5V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM
R7593 C7550
2
1
1
1
10% 16V X5R 402
R7561 1K
R7590 21
21
IN
MCP_VID
IN
MCP_VID
0
1
2
2
R7591 0
1
21
IN
0
1
2
RBIAS
2
SOFT
MCPCORES0_IMON_R 63 OUT MCPCORES0_PGOOD MCP_VID0_R MCP_VID1_R MCP_VID2_R MCPCORES0_OS0 MCPCORES0_OS1 =MCPCORES0_EN 63 IN MCPCORES0_FDE
5% 1/16W MF-LF 402
NOSTUFF
1
NOSTUFF
1
R7580 20.0K
PLACEMENT_NOTE=PLACE R7580 ON THE BOTTOM SIDE PLACEMENT_NOTE=PLACE R7581 ON THE BOTTOM SIDE
R7581 20.0K
1% 1/16W MF-LF 2 402
28
1% 1/16W MF-LF 2 402
31 25 26 27 23 24 29 30 32
MCPCORES0_VSEN MCPCORES0_RTN
C
8 9
1
R7582
VIN UGATE
18
MCPCORES0_UGATE
BOOT
17
MCPCORES0_BOOT DIDT=TRUE
PGOOD VID0 VID1 VID2 OFFSET0 OFFSET1 VR_ON AF_EN FDE VSEN RTN
PHASE
1
1
1
C7564 0.25 MM 0.2 MM DIDT=TRUE
2
MCPCORES0_PHASE
4
VW
MCPCORES0_COMP
5
COMP
MCPCORES0_LGATE
1
SWITCHNODE
1NO
5
PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP 60 8 =PPMCPCORE_S0_REG
1
100
60 8
=PPMCPCORE_S0_REG
1
MCPCORES0_RSEN_P
2
1
OMIT
1
2
MCPCORES0_RSEN_N
20
1
OMIT
1% 1/16W MF-LF 402
1
10% 16V CERM-X5R 402
FB
7
VDIFF
OCSET
VSS
S
1
3
C7566
2
3
20% 4V X5R 603
C7569
8 60
1
2
f = 300 kHz CRITICAL 1
1
NO STUFF
C7567 10UF
C7589 0.001UF
2
50V 10% X7R 402
12
MCPCORES0_VO
20% 4V X5R 603
C7565
CRITICAL 1
270UF 20% 2 2V TANT CASE-B4-SM
C7568 270UF
20% 2 2V TANT CASE-B4-SM
C
(MCPCORES0_VO)
R7569
3
ISP ISN
13 11
MCPCORES0_OCSET MCPCORES0_ISP MCPCORES0_ISN
ICOMP
10
MCPCORES0_ICOMP
1
11.3K
2
1% 1/16W MF-LF 402
1
R7573 10K
THRM_PAD 2
1% 1/16W MF-LF 402
C7573
1
47PF 5% 50V CERM 402
2
R7572
R7500
2
OMIT
1
MCPCORES0_ISP_R
2 (MCPCORES0_ISN)
1
(MCPCORES0_RTN)
2
1% 1/16W MF-LF 402
XW7561 VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM
10% 50V X7R 402
100
1
1% 1/16W MF-LF 2 402
GND_MCPCORES0_AGND
0.001UF 2
4
=PPMCPCORE_S0_REG
10% 50V 2 X7R 402
MCPCORE_SNUBBER
SM
C7570
2
1
0.001UF
150K
0.022UF
(MCPCORES0_VSEN)
1
R7568
SM
C7576
1% 1/16W MF-LF 402
2
1% 1/16W MF-LF 402
XW7563
2
1
PWRPK-12128
1
2
10UF
5% 1/10W MF-LF 2 603
DIDT=TRUE
20
R7563
20
6
PGND
1
R7566
PCMB065T-SM
(Q7560 Limit)
PPMCPCORE_S0_R MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V
1
CRITICAL Q7565 SIS426DN G
GATE_NODE=TRUE
1% 1W MF 0612 2
STUFF
MAX CURRENT: 13A
0.001
R7589
4
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
R7525
L7560
(MCPCORES0_PHASE)
(MCPCORES0_LGATE)
VO
1% 1/16W MF-LF 2 402
MCPCORES0_FB
SM
10% 2 16V X5R 603
R7583
MCPCORES0_VDIFF
XW7562
10% 25V X5R 603-1
C7590 2.2UF
0.68UH-16A
D
20.0K
1% 1/16W MF-LF 2 402
2
1
CRITICAL
SWITCH_NODE=TRUE DIDT=TRUE
21
1UF
3
CERM-X7R 10V 603 5%
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
LGATE
20% 2 16V ELEC C6-SM
C7561
0.22UF 1 2 MCPCORES0_BOOT_R
2
5% 1/10W MF-LF 603
0.2 MM 0.25 MM
19
1
68UF
20% 2 16V ELEC C6-SM
2
D
C7571
S
33
20.0K
MCPCORES0_VW
1
C7560
PWRPK-12128
G
GATE_NODE=TRUE DIDT=TRUE
14
R7565
15
1
PLACEMENT_NOTE=PLACE R7583 ON THE BOTTOM SIDE
CRITICAL
1
68UF
2
PLACEMENT_NOTE=PLACE R7582 ON THE BOTTOM SIDE
CRITICAL
CRITICAL Q7560 SIS426DN
4
(MCPCORES0_UGATE) MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
QFN
IMON
1
D
10% 16V X5R 402
U7500 1
2
5% 1/16W MF-LF 402
R7592 MCP_VID
MCPCORES0_SOFT
2
10% 50V X7R 402
5
C7562
PVCC
VDD
5% 1/16W MF-LF 402
MCPCORES0_RBIAS 5% 1/16W MF-LF 402
C7563
1UF 2
22
1UF
5% 1/16W MF-LF 402
ISL6263D
0
1
8
0.001UF
16
41
MCPCORES0_IMON
=PP5V_S0_MCPREG
2
5% 1/10W MF-LF 603
R7575
1% 1/16W MF-LF 2 402 OCP=14.5A
1
R7571 100
1
C7575 47PF
47.0K
PLACEMENT_NOTE=PLACE XW7561 CLOSE TO PIN 15 OF U7500
2
5% 50V CERM 402
(MCPCORES0_ICOMP)
1% 1/16W MF-LF 2 402
B
B (MCPCORES0_VW)
C7579 10% 50V X7R 402
68PF 1
1
0.001UF
C7580 2
2
1
VID
R7576
MCP TARGET
6.98K 5% 50V CERM 402-1
R7577 1
133K
C7581 2
560PF
MCPCORES0_COMP_C
2
1
1% 1/16W MF-LF 402
10% 50V CERM 402
(MCPCORES0_FB)
C7582
R7578 1
100
2
560PF MCPCORES0_VDIF_C
1% 1/16W MF-LF 402
R7579 1
2.21K 1% 1/16W MF-LF 402
+1.05V
001
+1.00V
010
+0.95V
011
+0.90V
100
+0.85V
101
+0.80V
110
+0.75V
111
+0.70V
2 (MCPCORES0_COMP)
1% 1/16W MF-LF 402
000
2
1
2 10% 50V CERM 402
(MCPCORES0_VDIFF)
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/15/2009
A
PAGE TITLE
MCP CORE REGULATOR DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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R
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1
CPUVTT POWER SUPPLY
D
8
D
=PPVIN_S0_CPUVTTS0 PLACEMENT_NOTE=PLACE C7696 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7620
CRITICAL
C7630
1
1
2
2
20% 16V POLY-TANT CASED2E-SM
C7695
C7696
1
0.001UF
1UF
33UF
10% 25V X5R 603-1
20% 50V CERM 402
2
C
C 5 D 4 8
CRITICAL Q7620
G
CSD58858Q3
=PPCPUVTT_S0_REG
L7620
3.3X3.3-QFN
=PP5V_S0_CPUVTTS0
8
2.2UH-8.0A S R7601
1
2
CRITICAL
VOUT = 1.052V 7.2A MAX OUTPUT F = 320 KHZ
301 1% 1/16W MF-LF
1 2 3
PP5V_S0_CPUVTTS0_V5FILT
R7603
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
C7601
402
1
1UF 10% 10V X5R 402-1
10
2
4
1
1
2
2
CRITICAL
1% 1/16W
PLACEMENT_NOTE=Place XW7665 next to L7620
5
MF-LF
10% 6.3V X5R-CERM 603
402
2
2
D
U7600
4
G
SYM 2 QFN
63
IN
63
OUT
CPUVTTS0_PGOOD
1
EN_PSV
6
PGOOD
TON
2
CPUVTTS0_TON
14
CPUVTTS0_VBST
C7603
(=PPCPUVTT_S0_REG)
3
VOUT
5
VFB
13
LL
12
CPUVTTS0_LL SWITCH_NODE=TRUE
CPUVTTS0_TRIP
11
TRIP
DRVL
9
THRM_PAD
C7660
S
DIDT=TRUE
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
20% 2.5V TANT CASE-B2-SM
PGND
B
8
C7670
OMIT
XW7600
2
5% 50V CERM 402
402
1
B 2
OMIT
SM 1
2
100PF
1/16W MF-LF
6.04K
2
1
NO STUFF
R7670 1%
R7604 1% 1/16W MF-LF 402
2
0.001UF
CPUVTTS0_VSNS
8.06K 1
2
C7661 20% 50V CERM 402
330UF
2
1
15
7
CRITICAL
1 2 3
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
1
20% 6.3V X5R 603
1
CPUVTTS0_DRVL GATE_NODE=TRUE
GND
OMIT
C7665 10UF
2
603-1
CPUVTTS0_DRVH GATE_NODE=TRUE
CPUVTTS0_VFB
10% 50V X7R
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
DRVH
SM
3.3X3.3-QFN
1
1
XW7665
0.1UF DIDT=TRUE
VBST
CRITICAL Q7621 CSD58858Q3
TPS51117RGY_QFN14 =CPUVTTS0_EN
PCMB065T-SM
200K
C7604 4.7UF
V5DRV
V5FILT
1
2
XW7601
(GND) SM
PLACEMENT_NOT=PLACE XW7600 BETWEEN PIN 7 AND PIN 15 OF U7600
1
R7671
1
PLACEMENT_NOT=PLACE XW7601 BY C7660
20.0K
ROUTING NOTE: 1%
1/16W MF-LF
Place XW7600 between Pin 7 and Pin 15 of U7600. 2
ROUTING NOTE:
402
GND_CPUVTTS0_SGND
Place XW7601 by C7660.
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
Vout = 0.75V * (1 + Ra / Rb) (CPUVTTS0_VFB) CPUVTTS0_VOUT
(=PPCPUVTT_S0_REG)
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/04/2009
A
PAGE TITLE
CPU VTT(1.05V) SUPPLY DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
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1
1.8V S0 SWITCHER
D
D
=PP3V3_S0_P1V8S0
8
1
C7760 10uF 20% 6.3V X5R 603
CRITICAL
CRITICAL
VI U7760
1
L7760 10UH-0.55A-330MOHM
TPS62202 4
2
=P1V8S0_EN
63
3
PCAA031B-SM
SOT23-5
FB EN
SW 5
1
P1V8S0_SW
MAX CURRENT = 200MA
=PP1V8_S0_REG
2
8
DIDT=TRUE
GND C7762
2
1
10uF 20% 6.3V X5R 603
2
C
C 1.05V S0 PLL LDO LDO_YES
R7743 =PP3V3_S0_MCP_PLL_VLDO
1
8
100
PP3V3_S0_MCP_PLL_VLDO_BIAS
2
MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
5% 1/16W MF-LF 402
LDO_NO
C7740
R7745
1
1UF LDO_YES
10% 6.3V CERM 402
8
=PP1V05_S0_MCP_PLL_UF_R
0
1
4
Vout = 1.05V
2
IN0 OUT0 IN1 LDO_YES OUT1
5
EN
PP1V05_S0_MCP_PLL_UF_LDO
9
LDO_YES
10
SON
1UF 2
P1V05S0_LDO_SS NOSTUFF
B
C7743
1
8
U7740 7
SS
1
MCP 1.05V S5 (AUXC) SUPPLY
10% 6.3V CERM 402
FB
PG
3
4.42K
11
6
C7750
2
NOSTUFF
20% 6.3V CERM 805
R7782 0
=P1V05_S5_EN
PP3V3_S5_P1V05S5_R_SKIP
IN
CRITICAL
IHLP1616BZ-SM
2
EN CRITICAL
3
POR
4
SKIP
LX
8
1V05S5_SW
VFB
6
1V05S5_FB
RSI
GND
2
=PP1V05_S5_REG
DIDT=TRUE
5
THRM_PAD
7
1
0
2
P1V05S0_LDO_PGOOD
63
5% 1/16W MF-LF 402
2.2UH-3.25A
DFN
R7783 0
P1V05S0_PGOOD1
L7770
ISL8009B
1
R7748
1
VIN
U7750 63
R7747
LDO_YES
5% 1/16W MF-LF 2 402
P1V05_S5_PGOOD
B
LDO_YES
LDO_YES
VOUT = 0.8V * (1 + RA / RB)
1
63
LDO_YES
20% 4V X5R 402
22UF
=PP3V3_S5_P1V05S5
8
2
1
CRITICAL 1
2
C7742
2
4.7UF
R7746
P1V05S0_LDO_FB
GND THRML_PAD
0.0022UF 10% 50V CERM 402
DIDT=TRUE
1
0 5% 1/16W MF-LF 402
2
LDO_YES
1.37K
1
2
TPS74701
C7741
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
1% 1/16W MF-LF 402
1
8 23
R7744
1% 1/16W MF-LF 402
=PP1V5_S0_MCP_PLL_VLDO
=PP1V05_S0_MCP_PLL_UF
MAX CURRENT = 0.5A
CRITICAL BIAS 8
2
5% 1/16W MF-LF 402
2
1
C7776
1
8
Vout = 1.05V
R7780
47PF 5% 50V CERM 402
25.5K
2 2
9
1% 1/16W MF-LF 402
CRITICAL 1
1
2
R7781
MAX CURRENT = 0.8A FREQ = 1.6MHZ
47UF
5% 1/16W MF-LF 2 402
C7771 20% 6.3V X5R 0805
80.6K
2
A
1% 1/16W MF-LF 402
SYNC_MASTER=K24_MLB
SYNC_DATE=03/24/2009
A
PAGE TITLE
MISC POWER SUPPLIES
VOUT = 0.8V * (1 + RA / RB)
DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
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1
3.3V 1.05V S5 ENABLE
Power Control Signals
R7802 100K 63 8
2
=PP3V42_G3H_PWRCTL
1
PM_G2_P3V3S5_EN_L
=P3V3S5_EN_L
57
OUT
3.3V_S0, 1.8V_S0 ENABLE
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
State
NO STUFF
1
D
2
3
MCPDDR, CPUVTT,MCPCORES0 ENABLE 1.5V S0 AND 1.05V S0 ENABLE
Run (S0)
1
1
1
Sleep (S3)
1
1
0
Soft-Off (S5)
1
0
0
Battery Off (G3Hot)
0
0
0
D
10V CERM 402
SMC_PM_G2_EN
IN
PM_SLP_S3_L
10%
D
SOD-VESM-HF
57 36 7
PM_SLP_S4_L
C7802 0.068UF
Q7800 SSM3K15FV
SMC_PM_G2_ENABLE
1
R7800 1
100K
G
S
2
5% 1/16W
R7801
MF-LF 402
5.1K
2
2
1 PM_G2_P1V05S5_EN
=P1V05_S5_EN
OUT
62
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
1
C7801 0.47UF 10% 6.3V
2
CERM-X5R
R7859
402
(PM_SLP_S3_L)
67 36 32 21 7
IN
PM_SLP_S3_L
100 2
1
PM_SLP_S3_L_BUF MAKE_BASE=TRUE
5% 1/16W MF-LF
=P5VS0_EN
OUT
64
=PBUSVSENS_EN
OUT
40
402
R7880
2
5% 1/16W
100K
S3 ENABLE
R7881
2
5%
5% 1/16W
MF-LF
1/16W
33K
1
0
R7884
5% 1/16W
5% 1/16W MF-LF
MF-LF
MF-LF 402
402 1
22K
R7883
2
5% 1/16W
MF-LF
402 1
MF-LF
R7882
2
2
1
R7879
402 1
402
10K
2
R7813
5.1K
1
402
68K 63 8
=PP3V42_G3H_PWRCTL
2
1 5% 1/16W
D
MF-LF
Q7813 3
PM_SLP_S3_L_INVERT
SSM3K15FV
=P5VS3_EN_L
OUT
P3V3S0_EN
57
MAKE_BASE=TRUE
402
=P3V3S0_EN
OUT
64
=P1V8S0_EN
OUT
62
=MCPDDR_EN
OUT
64
=CPUVTTS0_EN
OUT
61
=MCPCORES0_EN
OUT
60
MAKE_BASE=TRUE
SOD-VESM-HF
NO STUFF
1
C
37 36 21 7
IN
PM_SLP_S4_L
P1V8S0_EN
C7813
C
MAKE_BASE=TRUE
MAKE_BASE=TRUE
0.068UF
MCPDDR_EN
10%
2 1
1
R7810
G
S
10V
MAKE_BASE=TRUE
CERM
CPUVTTS0_EN
402
2
MAKE_BASE=TRUE
(PM_S4_STATE_L) 100K
MCPCORES0_EN
5%
MAKE_BASE=TRUE
1/16W MF-LF 402 2
NO STUFF
C7810 1
R7811
0.47UF
5.1K 1 1
2 5%
2
1/16W
10%
MF-LF
6.3V
1
C7880 0.47UF
2
C7881
1
1
C7882
C7883
0.47UF
0.47UF
10%
10%
10%
10%
6.3V
6.3V
6.3V
6.3V
2
CERM-X5R 402
CERM-X5R 402
2
1
C7884
0.47UF
2
CERM-X5R
0.47UF
402
10% 6.3V
2
CERM-X5R
CERM-X5R
402 402
CERM-X5R
402
402
DDRREG_EN
=DDRREG_EN
OUT
58
=USB_PWR_EN
OUT
35
MAKE_BASE=TRUE
NO STUFF
C7812 R7812
0.47UF
0 1 1
VOLTAGE MONITOR
2
2 5% 1/16W
10%
MF-LF
6.3V
402
CERM-X5R
63 8 =PP3V42_G3H_PWRCTL
402
P3V3S3_EN
=P3V3S3_EN
OUT
MAKE_BASE=TRUE
64 8 =PP3V3_S5_PWRCTL
C7840
1 1
0.1uF
B
10V CERM
100K
2
5%
402
1/16W MF-LF
6 2
VDD 5
SENSE
U7840 RESET*
1
402
RSMRST_PWRGD
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
=PP5V_S0_VMON
CT
8
4
CT
MR*
2
R7870 10K
OTHER S0 RAILS PGOOD
1%
C7841
1/16W
TP_U7840_MR_L
0
2
P1V05_S5_PGOOD 62
5% 1/16W
TPS3808 MR* HAS INTERNAL PULLUP
MF-LF 402
1
0.001UF
8 =PP3V3_S0_PWRCTL
MF-LF
1
3
GND 1
36
R7895
TPS3808G33DBVRG4 SOT23-6
B
R7840
20%
20%
402
50V
2
CERM
PP3V3_VMON_VDD
1
2
402
R7820 7
10K
2
353S2310
1
C7870
VDD
OMIT
1
2
402 2
57
3
V2MON
MR*
1
5
=PP1V05_S0_VMON
6
V3MON V4MON
RST*
8
1
P5V3V3_PGOOD
IN
0
2
5% 1/16W MF-LF 402
NC S0PGOOD_PWROK
R7892
THRM_PAD 9
GND
2
R7890
MF-LF
402
=PP1V5_S0_VMON
4
402
1/16W
10V CERM
TDFN
8
MF-LF
1%
U7870 8 =PP3V3_S0_VMON
1/16W
20.0K 20%
ISL88042IRTEZ
8
5%
R7871
0.1uF
60
MCPCORES0_PGOOD
IN
0
1
2
Unused PGOOD signal
5% 1/16W MF-LF 402
A
TP_DDRREG_PGOOD
DDRREG_PGOOD
V2MON THRESHOLD IS 2.866V
61
CPUVTTS0_PGOOD
IN
1
0
5% 1/16W MF-LF 402
62
V3MON THRESHOLD IS 0.6V V4MON THRESHOLD IS 0.6V
P1V05S0_LDO_PGOOD
IN
R7894 1
0
2
PAGE TITLE
POWER SEQUENCING
2
DRAWING NUMBER
Apple Inc.
R7893 1
0
7
6
5
051-7982
NOTICE OF PROPRIETARY PROPERTY:
5% 1/16W MF-LF 402
ALL_SYS_PWRGD
OUT
25 36
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
(S0PGOOD_PWROK)
SIZE
D
REVISION
C.0.0
R
2
5% 1/16W MF-LF 402
8
A
58
MAKE_BASE=TRUE
R7891
BRANCH
PAGE
78 OF 109 SHEET
OF
4
3
2
1
8
7
6
5
4
3
2
1
1.5V S0 FET
3.3V S3 FET
CRITICAL (1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
Q7910 FDC638P_G
3.3V S3 FET
SM
=PP3V3_S3_FET
8
8
=PP3V3_S5_P3V3S3FET 6
MOSFET
FDC638P
CHANNEL
P-TYPE
=PP1V5_S3_P1V5S0FET
8
5 4 2
R7912
C7911
1
RDS(ON)
48 mOhm @4.5V
Q7901
10% 5% 16V
LOADING
MF-LF
2
3
R7910 P3V3S3_EN_L
1
DFN
C7902
0.01UF
47K
1
P3V3S3_SS
2
Q7903
20% 10V CERM 402
R7901
8 =PP5V_S3_MCPDDRFET
16V
4
KELVIN
6
G
2
10K
CERM
402
1
402
D
SSM3K15FV
8
2
10%
MF-LF
NC
1
0.1UF
5% 1/16W
D
ROME
0.182 A (EDP)
C7910
MCPDDR_SS
2
41
402 402
SENSE
D
D
2 X5R
OUT
P1V5_S0_KELVIN
S GND
1/16W
CRITICAL
1
0.033UF
10K
9
1
3 7
1/16W
R7903
MF-LF 402
1
Q7971
1
G
S
2
2
3
5
OUT
P1V5_S0_SENSE =PP1V5_S0_FET
SOT563
5% 1/16W
8
MF-LF 402
=P3V3S3_EN
IN
1
6
SSM6N15FEAPE
100K
63
D
41
5% SOD-VESM-HF
2
R7971
G
2
S
1 1
1 5%
D
1/16W MF-LF
3
1.5V S0 FET
10% 10V
2 2
Q7971
C7903 0.068UF
47K MCPDDR_EN_L
CERM 402
402
MOSFET
Rome SenseFET
CHANNEL
N-TYPE
MCPDDR_EN_L_RC
SSM6N15FEAPE RDS(ON)
SOT563
6.3 mOHM @4.5V VGS
CRITICAL LOADING
Q7930
3.3V S0 FET
FDC606P_G
5
SOT-6
6
3.3V S0 FET =PP3V3_S0_FET
63
8
IN
S
5A (EDP)
4
=MCPDDR_EN
D
2 1
S
5
=PP3V3_S5_P3V3S0FET
4
8
G
C7931
1
0.033UF
100K
C
FDC606P
CHANNEL
P-TYPE
1
G
R7932
MOSFET
RDS(ON)
26 MOHM @4.5V
C
10%
3
5% 16V 2
1/16W X5R
LOADING
MF-LF
1.431 A (EDP)
402
C7930
402 2
R7930
0.01UF
47K P3V3S0_EN_L
1
1
P3V3S0_SS
2
2
5% 10% 1/16W 16V
MF-LF
Q7905
CERM
402
SSM3K15FV
402
D
3
S
2
SOD-VESM-HF
1 63
G
=P3V3S0_EN
IN
376S0778
CRITICAL
MCP79 DDRVTT FET
Q7940
5.0V RT S0 FET
TPCP8102
5.0V RT S0 FET
23V1K-SM
=PP5VRT_S0_FET
8
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
8
=PP5V_S3_P5VRTS0FET
TPCP8102
CHANNEL
P-TYPE
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP. IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
6
D
S
0.033UF
47K
MOSFET
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
5
C7941
1
G
R7942
1
1
2
7
3
8
RDS(ON)
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
13.5 MOHM @4.5V
4
10% 5% 16V
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
2
1/16W X5R
LOADING
MF-LF 402 402 2
B
R7940 47K P5V0RTS0_EN_L
1
C7940
WILL EXIT SELF-REFRESH PREMATURELY.
0.01UF
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
1
P5V0RTS0_SS
2
0.48 A (EDP)
2
LOW THROUGH VTT TERMINATION RESISTORS. 10%
1/16W
16V
MF-LF
Q7945 SSM3K15FV
B
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
5%
CERM
402
402
D
3
S
2
SOD-VESM-HF
1 64 63
IN
G
R7975 10
=P5VS0_EN
8
=PPVTT_S0_VTTCLAMP
2
1
VTTCLAMP_L
90mA max load @ 0.9V 81mW max power
5% 1/10W
376S0778
MF-LF 603
CRITICAL 8
Q7948
5.0V LT S0 FET
5.0V LT S0 FET
23V1K-SM
=PP5VLT_S0_FET
R7976
8
7
TPCP8102
SOT563
CHANNEL
P-TYPE
5% 1/16W 402
6
D
6
MF-LF 2
2
G
S
1
VTTCLAMP_EN
G
0.033UF
47K
MOSFET
5
1
S
2
C7942
1
1
R7943
D
SSM6N15FEAPE
1
100K
8
=PP5V_S3_P5VLTS0FET
3
8
CKT FROM T18
=PP5V_S3_VTTCLAMP
Q7975
TPCP8102
RDS(ON)
13.5 MOHM @4.5V
4
10% 5% 16V 1/16W
2 X5R
LOADING
MF-LF
1.302 A (EDP)
Q7975
402
C7943
402 2
R7944 P5V0LTS0_EN_L
1
2
P5V0LTS0_SS
1
D
3
NO STUFF
C7976
SSM6N15FEAPE
0.01UF
47K
1
0.001UF
SOT563
20% 50V
2
CERM
2
5%
A
1/16W MF-LF
Q7947 SSM3K15FV
402
D
402
10% 16V
5
CERM
G
S
4
SYNC_MASTER=K24_MLB
SYNC_DATE=02/15/2009
58 25
IN
PAGE TITLE
=DDRVTT_EN
POWER FETS DRAWING NUMBER
1 64 63
IN
G
S
A
402
3
SOD-VESM-HF
Apple Inc. 2
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
=P5VS0_EN
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
79 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
D
D
CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP 18
LCD
CONNECTOR
LVDS CONNECTOR:518S0650
LVDS_IG_PANEL_PWR
FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY
1
R9014
CRITICAL
1K
J9000
5% 1/16W MF-LF 2 402
20474-030E-11 F-RT-SM 31
C9015
CRITICAL
U9000
0.001UF
FPF1009 1 ON 8
=PP3V3_S5_LCD
GND
C9009
6
VOUT_1 4
PP3V3_LCDVDD_SW
VOUT_2 5
VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM
1
2
1
1
C9011 0.1UF
10% 16V 2 X5R 402
10% 16V X5R 402
1
2
2
L9008 1
10UF
=PP3V3_S0_LCD 1
R9008 100K
2
LVDS_IG_DDC_CLK
18 7
LVDS_IG_DDC_DATA
3
MIN_LINE_WIDTH=0.30 MM
7
4
MIN_LINE_WIDTH=0.25 MM
5% 1/16W MF-LF 402
2
C
6
PP3V3_S0_LCD_F VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20 MM
72 18 7
LVDS_IG_A_DATA_N
7
72 18 7
LVDS_IG_A_DATA_P
8
72 18 7
LVDS_IG_A_DATA_N
10
9
(LVDS DDC POWER) 1
18 7
VOLTAGE=3.3V
5
2 0402-LF
8
MIN_NECK_WIDTH=0.20 MM
CRITICAL
120-OHM-0.3A-EMI
C9012
20% 6.3V 2 X5R 603
PP3V3_LCDVDD_SW_F
7
0402-LF
MIN_NECK_WIDTH=0.20 MM
THRM PAD 7
0.1UF 2
32
10% 50V X7R 402
2
FERR-120-OHM-1.5A
3 VIN_2
1
1
0.001UF
10% 50V X7R 402
L9004
MFET-2X2
2 VIN_1
C
C9010
1
R9009
72 18 7
LVDS_IG_A_DATA_P
11
100K
72 18 7
LVDS_IG_A_DATA_N
12
72 18 7
LVDS_IG_A_DATA_P
13
5% 1/16W MF-LF 402
72 7
LVDS_IG_A_CLK_F_N
14
72 7
LVDS_IG_A_CLK_F_P
15
LVDS I/F
16
CRITICAL
L9080
NC
90-OHM-200MA AMC2012-SM
68 47 7
PPVOUT_S0_LCDBKLT
17 18
SYM_VER-1
72 18
72 18
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_P
4
3
1
C9017 1000PF
NC
5% 2 50V C0G-CERM 603
2
L9050 8
2
=PP5V_S3_CAMERA MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
19
PLACEMENT_NOTE=PLACE CLOSE TO J9000
1
1
7
LED_RETURN_6
21
68 7
LED_RETURN_5
22
68 7
LED_RETURN_4
23
68 7
LED_RETURN_3
24
68 7
LED_RETURN_2
25
68 7
LED_RETURN_1
26 27
PP5V_S3_CAMERA_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
FERR-120-OHM-1.5A 0402-LF
C9016
LED BKLT I/F
20
68 7
28 29
1
30
CAMERA I/F
0.1uF 20% 10V CERM 402
B
2
B
33 34
CRITICAL
CAMERA
L9060 90-OHM DLP0NS SYM_VER-1
73 20
73 20
USB_CAMERA_P
OUT
OUT
USB_CAMERA_N
3
4
2
1
73 7
73 7
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
PLACEMENT_NOTE=PLACE CLOSE TO J9000.
A
SYNC_MASTER=K24_MLB
SYNC_DATE=02/15/2009
A
PAGE TITLE
LVDS CONNECTOR DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
90 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
18
=MCP_HDMI_TXC_P
DP_ML_P
18
=MCP_HDMI_TXC_N
DP_ML_N
18
=MCP_HDMI_TXD_P
DP_ML_P
18
=MCP_HDMI_TXD_N
DP_ML_N
18
=MCP_HDMI_TXD_P
DP_ML_P
1
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
18
=MCP_HDMI_TXD_N
DP_ML_N
18
=MCP_HDMI_TXD_P
DP_ML_P
18
=MCP_HDMI_TXD_N
DP_ML_N
18
=MCP_HDMI_HPD
DP_HPD
18
=MCP_HDMI_DDC_CLK
DP_IG_DDC_CLK
18
=MCP_HDMI_DDC_DATA
DP_IG_DDC_DATA
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
67 72 MAKE_BASE=TRUE
D
67
D
MAKE_BASE=TRUE
66 MAKE_BASE=TRUE
66 MAKE_BASE=TRUE
DP_AUX_CH_C_N BI
C9300
R9300 DP_IG_DDC_DATA 66
0.1UF
33 1
BI
67 72
1
2 5% 1/16W MF-LF 402
2
72
DP_AUX_CH_SW_N
10% 16V X5R 402
Display Port Interoperability spec says that sources
DP_AUX_CH_C_P
or sinks which do both DP and DVI must depend on the
BI
67 72
external adapter for pull ups on DDC lines (since DP AUX CH has 100K pull up/down on the MLB)..
R9301 DP_IG_DDC_CLK 66
33 1
BI
2 5% 1/16W MF-LF 402
C9301 0.1UF 1
2
72
DP_AUX_CH_SW_P
10% 16V X5R 402
C
3
D
Q9300
Q9300
SSM6N15FEAPE
4
S
G
D
6
S
1
C
SSM6N15FEAPE
SOT563
SOT563
5
2
G
DP_IG_AUX_CH_P 72 18
BI
72 18
BI
DP_IG_AUX_CH_N =PP5V_S0_DP_AUX_MUX 8
1
R9302 100K
R9306
1
1K 5% 1/16W MF-LF 402
2
5% 1/16W MF-LF 402
2
DDC_CA_DET_LS5V_L
B
B Q9301 3
D
SSM3K15FV SOD-VESM-HF
2
S
G
1
DP_CA_DET 67
IN
DP_IG_CA_DET OUT
18
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
DISPLAYPORT SUPPORT DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
93 OF 109 SHEET
OF
8
7
6
5
4
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1
8
7
6
5
4
3
2
1
POR IS PLASTIC MINI DP CONNECTOR BUT METAL PART’S SCHEMATIC AND CAD SUMBOLS HAVE BEEN USED BEACUSE ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES
Port Power Switch CRITICAL
L9400
63 36 32 21 7
5
=PP3V3_S5_DP_PORT_PWR
4
PM_SLP_S3_L
IN
IN
OUT OC*
EN
1
1
PP3V3_S0_DPILIM
3
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
TP_DPPWR_OC_L
2 0603
1
GND
RCLAMP0524P
SLP2510P8
SLP2510P8
PP3V3_S0_DPPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
2
C9400
9
4.7UF
2 2
D
D9410
RCLAMP0524P
FERR-120-OHM-3A
TPS2051B SOT23 8
DP_ESD CRITICAL
D9410
IO NC
20% 6.3V X5R-CERM 402
IO NC
1
5
10
6
IO NC
IO NC GND
U9480
DP_ESD CRITICAL
GND
D
3
3
4 7
CRITICAL
C9480
1
1
2
2
22UF 20% 6.3V X5R-CERM-1 603
C9481
C9485
4.7UF
1
1
2
2
20% 6.3V X5R-CERM-1 603
C9486 22UF
22UF
20% 6.3V X5R-CERM 402
20% 6.3V X5R-CERM-1 603
1
R9420 100K 5% 1/16W MF-LF 402
2
OMIT
CRITICAL
HDMI_CEC
J9400 MINIDSPLYPRT-K83 F-RT-THSM
FL9400
1
R9425
C
1M 5% 1/16W MF-LF
FL9403 72 66
IN
DP_ML_P
C9414
72 66
IN
DP_ML_N
C9415
BI
DP_AUX_CH_C_P
BI
DP_AUX_CH_C_N
2
1
2
10%
SYM_VER-2
X5R
6 8
402
0.1uF
0.1uF 72 66
10%
3
72 DP_ML_C_N 16V
X5R
SM PINS
1
72 DP_ML_C_P 16V
TH PINS
4
12-OHM-100MA TCM1210-4SM 4 1
TOP ROW
2
402
2
BOT ROW
2
72
DP_ML_CONN_P
10
72
DP_ML_CONN_N
12
402
14 16 18
72 66
67 8
20
R9443
1
72
DP_ML_CONN_N
100K
5% 1/16W MF-LF 402
R9421
5%
1
1/16W MF-LF
2
402
DP_CA_DET
9
72
DP_ML_CONN_P
ML_LANE3N GND AUX_CHP AUX_CHN DP_PWR
11
72
DP_ML_CONN_N
C9410
2
12-OHM-100MA TCM1210-4SM
5 1
SYM_VER-2
3
C9411
72 DP_ML_C_N
2
22
1
2 10%
72 DP_ML_C_P
C9412
72 DP_ML_C_N
C9413
72 DP_ML_C_P
C9416
72 DP_ML_C_N
C9417
1
2
DP_ML_N 16V
X5R
IN
66 72
IN
66 72
IN
66 72
IN
66 72
IN
66 72
402
10%
DP_ML_P 16V
X5R
402
0.1uF 2
FL9402
3
12-OHM-100MA TCM1210-4SM 1
SYM_VER-2
1
2 10%
0.1uF
DP_ML_N 16V
X5R
402
4
72 DP_ML_CONN_P
1
2 10%
17
DP_ML_P 16V
X5R
402
0.1uF 2
72 DP_ML_CONN_N
3
1
2 10%
DP_ML_N 16V
X5R
402
21
514-0691
MF-LF 402
2 2
IO NC
IO NC
1 10
DP_ESD CRITICAL DP_ESD
D9411
CRITICAL
RCLAMP0524P
3
D9400 3
SLP2510P8
RCLAMP0504F SC70-6-1
D
Q9440
B
66 72
1/16W
2
DP_CA_DET_L_Q
1
IN 402
0.1uF
GND G
X5R
5%
2N7002DW-X-G
S
16V
SLP2510P8
9
SOT-363
DP_ML_P
0.1uF
4
13
19
2 10%
FL9401
3
15
1
SHIELD PINS
RCLAMP0524P
1
D
Q9440
5
2N7002DW-X-G 6
SOT-363
S
G
5
6
1
DP_CA_DET_Q
4
1
Q9440 must have Drain to Gate leakage of 5MOhm
R9422
Cable Adapter
1M
(CA) has 100k
2
IO NC
IO NC
B
4 7
GND
DP to DVI/HDMI 5
3
5%
402
4
pull-up to DP_PWR.
1/16W MF-LF
3
2
=PP3V3_S0_DPCONN
R9445
1
R9444
10K
5% 1/16W
MF-LF 402
MF-LF 402
2
DP_HPD
OUT
1
10K
5% 1/16W
66
C
4
0.1uF
7
ML_LANE1N GND ML_LANE2P ML_LANE2N RETURN
SYM_VER-2
100K
6
67 8
1
72 DP_ML_C_P
HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2 ML_LANE0N GND GND ML_LANE3P ML_LANE1P
D9411
1
R9442
100K
OUT
DP_ML_CONN_P
DP_ESD
=PP3V3_S0_DPCONN
CRITICAL
66
12-OHM-100MA TCM1210-4SM 72
2
6
R9446
1
MCP79 requires pull down HPD input with
D
Q9441 2N7002DW-X-G
100K
100K if DP_HPD is used.
5% 1/16W
SOT-363
S
G
2
DP_HPD_L_Q
MF-LF 402
2
3
1
D
Q9441
A
2N7002DW-X-G SOT-363
S
G
5
SYNC_MASTER=K24_MLB
DP_HPD_Q
SYNC_DATE=04/06/2009
A
PAGE TITLE 4
R9423
1
DisplayPort Connector
DP Source must pull down HPD input with
100K
DRAWING NUMBER greater than or equal
5%
Apple Inc.
1/16W MF-LF 402
to 100K (DPv1.1a). 2
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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D
D
PLACEMENT_NOTE=PLACE NEAR L9710
CRITICAL
R9700
CRITICAL
0.020
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=9V
69
1 3
2 4
PLACEMENT_NOTE=PLACE CLOSE TO L9710
2 OUT ISNS_LCDBKLT_P
76 47
OUT ISNS_LCDBKLT_N
PLACEMENT_NOTE=PLACE CLOSE TO L9710
10% 25V X5R 402
C9710
1
1
10% 25V X5R 805
GND_LCDBKLT_PGND
68
R9730 10
10UF
PLACEMENT_NOTEs:
D9710
2 2
SOD-123 2
IHLP2020BZ11-SM
CRITICAL
0.1UF
76 47
1
1 C9713
CRITICAL
L9710 10UH-2.1A
PPVIN_BKL
PPVOUT_S0_LCDBKLT_SW
1
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=50V SWITCH_NODE=TRUE
PLACEMENT_NOTE=PLACE C9717 CLOSE TO D9710 PIN 2 & XW9701
2
CRITICAL RB160M-40
1
DIDT=TRUE
5% 1/16W MF-LF 402
4.7UF
f = 600kHz 2 68
LCDBKLT_VIN MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM
PP2V5_S0_LCDBKLT
2
1
C
PLACEMENT_NOTE=PLACE CLOSE TO U9700 PIN 1
C9727 1000PF
20
10% 25V X5R 603-1
SWA SWB
PP5V5_S0_LCDBKLT
23
VDC2
VOUT
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5.5V
5% 50V 2 C0G-CERM 603
C9700
1
1
2.2UF
20% 10V X5R-CERM 402
20% 10V X5R-CERM 402
2
2
IN
2
LVDS_IG_BKL_PWM
1
LVDS_IG_BKL_PWM_R
24
NOSTUFF
R9715 1M
LLP
OVP 16
1% 1/16W MF-LF 402
OVP = Vovp * (1 + Ra/Rb) VOVP = 6.9V +/- 0.35V
MC34845
18
5% 1/16W MF-LF 402
OMIT
10% 100V X7R 603
XW9701 SM
2
3
U9700
R9725 69 18
2
4
CRITICAL
(SGND)
0
1000PF
10% 50V X7R 1206
1
1
C9701
2.2UF
2
C9717
WF: C9711 AND C9717 NOT IN REF SCHEMATIC.
VDC1
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=2.5V
1UF
2.2UF
20% 50V X7R-CERM 1206
PWM WAKE
CH1
22
7
2
1
C9723
1
100PF
5% 50V CERM 402
2
NOSTUFF
C9722
2
LCDBKLT_OVP
NOSTUFF
C9721 100PF
1
1
C9725
2
NOSTUFF
C9724
100PF
100PF
5% 50V CERM 402
5% 50V CERM 402
1
6
EN
CH2
8
17
COMP
CH3
9
5% 50V CERM 402
(C9721-C9726)
NOSTUFF
C9726
1
100PF 2
BKL_MC_CH1
5% 50V CERM 402
2
R9717 1
15
ISET
MIN_LINE_WIDTH=0.2 MM
R9726
LCDBKLT_ISET
22K
MIN_LINE_WIDTH=0.2 MM
5%
C9705 10%
1
1
50V
0.0022UF
R9710 7.68K
CERM 402
1% 1/16W MF-LF 2 402
2
LCDBKLT_COMP_RC
CH5
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 11 BKL_MC_CH5
CH6
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 12 BKL_MC_CH6
FAIL
B
2
2
13
5% 50V CERM 402
19
56PF
5
GND
1
21
C9706
1% 1/16W MF-LF 2 402
PGNDA PGNDB
R9705
14
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
R9718 10.2 1
LED_RETURN_2
2
10.2
1
2
2
R9721
LED_RETURN_4 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
10.2 1
LED_RETURN_5
2 1% 1/16W MF-LF 402
LED_RETURN_3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
1% 1/16W MF-LF 402
10.2 1% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
R9719
1% 1/16W MF-LF 402
R9720 1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
1
10K
CH4
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 10 BKL_MC_CH4
LED_RETURN_1
2
BKL_MC_CH3
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
R9722 10.2 1
2 1% 1/16W MF-LF 402
LED_RETURN_6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
IN
7 65
IN
7 65
IN
7 65
IN
7 65
IN
7 65
IN
7 65
LCDBKLT_FAIL
R9702 1 THRM
0
PAD
5% 1/16W MF-LF 402
R9716
1
243K 1% 1/16W MF-LF 402 2
NOSTUFF
25
1/16W MF-LF
2 402
10.2 1% 1/16W MF-LF 402
BKL_MC_CH2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
1
C
PLACE NEAR U9700
100PF
5% 50V CERM 402
2
PLACEMENT_NOTEs:
NOSTUFF
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
LCDBKLT_COMP
7 47 65
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.24 MM VOLTAGE=50V
GND_LCDBKLT_PGND
VIN
C9711
C9716
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 MM
(C9710-C9711)
1
C9715
PPVOUT_S0_LCDBKLT
NOSTUFF CRITICAL 1
1
1% 0.25W MF-LF 805
PPBUS_S0_LCDBKLT_PWR
2
GND_LCDBKLT_SGND
OMIT
XW9700 SM 1
B
2
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.24 MM VOLTAGE=0V
ISET = 153mA /
PLACEMENT_NOT=PLACE XW9700 FAR FROM THE NOISY
PINS 3 AND 4
13.3 Inch Panel (9 LEDs per string) TARGET: ISET = 20MA, ACTUAL: ISET = 19.9MA,
OVP = 35V OVP = 35.2V
A
SYNC_MASTER=VEMURI_K19I
SYNC_DATE=02/09/2009
A
PAGE TITLE
LCD Backlight Driver (MC34845) DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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OF
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5
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8
7
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5
4
3
2
1
CRITICAL
Q9806
PPBUS S0 LCDBkLT FET
FDC638APZ_SBMS001 SSOT6-HF 6
F9800
MIN_LINE_WIDTH=0.4 mm
4
PPBUS_S0_LCDBKLT_FUSED
FDC638APZ
CHANNEL
P-TYPE
D
2
2
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
0402-HF
1
D
1
=PPBUS_S0_LCDBKLT
IN
5
2AMP-32V
8
MOSFET
1
VOLTAGE=12.6V
R9808
1
43 mOhm @4.5V
C9802
301K
LOADING
0.1UF
0.4 A (EDP)
3
1%
10% 1/16W
RDS(ON)
16V
2
MF-LF
X5R 402
402
2
PPBUS_S0_LCDBKLT_EN_DIV
1
R9809 147K 1% 1/16W MF-LF 402
2
PPBUS_S0_LCDBKLT_EN_L
Q9807
D
3
SSM6N15FEAPE SOT563
5
69 18
LVDS_IG_BKL_ON
IN
G
S
PPBUS_S0_LCDBKLT_PWR 4
OUT
68
MIN_LINE_WIDTH=0.4 mm
BKLT_EN_L
MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
Q9807
D
6
SSM6N15FEAPE SOT563
C
2
25
BKLT_PLT_RST_L
IN
G
S
C 1
B
B
1
R9840
1
1K
18 68
R9841 5%
1/16W MF-LF 402
18 69
LVDS_IG_BKL_PWM
1K
5%
2
LVDS_IG_BKL_ON
1/16W MF-LF
2
402
MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
LCD Backlight Support DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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OF
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4
FSB (Front-Side Bus) Constraints
3
2
1
CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
NET_TYPE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
FSB_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_D_L
10 14
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DINV_L
10 14 10 14
TABLE_PHYSICAL_RULE_ITEM
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
*
=2x_DIELECTRIC
?
FSB_DSTB
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
FSB_DATA
TOP,BOTTOM
=4x_DIELECTRIC
?
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
D
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
FSB_ADDR
*
=STANDARD
?
FSB_ADSTB
*
=2x_DIELECTRIC
?
FSB_1X
*
=STANDARD
?
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_N
10 14
10 14
WEIGHT
TABLE_SPACING_RULE_ITEM
FSB_DATA
FSB_DSTB0
FSB_DSTB_L_P
TABLE_SPACING_RULE_HEAD
WEIGHT
FSB 4X Signal Groups
FSB_DSTB_50S
TABLE_SPACING_RULE_ITEM
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
?
FSB_ADSTB
TOP,BOTTOM
=4x_DIELECTRIC
?
FSB_1X
TOP,BOTTOM
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_D_L
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DINV_L
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_P
10 14 10 14
10 14
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_N
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_D_L
10 14 10 14
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DINV_L
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_P
10 14
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_N
10 14
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_D_L
10 14
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DINV_L
10 14 10 14 10 14
D
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended. FSB 4X signals / groups shown in signal table on right. Signals within each 4x group should be matched within 5 ps of strobe. FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_P
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB_L_N
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps. Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
FSB 2X
FSB 2X signals / groups shown in signal table on right. Signals within each 2x group should be matched within 20 ps.
ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
Signals
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_A_L
10 14
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_REQ_L
10 14
FSB_ADSTB0
FSB_50S
FSB_ADSTB
FSB_ADSTB_L
10 14
FSB_ADDR_GROUP1
FSB_50S
FSB_ADDR
FSB_A_L
10 14
FSB_ADSTB1
FSB_50S
FSB_ADSTB
FSB_ADSTB_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_ADS_L
10 14
FSB_BREQ0_L
FSB_50S
FSB_1X
FSB_BREQ0_L
10 14
FSB_BREQ1_L
FSB_50S
FSB_1X
FSB_BREQ1_L
14
FSB_1X
FSB_50S
FSB_1X
FSB_BNR_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_BPRI_L
10 14 10 14
FSB 1X signals shown in signal table on right. Signals within each 1x group should be matched to CPU clock, +0/-1000 mils. Design Guide recommends each strobe/signal group is routed on the same layer.
FSB 1X Signals
Intel Design Guide recommends FSB signals be routed only on internal layers. NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints
FSB_1X
FSB_50S
FSB_1X
FSB_DBSY_L
FSB_1X
FSB_50S
FSB_1X
FSB_DEFER_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_DRDY_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_HIT_L
FSB_1X
FSB_50S
FSB_1X
FSB_HITM_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_LOCK_L
10 14
FSB_CPURST_L
FSB_50S
FSB_1X
FSB_CPURST_L
10 13 14
FSB_1X
FSB_50S
FSB_1X
FSB_RS_L
10 14
FSB_1X
FSB_50S
FSB_1X
FSB_TRDY_L
10 14
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_A20M_L
10 14
CPU_BSEL
CPU_50S
CPU_AGTL
CPU_BSEL
9 10
CPU_FERR_L
CPU_50S
CPU_8MIL
CPU_FERR_L
10 14
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_IGNNE_L
10 14
CPU_INIT_L
CPU_50S
CPU_AGTL
CPU_INIT_L
10 14
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_INTR
10 14
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_NMI
10 14 37 10 13 14
10 14
TABLE_PHYSICAL_RULE_HEAD
C
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
CPU_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
C
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance. TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CPU_AGTL
*
=STANDARD
?
CPU_8MIL
*
8 MIL
?
TABLE_SPACING_RULE_ITEM
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
CPU_COMP
*
25 MIL
10 14
? CPU_PROCHOT_L
CPU_50S
CPU_AGTL
CPU_PROCHOT_L
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_SMI_L
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_STPCLK_L
10 14
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
PM_THRMTRIP_L
10 14 37
FSB_CPUSLP_L
CPU_50S
CPU_AGTL
FSB_CPUSLP_L
10 14
CPU_FROM_SB
CPU_50S
CPU_AGTL
CPU_DPSLP_L
10 14
CPU_DPRSTP_L
CPU_50S
CPU_AGTL
CPU_DPRSTP_L
10 14 59
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
CPU_ASYNC
CPU_50S
CPU_AGTL
FSB_DPWR_L
10 14
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_BCLK_VML_COMP_VDD
14
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_BCLK_VML_COMP_GND
14 14
TABLE_SPACING_RULE_ITEM
CPU_GTLREF
*
25 MIL
?
CPU_ITP
*
=2:1_SPACING
?
CPU_VCCSENSE
*
25 MIL
?
SR DG recommends at least 25 mils, >50 mils preferred TABLE_SPACING_RULE_ITEM
10 14
TABLE_SPACING_RULE_ITEM
Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance.
MCP FSB COMP Signal Constraints
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP_VCC
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP_GND
14
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU_P
10 14
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU_N
10 14
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP_P
13 14 13 14
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
MCP_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
B
=50_OHM_SE
=STANDARD
=STANDARD
B
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
MCP_FSB_COMP
*
8 MIL
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP_N
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP_P
14
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP_N
14
CPU_IERR_L
CPU_50S
CPU_IERR_L
10
PM_DPRSLPVR
CPU_50S
CPU_AGTL
PM_DPRSLPVR
21 59
(See above)
CPU_50S
CPU_AGTL
IMVP_DPRSLPVR
59
CPU_GTLREF
CPU_50S
CPU_GTLREF
CPU_GTLREF
10 26
?
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
FSB Clock Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
CLK_FSB_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
*
=3x_DIELECTRIC
CPU_50S
CPU_COMP
CPU_COMP
10
CPU_27P4S
CPU_COMP
CPU_COMP
10
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
10
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_COMP
10
XDP_TDI
CPU_50S
CPU_ITP
XDP_TDI
10 13
XDP_TDO
CPU_50S
CPU_ITP
XDP_TDO
10 13
XDP_TMS
CPU_50S
CPU_ITP
XDP_TMS
10 13
XDP_TCK
CPU_50S
CPU_ITP
XDP_TCK
10 13
XDP_TRST_L
CPU_50S
CPU_ITP
XDP_TRST_L
10 13
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_L
10 13 10 13
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CLK_FSB
CPU_COMP CPU_COMP
TABLE_SPACING_RULE_ITEM
?
CLK_FSB
TOP,BOTTOM
=4x_DIELECTRIC
?
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
A
XDP_BPM_L5
CPU_50S
CPU_ITP
XDP_BPM_L
(FSB_CPURST_L)
CPU_50S
CPU_ITP
XDP_CPURST_L
13
CPU_50S
CPU_8MIL
CPU_VID
11 59
CPU_50S
CPU_8MIL
IMVP6_VID
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE_P
11 59
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE_N
11 59
(CPU_VCCSENSE)
CPU_27P4S
CPU_VCCSENSE
IMVP6_VSEN_P
(CPU_VCCSENSE)
CPU_27P4S
CPU_VCCSENSE
IMVP6_VSEN_N
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
CPU/FSB Constraints DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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100 OF 109 SHEET
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Memory Bus Constraints
4
3
2
1
Memory Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
NET_TYPE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CLK_P
15 27
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CLK_N
15 27
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CKE
15 27
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CS_L
15 27 15 27
TABLE_PHYSICAL_RULE_ITEM
MEM_40S_VDD
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD TABLE_PHYSICAL_RULE_ITEM
MEM_70D
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_70D_VDD
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_ODT
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_A
15 27
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_BA
15 27
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_RAS_L
15 27
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CAS_L
15 27 15 27
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
D
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4:1_SPACING
?
D
TABLE_SPACING_RULE_ITEM
MEM_CLK2MEM
*
TABLE_SPACING_RULE_ITEM
MEM_CTRL2CTRL
*
=2:1_SPACING
?
MEM_CTRL2MEM
*
=2.5:1_SPACING
?
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_WE_L
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ
15 27 15 27
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MEM_CMD2CMD
*
=1.5:1_SPACING
? TABLE_SPACING_RULE_ITEM
MEM_CMD2MEM
*
=3:1_SPACING
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ
15 27
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ
15 27 15 27
? TABLE_SPACING_RULE_ITEM
MEM_DATA2DATA
*
=1.5:1_SPACING
?
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ
15 27
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ
15 27 15 27
TABLE_SPACING_RULE_ITEM
MEM_DATA2MEM
*
=3:1_SPACING
? TABLE_SPACING_RULE_ITEM
MEM_DQS2MEM
*
=3:1_SPACING
?
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQ
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DM
15 27
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27 15 27
TABLE_SPACING_RULE_ITEM
MEM_2OTHER
*
25 MIL
?
Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
*
MEM_CLK2MEM
MEM_CLK
MEM_CTRL
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CLK
*
MEM_CMD2MEM
MEM_CMD
MEM_CTRL
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CMD
*
MEM_CLK2MEM
MEM_CLK
MEM_DATA
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CMD
*
MEM_CMD2CMD
MEM_CMD
MEM_DATA
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_DQS
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK2MEM
MEM_CMD
MEM_DQS
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
C
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
*
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
*
MEM_CTRL2MEM
MEM_DATA
MEM_CTRL
*
MEM_DATA2MEM
MEM_DATA
MEM_CMD
*
MEM_DATA2MEM
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_CTRL2MEM
MEM_DATA
*
MEM_DQS
*
NET_SPACING_TYPE2
AREA_TYPE
MEM_DATA
SPACING_RULE_SET
MEM_DQS
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
MEM_CLK
*
MEM_DQS2MEM
MEM_DQS
MEM_CTRL
*
MEM_DQS2MEM
MEM_CLK
*
*
MEM_2OTHER
MEM_CTRL
*
*
MEM_2OTHER
*
MEM_DATA
MEM_DQS2MEM
*
15 27
MEM_A_DQS4
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_A_DQS_P
15 27
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_A_DQS_N
15 27
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CLK_P
15 28
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CLK_N
15 28
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CKE
15 28
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CS_L
15 28
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_ODT
MEM_CMD
*
*
MEM_2OTHER
15 28
15 28
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS2MEM
MEM_DATA
*
*
MEM_2OTHER MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_A
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_BA
15 28
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_RAS_L
15 28
DDR2:
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CAS_L
15 28
DQ signals should be matched within 20 ps of associated DQS pair.
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_WE_L
15 28
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_DQS
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS2MEM
MEM_DQS
*
*
MEM_2OTHER
Need to support MEM_*-style wildcards!
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. All DQS pairs should be matched within 100 ps of clocks. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
B
All memory signals maximum length is 1.005 ps.
CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric. MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
DDR3:
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
DQ signals should be matched within 5 ps of associated DQS pair.
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DQ
15 28
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DM
15 28
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DM
15 28
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DM
15 28
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DM
15 28
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DM
15 28 15 28
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. A/BA/cmd signals should be matched within 5 ps of CLK pairs. All memory signals maximum length is 1.005 ps.
C
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_A_DQS_P
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_DQS
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_70D
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
15 27
MEM_A_DQS4
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
MEM_A_DQS_N
MEM_DATA2DATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DQS
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_DQS
MEM_70D
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_70D
MEM_A_DQS3
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_A_DQS3
MEM_A_DQS_P
CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric. MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DM
15 28
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DM
15 28
MCP MEM COMP Signal Constraints
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28 15 28
B
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS_P
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28 15 28
TABLE_PHYSICAL_RULE_ITEM
MCP_MEM_COMP
*
Y
7 MIL
7 MIL
=STANDARD
=STANDARD
=STANDARD
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS_N
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28 15 28
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
MCP_MEM_COMP
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
A
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_B_DQS_N
MEM_B_DQS7
MEM_70D
MEM_DQS
MEM_B_DQS_P
15 28
MEM_B_DQS7
MEM_70D
MEM_DQS
MEM_B_DQS_N
15 28
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP_VDD
16
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP_GND
16
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
Memory Constraints DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
101 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
NET_TYPE
PCI-Express
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP PCIE_90D
PCIE
PCIE_MINI_R2D_P
30
PCIE_90D
PCIE
PCIE_MINI_R2D_N
30
PCIE_90D
PCIE
PCIE_MINI_R2D_C_P
17 30
PCIE_90D
PCIE
PCIE_MINI_R2D_C_N
17 30
PCIE_90D
PCIE
PCIE_MINI_D2R_P
17 30
PCIE_90D
PCIE
PCIE_MINI_D2R_N
17 30
PCIE_90D
PCIE
PCIE_FW_R2D_P
PCIE_90D
PCIE
PCIE_FW_R2D_N
PCIE_90D
PCIE
PCIE_FW_R2D_C_P
9 17
PCIE_90D
PCIE
PCIE_FW_R2D_C_N
9 17
PCIE_90D
PCIE
PCIE_FW_D2R_P
9 17
PCIE_90D
PCIE
PCIE_FW_D2R_N
9 17
PCIE_90D
PCIE
PCIE_FW_D2R_C_P
PCIE_90D
PCIE
PCIE_FW_D2R_C_N
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_MINI_P
17 30
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_MINI_N
17 30
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_MINI_CONN_P
7 30
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_MINI_CONN_N
7 30
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_FC_P
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_FC_N
PCIE_90D
PCIE
CONN_PCIE_MINI_R2D_P
7 30
PCIE_90D
PCIE
CONN_PCIE_MINI_R2D_N
7 30
TABLE_PHYSICAL_RULE_ITEM
PCIE_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM
CLK_PCIE_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
PCIE_MINI_R2D
=100_OHM_DIFF
PCIE_MINI_D2R TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PCIE
*
TABLE_SPACING_RULE_ITEM
?
=3X_DIELECTRIC
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
D
CLK_PCIE
*
20 MIL
?
MCP_PEX_COMP
*
8 MIL
?
TABLE_SPACING_RULE_ITEM
PCIE_FW_R2D
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4
PCIE_FW_D2R
MCP_PE1_REFCLK
MCP_PE4_REFCLK
D
PCIE_90D PCIE
CONN_PCIE_MINI_D2R_P
7 30
PCIE
CONN_PCIE_MINI_D2R_N
7 30
PCIE_90D
MCP_PEX_CLK_COMP
C
MCP_PEX_COMP
MCP_PEX_CLK_COMP
17
C
Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
DP_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LVDS_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_DV_COMP
*
Y
20 MIL
20 MIL
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TMDS_IG_TXC
DP_100D
DISPLAYPORT
TMDS_IG_TXC_P
TMDS_IG_TXC
DP_100D
DISPLAYPORT
TMDS_IG_TXC_N
TMDS_IG_TXD
DP_100D
DISPLAYPORT
TMDS_IG_TXD_P
TMDS_IG_TXD
DP_100D
DISPLAYPORT
TMDS_IG_TXD_N
DP_ML
DP_100D
DISPLAYPORT
DP_ML_P
66 67
DP_100D
DISPLAYPORT
DP_ML_C_P
67
DP_100D
DISPLAYPORT
DP_ML_N
66 67
DP_100D
DISPLAYPORT
DP_ML_C_N
67
DP_100D
DISPLAYPORT
DP_IG_AUX_CH_P
18 66
DP_100D
DISPLAYPORT
DP_IG_AUX_CH_N
18 66
DP_100D
DISPLAYPORT
DP_AUX_CH_SW_P
66
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
DP_100D
DISPLAYPORT
DP_AUX_CH_SW_N
66
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
DP_100D
DISPLAYPORT
DP_AUX_CH_C_P
66 67
DP_100D
DISPLAYPORT
DP_AUX_CH_C_N
66 67
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
DISPLAYPORT
*
=3x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
DP_ML
LVDS
*
=3x_DIELECTRIC
LVDS intra-pair matching should be 5 mils.
?
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
?
Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. DIsplayPort AUX CH intra-pair matching should be 5 ps.
DP_AUX_CH
Inter-pair matching should be within 150 ps. No relationship to other signals.
SATA Interface Constraints MCP_HDMI_RSET
MCP_DV_COMP
MCP_HDMI_RSET
18 24
MCP_HDMI_VPROBE
MCP_DV_COMP
MCP_HDMI_VPROBE
18 24
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_CLK_P
18 65
LVDS_100D
LVDS
LVDS_IG_A_CLK_F_P
7 65
LVDS_100D
LVDS
LVDS_IG_A_CLK_N
18 65
LVDS_100D
LVDS
LVDS_IG_A_CLK_F_N
7 65
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA_P
7 18 65
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA_N
7 18 65
DP_ML
DP_100D
DISPLAYPORT
DP_ML_CONN_P
67
DP_100D
DISPLAYPORT
DP_ML_CONN_N
67
MCP_IFPAB_RSET
18 24
MCP_IFPAB_VPROBE
18 24
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
SATA_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SATA_90D_HDD
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
LVDS_IG_A_CLK
TABLE_SPACING_RULE_HEAD
B
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SATA
*
=4x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
SATA
TOP,BOTTOM
=3x_DIELECTRIC
B
?
TABLE_SPACING_RULE_ITEM
SATA_TERMP
*
8 MIL
? I183
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
I182
MCP_IFPAB_RSET
MCP_DV_COMP
MCP_IFPAB_VPROBE
SATA_HDD_R2D
SATA_HDD_D2R
SATA_ODD_R2D
A
SATA_ODD_D2R
MCP_SATA_TERMP
SATA_90D_HDD
SATA
SATA_HDD_R2D_C_P
20 34
SATA_90D_HDD
SATA
SATA_HDD_R2D_C_N
20 34
SATA_90D_HDD
SATA
SATA_HDD_R2D_P
7 34
SATA_90D_HDD
SATA
SATA_HDD_R2D_N
7 34
SATA_90D_HDD
SATA
SATA_HDD_R2D_UF_P
34
SATA_90D_HDD
SATA
SATA_HDD_R2D_UF_N
34
SATA_90D_HDD
SATA
SATA_HDD_D2R_P
20 34
SATA_90D_HDD
SATA
SATA_HDD_D2R_N
20 34
SATA_90D_HDD
SATA
SATA_HDD_D2R_C_P
7 34
SATA_90D_HDD
SATA
SATA_HDD_D2R_C_N
7 34
SATA_90D_HDD
SATA
SATA_HDD_D2R_UF_P
34
SATA_90D_HDD
SATA
SATA_HDD_D2R_UF_N
34
SATA_100D
SATA
SATA_ODD_R2D_C_P
20 34
SATA_100D
SATA
SATA_ODD_R2D_C_N
20 34
SATA_100D
SATA
SATA_ODD_R2D_P
7 34
SATA_100D
SATA
SATA_ODD_R2D_N
7 34
SATA_100D
SATA
SATA_ODD_R2D_UF_P
34
SATA_100D
SATA
SATA_ODD_R2D_UF_N
34
SATA_100D
SATA
SATA_ODD_D2R_P
20 34
SATA_100D
SATA
SATA_ODD_D2R_N
20 34
SATA_100D
SATA
SATA_ODD_D2R_C_P
7 34
SATA_100D
SATA
SATA_ODD_D2R_C_N
7 34
SATA_100D
SATA
SATA_ODD_D2R_UF_P
34
SATA_100D
SATA
SATA_ODD_D2R_UF_N
34
SATA_TERMP
MCP_SATA_TERMP
20
SYNC_MASTER=K24_MLB
SYNC_DATE=03/30/2009
A
PAGE TITLE
MCP Constraints 1 DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
102 OF 109 SHEET
OF
8
7
6
5
4
3
2
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8
7
6
5
4
3
2
1
PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD
NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
PCI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PHYSICAL
ELECTRICAL_CONSTRAINT_SET
SPACING
TABLE_PHYSICAL_RULE_ITEM
MCP_DEBUG
PCI_55S
PCI
MCP_DEBUG
PCI_AD
PCI_55S
PCI
PCI_AD
13 19
TABLE_PHYSICAL_RULE_ITEM
CLK_PCI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PCI_AD24
PCI_55S
PCI
PCI_AD
PCI_AD
PCI_55S
PCI
PCI_AD
PCI_AD
PCI_55S
PCI
PCI_PAR
PCI_C_BE_L
PCI_55S
PCI
PCI_C_BE_L
PCI_CNTL
PCI_55S
PCI
PCI_IRDY_L
PCI_CNTL
PCI_55S
PCI
PCI_DEVSEL_L
PCI_CNTL
PCI_55S
PCI
PCI_PERR_L
PCI_CNTL
PCI_55S
PCI
PCI_SERR_L
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
PCI
*
=STANDARD
? TABLE_SPACING_RULE_ITEM
CLK_PCI
D
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LPC Bus Constraints
D
PCI_CNTL
PCI_55S
PCI
PCI_STOP_L
PCI_CNTL
PCI_55S
PCI
PCI_TRDY_L
PCI_CNTL
PCI_55S
PCI
PCI_FRAME_L
PCI_REQ0_L
PCI_55S
PCI
PCI_REQ0_L
PCI_GNT0_L
PCI_55S
PCI
PCI_GNT0_L
PCI_REQ1_L
PCI_55S
PCI
PCI_REQ1_L
PCI_GNT1_L
PCI_55S
PCI
PCI_GNT1_L
PCI_INTW_L
PCI_55S
PCI
PCI_INTW_L
PCI_INTX_L
PCI_55S
PCI
PCI_INTX_L
PCI_INTY_L
PCI_55S
PCI
PCI_INTY_L
PCI_INTZ_L
PCI_55S
PCI
PCI_INTZ_L
MCP_PCI_CLK2
CLK_PCI_55S
CLK_PCI
PCI_CLK33M_MCP_R
CLK_PCI_55S
CLK_PCI
PCI_CLK33M_MCP
19
LPC_AD
LPC_55S
LPC
LPC_AD
19 36 38
LPC_FRAME_L
LPC_55S
LPC
LPC_FRAME_L
19 36 38
LPC_RESET_L
LPC_55S
LPC
LPC_RESET_L
19 25
MCP_LPC_CLK0
CLK_LPC_55S
CLK_LPC
LPC_CLK33M_SMC_R
19 25
CLK_LPC_55S
CLK_LPC
LPC_CLK33M_SMC
25 36
CLK_LPC_55S
CLK_LPC
LPC_CLK33M_LPCPLUS
25 38
USB_90D
USB
USB_EXTA_P
20 35
USB_90D
USB
USB_EXTA_N
20 35
USB_90D
USB
USB_EXTA_MUXED_P
35
USB_90D
USB
USB_EXTA_MUXED_N
35
USB_90D
USB
CONN_USB_EXTA_P
35
USB_90D
USB
CONN_USB_EXTA_N
35
USB_90D
USB
USB_CAMERA_P
20 65
USB_90D
USB
USB_CAMERA_N
20 65
USB_90D
USB
USB_CAMERA_CONN_P
7 65
USB_90D
USB
USB_CAMERA_CONN_N
7 65
USB_90D
USB
USB_BT_P
20 30
USB_90D
USB
USB_BT_N
20 30
USB_90D
USB
CONN_USB2_BT_P
USB_90D
USB
CONN_USB2_BT_N
7 30
USB_90D
USB
USB_TPAD_P
20 44
USB_90D
USB
USB_TPAD_N
20 44
USB_90D
USB
USB_TPAD_R_P
44
USB_90D
USB
USB_TPAD_R_N
44
USB_90D
USB
USB_IR_P
9 20
USB_90D
USB
USB_IR_N
9 20
USB_90D
USB
USB_EXTB_P
20 35
USB_90D
USB
USB_EXTB_N
20 35
USB_90D
USB
CONN_USB_EXTB_P
35
USB_90D
USB
CONN_USB_EXTB_N
35
USB_90D
USB
USB_CARDREADER_P
9 20
USB_90D
USB
USB_CARDREADER_N
9 20
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
LPC_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
19
=STANDARD TABLE_PHYSICAL_RULE_ITEM
CLK_LPC_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LINE-TO-LINE SPACING
WEIGHT
LPC
LAYER *
6 MIL
?
CLK_LPC
*
8 MIL
?
19
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.
USB 2.0 Interface Constraints
19
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
MCP_USB_RBIAS
*
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD TABLE_PHYSICAL_RULE_ITEM
USB_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_HEAD
USB_EXTA
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
USB
C
*
TABLE_SPACING_RULE_ITEM
USB
TOP,BOTTOM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.
C
SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SMB_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
USB_CAMERA TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
SMB
*
USB_BT
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.
HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
USB_TPAD
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
7 30
TABLE_PHYSICAL_RULE_ITEM
HDA_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
USB_IR
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
HDA
=2x_DIELECTRIC
*
?
USB_EXTB TABLE_SPACING_RULE_ITEM
MCP_HDA_COMP
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1. USB_SD
B
SIO Signal Constraints
B
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
MCP_USB_RBIAS
MCP_USB_RBIAS
MCP_USB_RBIAS_GND
20
SMBUS_MCP_0_CLK
SMB_55S
SMB
SMBUS_MCP_0_CLK
13 21 39
SMBUS_MCP_0_DATA
SMB_55S
SMB
SMBUS_MCP_0_DATA
13 21 39
SMBUS_MCP_1_CLK
SMB_55S
SMB
SMBUS_MCP_1_CLK
21 39
SMBUS_MCP_1_DATA
SMB_55S
SMB
SMBUS_MCP_1_DATA
21 39
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.
HDA_BIT_CLK
HDA_55S
HDA
HDA_BIT_CLK
21 49
HDA_55S
HDA
HDA_BIT_CLK_R
21
SPI Interface Constraints
HDA_SYNC
HDA_55S
HDA
HDA_SYNC
HDA_55S
HDA
HDA_SYNC_R
21
HDA_55S
HDA
HDA_RST_R_L
21
HDA_55S
HDA
HDA_RST_L
21 49
HDA_55S
HDA
HDA_SDIN0
21 49
HDA_55S
HDA
HDA_SDIN_CODEC
HDA_55S
HDA
HDA_SDOUT
21 49
HDA_55S
HDA
HDA_SDOUT_R
21
CLK_SLOW_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
8 MIL
?
TABLE_SPACING_RULE_ITEM
CLK_SLOW
*
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
=55_OHM_SE
=55_OHM_SE
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP HDA_RST_L
21 49
TABLE_PHYSICAL_RULE_ITEM
SPI_55S
*
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD HDA_SDIN0
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT HDA_SDOUT TABLE_SPACING_RULE_ITEM
SPI
*
8 MIL
?
MCP_HDA_COMP
MCP_HDA_PULLDN_COMP
21
CLK_SLOW_55S
CLK_SLOW
PM_CLK32K_SUSCLK_R
21 25
CLK_SLOW_55S
CLK_SLOW
PM_CLK32K_SUSCLK
25 36
SPI_55S
SPI
SPI_CLK_R
21 38 48
SPI_55S
SPI
SPI_CLK
48
SPI_55S
SPI
SPI_ALT_CLK
38
SPI_55S
SPI
SPI_MOSI_R
21 38 48
SPI_55S
SPI
SPI_MOSI
48
SPI_55S
SPI
SPI_ALT_MOSI
38
SPI_55S
SPI
SPI_MISO
21 38 48
SPI_55S
SPI
SPI_MISO_R
48
SPI_55S
SPI
SPI_ALT_MISO
38
SPI_55S
SPI
SPI_CS0_R_L
21 38
SPI_55S
SPI
SPI_CS0_L
SPI_55S
SPI
SPI_CS1_R_L
SPI_55S
SPI
SPI_CS1_R_L_USE_MLB
MCP_HDA_PULLDN_COMP
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14. MCP_SUS_CLK
SPI_CLK
A
SPI_MOSI
SPI_MISO
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
MCP Constraints 2 DRAWING NUMBER
Apple Inc.
051-7982
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
REVISION
C.0.0
R SPI_CS0
A
PAGE TITLE
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MCP RGMII (Ethernet) Constraints TABLE_PHYSICAL_RULE_HEAD
NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MCP_MII_COMP
*
=STANDARD
7.5 MIL
7.5 MIL
=STANDARD
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP_VDD
18
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP_GND
18
MCP_CLK25M_BUF0
ENET_MII_55S
MCP_BUF0_CLK
MCP_CLK25M_BUF0_R
18 32
ENET_MII_55S
MCP_BUF0_CLK
RTL8211_CLK25M_CKXTAL1
31 32
ENET_MII_55S
ENET_MII
ENET_INTR_L
ENET_MDIO
ENET_MII_55S
ENET_MII
ENET_MDIO
18 31
ENET_MDC
ENET_MII_55S
ENET_MII
ENET_MDC
18 31
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII
ENET_CLK125M_RXCLK_R
31
ENET_MII_55S
ENET_MII
ENET_CLK125M_RXCLK
18 31
ENET_MII_55S
ENET_MII
ENET_RXD_R
31 18 31
TABLE_PHYSICAL_RULE_ITEM
ENET_MII_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
MCP_BUF0_CLK
*
=3:1_SPACING
?
ENET_MII
*
12 MIL
?
ENET_INTR_L TABLE_SPACING_RULE_ITEM
D
D
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
88E1116R (Ethernet PHY) Constraints
ENET_RXCLK TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ENET_MDI_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_RXD
ENET_RXD_STRAP
ENET_MII_55S
ENET_MII
ENET_RXD
18 31
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_RX_CTRL
18 31
ENET_MII_55S
ENET_MII
ENET_RXCTL_R
31
ENET_MII_55S
ENET_MII
ENET_CLK125M_TXCLK_R
31 18 31
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
25 MIL
?
TABLE_SPACING_RULE_ITEM
ENET_MDI
*
ENET_TXCLK
ENET_MII_55S
ENET_MII
ENET_CLK125M_TXCLK
ENET_TXD0
ENET_MII_55S
ENET_MII
ENET_TXD
18 31
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_TXD
18 31
ENET_MII_55S
ENET_MII
ENET_TX_CTRL
18 31
ENET_MII_55S
ENET_MII
ENET_RESET_L
18 31
ENET_MDI_100D
ENET_MDI
ENET_MDI_P
31 33
ENET_MDI_100D
ENET_MDI
ENET_MDI_N
31 33
ENET_MDI_100D
ENET_MDI
ENET_MDI_TRAN_P
33
ENET_MDI_100D
ENET_MDI
ENET_MDI_TRAN_N
33
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4 ENET_TXD
ENET_MDI
C
C
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
Ethernet Constraints DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
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C.0.0
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SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
NET_TYPE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
D
SMBUS_SMC_A_S3_SCL
SMB_55S
SMB
SMBUS_SMC_A_S3_SCL
7 39
SMBUS_SMC_A_S3_SDA
SMB_55S
SMB
SMBUS_SMC_A_S3_SDA
7 39 39
SMBUS_SMC_B_S0_SCL
SMB_55S
SMB
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMB_55S
SMB
SMBUS_SMC_B_S0_SDA
39
SMBUS_SMC_0_S0_SCL
SMB_55S
SMB
SMBUS_SMC_0_S0_SCL
39
SMBUS_SMC_0_S0_SDA
SMB_55S
SMB
SMBUS_SMC_0_S0_SDA
39
SMBUS_SMC_BSA_SCL
SMB_55S
SMB
SMBUS_SMC_BSA_SCL
7 39
SMBUS_SMC_BSA_SDA
SMB_55S
SMB
SMBUS_SMC_BSA_SDA
7 39
SMBUS_SMC_MGMT_SCL
SMB_55S
SMB
SMBUS_SMC_MGMT_SCL
39
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB
SMBUS_SMC_MGMT_SDA
39
D
SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET
PHYSICAL
CHGR_CSI
CHGR_CSO
SPACING
1TO1_DIFFPAIR
CHGR_CSI_P
1TO1_DIFFPAIR
CHGR_CSI_N
1TO1_DIFFPAIR
CHGR_CSO_P
1TO1_DIFFPAIR
CHGR_CSO_N
C
C
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=04/06/2009
A
PAGE TITLE
SMC Constraints DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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K84 SENSOR NET PROPERTIES TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
NET_TYPE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP PHYSICAL
ELECTRICAL_CONSTRAINT_SET
SPACING
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
D
DIFFPAIR
CHGR_CSO_R_P
56
DIFFPAIR
CHGR_CSO_R_N
56
DIFFPAIR
CPUTHMSNS_D2_P
42
DIFFPAIR
CPUTHMSNS_D2_N
42
DIFFPAIR
CPU_THERMD_P
10 42
DIFFPAIR
CPU_THERMD_N
10 42
DIFFPAIR
ISNS_CPUVTT_P
41
DIFFPAIR
ISNS_CPUVTT_N
41
DIFFPAIR
ISNS_HDD_P
34 47
DIFFPAIR
ISNS_HDD_N
34 47
DIFFPAIR
ISNS_HDD_R_P
47
DIFFPAIR
ISNS_HDD_R_N
47
DIFFPAIR
MCPTHMSNS_D2_P
42
DIFFPAIR
MCPTHMSNS_D2_N
42
DIFFPAIR
MCP_THMDIODE_P
21 42
DIFFPAIR
MCP_THMDIODE_N
21 42
DIFFPAIR
ISNS_ODD_P
34 47
DIFFPAIR
ISNS_ODD_N
34 47
DIFFPAIR
ISNS_ODD_R_P
47
DIFFPAIR
ISNS_ODD_R_N
47
DIFFPAIR
ISNS_AIRPORT_P
30 47
DIFFPAIR
ISNS_AIRPORT_N
30 47
DIFFPAIR
ISNS_AIRPORT_R_P
47
DIFFPAIR
ISNS_AIRPORT_R_N
47
DIFFPAIR
ISNS_1V5_S3_P
47 58
DIFFPAIR
ISNS_1V5_S3_N
47 58
DIFFPAIR
ISNS_1V5_S3_R_P
47
DIFFPAIR
ISNS_1V5_S3_R_N
47
DIFFPAIR
ISNS_LCDBKLT_P
47 68
DIFFPAIR
ISNS_LCDBKLT_N
47 68
D
C
C
B
B
A
SYNC_MASTER=K24_MLB
SYNC_DATE=01/19/2009
A
PAGE TITLE
K84 SPECIAL CONSTRAINTS DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
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K84 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS (MIL or MM)
ALLEGRO VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA_P1MM
MM
15.5.1
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.1 MM
?
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
*
*
BGA_P1MM
BGA_P1MM
TABLE_SPACING_RULE_ITEM
DEFAULT
*
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
STANDARD
*
=DEFAULT
?
DEFAULT
*
Y
=50_OHM_SE
0.100MM
30 MM
0 MM
0 MM
*
Y
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
MEM_CLK
*
BGA_P1MM
BGA_P1MM
*
=DEFAULT
?
BGA_P2MM
*
=DEFAULT
?
CLK_FSB
*
BGA_P1MM
BGA_P2MM
CLK_LPC
*
BGA_P1MM
BGA_P2MM
BGA_P3MM
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
=DEFAULT
*
?
TOP,BOTTOM
Y
STANDARD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
CLK_PCI
*
BGA_P1MM
BGA_P2MM
CLK_PCIE
*
BGA_P1MM
BGA_P2MM
CLK_SLOW
*
BGA_P1MM
BGA_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
DIFFPAIR NECK GAP
D
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
BGA_P1MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
MEM_40S_VDD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
LAYER
STANDARD
BGA_P2MM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
BGA_P1MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
D
AREA_TYPE
MEM_40S
DIFFPAIR NECK GAP
STANDARD
ALLOW ROUTE ON LAYER?
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM
0.090 MM
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.090 MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
1.5:1_SPACING
*
0.15 MM
?
2:1_SPACING
*
0.2 MM
?
TABLE_SPACING_ASSIGNMENT_ITEM
FSB_DSTB
=STANDARD
FSB_DSTB
BGA_P1MM
BGA_P3MM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
50_OHM_SE
TOP,BOTTOM
Y
0.115 MM
0.115 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAP
2.5:1_SPACING
*
0.25 MM
?
3:1_SPACING
*
0.3 MM
?
4:1_SPACING
*
0.4 MM
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
50_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
TOP,BOTTOM
Y
0.165 MM
0.100 MM
40_OHM_SE
*
Y
0.126 MM
0.100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
2X_DIELECTRIC
TOP,BOTTOM
0.140 MM
?
3X_DIELECTRIC
TOP,BOTTOM
0.210 MM
?
4X_DIELECTRIC
TOP,BOTTOM
0.280 MM
?
5X_DIELECTRIC
TOP,BOTTOM
0.350 MM
?
2X_DIELECTRIC
*
0.126 MM
?
3X_DIELECTRIC
*
0.189 MM
?
4X_DIELECTRIC
*
0.252 MM
?
5X_DIELECTRIC
*
0.315 MM
?
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
0.310 MM
27P4_OHM_SE
*
Y
0.222 MM
0.222 MM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
TABLE_SPACING_RULE_ITEM
=STANDARD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
70_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
70_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.151 MM
0.100 MM
=STANDARD
0.224 MM
=STANDARD
0.224 MM
70_OHM_DIFF
TOP,BOTTOM
Y
0.185 MM
0.100 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
90_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.095 MM
0.095 MM
0.234 MM
0.234 MM
90_OHM_DIFF
TOP,BOTTOM
Y
0.112 MM
0.112 MM
0.220 MM
0.220 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.075 MM
0.075 MM
0.244 MM
0.244 MM
100_OHM_DIFF
TOP,BOTTOM
Y
0.091 MM
0.091 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_OHM_DIFF_HDD
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF_HDD
ISL3,ISL4,ISL9,ISL10
Y
0.083 MM
0.083 MM
0.400 MM
0.400 MM
100_OHM_DIFF_HDD
TOP,BOTTOM
Y
0.095 MM
0.095 MM
0.400 MM
0.400 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
110_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.075 MM
0.075 MM
0.330 MM
0.330 MM
TABLE_PHYSICAL_RULE_ITEM
C
C
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
B
B
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
110_OHM_DIFF
TOP,BOTTOM
Y
0.077 MM
0.077 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
1:1_DIFFPAIR
*
Y
=STANDARD
=STANDARD
0.330 MM
0.330 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
0.1 MM
0.1 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
A
SYNC_MASTER=K24_MLB
SYNC_DATE=01/19/2009
A
PAGE TITLE
K84 RULE DEFINITIONS DRAWING NUMBER
Apple Inc.
051-7982
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
D
REVISION
C.0.0
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
BRANCH
PAGE
109 OF 109 SHEET
OF
8
7
6
5
4
3
2
1
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