Acer Aspire 4310 - WISTRON VOLVI
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A
C
D
Volvi Block Diagram Yonah 478 Celeron M
ICS 9LPRS502 (RTM875T-605) 3 71.09502.00W
62.10079.001
HOST BUS 533/667MHz
533/667 MHz
5V_S5 DCBATOUT
4
20
SYSTEM DC/DC MAX8717 37
PCB STACKUP
TV Out
4, 5
400/533/[email protected]
TOP
14
INPUTS DCBATOUT
1D05V_S0
S
LCD
TPS51100
S
13
1D8V_S3
GND BOTTOM
APL5312
LVDS, CRT I/F
533/667MHz
71.CALIS.00U
13,14
VGA Borad
6,7,8,9,10
X4 DMI 400MHz
2D5V_S0
26
C-Link0
APL5912 1D8V_S3
Codec
AZALIA
ICH7M
ALC268 28
PCI/PCI BRIDGE
14
OZ129 1394 CardReader
PCI BUS
ACPI 2.0 2 SATA
1394 CONN
INPUTS 25
BT+
MS/MS Pro/xD/ MMC/SD
24
5 in 1
DCBATOUT
INT.SPKR
5V
High Definition Audio
Giga LAN
LPC I/F
BCM5787MKMLG
22
TXFM
MAX8770
23
INPUTS
OP AMP G1412
PCIex1
Kedron a/b/g/n
MODEM MDC Card
71.ICH7M.00U
15,16,17,18
HDD 20
USB
PATA
PCI Express
SATA
21
28
100mA
2
VCC_CORE 0~1.3V 48A
LPC BUS
MINI USB BlueTooth
KBC
20
SPI I/F
Winbond 22
WPC8768L
MEDIA BD
CDROM
DCBATOUT
27
35
OUTPUTS
Mini Card
29
P2231NFC1
4.0A
CPU DC/DC
RJ45
23
Serial Peripheral I/F
1
18V
UP+5V
25
ETHERNET (10/100/1000MbE)
G1431Q 29
New card27
40
OUTPUTS
8 USB 2.0/1.1 ports
Line Out (No-SPDIF)
31
Touch Pad 31
32
30
INT. KB 31
BIOS W25X80-VSS
LPC
DEBUG CONN. 32 UMA
1
CIR 31
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
USB 4 Port21
Title
BLOCK DIAGRAM
CAMERA
Size A3
13
Document Number
Date: Wednesday, April 18, 2007
A
3
1D5V_S0
MAX8731
Cardreader
1 PATA 66/100
OP AMP
38
Intersil CHARGER
4 PCIe ports
MIC In
39
3D3V_S0
Line In
RJ11
39
DDR_VREF
DDR Memory I/F
533/667 MHz
31
OUTPUTS 1D8V_S3
VCC
CRT
INTEGRATED GRAHPICS
DDR2 3
OUTPUTS
G792
Calistoga AGTL+ CPU I/F
13,14
36
MAX8744 INPUTS
3V_S5
14
DDR2
E
SYSTEM DC/DC
Project code: 91.4U701.001 PCB P/N : 07200 REVISION : -1
Mobile CPU
CLK GEN.
4
2
B
B
C
D
Rev
-1
Volvi Sheet
E
1
of
43
4
3
A
B
ICH7M Functional Strap Definitions ICH8-M EDS 21762 Usage/When Sampled
Signal HDA_SDOUT
2.0V1
C page 16
Comment
PCIE config1 bit0, Rising Edge of PWROK.
This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h)
GNT2#
PCIE config2 bit0, Rising Edge of PWROK.
GPIO20
Reserved
This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high.
GNT1#/ GPIO51
GNT3#
GNT0#/ SPI_CS1#
INTVRMEN
ESI Strap (Server Only) ESI compatible mode is for server platforms only. This signal should not be pulled low for desttop Rising Edge of PWROK and mobile. Top-Block Swap Override. Rising Edge of PWROK.
Boot BIOS Destination Selection. Rising Edge of PWROK. Integrated VccSus1_05, VccSus1_5 and VccCL1_5 VRM Enable/Disable. Always sampled.
Integrated VccLAN1_05 LAN100_SLP and VccCL1_05 VRM Enable/Disable. Always sampled.
Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. Enables integrated VccSus1_05, VccSus1_5 and VccCL1_5 VRM's when sampled high
Enables integrated VccLAN1_05 and VccCL1_05 VRM's when sampled high
PCI Express Lane Reversal. Rising Edge of PWROK. No Reboot. Rising Edge of PWROK.
Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8)
TP3
XOR Chain Entrance. Rising Edge of PWROK.
This signal should not be pull low unless using XOR Chain testing.
GPIO33/ HDA_DOCK _EN#
This signal has a weak internal pull-up. Flash Descriptor Security Override Strap Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be Rising Edge of PWROK in effect.This should only be used in manufacturing environments.
SATALED# SPKR
ICH7M Integrated Pull-up and Pull-down Resistors
Allows entrance to XOR Chain testing when TP3 XOR Chain Entrance/ PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: Rising Edge of PWROK offset 224h)
HDA_SYNC
D
If sampled high, the system is strapped to the "No Reboot" mode(ICH8 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.
ICH8-M EDS 21762
SIGNAL
E
Crestline Strapping Signals and Crestline EDS 20954 Configuration page 7 2.0V1
Resistor Type/Value
Pin Name
Strap Description
CFG[2:0]
FSB Frequency Select
HDA_BIT_CLK
PULL-DOWN 20K
HDA_RST#
NONE
HDA_SDIN[3:0]
PULL-DOWN 20K
CFG[4:3]
Reserved
HDA_SDOUT
PULL-DOWN 20K
CFG5
DMI x2 Select
HDA_SYNC
PULL-DOWN 20K
CFG[8:6]
Reserved
GNT[3:0]
PULL-UP 20K
GPIO[20]
PULL-DOWN 20K
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
LAN_RXD[2:0]
PULL-UP 10K
LDRQ[0]
PULL-UP 20K
LDRQ[1]/GPIO23
PULL-UP 20K
PME#
PULL-UP 20K
PWRBTN#
PULL-UP 20K
SATALED#
PULL-UP 15K
SPI_CS1#
PULL-UP 20K
SPI_CLK
PULL-UP 20K
SPI_MOSI
PULL-UP 20K
SPI_MISO
PULL-UP 20K
TACH_[3:0]
PULL-UP 20K
SPKR
PULL-DOWN 20K
TP[3]
PULL-UP 20K
USB[9:0][P,N]
PULL-DOWN 15K
CL_RST#
PULL-UP 13K
1.0
Configuration 001 = FSB533 011 = FSB667 010 = FSB800 others = Reserved
4
0 = DMI x2 1 = DMI x4 (Default)
Low Power PCI Express
0 = Normal mode 1 = Low Power mode
CFG9
PCI Express Graphics Lane Reversal
0 = Reverse Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane Numbered in order
CFG[11:10]
Reserved
CFG[13:12]
XOR/ALL Z test straps
CFG[15:14]
Reserved
CFG16
FSB Dynamic ODT
00 01 10 11
= = = =
(Default)
Reserved XOR mode enabled All Z mode enabled Normal Operation (Default)
Reserved 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default)
CFG[18:17]
Reserved
CFG19
DMI Lane Reversal
3
0 = Normal operation (Default):lane Numbered in order 1 =Reverse Lane,4->0,3->1 ect...
CFG20
SDVO/PCIE Concurrent
0 = Only SDVO or PCIE x1 is operational (Default) 1 =SDVO and PCIE x1 are operating simultaneously via the PEG port
SDVOCRTL _DATA
SDVO Present
0 = No SDVO Card present (Default) 1= SDVO Card present
NOTE: All strap signals are sampled with respect to the leading edge of the Crestline GMCH PWORK in signal.
History
2
2
ICH7M IDE Integrated Series Termination Resistors DD[15:0], DIOW#, DIOR#, DREQ, approximately 33 ohm DDACK#,
IORDY, DA[2:0], DCS1#,
DCS3#, IDEIRQ
PCIE Routing
USB Table
LAN BCM5787M
USB ports definition
LANE2
MiniCard WLAN
Pair
LANE3
NewCard WLAN
LANE1
1
Device
0
USB1
1
USB3
2
USB2
3
USB4
4
PCI Routing IDSEL OZ129 AD22
page 16
INT
REQ
GNT
INT_PIRQG#
PCI_REQ#0
PCI_GNT#0
1
UMA
Wistron Corporation
MINICARD
5
BlueTooth
6
CCD
7
NewCard
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Reference Size A3
Document Number
Date: Wednesday, April 18, 2007
A
B
C
D
Rev
-1
Volvi Sheet
E
2
of
42
B
2
1
1
1
1 2
2
2
1
1 2
1 2
1 2
1 2
H/L: 100/96MHz 1
PCLK_KBC
2 R328
1 33R2J-2-GP
PCLKKBC
PCLK_PCM
2 R331
1 33R2J-2-GP
PCLKPCM
56 3 4 5
1 33R2J-2-GP
SS_SEL PCLKICH
9 8
2
24
-1 0411 Del R321 2 R329
CLK_ICHPCI
PCI_2/REQ_SEL PCI_3 PCI_4 PCI_5 PCIF_1/DOT96SS_SEL# PCIF_0/ITP_EN
1
16
2
R327 10KR2J-3-GP
CL=20pF±0.2pF C188 SC27P50V2JN-2-GP 1 2
7 7
X2
46 47
SCLK SDATA
DREFCLK_1 DREFCLK#_1
14 15
DOT96 DOT96#
GEN_XTAL_IN GEN_XTAL_OUT
50 49
X1 X2
0R0402-PAD
52 39
REF_0 IREF
10
VTT_POWER_GOOD#/PWRDWN
1 R119
2
PCI_STOP#
X-14D31818M-44GP 2
PCLK_PCM
2
11,18 SMBC_ICH 11,18 SMBD_ICH
RN31 SRN33J-5-GP-U 3 UMA 2 4 1
DREFCLK DREFCLK#
82.30005.951 1
16 PM_STPPCI#
55
-1 0413
1
SB 0313 for EMI
16
CLK_ICH14
GEN_XTAL_OUT_R
C189 SC27P50V2JN-2-GP
35
CLK_EN#
GEN_REF 2 R320 1 22R2J-2-GP GEN_IREF 2 R311 1 475R2F-L1-GP R319 2 1 0R2J-2-GP
3D3V_S0
DY
1
2
2
R323 10KR2J-3-GP EC129 SC22P50V2JN-4GP
1
RN27 SRN33J-5-GP-U 3 4
CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7
CLK_PCIE_ICH_1 2 CLK_PCIE_ICH_1# 1
RN25 SRN33J-5-GP-U 3 4
CLK_PCIE_ICH 16 CLK_PCIE_ICH# 16
CLK_PCIE_NEW_R 2 CLK_PCIE_NEW#_R 1
RN23 SRN33J-5-GP-U 3 4
CLK_PCIE_NEW 27 CLK_PCIE_NEW# 27
CLK_PCIE_SATA_1 2 CLK_PCIE_SATA_1#1
RN21 SRN33J-5-GP-U 3 4
CLK_PCIE_SATA 15 CLK_PCIE_SATA# 15
4
RN22
SRN33J-5-GP-U 4 CLK_PCIE_LAN 22 3 CLK_PCIE_LAN# 22
RN24
SRN33J-5-GP-U 4 CLK_PCIE_MINI1 27 3 CLK_PCIE_MINI1# 27
RN26
SRN33J-5-GP-U 4 CLK_PCIE_PEG 26 3 CLK_PCIE_PEG# 26
U10 30
SS_SEL
2
CLK_MCH_3GPLL_1 2 CLK_MCH_3GPLL_1# 1
CLK_PCIE_LAN_R 1 CLK_PCIE_LAN#_R 2
R325 10KR2J-3-GP
DY
DREFSSCLK 7 DREFSSCLK# 7
C412
3D3V_S0
3
RN29 SRN33J-5-GP-U UMA 3 4
C396 SCD1U16V2ZY-2GP
1
C425 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
C408
2 1
DREFSSCLK_1 DREFSSCLK#_1
SCD1U16V2ZY-2GP
SC4D7U6D3V3KX-GP
C392 SC1U16V3ZY-GP
C393
C399 SCD1U16V2ZY-2GP
3D3V_S0 R291 0R0603-PAD 1 2
C430 SCD1U16V2ZY-2GP
-1 0412
3D3V_CLKPLL_S0
DY
C416 SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
4
E
3D3V_S0 R297 0R0603-PAD 1 2
3D3V_CLKGEN_S0
C422 SC1U16V3ZY-GP
C426
D
2
3D3V_S0 R318 0R3-0-U-GP 2 1
3D3V_48MPWR_S0
DY
C
-1 0412
1
-1 0413
2
A
RN58 SRN49D9F-GP 4 3
DREFSSCLK# DREFSSCLK
1 2
DREFCLK# DREFCLK
RN60 SRN49D9F-GP 1 4 2 3
CLK_CPU_BCLK# CLK_CPU_BCLK
RN59 SRN49D9F-GP 1 4 2 3
CLK_MCH_BCLK CLK_MCH_BCLK#
1 2
RN57 SRN49D9F-GP 4 3
CLK_PCIE_SATA CLK_PCIE_SATA#
2 1
RN49 SRN49D9F-GP 3 4
CLK_MCH_3GPLL 2 CLK_MCH_3GPLL# 1
RN56 SRN49D9F-GP 3 4
CLK_PCIE_ICH CLK_PCIE_ICH#
2 1
RN54 SRN49D9F-GP 3 4
CLK_PCIE_MINI1 CLK_PCIE_MINI1#
RN53 SRN49D9F-GP 1 4 2 3
2 6 51 45 38 13 29
GND_PCI GND_PCI GND_REF GND_CPU GND_CORE GND_48 GND_SRC
SRC_0/DOT96SS SRC_0#/DOT96SS#
17 18
DREFSSCLK_1 DREFSSCLK#_1
SRC_1 SRC_1# SRC_2 SRC_2# SRC_3 SRC_3# SRC_4_SATA SRC_4_SATA# SRC_5 SRC_5# SRC_6/PCIE_REQ_1# SRC_6#/PCIE_REQ_2#
19 20 22 23 24 25 26 27 31 30 33 32
CLK_MCH_3GPLL_1 CLK_MCH_3GPLL_1# CLK_PCIE_ICH_1 CLK_PCIE_ICH_1# CLK_PCIE_NEW_R CLK_PCIE_NEW#_R CLK_PCIE_SATA_1 CLK_PCIE_SATA_1# CLK_PCIE_LAN_R CLK_PCIE_LAN#_R CLK_PCIE_MINI_1 CLK_PCIE_MINI_1#
CPU_2_ITP/SRC_7 CPU_2_ITP#/SRC_7#
36 35
CLK_PCIE_PEG_1 CLK_PCIE_PEG_1#
CPU_0 CPU_0# CPU_1 CPU1_#
44 43 41 40
CLK_CPU_BCLK_1 CLK_CPU_BCLK_1# CLK_MCH_BCLK_1 CLK_MCH_BCLK_1#
CPU_STOP# FSC/TEST_SEL/REF_1 FSB/TEST_MODE USB48MHZ/FSA
54 53 16 12
VDD_3.3_SRC VDD_3.3_SRC
34 21
VDD_3.3_PCI VDD_3.3_PCI
7 1
VDD_3.3_REF VDD_3.3_CPU VDD_3.3_CORE VDD_3.3_48M VDD_3.3_SRC
48 42 37 11 28
CLK_PCIE_MINI_1 1 CLK_PCIE_MINI_1# 2
CLK_PCIE_PEG_1 1 CLK_PCIE_PEG_1# 2
MXM RN30
SRN33J-5-GP-U 4 CLK_CPU_BCLK 4 3 CLK_CPU_BCLK# 4
RN28
SRN33J-5-GP-U 4 CLK_MCH_BCLK 6 3 CLK_MCH_BCLK# 6
CLK_CPU_BCLK_1 1 CLK_CPU_BCLK_1# 2
CLK_MCH_BCLK_1 1 CLK_MCH_BCLK_1# 2
3
PM_STPCPU# 16
CPU_SEL2_R CPU_SEL1_R CLK48
2 R324 1 2K2R2J-2-GP 2 R314 1 2K2R2J-2-GP 2 R317 1 22R2J-2-GP 2 R316 1 2K2R2J-2-GP
CPU_SEL2 4,7 CPU_SEL1 4,7 CLK48_ICH 16 2
CPU_SEL0 4,7
3D3V_CLKPLL_S0 3D3V_48MPWR_S0 3D3V_CLKGEN_S0
RTM865T-433-GP CLK_PCIE_NEW CLK_PCIE_NEW#
RN52 SRN49D9F-GP 2 3 1 4
71.00865.B0W
RN51 SRN49D9F-GP CLK_PCIE_LAN# 2 3 CLK_PCIE_LAN 1 4
FSC
FSB
FSA
CPU
FSB
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
266M 133M 200M 166M 333M 100M 400M Reserved
X 533M X 667M X X X X
EMI 1
CLK_ICH14
EC19 1
DY 2 SC10P50V2JN-4GP
SB 0313 for EMI PCLK_KBC
EC86 1
2 SC22P50V2JN-4GP
CLK_ICHPCI
EC21 1
DY 2 SC10P50V2JN-4GP
CLK48_ICH
EC15 1
DY 2 SC10P50V2JN-4GP
CLK_PCIE_PEG CLK_PCIE_PEG#
RN55 SRN49D9F-GP 1 4 2 MXM 3
UMA
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Clock Generator Size
Document Number
Rev
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
-1 Sheet E
3
of
42
A
B
C
D
E
H_DINV#[3..0] TP5
TPAD30
U39A
D21 A24 A25
THERMTRIP#
H_TRDY# 6
1D05V_S0 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#
TP23 TP18 TP22 TP21 TP19 TP6
A22 A21
RSVD[12]
T22
RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17] RSVD[18] RSVD[19] RSVD[20]
D2 F6 D3 C1 AF1 D22 C23 C24
TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30
CPU_PROCHOT#_R H_THERMDA 19 H_THERMDC 19
C7
BCLK[0] BCLK[1]
6 6
6 6 6
R280 56R2J-4-GP
H_THERMDC
C362 SC2200P50V2KX-2GP
1D05V_S0
R330 1KR2J-1-GP
6 6 6
R332 2KR2F-3-GP
2nd source: 62.10053.401
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#
N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26
D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
AD26
GTLREF
C173
DY
2
62.10079.001
H_DSTBN#1 H_DSTBP#1 H_DINV#1
CPU_GTLREF0 SC1KP50V2KX-1GP
RSVD[11]
PM_THRMTRIP# should connect to ICH7 and Calistoga without T-ing ( No stub)
BGA479-SKT6-GPU3
2
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
H_THERMDA
PM_THRMTRIP-A# 7,33
CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3
H_DSTBN#0 H_DSTBP#0 H_DINV#0
E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 H23 G22 J26
Layout Note: 0.5" max length.
TEST1 C26 1KR2J-1-GP TEST2 D25 51R2F-2-GP
1 R61 1 R270
DY
3,7 3,7 3,7
CPU_SEL0 CPU_SEL1 CPU_SEL2
2 2
B22 B23 C21
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]#
AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#
AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
DATA GRP 2
PROCHOT# THERMDA THERMDC
XDP/ITP SIGNALS
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
U39B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
6
DATA GRP 3
CONTROL
G6 E4
THERM
ADDR GROUP 1
B25
HIT# HITM#
Place testpoint on H_IERR# with a GND 0.1" away
1
RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]
B1 F3 F4 G3 G2
H_INIT# 15
2
AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3
RESET# RS[0]# RS[1]# RS[2]# TRDY#
H_LOCK# 6 H_CPURST# 6,31 H_RS#[2..0]
1
STPCLK# LINT0 LINT1 SMI#
H4
2
D5 C6 B4 A3
LOCK#
BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
4
2
15 H_STPCLK# 15 H_INTR 15 H_NMI 15 H_SMI#
H_IERR#
H_HIT# H_HITM#
6
R80 56R2J-4-GP
1
A20M# FERR# IGNNE#
IERR# INIT#
D20 B3
H_RS#0 H_RS#1 H_RS#2
H_D#[63..0]
1D05V_S0
1
15 H_A20M# 15 H_FERR# 15 H_IGNNE#
A6 A5 C4
3
A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]#
H_BREQ#0 6
6
1
6 H_ADSTB#1
Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4
F1
6
H_DSTBP#[3..0]
2
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
H_DEFER# 6 H_DRDY# 6 H_DBSY# 6
2
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#
H5 F21 E1
6 6 6
1
K3 H2 K2 J3 L5
H_ADSTB#0 H_REQ#[4..0]
BR0#
H CLK
6 6
DEFER# DRDY# DBSY#
H_ADS# H_BNR# H_BPRI#
DATA GRP 1
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
4
ADS# BNR# BPRI#
H1 E2 G5
DATA GRP 0
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
H_A#[31..3]
ADDR GROUP 0
J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2
RESERVED
6
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
6
H_DSTBN#[3..0]
MISC
TEST1 TEST2 BSEL[0] BSEL[1] BSEL[2]
COMP[0] COMP[1] COMP[2] COMP[3]
R26 U26 U1 V1
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
E5 B5 D24 D6 D7 AE6
H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 3
H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3
R287 R309 R96 R102
1 1 1 1
2 2 2 2
27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP
H_DPRSTP# 15,35 H_DPSLP# 15 H_DPWR# 6 H_PWRGD 15,31,33 H_CPUSLP# 6,15 PSI# 35
2
BGA479-SKT6-GPU3 Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .
62.10079.001
2nd source: 62.10053.401 1D05V_S0
R111 1
DY
2 39D2R3F-2-GP
XDP_TDO
R110 1
DY
2 54D9R2F-L1-GP
H_CPURST#
R54
1
XDP_DBRESET# R64
1
2 54D9R2F-L1-GP 3D3V_S0
1
DY
2 150R2F-1-GP
XDP_TCK
R112 1
2 27D4R2F-L1-GP
XDP_TRST#
R113 1
2 680R3F-GP
H_INIT# 1
XDP_TMS
2 150R2F-1-GP
DY 2
R107 1
C66 SC4700P50V2KX
XDP_TDI
UMA
1
All place within 2" to CPU
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (1 of 2) Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
4
of
42
A
B
C
D
E
U39D A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VCC_CORE_S0
VCC_CORE_S0 U39C
SCD1U10V2KX-4GP
1D5V_VCCA_S0
1D5V_S0
2
2
1 2
1
C127
2
1
C126
2
1 2
1 2
1 2
1 2
1
C96
SC4D7U6D3V3KX-GP
VCC_CORE_S0
1 2
1
C54 SC10U10V5ZY-1GP
2
1
C169 SC10U10V5ZY-1GP
2
1
C167 SC10U10V5ZY-1GP
2
1
C164 SCD1U10V2KX-4GP
2
C85 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.
C165
DY
2
C84
2
VCCSENSE and VSSSENSE lines should be of equal length.
2
R118 100R2F-L1-GP-U
1
Layout Note:
1
62.10079.001
C162
SC4D7U6D3V3KX-GP
VSS_SENSE 35
C142
SCD1U10V2KX-4GP
AE7
C154
SCD1U10V2KX-4GP
VSSSENSE
C104
SCD1U10V2KX-4GP
VCC_SENSE 35
C99
68.00230.041
SCD1U10V2KX-4GP
AF7
35 VCC_CORE_S0 35 35 35 35 R117 35 100R2F-L1-GP-U 35
SCD1U10V2KX-4GP
VCCSENSE
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
SCD1U10V2KX-4GP
AD6 AF5 AE5 AF4 AE3 AF2 AE2
2 HCB1608KF121T30-GP
C370
2
C372
1
1 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
BGA479-SKT6-GPU3
1D05V_S0
L19
2
B26
1 R95 2 0R0402-PAD C161
1
VCCA
1D05V_CPU_V6
1
V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
1
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
Layout Note 1D05V_S0
SC4D7U6D3V3KX-GP
2
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
1
3
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
2
4
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
SCD01U16V2KX-3GP
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24
4
3
2
BGA479-SKT6-GPU3
62.10079.001
1
C129
DY 2
1
DY 2
1 2
1
C177
C170 SC10U10V5ZY-1GP
DY
SC10U10V5ZY-1GP
2
1
C151
SC10U10V5ZY-1GP
DY
SC10U10V5ZY-1GP
2
1
C183 SC10U10V5ZY-1GP
2
1
C108 SC10U10V5ZY-1GP
2
1
C184 SC10U10V5ZY-1GP
2
1
C128 SC10U10V5ZY-1GP
2
1
C182 SC10U10V5ZY-1GP
2
1
C152 SC10U10V5ZY-1GP
2
1
C168 SC10U10V5ZY-1GP
2
1
C109 SC10U10V5ZY-1GP
2
1
C53 SC10U10V5ZY-1GP
2
C73 SC10U10V5ZY-1GP
1
C72 SC10U10V5ZY-1GP
2
1
VCC_CORE_S0
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (2 of 2) Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
5
of
42
A
B
C
D
E
1
H_XRCOMP
R272 24D9R2F-L-GP
2
2
3
C355 SCD1U16V2ZY-2GP
1
1
H_XSWING R248 100R2F-L1-GP-U
1
H_YRCOMP
2
R281 24D9R2F-L-GP
2
1D05V_S0
R275 54D9R2F-L1-GP 1
2
H_YSCOMP
1
1D05V_S0
H_XRCOMP H_XSCOMP H_XSWING
H_YRCOMP H_YSCOMP H_YSWING
Y1 U1 W1
H_YRCOMP H_YSCOMP H_YSWING
3 CLK_MCH_BCLK 3 CLK_MCH_BCLK#
AG2 AG1
H_CLKIN H_CLKIN#
1
2
2
C374
CALISTOGA
SCD1U16V2ZY-2GP
R279 100R2F-L1-GP-U
1
E1 E2 E4
H_YSWING
1
2
R277 221R2F-2-GP
H_XRCOMP H_XSCOMP H_XSWING
71.CALIS.00U
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF_0 H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# H_VREF_1
E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13
1D05V_S0
H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4
R70 100R2F-L1-GP-U H_VREF
3
H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_CPURST# 4,31 H_DBSY# 4 H_DEFER# 4 H_DPWR# 4 H_DRDY# 4
J7 W8 U3 AB10
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
K4 T7 Y5 AC4
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
K3 T6 AA5 AC5
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_HIT# H_HITM# H_LOCK#
D3 D4 B3
H_HIT# 4 H_HITM# 4 H_LOCK# 4
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
D8 G8 B8 F8 A8
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#_0 H_RS#_1 H_RS#_2
B4 E6 D6
H_RS#0 H_RS#1 H_RS#2
H_SLPCPU# H_TRDY#
E3 E7
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
4
1
2
R263 221R2F-2-GP
4
2
1
1D05V_S0
H_A#[31..3]
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
H_DINV#[3..0]
4
H_DSTBN#[3..0]
4
H_DSTBP#[3..0]
4
C74
1
H_XSCOMP
H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14
R65 200R2F-L-GP 2
1
R59 54D9R2F-L1-GP
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31
2
2
1D05V_S0
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
1
4
F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8
SCD1U16V2ZY-2GP
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
HOST
U38A
H_D#[63..0]
2
4
2
H_REQ#[4..0]
H_RS#[2..0]
4
4
H_CPUSLP# 4,15 H_TRDY# 4
DIS :PM945 KI.94501.006 UMA :GM945 KI.94501.005
Place them near to the chip ( < 0.5")
UMA
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Document Number
GMCH (1 of 5)
Date: Wednesday, April 18, 2007 A
B
C
D
Volvi
Rev
-1 Sheet E
6
of
42
A
B
C
D
E
U38B
AU20 AT20 BA29 AY29
SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3
11,12 11,12 11,12 11,12
M_CS0# M_CS1# M_CS2# M_CS3#
AW13 AW12 AY21 AW21
SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3
BA13 BA12 AY20 AU21
SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3
1
SM_OCDCOMP_0 SM_OCDCOMP_1
DY
2
2
R106 R92 40D2R2F-GP 40D2R2F-GP
DY
11,12 11,12 11,12 11,12
M_RCOMPN M_RCOMPP
1 2
C419 3 CLK_MCH_3GPLL# 3 CLK_MCH_3GPLL 3 DREFCLK# 3 DREFCLK 3 DREFSSCLK# 3 DREFSSCLK
AV9 AT9
SM_RCOMP# SM_RCOMP
AK1 AK41
SM_VREF_0 SM_VREF_1
AF33 AG33 A27 A26 C40 D41
G_CLKIN# G_CLKIN D_REFCLKIN# D_REFCLKIN D_REFSSCLKIN# D_REFSSCLKIN
3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
16 16 16 16
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
AE37 AF41 AG37 AH41
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
16 16 16 16
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
AC37 AE41 AF37 AG41
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
SDVO_CTRLCLK SDVO_CTRLDATA LT_RESET# NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18
DMI
AC35 AE39 AF35 AG39
PM_EXTTS#0 PM_EXTTS#1 CALISTOGA
1D8V_S3
13 GMCH_LCDVDD_ON
1 2
CPU_SEL0 3,4 CPU_SEL1 3,4 CPU_SEL2 3,4
UMA
-1 0411 CFG9
4 3 13 13 13 13
RN15 SRN0J-6-GP
GMCH_TXACLKGMCH_TXACLK+ GMCH_TXBCLKGMCH_TXBCLK+
13 GMCH_TXAOUT013 GMCH_TXAOUT113 GMCH_TXAOUT2-
R504 1 2 0R0402-PAD
-1 0411
LA_CLK# LA_CLK LB_CLK# LB_CLK
C37 B35 A37
LA_DATA#_0 LA_DATA#_1 LA_DATA#_2
B37 B34 A36
LA_DATA_0 LA_DATA_1 LA_DATA_2
13 GMCH_TXBOUT013 GMCH_TXBOUT113 GMCH_TXBOUT2-
G30 D30 F29
LB_DATA#_0 LB_DATA#_1 LB_DATA#_2
F30 D29 F28
LB_DATA_0 LB_DATA_1 LB_DATA_2
G28 PM_BMBUSY# 16 F25 PM_EXTTS#0 13 GMCH_TXBOUT0+ R305 0R2J-2-GP H26 PM_EXTTS#1 13 GMCH_TXBOUT1+ G6 PM_THRMTRIP-A# 4,33 13 GMCH_TXBOUT2+ 1 2 AH33 PWROK_GD DY VGATE_PWRGD 16,35 R298 0R0402-PAD AH34 RSTIN# 1 2 PWROK 16,19 R93 1 2 PLT_RST1# 16,26,30 TP8 TPAD30 100R2J-2-GP H28 CTRLCLK 14 TV_DACA TP7 TPAD30 C157 H27 CTRLDATA 14 TV_DACB K28 DY MCH_ICH_SYNC# 16 14 TV_DACC D1 C41 C1 BA41 BA40 BA39 BA3 BA2 BA1 B41 B2 AY41 AY1 AW41 AW1 A40 A4 A39 A3
A33 A32 E27 E26
13 GMCH_TXAOUT0+ 13 GMCH_TXAOUT1+ 13 GMCH_TXAOUT2+
A16 C18 A19
SC100P50V2JN-3GP
R69 1 1 4K99R2F-L-GP UMA 1 R43 0R2J-2-GP UMA 1 R45 0R2J-2-GP UMA R44 0R2J-2-GP UMA
2 2 2 2
TV_IREF J20 TV_IRTNA B16 TV_IRTNB B18 TV_IRTNC B19
TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC
3D3V_S0
E23 D23 C22 B22 A21 GMCH_RGB# B21
14 GMCH_BLUE 14 GMCH_GREEN RN10 SRN10KJ-5-GP
14 GMCH_RED 2 1D05V_S0
1
MXM
R262 0R2J-2-GP
14 GMCH_DDCCLK 14 GMCH_DDCDATA 14 GMCH_HSYNC
CRT_IREF
14 GMCH_VSYNC
71.CALIS.00U
C26 C25 G23 J22 H23
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC
1
2
LIBG L_LVBG
TPAD30 TP3
L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL
VGA
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
13 CLK_DDC_EDID 13 DAT_DDC_EDID
D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32
TV
16 16 16 16
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
NC
RN11 SRN10KJ-5-GP 1 4 2 3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
MISC
3D3V_S0
16 16 16 16
AE35 AF39 AG35 AH39
PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 PM_THRMTRIP# PWROK RSTIN#
PM
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
1
DDR_VREF_S3
C415
M_ODT0 M_ODT1 M_ODT2 M_ODT3
CFG
AL20 AF10
LCTLA_CLK LCTLB_DATA
LVDS
1
M_OCDCOMP0 M_OCDCOMP1
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26
L_BKLTCTL GMCH_BL_ON
GRAPHICS
M_CKE0 M_CKE1 M_CKE2 M_CKE3
13 30
R77
PCI-EXPRESS
11,12 11,12 11,12 11,12
1D05V_S0 U38C L_BKLTCTL
1
SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3
2
AW35 AT1 AY7 AY40
for calistoga configuration
3 4
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
H32 T32 R32 F3 F7 AG11 AF11 H7 J19 K30 J29 A41 A35 A34 D28 D27
2 1
11 11 11 11
RSVD_0 RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15
MUXING
SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3
DDR
AY35 AR1 AW7 AW40
CLK
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
RSVD
4
11 11 11 11
2
R114 80D6R2F-L-GP
PEG_CMP 2
1 24D9R2F-L-GP
EXP_A_COMPI EXP_A_COMPO
D40 D38
EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8 EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15
F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38
PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0
EXP_A_RXP_0 EXP_A_RXP_1 EXP_A_RXP_2 EXP_A_RXP_3 EXP_A_RXP_4 EXP_A_RXP_5 EXP_A_RXP_6 EXP_A_RXP_7 EXP_A_RXP_8 EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15
D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38
PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0
EXP_A_TXN_0 EXP_A_TXN_1 EXP_A_TXN_2 EXP_A_TXN_3 EXP_A_TXN_4 EXP_A_TXN_5 EXP_A_TXN_6 EXP_A_TXN_7 EXP_A_TXN_8 EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12 EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15
F36 GTXN0 G40 GTXN1 H36 GTXN2 J40 GTXN3 L36 GTXN4 M40 GTXN5 N36 GTXN6 P40 GTXN7 R36 GTXN8 T40 GTXN9 V36 GTXN10 W40 GTXN11 Y36 GTXN12 AA40 GTXN13 AB36 GTXN14 AC40 GTXN15
1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C45 C57 C43 C58 C60 C67 C83 C90 C94 C102 C113 C120 C130 C136 C145 C150
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
EXP_A_TXP_0 EXP_A_TXP_1 EXP_A_TXP_2 EXP_A_TXP_3 EXP_A_TXP_4 EXP_A_TXP_5 EXP_A_TXP_6 EXP_A_TXP_7 EXP_A_TXP_8 EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15
D36 GTXP0 F40 GTXP1 G36 GTXP2 H40 GTXP3 J36 GTXP4 L40 GTXP5 M36 GTXP6 N40 GTXP7 P36 GTXP8 R40 GTXP9 T36 GTXP10 V40 GTXP11 W36 GTXP12 Y40 GTXP13 AA36 GTXP14 AB40 GTXP15
1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C39 C50 C37 C51 C52 C65 C76 C87 C89 C98 C110 C114 C121 C131 C138 C144
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
PEG_RXN[15..0]
26 4
PEG_RXP[15..0] 26
PEG_TXN[15..0] 26 3
PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TXP[15..0] 26
PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
2
CALISTOGA
71.CALIS.00U
M_RCOMPN LCTLA_CLK LCTLB_DATA
1 2
RN12 SRN10KJ-5-GP 4 UMA 3
GMCH_HSYNC GMCH_VSYNC
1 2
RN19 SRN0J-6-GP 4 MXM 3
M_RCOMPP
1
R57 150R2F-1-GP R109 80D6R2F-L-GP
GMCH_BLUE
1
UMA
2
RN20 SRN100KJ-6-GP GMCH_BL_ON GMCH_LCDVDD_ON
2
R56 150R2F-1-GP GMCH_GREEN
1
UMA
2
2 1
1
UMA
2
LIBG
1
1
UMA
2
TV_DACB
1
UMA
1
UMA
R249 0R2J-2-GP UMA 2
CRT_IREF
R76 255R2F-L-GP 1 UMA 2
GMCH_GREEN GMCH_BLUE
RN18 SRN0J-6-GP 2 3 1 MXM 4
CRT_IREF
R264 0R2J-2-GP 1 MXM 2 R75 0R2J-2-GP 1 MXM 2
TV_DACA TV_DACB
1 2
TV_IREF TV_DACC
RN17 SRN0J-6-GP 1 4 2 MXM 3
TV_IRTNA
R259 0R2J-2-GP 1 MXM 2
TV_IRTNB
R260 0R2J-2-GP 1 MXM 2
TV_IRTNC
R261 0R2J-2-GP 1 MXM 2
GMCH_RED
2
R47 150R2F-1-GP TV_DACC
2
1
R48 150R2F-1-GP
1
UMA
GMCH_RGB#
R49 150R2F-1-GP TV_DACA
UMA
R53 1K5R2F-2-GP
R256 150R2F-1-GP GMCH_RED
3 4
2
1D05V_S0
RN16 SRN0J-6-GP 4 MXM 3
1D5V_S0
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
GMCH (2 of 5) Size
B
C
Document Number
Rev
-1
Volvi Date:
A
3D3V_S0
D
Wednesday, April 18, 2007
Sheet E
7
of
42
A
B
C
D
E
4
4
2
SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13
AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13
SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE#
AW14 AK23 AK24 AY14
SA_RCVENIN# SA_RCVENOUT#
M_A_BS#0 11,12 M_A_BS#1 11,12 M_A_BS#2 11,12 M_A_CAS# 11,12 M_A_DM[7..0] 11
M_A_DQS[7..0]
M_A_DQS#[7..0]
11
11
M_A_A[13..0] 11,12
M_A_RAS# 11,12
TP15 TPAD30 TP14 TPAD30
M_A_WE# 11,12
Place Test PAD Near to Chip as could as possible
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
B
AU12 AV14 BA20
MEMORY
SA_BS_0 SA_BS_1 SA_BS_2
AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3
SYSTEM
A
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
MEMORY
3
AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8
SYSTEM
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
DDR
11 M_A_DQ[63..0]
U38E M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
DDR
11 M_B_DQ[63..0] U38D
SB_BS_0 SB_BS_1 SB_BS_2
AT24 AV23 AY28
SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13
AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23
SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE#
AU23 AK16 AK18 AR27
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 SB_RCVENIN# SB_RCVENOUT#
M_B_BS#0 11,12 M_B_BS#1 11,12 M_B_BS#2 11,12 M_B_CAS# 11,12 M_B_DM[7..0] 11
M_B_DQS[7..0] 11
M_B_DQS#[7..0]
3
11
M_B_A[13..0] 11,12
2
M_B_RAS# 11,12
TP16 TPAD30 TP17 TPAD30
M_B_WE# 11,12
Place Test PAD Near to Chip ascould as possible
CALISTOGA
71.CALIS.00U
CALISTOGA
71.CALIS.00U 1
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
GMCH (3 of 5) Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
8
of
42
B
C
D
VCCD_QTVDAC
1
2 2
1
1
UMA
UMA
C61
2
SC10U10V5ZY-1GP
C38
1
1
C158
2
C134
1
C139
2
2
2
V_DACC
1
1 2
2
2
SCD1U10V2KX-4GP
R245 0R3-0-U-GP V_TVBG 2 UMA 1
UMA C353
SCD1U10V2KX-4GP
C149 SCD1U10V2KX-4GP
UMA
SCD1U10V2KX-4GP
1
UMA C46
1
V_DACB
2
1
1D5V_S0
SCD1U10V2KX-4GP
2
L17 HCB1608KF121T30-GP 68.00230.041
C86
C64 SCD1U10V2KX-4GP
R246 0R3-0-U-GP 2 UMA 1
2
V_DACA
1
2
1
C63
2
1 2
VCCP_GMCH_CAP2 VCCP_GMCH_CAP1 C375
C40
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
SCD1U10V2KX-4GP
GMCH (4 of 5)
CALISTOGA
SCD1U10V2KX-4GP
C356
SCD22U16V3ZY-GP
R42
DY 10R2J-2-GP
1D5V_QTVDAC_S0
2 1 R78 0R0603-PAD
VCCP_GMCH_CAP3
SCD47U10V3ZY-GP
R242 0R3-0-U-GP UMA 1
1D5V_S0 1D05V_S0
SCD1U10V2KX-4GP
R41 0R5J-6-GP
2
2
VCCA_CRTDAC R240 0R3-0-U-GP 1 MXM 2 1
1
VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40
SCD47U10V3ZY-GP
UMA
C34 SCD1U10V2KX-4GP
2
C30
SCD1U10V2KX-4GP
2
1
1
2
2
AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12
1
H19 3D3V_S0_VCC_HV
1
VCC_HV0 VCC_HV1 VCC_HV2
C35 SCD1U10V2KX-4GP
4
3
2
VCCD_TVDAC
A23 B23 B25
1D5V_TVDAC_S0
1
1
2
C101
2
2
D21
VCCD_LVDS 1 R265 0R3-0-U-GP
POWER
C137
1
2
2
UMA
1
3D3V_S0
R247 0R3-0-U-GP 2 UMA 1
Divide by Trace (Layout Rule approve)
VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2
V_DACC
R258 0R0603-PAD
1D5V_3D3V_S0
UMA
A28 B28 C28
2 0R2J-2-GP
C92
2
1
1D5V_S0
2
1
VCCD_HMPLL0 VCCD_HMPLL1
MXM
1D5V_MPLL_S0
3D3V_TVDAC
3D3V_S0
AH1 AH2
MXM MXM
R253 1
2
2D5V_CRTDAC
2
VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1
V_DACA V_DACB
R257 0R3-0-U-GP 2 MXM 1
D3 DY BAT54-4-GP 1
1
E19 F19 C20 D20 E20 F20
2 0R2J-2-GP 2 0R2J-2-GP
R239
3
VCCA_TVBG VSSA_TVBG
1D5V_S0
L4 HCB1608KF121T30-GP 68.00230.041
1D5V_S0
VCCA_MPLL
H20 G20
R251 1 R250 1
DY 10R2J-2-GP
2D5V_S0
VCCA_LVDS VSSA_LVDS
1D5V_MPLL_S0 AF2
2
1D5V_HPLL_S0
C147
UMA
A38 B39
UMA 1 VSSA_LVDS
V_TVBG
1D5V_2D5V_S0
1
VCCA_DPLLA VCCA_DPLLB VCCA_HPLL
2 0R2J-2-GP
R46 0R0603-PAD
2
B26 C39 AF1
MXM
R252 1
1D5V_S0
D25 DY BAT54-4-GP 1 3
VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC
1
1 2 1 2 1
1
1 2 1 2
2
1 2 1 2 1 2 1 2
2
2 1 2 1
1 2 1 2 1 2 1 2
UMA
VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG
AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1
SC4D7U10V5ZY-3GP
R269 0R2J-2-GP 2 MXM 1
R52 2 C361 0R2J-2-GP SCD1U10V2KX-4GP
VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76
VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2
F21 E21 G21
VCCA_CRTDAC
SC10U10V5ZY-1GP
1D5V_S0
2D5V_3GBG_S0
2D5V_S0_LVDS
SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
-1 0411
C414
AJ41 AB41 Y41 V41 R41 N41 L41 AC33 G41 H41
VCCSYNC
SC2D2U6D3V3MX-1-GP
C397
C30 B30 A30
2D5V_VCC
1D5V_DPLLA 1D5V_DPLLB 1D5V_HPLL_S0
C148 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
R289 0R0603-PAD 1 2
C367
2
1D05V_S0
U38H H22
SCD1U10V2KX-4GP
C376
VCCSYNC C103 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R285 0R0603-PAD 1 2
SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
3
1D5V_DPLLB
C32
UMA
2
SC4D7U6D3V3KX-GP
C29
UMA
2D5V_S0
R271 0R3-0-U-GP 1 UMA 2
C378 SC4D7U6D3V3KX-GP
UMA
UMA
C123
SC4D7U6D3V3KX-GP
R55 0R3-0-U-GP 1 2
C44 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
UMA
R243
UMA 0R3-0-U-GP
1 MXM R51 0R2J-2-GP
C373
SCD1U10V2KX-4GP
1D5V_DPLLA C33
C141 SC4D7U6D3V3KX-GP
R50 0R3-0-U-GP 1 2
R66
UMA 0R3-0-U-GP
UMA
1D5V_3GPLL_S0 R89 0R0603-PAD 2 1
1D5V_S0
UMA
R85 0R2J-2-GP 1 MXM
1D5V_PCIE_S0 R310 0R0805-PAD 1 2
1D5V_S0
1D5V_S0
2
C47 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
4
C365
C31 SC4D7U6D3V3KX-GP
R273 0R0603-PAD 2 1
1
2D5V_3GBG_S0
2
1
2D5V_VCC 2D5V_S0
E
2D5V_S0 1
2D5V_S0
2
A
Size
71.CALIS.00U
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
9
of
42
A
D
71.CALIS.00U VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72
E
U38I
NCTF
VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12
AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17
VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57
AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15
AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34
1D5V_S0
TC2 ST220U2D5VBM-2GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
1
C93
2
1
C111
2
1
C95
2
1
C112
2
1
C117 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
2
1
C122
2
C68
1
Place these Caps close VCC_0 ~ VCC_110
-1 0409
1
VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96
U38J
VSS
VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179
AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23
AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21 AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11
VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272
VSS
VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360
J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1
3
2
CALISTOGA
71.CALIS.00U
CALISTOGA
71.CALIS.00U 1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
CALISTOGA
71.CALIS.00U
4
C159 SCD1U16V2ZY-2GP
2
1
C175 SCD1U16V2ZY-2GP
2
1
C166 SCD1U16V2ZY-2GP
2
1
C172 SCD1U16V2ZY-2GP
DY 2
1
C176 SCD1U10V2KX-4GP
2
1
C181 SCD1U10V2KX-4GP
2
1
C171 SCD1U10V2KX-4GP
2
1
C174 SCD1U10V2KX-4GP
2
1
C163 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
ST220U2D5VBM-2GP
DY
C156
2
TC11
1
1D8V_S3
2
VCC
VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99 VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107
SC10U10V5ZY-1GP
1
C
U38F CALISTOGA
AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18
1
2
1D05V_S0
AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1
2
3
VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110
1
4
AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19 M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16
2
1D05V_S0
B
U38G
-1 0409
Title
GMCH (5 of 5) Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
10
of
42
A
B
C
D
E
DM1
8 M_B_DQS#[7..0]
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
13 31 51 70 131 148 169 188
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
8 M_B_DQS[7..0]
DDR_VREF_S3
A
1
C223 SCD1U16V2ZY-2GP
1
DY
2
C228
SDA SCL
195 197
VDDSPD
199
SA0 SA1
198 200
NC#50 NC#69 NC#83 NC#120 NC#163/TEST
50 69 83 120 163
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
VREF VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
202
GND
GND
201
MH1
MH1
MH2
MH2
114 119
M_ODT2 M_ODT3
2
7,12 7,12
SC4D7U6D3V3KX-GP
1
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
10 26 52 67 130 147 170 185
M_CLK_DDR2 7 M_CLK_DDR#2 7 M_B_DM[7..0] 8
1 2
OTD0 OTD1
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
8,12
TPAD30 TP25 TPAD30 TP24 M_A_BS#2
8,12 8,12
M_A_BS#0 M_A_BS#1 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
8 M_A_DQ[63..0] SMBD_ICH 3,18 SMBC_ICH 3,18 3D3V_S0
DDRB_SA02 R139
1
10KR2J-3-GP C231
1D8V_S3
7,12 7,12 7,12 7,12 8,12 8,12 8,12
M_CS0# M_CS1# M_CKE0 M_CKE1 M_A_RAS# M_A_CAS# M_A_WE# SMBC_ICH SMBD_ICH
DDR_VREF_S3 7,12 7,12
DY
M_ODT0 M_ODT1
C454
C202
DDR2-200P-23-GP-U1
62.10017.A71
High 9.2mm B
C
MH1
MH2
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2
107 106
BA0 BA1
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
50 69 83 120 163
NC#50 NC#69 NC#83 NC#120 NC#163/TEST
110 115 79 80 108 113 109
CS0# CS1# CKE0 CKE1 RAS# CAS# WE#
197 195
SCL SDA
114 119
ODT0 ODT1
1 201
MH2
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
10 26 52 67 130 147 170 185
CK0 CK0# CK1 CK1#
30 32 164 166
SA0 SA1
198 200
VDD_SPD
199
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
81 82 87 88 95 96 103 104 111 112 117 118
VREF
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
GND
GND
202
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS[7..0]
M_A_DQS#[7..0]
8
8 4
M_A_DM[7..0] 8
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_CLK_DDR0 7 M_CLK_DDR#0 7 M_CLK_DDR1 7 M_CLK_DDR#1 7 3D3V_S0
C208
1
11 29 49 68 129 146 167 186
2
CK1 CK1#
164 166
0122 swap CLK2 and CLK3
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
2
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
3
M_CLK_DDR3 7 M_CLK_DDR#3 7
1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
30 32
2
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
8 M_B_DQ[63..0]
M_CKE2 7,12 M_CKE3 7,12
CK0 CK0#
SCD1U16V2ZY-2GP
BA0 BA1
79 80
1
M_B_BS#0 M_B_BS#1
M_CS2# 7,12 M_CS3# 7,12
CKE0 CKE1
2
8,12 8,12
CS0# CS1#
110 115
SC4D7U6D3V3KX-GP
TPAD30 TP26 TPAD30 TP27 M_B_BS#2
M_B_RAS# 8,12 M_B_WE# 8,12 M_B_CAS# 8,12
1
8,12
108 109 113
2
107 106
4
MH1 8,12 M_A_A[13..0]
RAS# WE# CAS#
SCD1U16V2ZY-2GP
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
SCD1U16V2ZY-2GP
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85
REVERSE TYPE
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
REVERSE TYPE
DM2 8,12 M_B_A[13..0]
3
1D8V_S3
2
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
SKT-SODIMM20022U2GP
62.10017.691
Title
High 5.2mm Size Date: D
Document Number
DDR2 Socket
Wednesday, April 18, 2007
Rev
-1
Volvi
Sheet E
11
of
42
A
B
D
PARALLEL TERMINATION
1
1 2
2
1 2
2
2
2
1
1
1
1 2
SCD1U16V2ZY-2GP
2
C230
SCD1U16V2ZY-2GP
DY
C218
SCD1U16V2ZY-2GP
2
C235
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
1
1
1
1
C207
1
1
2
1
2
SCD1U16V2ZY-2GP
2
C453
SCD1U16V2ZY-2GP
DY
C241
SCD1U16V2ZY-2GP
DY
C243
2
C199 SCD1U16V2ZY-2GP
2
1
1
1
1
C220 SCD1U16V2ZY-2GP
2
C211 SCD1U16V2ZY-2GP
DY
C234 SCD1U16V2ZY-2GP
2
C210
2
C242
2
C217
1
1
1
M_B_A[13..0] 8,11 SCD1U16V2ZY-2GP
SRN56J-5-GP
C219
M_A_A[13..0] 8,11
C452
M_ODT2 7,11 M_ODT3 7,11 M_B_RAS# 8,11
C221
SCD1U16V2ZY-2GP
M_B_WE# 8,11
C216
SCD1U16V2ZY-2GP
M_B_A[13..0]
SCD1U16V2ZY-2GP
8 7 6 5
SRN56J-5-GP RN45 1 M_B_A13 2 3 4
M_A_A[13..0]
M_B_A3 M_B_A1 M_B_A10
DY
C206
SCD1U16V2ZY-2GP
SRN56J-5-GP RN41 1 2 3 4
C229
SCD1U16V2ZY-2GP
8 7 6 5
DY
M_CKE2 7,11 M_CKE3 7,11 M_B_BS#2 8,11
C240 SCD1U16V2ZY-2GP
SRN56J-5-GP RN39 1 2 3 4 M_B_A12
4
C198
SCD1U16V2ZY-2GP
8 7 6 5
Put decap near power(0.9V) and pull-up resistor
DDR_VREF_S0
SCD1U16V2ZY-2GP
8 7 6 5
2
M_A_A12
SRN56J-5-GP RN40 M_B_A8 1 2 M_B_A9 3 M_B_A5 4
M_CKE0 7,11 M_CKE1 7,11 M_A_BS#2 8,11
1
1 2 3 4
2
8 7 6 5
E
Decoupling Capacitor
Put decap near power(0.9V) and pull-up resistor
RN32
2
DDR_VREF_S0
4
C
RN44 M_B_BS#1 8,11
1
1
2
2 1
2
DY
2
2 SRN56J-5-GP
2
DY
DY
SCD1U16V2ZY-2GP
DY M_ODT0 7,11 M_CS0# 7,11 M_A_RAS# 8,11
C212
SCD1U16V2ZY-2GP
M_A_A13
C209
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN38 1 2 3 4
C205
2
C197
SRN56J-5-GP
8 7 6 5
1
2 1
M_B_BS#0 8,11 M_B_CAS# 8,11 M_CS3# 7,11 M_CS2# 7,11
SC2D2U6D3V3MX-1-GP
1 2 3 4
C446
SC2D2U6D3V3MX-1-GP
RN42 8 7 6 5
C214
SC2D2U6D3V3MX-1-GP
SRN56J-5-GP
C448
SC2D2U6D3V3MX-1-GP
M_B_A6 M_B_A7 M_B_A11
C213
SC2D2U6D3V3MX-1-GP
1 2 3 4
1
C447
RN43 8 7 6 5
1
1
SRN56J-5-GP
3
Place these Caps near DM1
1D8V_S3
1
M_B_A2 M_B_A0 M_B_A4
2
1 2 3 4
2
8 7 6 5
3
2
RN37 8 7 6 5
1 2 3 4
M_A_A0 M_A_A2 M_A_A4
M_A_BS#1 8,11
Place these Caps near DM2
1D8V_S3
SRN56J-5-GP
DY
1 2
1 2 1
1 2 1
1
DY
2
2
DY
C222
DY
SCD1U16V2ZY-2GP
M_A_A6 M_A_A7 M_A_A11
C239 SCD1U16V2ZY-2GP
1 2 3 4
SCD1U16V2ZY-2GP
1
SCD1U16V2ZY-2GP
RN36 8 7 6 5
C224
2
C238
SRN56J-5-GP
2
2 1
M_A_A9 M_A_A8 M_A_A5 M_A_A3
C246 SC2D2U6D3V3MX-1-GP
1 2 3 4
C236 SC2D2U6D3V3MX-1-GP
RN33 8 7 6 5
C227 SC2D2U6D3V3MX-1-GP
M_CS1# 7,11 M_ODT1 7,11
SRN56J-5-GP
C245 SC2D2U6D3V3MX-1-GP
M_A_CAS# 8,11
SC2D2U6D3V3MX-1-GP
1 2 3 4
1
C226
RN35 8 7 6 5
2
1
SRN56J-5-GP
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
RN34 8 7 6 5
1 2 3 4
M_A_A1 M_A_A10 Title
M_A_BS#0 8,11 M_A_WE# 8,11
DDR2 Termination Resistor Size
SRN56J-5-GP
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
12
of
42
LCDVDD
3D3V_S0 Q15 GND 2
U35
R224 0R2J-2-GP
MXM
GND IN#8 IN#7 IN#6 IN#5
C339
3 OUT
R2
G5281RC1U-GP
74.05281.093
30
1
IN#1 OUT EN GND
IN
PWR_G_LED
R1
1
CHDTC143ZUPT-GP
C337
3D3V_S0
84.00143.B1K
2
C338
SCD1U16V2ZY-2GP 2 1
2
0R2J-2-GP
2
SC1U16V3ZY-GP
2LCDVDD_ON_1
1
R226
UMA 1
7 GMCH_LCDVDD_ON
9 8 7 6 5
SC1U16V3ZY-GP
1 2 3 4
LED1 31 PWRLED#_DB
1 2FRONT_PWRLED#_R R500 100R2J-2-GP
3
STDBY_LED#_DB
STDBY_LED#_R 1 2 R499 100R2J-2-GP
4
1
31 STDBY_LED#_DB
PWRLED#_DB
3D3V_S5
1 2 LED-GY-14-GP
Q14
83.00195.I70
GND 2
26 NV_LCDVDD_ON
3 OUT
R2 IN
PWR_O_LED
R1
1
CHDTC143ZUPT-GP
84.00143.B1K
R333
1 2 33R2J-2-GP
27 WLAN_LED#_MC
WLAN_LED# 31
Q10
LCD/INVERTER CONN
D
30
2N7002-11-GP
G
30 WLAN_TEST_LED
S
84.27002.W31
LCDVDD
DCBATOUT
1 1
F1
1 2 FUSE-3A32V-8-GP
69.43001.111 SCD1U50V3ZY-GP
SC10U35V0ZY-GP
2 2
EC1
1 2 3 4
UMA 8 7 6 5
GMCH_TXBOUT1GMCH_TXBOUT1+ GMCH_TXBOUT0GMCH_TXBOUT0+
30
IN
BT_LED
R1
1
84.00143.B1K
CHDTC143ZUPT-GP
ODD CHANNEL
RN3 LCD_TXBCLKLCD_TXBCLK+ LCD_TXBOUT2LCD_TXBOUT2+
1 2 3 4
EVEN CHANNEL
GND 2
8 7 6 5
GMCH_TXBCLK- 7 GMCH_TXBCLK+ 7 GMCH_TXBOUT2- 7 GMCH_TXBOUT2+ 7
RN9
1 2 3 4
IN
30 CHARGE_LED
R1
1
GMCH_TXACLKGMCH_TXACLK+ GMCH_TXAOUT2GMCH_TXAOUT2+
7 7 7 7
GMCH_TXAOUT1GMCH_TXAOUT1+ GMCH_TXAOUT0GMCH_TXAOUT0+
7 7 7 7
IN
30 DC_BATFULL
1
LCD_TXAOUT1LCD_TXAOUT1+ LCD_TXAOUT0LCD_TXAOUT0+
1 2 3 4
RN6 LCD_TXBOUT0+ LCD_TXBOUT0LCD_TXBOUT1+ LCD_TXBOUT1-
F2
2
1 2 3 4
84.00143.B1K
8 7 6 5
RN5 SRN2K2J-1-GP
R35 2 0R2J-2-GP 1 R29 2 0R2J-2-GP R34
26 26 26 26
1
7 DAT_DDC_EDID
LVDS_TXBOUT2+ 26 LVDS_TXBOUT2- 26 LVDS_TXBCLK+ 26 LVDS_TXBCLK- 26
LCD_TXAOUT0+ LCD_TXAOUT0LCD_TXAOUT1+ LCD_TXAOUT1-
1 2 3 4
8 7 6 5
LVDS_TXAOUT2+ LVDS_TXAOUT2LVDS_TXACLK+ LVDS_TXACLK-
26 26 26 26
LVDS_TXAOUT0+ LVDS_TXAOUT0LVDS_TXAOUT1+ LVDS_TXAOUT1-
26 26 26 26
LCD_TXBCLKLCD_TXBOUT2+
2 R2
DY 330R2J-3-GP
2 1
LCD_TXAOUT2LCD_TXAOUT1+ R7
R3
DY 330R2J-3-GP LCD_TXBOUT1LCD_TXBOUT0+
DY 330R2J-3-GP LCD_TXAOUT1LCD_TXAOUT0+
2 1
SRN0J-7-GP
R8
1
BRIGHTNESS 30 BLON_OUT 30
R6 LCD_TXBOUT2LCD_TXBOUT1+
LCD_TXBOUT0-
UMA
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
R4
DY 330R2J-3-GP 1
L_BKLTCTL 7
8 7 6 5
DY 330R2J-3-GP LCD_TXACLKLCD_TXAOUT2+
DY 330R2J-3-GP
MXM
R1
2
SC100P50V2JN-3GP 2 1
SC100P50V2JN-3GP 2 1
C4
10KR2J-3-GP
C340
RN13
R5
DY 330R2J-3-GP
SRN0J-7-GP 16 16
LCD_TXACLK+ R9
MXM
2 1
1 2 3 4
2 1
LCD_TXAOUT2+ LCD_TXAOUT2LCD_TXACLK+ LCD_TXACLK-
EC4 DY SCD1U16V2ZY-2GP
EMI LCD_TXBCLK+
2 1
SB 0226
-1 0416
EC3 DY SCD1U16V2ZY-2GP
DY 330R2J-3-GP LCD_TXAOUT0-
Title
1
8 7 6 5
RN8
BRIGHTNESS_CN BLON_OUT
NV_EDID_DAT
MXM
2
1 2 3 4
SRN0J-7-GP
1 0R2J-2-GP R227 1 2 0R0402-PAD
UMA
2 0R2J-2-GP
1 R28 2 0R2J-2-GP
26 NV_EDID_DAT_1
2 1
1
RN4 LCD_TXBOUT2+ LCD_TXBOUT2LCD_TXBCLK+ LCD_TXBCLK-
DY
NV_EDID_CLK
MXM
MXM
2
2
1
LVDS_TXBOUT0+ LVDS_TXBOUT0LVDS_TXBOUT1+ LVDS_TXBOUT1-
UMA
1
69.50007.721 C2 SCD1U16V2ZY-2GP
83.00195.I70 3D3V_S0
UMA
SRN0J-7-GP
FUSE-1A6V-2-GP
R2252
2 DC_BATFULL#_R 100R2J-2-GP
MXM 8 7 6 5
1
CHDTC143ZUPT-GP
26 NV_EDID_CLK_1
USBPN6 USBPP6
1
R1
7 CLK_DDC_EDID
2 2
3 OUT
R2
2
LED-GY-14-GP
R498
UMA
4 3
CHDTC143ZUPT-GP Q27 GND 2
8 7 6 5
RN14
0R0402-PAD 1 R11 0R0402-PAD 1 R10
R497 CHARGE_LED#_R 1 2 100R2J-2-GP
84.00143.B1K
SRN0J-7-GP
USB_6USB_6+
3 OUT
R2
SRN0J-7-GP LCD_TXACLKLCD_TXACLK+ LCD_TXAOUT2LCD_TXAOUT2+
LED2
UMA
SRN0J-7-GP
3D3V_S0
C1 SC4D7U10V5ZY-3GP
3D3V_S5
Q8
20.F0993.040
CCD_PWR
2nd 84.00143.D1K
SRN0J-7-GP
ACES-CONN40A-2GP
1
3 OUT
R2
7 7 7 7
1
BRIGHTNESS_CN BLON_OUT
RN7 LCD_TXBOUT1LCD_TXBOUT1+ LCD_TXBOUT0LCD_TXBOUT0+
2
CCD_PWR
LCD_TXAOUT2LCD_TXAOUT2+ LCD_TXAOUT1LCD_TXAOUT1+ LCD_TXAOUT0LCD_TXAOUT0+ LCD_TXACLKLCD_TXACLK+ LCD_TXBOUT2LCD_TXBOUT2+ LCD_TXBOUT1LCD_TXBOUT1+ LCD_TXBOUT0LCD_TXBOUT0+ LCD_TXBCLKLCD_TXBCLK+
2 1
3D3V_S0 NV_EDID_CLK NV_EDID_DAT
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Q9 GND 2
SCD1U25V3ZY-1GP
3 4
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
C5
1
2
USB_6USB_6+
DY
1
BT_LED#
BT_LED#
2
41 2
C3
31
1
LCD1
LCD CONN & LED Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007
Sheet
13
of
42
A
B
C
3
CRT_VSYNC1
14
C16
MH2
1CRT_DEC_R 1
2
CRT_DEC#
2
2
3
BAV99-5-GP
5V_CRT_S0
2 1
C341 SCD1U16V2ZY-2GP
2nd 83.R3004.A8F CH751H-40PT D1 3D3V_S0
3D3V_S0 RN1 SRN2K2J-1-GP
1
14
SRN10KJ-6-GP RN2
7
4
14
CRT_HSYNC1_R 1 2CRT_HSYNC1 0R2J-2-GP 26 NV_DDCDAT
3
CRT_VSYNC 0R2J-2-GP
1
C352DY
2
2C
C354 354
DY
SC18P50V2JN-1-GP 7
5
1
SC18P50V2JN-1-GP
2
6
MXM
U2A TSAHCT125PW-GP
CRT_VSYNC1_R
1 R13 R12 1
7 GMCH_DDCDATA
Q1
2
0R2J-2-GP 2 0R2J-2-GP
NV_DDCDAT_1
CRT_DEC#
4
3
5
2
6
1
DAT_DDC1_5
UMA
1 2CRT_VSYNC1 0R2J-2-GP
U2B TSAHCT125PW-GP
1 2 3 4
2
3 4
CRT_HSYNC 0R2J-2-GP
2
1 R237
NV_VSYNC
5V_S0
1
SC100P50V2JN-3GP
3D3V_S0
R26
MXM 26
DY
3
C6
1 2 2
UMA
R2381 2 0R2J-2-GP
7 GMCH_VSYNC
SC100P50V2JN-3GP
R27
MXM 1 R236
C7
5V_S0
D2
UMA
NV_HSYNC
SC18P50V2JN-1-GP
SCD01U16V2KX-3GP
20.20334.015
5V_S0
26
C17
VIDEO-15-21-U4-GP
Hsync & Vsync level shift
7 GMCH_HSYNC
CLK_DDC1_5
15 5 16
470R2J-2-GP
R2351 2 0R2J-2-GP
C10
10
SC18P50V2JN-1-GP
R15
3
5V_CRT_S0
4
C15 to 18P C12 to 27P C9 to 27P For ATI MXM M66M R,G,B 30
9
1
2
SC100P50V2JN-3GP CRT_B
C9
2
1
C12
CRT_HSYNC1
1
MXM
Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
1
CRT_B C15
CRT_G
13
2
MXM
68.00230.021
1
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
MXM
2 FCB1608CF-GP
4
2 8
2
R18
C8
2
R20
C11
C13
SC6D8P50V2DN-GP
R23
1 C14
SC22P50V2JN-4GP
0R2J-2-GP
1
CRT_B_1 0R2J-2-GP
SC22P50V2JN-4GP
2
1
2
UMA
1
SC22P50V2JN-4GP
R17
1
2
R19
1
NV_BLUE GMCH_BLUE
12
2
L1
2
26 7
1
68.00230.021
0R2J-2-GP
2
2
MXM
SC6D8P50V2DN-GP
UMA
1
SC6D8P50V2DN-GP
R21
7 DAT_DDC1_5
1
7 GMCH_GREEN
0R2J-2-GP
1
CRT_G
2 FCB1608CF-GP
2
R22
1
NV_GREEN
1
11
CRT_R
L2 CRT_G_1
2
26 4
2
MH1 6
8 7 6 5
0R2J-2-GP
MXM 1
17
CRT_R
2 FCB1608CF-GP
68.00230.021
1
2
1
2
UMA
1
CRT1
L3
CRT_R_1 0R2J-2-GP
1
R24
2
2
GMCH_RED
1
2
7
R25
Ferrite bead impedance: 10 ohm@100MHz
1
MXM NV_RED
E
CRT I/F & CONNECTOR
Layout Note: Place these resistors close to the CRT-out connector 26
D
MXM 1 R16 R14 1
26 NV_DDCCLK 7 GMCH_DDCCLK
0R2J-2-GP 2 0R2J-2-GP
2N7002DW-1-GP
84.27002.D3F
2
NV_DDCCLK_1
UMA
CLK_DDC1_5
2
DDC_CLK & DATA level shift C194
R124 150R2F-1-GP
TVOUT1
1 2 IND-1D2UH-5-GP
68.1R220.10A
LUMA_1 1
1
LUMA_1_1
C193
C195
SC150P50V2JN-3GP
2
TV_DACB
L11
L9 1 2 IND-1D2UH-5-GP
68.1R220.10A
1 3 8 9
5V_S0
1
3
1 BAV99-5-GP D23
2
3
68.1R220.10A
COMP_1 C190
2
C192
SC150P50V2JN-3GP
SC270P50V2JN-2GP
3
2 CRT_G 3
DY
SC270P50V2JN-2GP
COMP_1 1
1 R121 150R2F-1-GP
L10 1 2 IND-1D2UH-5-GP
2
TV_DACA
1
DY
1
1
BAV99-5-GP D6
BAV99-5-GP D22
2
2 CRT_B 3
DY
1
Wistron Corporation
DY
1
1
BAV99-5-GP
BAV99-5-GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
2
7
R122 UMA 0R2J-2-GP 1 2
COMP_1_1 1
26 NV_TV_COMP
DY
BAV99-5-GP D5
2 SC33P50V2JN-3GP
1
2 CRT_R 3
DY
2 CRMA_1
C185
C191 R123 MXM 0R2J-2-GP 1 2
D24 2
LUMA_1
C187
SC150P50V2JN-3GP
5V_S0
D7
CRMA_1 1
1 R115 150R2F-1-GP
NC#5
2
GND GND GND GND
22.10021.H61
2 SC33P50V2JN-3GP
2
TV_DACC
R116 UMA 0R2J-2-GP 1 2
CRMA_1_1
5
NC#2
2
7
R120 MXM 0R2J-2-GP 1 2
1
26 NV_TV_CRMA
LUMA CRMA COMP
MINDIN7-19-GP-U2
C186 1
4 6 7
SC270P50V2JN-2GP
2
7
R125 UMA 0R2J-2-GP 1 2
2 SC33P50V2JN-3GP
1
2
26 NV_TV_LUMA
R126 MXM 0R2J-2-GP 1 2
1
TV CONN
CRT/TV Connector
Document Number
Date: Wednesday, April 18, 2007 A
B
C
D
Volvi
Rev
-1 Sheet E
14
of
42
A
B
C
D
E
SB 0305
4
4
1
AA3
RTCRST#
R373 1
2 1MR2J-1-GP
INTRUDER# INTVRMEN
Y5 W4
INTRUDER#
3
SC1U10V3ZY-6GP
19
C520
R393 0R2J-2-GP 2 DY 1 LAN_RSTYNC
SB 0313 for EMI
2 R407 1 22R2J-2-GP
28 ACZ_SDATAIN0 21 ACZ_SDATAIN1
1
ACZ_BTCLK_MDC 2 1
EC132
2 R406 1 22R2J-2-GP1 R379 1 R385
ACZ_BITCLK 21,28 ACZ_SYNC 21,28 ACZ_RST#
R358 10KR2J-3-GP
R397 1 39R2J-L-GP
21,28 ACZ_SDATAOUT
DY
ACZ_BIT_CLK ACZ_SYNC_R 2 39R2J-L-GP ACZ_RST#_R 2 33R2J-2-GP
SATA_LED#
20 20 20 20
SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0
1 1 1 1
2 2 2 2
SC3900P50V3KX-GP SC3900P50V3KX-GP SC3900P50V3KX-GP SC3900P50V3KX-GP
SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C
3 CLK_PCIE_SATA# 3 CLK_PCIE_SATA
RTC_AUX_S5 1
SATARBIAS 1 R372 2 24D9R2F-L-GP R386 300KR2J-GP
2
P.H. for internal VCCSUS1_05
INTVRMEN 1
Place within 500 mils of ICH7ball
20 20 20 20 20 20
IDE_PDIOR# IDE_PDIOW# IDE_PDDACK# INT_IRQ14 IDE_PDIORDY IDE_PDDREQ
R395
2
V3
LAN_CLK
U3
LAN_RSTSYNC
U5 V4 T5
LAN_RXD0 LAN_RXD1 LAN_RXD2
U7 V6 V7
LAN_TXD0 LAN_TXD1 LAN_TXD2
U1 R6
ACZ_BIT_CLK ACZ_SYNC
R5
ACZ_RST# ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2
AA6 AB5 AC4 Y6
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LDRQ0# 30
30 30 30 30
AC3 AA5 3D3V_LDRQ1_S0 1 R377 2 10KR2J-3-GP
LFRAME#
AB3
LPC_LFRAME# 30
A20GATE A20M#
AE22 AH28
KA20GATE 30 H_A20M# 4
CPUSLP#
AG27
TP1/DPRSTP# TP2/DPSLP#
AF24 AH25
1D05V_S0
H_CPUSLP#_2
AF7 AE7 AG6 AH6
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
AF1 AE1
SATA_CLKN SATA_CLKP
AH10 AG10
SATARBIASN SATARBIASP
AF15 AH15 AF16 AH16 AG16 AE15
DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ
IDE
3
R339 56R2J-4-GP
H_CPUSLP# 4,6
H_DPRSTP# 4,35 H_DPSLP# 4
FERR# GPIO49/CPUPWRGD
AG24
H_PWRGD 4,31,33
IGNNE# INIT3_3V# INIT# INTR
AG22 AG21 AF22 AF25
H_IGNNE# 4
RCIN#
AG23
KBRCIN# 30
NMI SMI#
AH24 AF23
H_NMI 4 H_SMI# 4
STPCLK#
AH22
H_STPCLK# 4
THERMTRIP#
AF26
H_THERMTRIP_R
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15
IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15
DA0 DA1 DA2
AH17 AE17 AF17
IDE_PDA0 20 IDE_PDA1 20 IDE_PDA2 20
DCS1# DCS3#
AE16 AD16
IDE_PDCS1# 20 IDE_PDCS3# 20
H_FERR# 4
-1 0411 TP64 TPAD30
FWH_INIT#
H_INIT# 4 H_INTR 4
H_PWRGD 1D05V_S0
R342 200R2F-L-GP 1 DY 2
1D05V_S0
R335 56R2J-4-GP
Layout Note: R568 needs to placed within 2" of ICH7, R568 must be placed within 2" of R169 w/o stub.
SATALED# SATA0RXN SATA0RXP SATA0TXN SATA0TXP
3D3V_S0
R334 0R2J-2-GP 1 DY 2
AG26
ACZ_SDOUT
AF3 AE3 AG2 AH2
Open R for Dothan A step Shunt for Dothan B step & all Yonah
20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
2
ICH7-M-GP
71.ICH7M.00U
INTVRMEN
DY 0R2J-2-GP
1
EE_CS EE_SHCLK EE_DOUT EE_DIN
AF18 C515 C518 C509 C500
LDRQ0# LDRQ1#/GPIO23
W1 Y1 Y2 W3
T2 T3 ACZ_SDIN2 T1 TPAD30 TP58 ACZ_SDATAOUT_R T4 2
31 SATA_LED#
2
ACZ_BITCLK EC131
SC22P50V2JN-4GP
2
28
3D3V_S0
SC22P50V2JN-4GP
1
2
21 ACZ_BTCLK_MDC
0130
INTRUDER# INTVRMEN
LAD0 LAD1 LAD2 LAD3
1
RTXC1 RTCX2
RTC_RST#
2
2 20KR2J-L2-GP
1
1
R374 1
2
AB1 AB2
RTC LPC
U15A RCT_X1 RCT_X2
LAN CPU
2 SC10P50V2JN-4GP
AC-97/AZALIA
C247 1
2
20.F1000.003
C225 SC1U10V3ZY-6GP
SATA
MLX-CON3-10-GP
C590
1
1
5
1 2
2
DY
3 BAT_D
SCD1U16V2ZY-2GP
2 3
2
R376 1KR2J-1-GP 1 2
BAT
1
RTC_AUX_S5
2
RTC1 4
R145 10MR2J-L-GP
82.30001.691 1
RTC circuitry
X3 X-32D768KHZ-38GPU
D11 BAS40CW-GP
2
3D3V_AUX_S5
4
2 SC10P50V2JN-4GP
3
C250 1
Enable
1
Disable
0
Change to KI.80101.017 UMA
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Placement Note: Diatance between the ICH-7 M and cap on the "P" signal should be identical distance between the ICH-7 M and cap on the "N" signal for same pair.
Title Size
Document Number
ICH7-M (1 of 4)
Date: Wednesday, April 18, 2007 A
B
C
D
Volvi
Rev
-1 Sheet E
15
of
42
C
E
7
SMB_ALERT# B23
24 24 24 24
3 3
R354 A7 PCI_IRDY# 24 47R2J-2-GP E10 PCI_PAR 24 PCIRST# 1 B18 2 A12 PCI_DEVSEL# 24 C9 PCI_PERR# E11 PCI_LOCK# B10 PCI_SERR# F15 PCI_STOP# 24 F14 PCI_TRDY# 24 F16 PCI_FRAME# 24
G8 F7 F8 G7
RSVD[6] RSVD[7] RSVD[8] RSVD[9] MCH_SYNC#
SRN8K2J-2-GP-U 10 PCI_IRDY# 9 PCI_PERR# 8 INT_PIRQE# 7 PCI_DEVSEL# 6
3D3V_S0
RP2 PCI_STOP# PCI_REQ#2 PCI_TRDY# PCI_REQ#3
SRN8K2J-2-GP-U 10 PCI_REQ#1 9 PCI_FRAME# 8 PCI_REQ#4 7 PCI_LOCK# 6
1 2 3 4 5
3D3V_S0
RP4 INT_PIRQF# INT_PIRQC# INT_SERIRQ MCH_ICH_SYNC# 3D3V_S0
SRN8K2J-2-GP-U 10 PCI_SERR# 9 INT_PIRQD# 8 INT_PIRQB# 7 INT_PIRQA# 6
1 2 3 4 5
R360 1
ACZ_SPKR
R353 1
INT_PIRQG# 24
AE9 AG8 AH8 F21 AH20
ECSCI#_1
R359 1
2 10KR2J-3-GP
PWROK
R390 2
1 10KR2J-3-GP
2 1KR2J-1-GP
GPIO26
B21 E23
GPIO27 GPIO28
AG18
GPIO32/CLKRUN#
AC19 U2
GPIO33/AZ_DOCK_EN# GPIO34/AZ_DOCK_RST#
F20 AH21 AF20
WAKE# SERIRQ THRM#
AC21 AC18 ECSMI# E21
TPAD30 TP49
GPIO18/STPPCI# GPIO20/STPCPU#
A21
AD22
ECSCI#_1
GPIO11/SMBALERT#
PWROK GPIO16/DPRSLPVR TP0/BATLOW# PWRBTN# LAN_RST# RSMRST# GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35 GPIO38 GPIO39
VRMPWRGD GPIO6 GPIO7 GPIO8
GPIO
AA4
E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20
MCH_ICH_SYNC#
7
TXN1 TXP1
PERn1 PERp1 PETn1 PETp1
1 1
TXN2 TXP2
H26 H25 G28 G27
PERn2 PERp2 PETn2 PETp2
1 1
TXN3 TXP3
K26 K25 J28 J27
PERn3 PERp3 PETn3 PETp3
M26 M25 L28 L27
PERn4 PERp4 PETn4 PETp4
PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1
C438 SCD1U10V2KX-5GP 2 C439 SCD1U10V2KX-5GP 2
1 1
27 27 27 27
PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2
C436 SCD1U10V2KX-5GP 2 C437 SCD1U10V2KX-5GP 2
27 27 27 27
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
C434 SCD1U10V2KX-5GP 2 C435 SCD1U10V2KX-5GP 2
LAN
MINI CARD 3D3V_S0
NEW CARD RP1 3D3V_S0
ICH7_GPI12 1 PM_BATLOW#_R 2 DBRESET# 3 SMB_LINK_ALERT# 4 5 3D3V_S5 RP5
3D3V_S0
USB_OC#3 USB_OC#1 USB_OC#4 USB_OC#0
1 2 3 4 5
3D3V_S5
SRN10KJ-L3-GP 3D3V_S5 10 9 PCIE_WAKE# 8 PSW_CLR# 7 SMB_ALERT# 6 PM_RI# SRN10KJ-L3-GP 10 9 8 7 6
3D3V_S5 USB_OC#2 USB_OC#7 USB_OC#6 USB_OC#5 TPAD30 TP59
3D3V_S5
ECSWI# ECSMI#
SMLINK0 SMLINK1
3 4
21 21
USB_OC#0 USB_OC#1
RN67 SRN100KJ-6-GP 2 1
SPI_ARB
USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7
RN66 SRN10KJ-5-GP 3 2 4 1
P26 P25 N28 N27
PERn5 PERp5 PETn5 PETp5
H
PCI
H
L
SPI
L
H
T25 T24 R28 R27
PERn6 PERp6 PETn6 PETp6
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
7 7 7 7
DMI1RXN DMI1RXP DMI1TXN DMI1TXP
Y26 Y25 W28 W27
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
7 7 7 7
DMI2RXN DMI2RXP DMI2TXN DMI2TXP
AB26 AB25 AA28 AA27
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
7 7 7 7
DMI3RXN DMI3RXP DMI3TXN DMI3TXP
AD25 AD24 AC28 AC27
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
7 7 7 7
DMI_CLKN DMI_CLKP
AE28 AE27
CLK_PCIE_ICH# 3 CLK_PCIE_ICH 3
C25 D25
DMI_IRCOMP_R
R2 P6 P1
SPI_CLK SPI_CS# SPI_ARB
P5 P2
SPI_MOSI SPI_MISO
D3 C4 D5 D4 E5 C3 A2 B3
OC0# OC1# OC2# OC3# OC4# OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P
F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3
USBRBIAS# USBRBIAS
D2 D1
USBPN0 USBPP0 USBPN1 USBPP1 USBPN2 USBPP2 USBPN3 USBPP3 USBPN4 USBPP4 USBPN5 USBPP5 USBPN6 USBPP6 USBPN7 USBPP7
PM_DPRSLPVR 35
PM_PWRBTN# 30,31
3D3V_S0
L:UMA
H:IDTCV125 L:RTM865-433
R349 10KR2J-3-GP
IDT CLKGNT_SEL R350 10KR2J-3-GP
R345 10KR2J-3-GP
RTL
3
Layout Note: PCIE AC coupling caps need to be within 250 mils of the driver.
1D5V_S0 Place within 500 mils of ICH R341 24D9R2F-L-GP
21 21 21 21 21 21 21 21 27 27 21 21 13 13 27 27
2
USB ports definition Pair
Device
0
USB1
1
USB3
2
USB2
USB_RBIAS_PN
3
USB4
4
MINICARD
5
BlueTooth
6
CCD
7
NewCard
R404 22D6R2F-L1-GP
71.ICH7M.00U
UMA 1 R411 2K2R2J-2-GP
GAP放在Dimm Door打開可量測處
D13 BAT54PT-GP 1
G68 PSW_CLR#
1
2 30 RSMRST#_KBC GAP-OPEN
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
3
RSMRST#_SB Title R401 100KR2D-1-GP
2
Size
2 A
H:MXM
R352 10KR2J-3-GP
MXM UMA_DIS_SEL
V26 V25 U28 U27
ICH7-M-GP
2
H
30
3D3V_S0
UMA
1
GNT5# GNT4#
ECSWI# ICH7_GPI12
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
DMI_ZCOMP DMI_IRCOMP
4
7,19
PM_DPRSLPVR_R
U15D
F26 F25 E28 E27
22 22 22 22
Default:H LPC
PWROK
R346 2 1100R2J-2-GP 1 2 R348 DY C21 PM_BATLOW#_R 100KR2J-1-GP PWRBTN#_ICH 1 D9 C23 R355 BAS16-1-GP 10KR2J-3-GP 3 LAN_RST# 1 C19 2 2 RSMRST#_SB Y4 AC22
3D3V_S5
1
PM_SLP_S3# 19,26,27,30,33,36,37,38,39 PM_SLP_S4# 27,30,37,39 TP47 TPAD30
ICH7-M-GP
2 8K2R2J-3-GP
DY
22,27 PCIE_WAKE# 30 INT_SERIRQ 19 THRM#
30
3D3V_S0 PM_CLKRUN#
PCB_VER0 PCB_VER1
GPIO0/BM_BUSY#
B24 D23 F22 SLPS5#
1
RP3
30 30
7,35 VGATE_PWRGD
71.ICH7M.00U
1 2 3 4 5
SB 0314
TP50 TPAD30
ICH7-M-GP
PCI_REQ#0 INT_PIRQG# INT_PIRQH# PCI_REQ#5
PSW_CLR#
24,30 PM_CLKRUN#
PLT_RST1# 7,26,30 CLK_ICHPCI 3
INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#
AC20 AF21
PM_STPPCI# PM_STPCPU#
PCIRST1# 20,22,24,27
-1 0416
R340 1 C26 PLTRST# 2 0R0402-PAD A9 B19 ICH_PME#
AB18
PM_BMBUSY#
PM_SUS_CLK 19
SLP_S3# SLP_S4# SLP_S5#
1
TPAD30
C20
2
TP55
DBRESET#
CLK_ICH14 3 CLK48_ICH 3
SUSCLK
1
TPAD30 TP45
SPKR SUS_STAT# SYS_RST#
2
TPAD30
A19 A27 A22
AC1 B2
3D3V_S0 RN68 SRN10KJ-6-GP 8 7 6 5
2
RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]
TP53
ACZ_SPKR
CLK14 CLK48
71.ICH7M.00U
MISC
AE5 AD5 AG4 AH4 AD9
28
RI#
Direct Media Interface
3
GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH#
TPAD30
A28
PCI-Express
PIRQA# PIRQB# PIRQC# PIRQD#
TP54
PM_RI#
1 2 3 4
1
Interrupt I/F
A3 B4 C5 B5
TPAD30
SATA0_R1 SATA0_R3 SATA0_R0 SATA0_R2
2
PLTRST# PCICLK PME#
TPAD30
TP51
SATA0_R0 SATA0_R1 SATA0_R2 SATA0_R3
1
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3
TP52
AF19 AH18 AH19 AE19
2
C/BE0# C/BE1# C/BE2# C/BE3#
B15 C12 D12 C15
PCI_REQ#0 24 PCI_GNT#0 24
PCI_REQ#1 PCI_GNT#1 PCI_REQ#2 PCI_GNT#2 PCI_REQ#3 PCI_GNT#3 PCI_REQ#4 PCI_GNT#4 PCI_REQ#5 PCI_GNT#5
GPIO21/SATA0GP GPIO19/SATA1GP GPIO36/SATA2GP GPIO37/SATA3GP
Clocks
D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8
SMB
REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ4#/GPIO22 GNT4#/GPIO48 GPIO1/REQ5# GPIO17/GNT5#
PCI
SPI
INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1
USB
4
E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6
C22 B22 SMB_LINK_ALERT# A26 SMLINK0 B25 SMLINK1 A25
18,22,27 SMB_CLK 18,22,27 SMB_DATA
SYS GPIO Power MGT
U15B PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
SATA GPIO
U15C
24 PCI_AD[31..0]
2
D
1
B
2
A
B
C
Document Number
ICH7-M (2 of 4)
Date: Wednesday, April 18, 2007
D
Volvi
Rev
-1 Sheet
E
16
of
42
1
A
B
C
D
E
Layout Note: Place near pin AA19
1D05V_S0
1
2
1
1 2
2
1 2
2 1
TP56 TPAD28 TP44 TPAD28 TP48 TPAD28
1 2
B
1
2
3D3V_S5 R375 0R0603-PAD 1 2
2 1
1D5V_S0
2
C458
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
1D5V_S0
ICH7-M (3 of 4) Size
71.ICH7M.00U
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007
A
2
1 2
1
Layout Note: Place near AB3 C501
1
2
1
RTC_AUX_S5
DY C498
1
2
1
C508
2 VccSus1_05[1]
2
1 2
1 2
1
1 2
1 2
2
1
2 1 2 2
SCD1U10V2KX-4GP
C459
C28 VccSus1_05[2] G20 VccSus1_05[3] A1 H6 H7 J6 J7
C490
C466
AB8 AC8 K7
1
1 2
1
1
2
2
1 2
1
2 1 2 1 2
1
IDE PCI
2
CORE
ICH7-M-GP
1
1 2
1
1 2
2 1 2
VccSus1_05[2] VccSus1_05[3] VccSus1_05/VccLAN1_05[1] VccSus1_05/VccLAN1_05[2]Vcc1_5_A[26] Vcc1_5_A[27] Vcc1_5_A[28] Vcc1_5_A[29] Vcc1_5_A[30]
2
1 2
1 2
1
1 2
2
1 2
1 2
USB
1 2 1
2
VccSus1_05[1]
USB CORE
1 2
1
1 2
2
2
1
1 2
1 2
2
1
1
2
2 1 1 2 2 1 1 2 1 2
Vcc1_5_A[24] Vcc1_5_A[25]
C477
DY
SC10U10V5ZY-1GP
VccLan1_05[1] AA2 Y7
T7 F17 G17
DY
C487 SC10U10V5ZY-1GP
VccUSBPLL
Vcc1_5_A[21] Vcc1_5_A[22] Vcc1_5_A[23]
C483
SCD1U10V2KX-4GP
VccSus3_3[19]
C1
AB17 AC17
C502
C467
SCD1U10V2KX-4GP
E3
Vcc1_5_A[19] Vcc1_5_A[20]
SCD1U10V2KX-4GP
Vcc1_5_A[10] Vcc1_5_A[11] Vcc1_5_A[12] Vcc1_5_A[13] Vcc1_5_A[14] Vcc1_5_A[15] Vcc1_5_A[16] Vcc1_5_A[17] Vcc1_5_A[18]
C506
C476
3D3V_S0
3D3V_S5 V3D3A_VCCPSUS R343 0R0603-PAD 2 1
3D3V_ICH_S5
3
3D3V_S0
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
TP57 TPAD28
Vcc3_3[2]
AB10 AB9 AC10 AD10 AE10 AF10 AF9 AG9 AH9
K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7
C481
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C511
VccSATAPLL
VccSus3_3[7] VccSus3_3[8] VccSus3_3[9] VccSus3_3[10] VccSus3_3[11] VccSus3_3[12] VccSus3_3[13] VccSus3_3[14] VccSus3_3[15] VccSus3_3[16] VccSus3_3[17] VccSus3_3[18]
C440
C492
SCD1U10V2KX-4GP
C517
SCD01U16V2KX-3GP
C473
AD2 AH11
A24 C24 D19 D22 G19
C488
SCD1U10V2KX-4GP
1D5V_S0
Vcc1_5_A[1] Vcc1_5_A[2] Vcc1_5_A[3] Vcc1_5_A[4] Vcc1_5_A[5] Vcc1_5_A[6] Vcc1_5_A[7] Vcc1_5_A[8] Vcc1_5_A[9]
VccSus3_3[2] VccSus3_3[3] VccSus3_3[4] VccSus3_3[5] VccSus3_3[6]
C471
SCD1U10V2KX-4GP
DY C495 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
3D3V_ICH_S5
AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5
P7
C494
SCD1U10V2KX-4GP
C461
VccDMIPLL
ATX
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0 C482
AG28
VccSus3_3[1]
3D3V_S0
SC4D7U10V5ZY-3GP
C442
Vcc3_3[1]
ARX
3D3V_S0
C465
B27
SCD1U10V2KX-4GP
C516
1D5V_S0
DY
1D5V_S0
1
R396 0R0603-PAD
1
C441
VccRTC
W5
C521
1D05V_S0
SCD1U10V2KX-4GP
68.1R220.10A
Vcc3_3[12] Vcc3_3[13] Vcc3_3[14] Vcc3_3[15] Vcc3_3[16] Vcc3_3[17] Vcc3_3[18] Vcc3_3[19] Vcc3_3[20] Vcc3_3[21]
A5 B13 B16 B7 C10 D15 F9 G11 G12 G16
3D3V_S5
SCD1U10V2KX-4GP
2 IND-1D2UH-5-GP
SCD1U10V2KX-4GP
2
1 C196
SCD01U16V2KX-3GP
1D5V_ICH_S0
1D5V_GPLL_ICH_S0
L12
SC10U10V5ZY-1GP
1D5V_S0
SCD1U10V2KX-4GP
1D5V_S0
Vcc3_3[3] Vcc3_3[4] Vcc3_3[5] Vcc3_3[6] Vcc3_3[7] Vcc3_3[8] Vcc3_3[9] Vcc3_3[10] Vcc3_3[11]
AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19
4
SCD1U10V2KX-4GP SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C512
AE23 AE26 AH26
C451
3D3V_S5
C496
3D3V_S0
C475
C472
DY
SCD1U10V2KX-4GP
C510 SCD1U16V2ZY-2GP
2
3D3V_S0
V_CPU_IO[1] V_CPU_IO[2] V_CPU_IO[3]
C474
SCD1U10V2KX-4GP
V5REF_S5
R394 100R2J-2-GP
R7
C479
SCD1U10V2KX-4GP
D12 CH751H-40PT
2nd 83.R3004.A8F
U6
C486
SCD1U10V2KX-4GP
5V_S5
Vcc3_3/VccHDA VccSus3_3/VccSusHDA
C480
SCD1U10V2KX-4GP
3D3V_S5
V5 V1 W2 W7
VCCA3GP
SCD1U16V2ZY-2GP
Layout Note: Place near ICH7
C478
VccSus3_3/VccLAN3_3[1] VccSus3_3/VccLAN3_3[2] VccSus3_3/VccLAN3_3[3] VccSus3_3/VccLAN3_3[4]
C489
SCD1U10V2KX-4GP
V5REF_S0 3
R363 100R2J-2-GP
Vcc1_5_B[1] Vcc1_5_B[2] Vcc1_5_B[3] Vcc1_5_B[4] Vcc1_5_B[5] Vcc1_5_B[6] Vcc1_5_B[7] Vcc1_5_B[8] Vcc1_5_B[9] Vcc1_5_B[10] Vcc1_5_B[11] Vcc1_5_B[12] Vcc1_5_B[13] Vcc1_5_B[14] Vcc1_5_B[15] Vcc1_5_B[16] Vcc1_5_B[17] Vcc1_5_B[18] Vcc1_5_B[19] Vcc1_5_B[20] Vcc1_5_B[21] Vcc1_5_B[22] Vcc1_5_B[23] Vcc1_5_B[24] Vcc1_5_B[25] Vcc1_5_B[26] Vcc1_5_B[27] Vcc1_5_B[28] Vcc1_5_B[29] Vcc1_5_B[30] Vcc1_5_B[31] Vcc1_5_B[32] Vcc1_5_B[33] Vcc1_5_B[34] Vcc1_5_B[35] Vcc1_5_B[36] Vcc1_5_B[37] Vcc1_5_B[38] Vcc1_5_B[39] Vcc1_5_B[40] Vcc1_5_B[41] Vcc1_5_B[42] Vcc1_5_B[43] Vcc1_5_B[44] Vcc1_5_B[45] Vcc1_5_B[46] Vcc1_5_B[47] Vcc1_5_B[48] Vcc1_5_B[49] Vcc1_5_B[50] Vcc1_5_B[51] Vcc1_5_B[52] Vcc1_5_B[53]
SCD1U10V2KX-4GP
5V_S0
D10 CH751H-40PT
2nd 83.R3004.A8F
C443 SCD1U10V2KX-4GP
3D3V_S0
C484 SCD1U10V2KX-4GP
*Within a given well, 5VREF needs to be up before the corresponding 3.3V rail
C524 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
2
C460
C491
SC10U10V5ZY-1GP
C457
AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28 D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 R25 R26 T22 T23 T26 T27 T28 U22 U23 V22 V23 W22 W23 Y22 Y23
V5REF_Sus
SCD1U10V2KX-4GP
C497
V5REF[2]
F6
SCD1U10V2KX-4GP
C507
AD17
V5REF_S5
L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
SCD1U10V2KX-4GP
C444
V5REF_S0
Vcc1_05[1] Vcc1_05[2] Vcc1_05[3] Vcc1_05[4] Vcc1_05[5] Vcc1_05[6] Vcc1_05[7] Vcc1_05[8] Vcc1_05[9] Vcc1_05[10] Vcc1_05[11] Vcc1_05[12] Vcc1_05[13] Vcc1_05[14] Vcc1_05[15] Vcc1_05[16] Vcc1_05[17] Vcc1_05[18] Vcc1_05[19] VCC PAUX Vcc1_05[20]
SCD1U10V2KX-4GP
1D5V_S0
V5REF[1]
SCD1U10V2KX-4GP
4
G10
1
U15F
C
D
Sheet E
17
of
42
A
B
C
D
E
U15E
2
1
P28 R1 R11 R12 R13 R14 R15 R16 R17 R18 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U14 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V27 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA24 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB27 AB28 AC2 AC5 AC9 AC11 AD1 AD3 AD4 AD7 AD8 AD11 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27
4
3
3D3V_S5
3D3V_S0
8 7 6 5
3
VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194]
RN64
1 2 3 4
4
VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97]
SRN4K7J-10-GP
A4 A23 B1 B8 B11 B14 B17 B20 B26 B28 C2 C6 C27 D10 D13 D18 D21 D24 E1 E2 E4 E8 E15 F3 F4 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G18 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J1 J2 J5 J24 J25 J26 K24 K27 K28 L13 L15 L24 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M17 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N14 N15 N16 N17 N18 N24 N25 N26 P3 P4 P12 P13 P14 P15 P16 P17 P24 P27
5V_S0
Q11 16,22,27 SMB_CLK
3
4
2
5
1
6 2N7002DW-1-GP
SMBC_ICH 3,11 2
84.27002.D3F 16,22,27 SMB_DATA SMBD_ICH 3,11
Q13 & Q14 connect SMLINK and SMBUS in S) for SMBus 2.0 compliance
SMBUS
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
ICH7-M-GP
71.ICH7M.00U Title
ICH7-M (4 of 4) Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
18
of
42
Digital Output Data Bits TEMP. Sign
MSB
LSB
EXT
+127.875
0
111
1111
111
+126.375
0
111
1110
011
+25.5
0
001
1001
100
+1.75
0
000
0001
110
SB 0306 Test Point FAN1_VCC FAN1_FG1 PURE_HW_SHUTDOWN#
5V_S0
TP172 TPAD30 TP100 TPAD30 TP101 TPAD30
FAN1_VCC
111
-1.125
1
111
1110
111
-25.5
1
110
0110
100
-55.25
1
100
1000
110
001
2
4
1
3
C343 SC2200P50V2KX-2GP
2
2
1
FAN1
1 D21
1
5
*Layout* 15 mil
2
C385 SC1KP50V2KX-1GP
2
1
BAS16-1-GP
3D3V_S0
U36
ALERT# THERM# THERM_SET RESET#
V_DEGREE
5 17 8 10 12
G792_DXN2 G792_DXN3 GAP-CLOSE
DGND DGND SGND1 SGND2 SGND3
1
ALERT#
R233 2
DY 0R2J-2-GP
R230 49K9R2F-L-GP G792SFUF-GP
74.00792.A79
G63
1
2
33 PURE_HW_SHUTDOWN#
C346
G1
C348
Q19 MMBT3904-3-GP B C360 SC470P50V3JN-2GP
Q5 MMBT3904-3-GP B C116 SC470P50V3JN-2GP
SC2200P50V2KX-2GP SC2200P50V2KX-2GP
3.System Sensor, Put between CPU and NB.
H_THERMDA 4
Place near chip as close as possible
2
DXP1:108 Degree (CPU) DXP2:H/W Setting 100(System) DXP3:105 Degree (SYSTEM)
C347 SC2200P50V2KX-2GP H_THERMDC 4
1 R231 2 G792_RESET# 4K7R2F-GP
1
7,16 PWROK
1.For CPU Sensor
2
R229 10KR2F-2-GP
1
D18 R444 0R0402-PAD
1
2
PURE_HW_SHUTDOWN#
3D3V_AUX_S5
R443 DY 0R2J-2-GP 2 1
DY
INTRUDER#
15
1
2
2
3
BAW56PT-U
R446 10KR2J-3-GP
RSMRST# 30
D17 BAT54-7-F-GP
2004/11/10 CHANGE
DY 3
1
-1 0411 2
1
(dummy, KBC already delay) C569 DY SCD1U16V2ZY-2GP
2
3D3V_S5
32K suspend clock output U16
1 2 3
OE A GND
DY
VCC
5
Y
4
R399 10R2J-2-GP 1 2
32KHZ
G792_32K
1
16,26,27,30,33,36,37,38,39 PM_SLP_S3# 16 PM_SUS_CLK
NC7SZ126P5X-GP
R400 240KR3-GP
RUN_POWER_ON
D
20060810
2
73.7S126.AAH
G
V_DEGREE =(((Degree-72)*0.02)+0.34)*VCC
G792_DXP2 G792_DXP3
2
2
1
THRM#
2.HW T8 sensor
SMBD_G792 26,30 SMBC_G792 26,30
C
15 13 3 2
G792_32K
C
DXP1 DXP2 DXP3
1 4 14 16 18 19
2
7 9 11
FAN1 FG1 CLK SDA SCL NC#19
1
2
C351 C349 C350 SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
1
16
Setting T8 as 90 Degree
VCC DVCC
1
1 R234 10KR2J-3-GP
2
1
1 R232 21KR2F-GP
6 20
2
SC1U16V3ZY-GP
1
5V_G792_S0 C344
MLX-CON3-10-GP
20.F1000.003
5V_S0
*Layout* 30 mil
R228
1 2 10R3J-3-GP
2
5V_S0
2 3
FAN1_FG1
000
1111
GAP-CLOSE 2
011
C342 SC4D7U6D3V3KX-GP
1
1
1
C345 SCD1U16V2ZY-2GP
-65.000
R290 10KR2J-3-GP
FAN1_VCC
*Layout* 15 mil
E
1111
E
0000
111
1
0000
000
1
2
000
0
-0.125
1
100
0
+0.125
2
+0.5
Q13
S
2N7002-11-GP
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Thermal/Fan Controllor
Document Number
Date: Wednesday, April 18, 2007
Volvi
Rev
-1 Sheet
19
of
42
ODD Connector
SATA HD Connector SATA1
5V_S0
1
C551 SCD1U16V2ZY-2GP
DEVICE_CONFIG(CSEL)
IDE_PDCS1# IDE_PDCS3#
35 36
CSIFX# CS3FX#
IDE_PDA0 IDE_PDA1 IDE_PDA2
33 31 34
DA0 DA1 DA2
2
47 15 15
2
2
RN70
SCD1U16V2ZY-2GP
5 6 7 8
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NP2 24
ODD1
SC10U10V5ZY-1GP
3D3V_S0
5V_S0
41 42
+5V(LOGIC) +5V(LOGIC)
38 39 40
+5V(MOTOR) +5V(MOTOR) +5V(MOTOR)
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
21 19 17 15 13 11 9 7 6 8 10 12 14 16 18 20
VENDER_UNIQUE#50 VENDER_UNIQUE#49
50 49
AUDIO_GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND
3 4 23 26 43 44 45 46 48
GND GND
51 52
4 3 2 1
SRN10KJ-6-GP
ODD_LED# PDIAG
15
IDE_PDIORDY 15 INT_IRQ14
TYCO-CON22-GP
20.80392.022 31
15 15 15
15
IDE_PDDREQ
27 29 22
IORDY INTRQ DMARQ
15 15
IDE_PDIOR# IDE_PDIOW#
24 25
DIOR# DIOW#
37 32 28 5 30
DASP# PDIAG# DMACK# RESET# IOCS16#
ODD_LED# 15 IDE_PDDACK# 2
3D3V_S0
R430 1 10KR2J-3-GP
PDIAG IDE_PDDACK# HDDDRV#_5
DY
1 2
AUDIO_L_CH AUDIO_R_CH
IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15
SPD-CONN50-4R-13GP-U1 5V_S0
20.80640.050
-1 0411 13
R244 12
11
2
1
HDDDRV#_5
0R0402-PAD
U2D TSAHCT125PW-GP 1
16,22,24,27 PCIRST1#
R241 10KR2J-3-GP 2
2
2
C549
DY
14
A
SC10U10V5ZY-1GP
SSM24PT-GP
DY
C578 SCD1U16V2ZY-2GP
D31
TC15
1
1
K
5V_S0
C546
7
15 SATA_RXN0 15 SATA_RXP0
1
2 3 4 5 6 7
15 SATA_TXP0 15 SATA_TXN0
1
23 NP1 1
UMA
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
HDD and CDROM
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007
Sheet
20
of
42
SB 0226 5V_USB1_S0
USBCN1
5V_S5
1
SB 0306 Test Point 3D3V_S0
U56
EC114 DY SCD1U16V2ZY-2GP
1 2 3
OUT GND NC#3
IN
5
EN
4
1
C589 SC4D7U10V5ZY-3GP 2
BLUETOOTH_EN 30
USB_5+
TP102 TPAD30
USB_5-
TP103 TPAD30
2
TP104 TPAD30
USBPP1
TP105 TPAD30
USBPN3
TP106 TPAD30
USBPP3
TP107 TPAD30
USB_OC#1
TP108 TPAD30
USB_PWR_EN#
TP109 TPAD30
21.D0214.115
EC103
DY
74.05240.A7F
30
EC142 SC220P50V2JN-3GP
5V_S5 C505
-1 0412 for EMI
5V_USB1_S0 0R0402-PAD
2
1 R138 USB2 6 1 USB_2USB_2+
USBPN2 USBPP2
2 3 4 5
-1 0412 Test Point
SKT-USB-97-UGP
22.10218.H01
-1 0410 change to 0 ohm pad Remove TR1, TR2
G5240B1T1U-GP
EC21 put near BLUE1 / all USB put one choke near connector by EMI request
USBPN1
USB_OC#1 16 USB_PWR_EN#
DY 1 2 R465 0R3-0-U-GP
3D3V_BT_S0
TP175 TPAD30
16 16
BLUETOOTH MODULE 3D3V_BT_S0
TP176 TPAD30
5V_S5
R378 1
SC1U16V3ZY-GP
SCD1U16V2ZY-2GP
17 5V_S5
2
-1 0411
JST-CON15-1-GP
2nd:74.09711.073 (RT9711-BPQW-GP)
1
0R0402-PAD
2
SB 0226
1
DY
16 16
USBPN3 16 USBPP3 16
1
74.00545.073
DY
USBPN1 USBPP1
2
G545B2RD1U-GP
1
1
1
-1 0409
1 9
GND GND
2
OC#
2
EN/EN#
5
2 3 4 5 6 7 8 9 10 11 12 13 14 15
EC30
1
1 2
DY
SCD1U16V2ZY-2GP
EC105
4
EC23
SC1000P50V3JN-GP
USB_OC#0
TC13
SCD1U16V2ZY-2GP
16
100 mil
6 7 8
OUT#6 OUT#7 OUT#8
ST100U10VDM-6GP
USB_PWR_EN#
C541
IN#2 IN#3
2
2 3
2
U47 SCD1U16V3KX-3GP 2 1
16
5V_USB1_S0
0R0402-PAD
2
1 R137
0R0402-PAD
2
1 R136
5V_USB1_S0
USB1
BLUE1 6
6 1
3D3V_BT_S0
4 3 2 1
USB_5+
R482 2
1 0R0402-PAD
USBPP5
16
USB_5-
R481 2
1 0R0402-PAD
USBPN5
16
16 16
USB_0USB_0+
USBPN0 USBPP0
2 3 4 5 SKT-USB-97-UGP
5
22.10218.H01
ACES-CON4-GP
20.F0714.004
0R0402-PAD
-1 0411
2
1 R135
3 5 7 9 11
4 6 8 10 12
18
16
C581
R464 0R0603-PAD
-1 3D3V_S5 U53 1 2 3
ACZ_BTCLK_MDC 15
1
DY
2
C579 DUMMY-C2 2
100KR2J-1-GP
1
1 1 R463
2
SC4D7U10V5ZY-3GP
20.F0757.012
2
17 AMP-CONN12A-2GP
C583
IN GND EN
OUT
5
NC#4
4
DY
ME615ASN5A15-GP
74.00615.D3F
SC1U16V3ZY-GP
NP2
C580
SC1U16V3ZY-GP
C575 SC22P50V2JN-4GP
1D5V_S5
3D3V_S5
UMA 1
2
1
15
1
DY
C585
Wistron Corporation
2
ACZ_SYNC 1 2ACSDATAIN1_A R461 39R2J-L-GP ACZ_RST#
13
1D5V_S5
1
15,28 ACZ_SYNC 15 ACZ_SDATAIN1 15,28 ACZ_RST#
ACZ_SDATAOUT
2
15,28 ACZ_SDATAOUT
14
2
MDC1 NP1
SC4D7U10V5ZY-3GP 1 2
MDC 1.5 CONN
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
USB / MDC / BLUETOOTH
Document Number
Volvi
Date: Wednesday, April 18, 2007
Rev
-1 Sheet
21
of
42
5
4
3
2
1
1 2
GPIO2
PCIE_RXDP PCIE_RXDN
26 25 31 32 12 10 29 28
UART_MODE GPIO1_SERIALDI GPIO0_SERIALDO
9 7 4
UART_MODE EE_WP GPIO0
3D3V_LAN_S5
Q4 BCP69T1-1-GP
-1 0411
C56
1 2
1 2
1 2 1 2 1 2
1
1
1
2
2
68.00217.241
GPHY_PLLVDD 1
1
1
2
C48
2
PCIE_PLLVDD C62
2 R286 1 0R0402-PAD
1
2 R62 1 0R0402-PAD
2
R313 C420 SC4D7U10V5ZY-3GP FCM1608K-601T03GP C381 68.00217.241
2
1
1
C
D
Volvi Block Diagram Yonah 478 Celeron M
ICS 9LPRS502 (RTM875T-605) 3 71.09502.00W
62.10079.001
HOST BUS 533/667MHz
533/667 MHz
5V_S5 DCBATOUT
4
20
SYSTEM DC/DC MAX8717 37
PCB STACKUP
TV Out
4, 5
400/533/[email protected]
TOP
14
INPUTS DCBATOUT
1D05V_S0
S
LCD
TPS51100
S
13
1D8V_S3
GND BOTTOM
APL5312
LVDS, CRT I/F
533/667MHz
71.CALIS.00U
13,14
VGA Borad
6,7,8,9,10
X4 DMI 400MHz
2D5V_S0
26
C-Link0
APL5912 1D8V_S3
Codec
AZALIA
ICH7M
ALC268 28
PCI/PCI BRIDGE
14
OZ129 1394 CardReader
PCI BUS
ACPI 2.0 2 SATA
1394 CONN
INPUTS 25
BT+
MS/MS Pro/xD/ MMC/SD
24
5 in 1
DCBATOUT
INT.SPKR
5V
High Definition Audio
Giga LAN
LPC I/F
BCM5787MKMLG
22
TXFM
MAX8770
23
INPUTS
OP AMP G1412
PCIex1
Kedron a/b/g/n
MODEM MDC Card
71.ICH7M.00U
15,16,17,18
HDD 20
USB
PATA
PCI Express
SATA
21
28
100mA
2
VCC_CORE 0~1.3V 48A
LPC BUS
MINI USB BlueTooth
KBC
20
SPI I/F
Winbond 22
WPC8768L
MEDIA BD
CDROM
DCBATOUT
27
35
OUTPUTS
Mini Card
29
P2231NFC1
4.0A
CPU DC/DC
RJ45
23
Serial Peripheral I/F
1
18V
UP+5V
25
ETHERNET (10/100/1000MbE)
G1431Q 29
New card27
40
OUTPUTS
8 USB 2.0/1.1 ports
Line Out (No-SPDIF)
31
Touch Pad 31
32
30
INT. KB 31
BIOS W25X80-VSS
LPC
DEBUG CONN. 32 UMA
1
CIR 31
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
USB 4 Port21
Title
BLOCK DIAGRAM
CAMERA
Size A3
13
Document Number
Date: Wednesday, April 18, 2007
A
3
1D5V_S0
MAX8731
Cardreader
1 PATA 66/100
OP AMP
38
Intersil CHARGER
4 PCIe ports
MIC In
39
3D3V_S0
Line In
RJ11
39
DDR_VREF
DDR Memory I/F
533/667 MHz
31
OUTPUTS 1D8V_S3
VCC
CRT
INTEGRATED GRAHPICS
DDR2 3
OUTPUTS
G792
Calistoga AGTL+ CPU I/F
13,14
36
MAX8744 INPUTS
3V_S5
14
DDR2
E
SYSTEM DC/DC
Project code: 91.4U701.001 PCB P/N : 07200 REVISION : -1
Mobile CPU
CLK GEN.
4
2
B
B
C
D
Rev
-1
Volvi Sheet
E
1
of
43
4
3
A
B
ICH7M Functional Strap Definitions ICH8-M EDS 21762 Usage/When Sampled
Signal HDA_SDOUT
2.0V1
C page 16
Comment
PCIE config1 bit0, Rising Edge of PWROK.
This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h)
GNT2#
PCIE config2 bit0, Rising Edge of PWROK.
GPIO20
Reserved
This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high.
GNT1#/ GPIO51
GNT3#
GNT0#/ SPI_CS1#
INTVRMEN
ESI Strap (Server Only) ESI compatible mode is for server platforms only. This signal should not be pulled low for desttop Rising Edge of PWROK and mobile. Top-Block Swap Override. Rising Edge of PWROK.
Boot BIOS Destination Selection. Rising Edge of PWROK. Integrated VccSus1_05, VccSus1_5 and VccCL1_5 VRM Enable/Disable. Always sampled.
Integrated VccLAN1_05 LAN100_SLP and VccCL1_05 VRM Enable/Disable. Always sampled.
Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. Enables integrated VccSus1_05, VccSus1_5 and VccCL1_5 VRM's when sampled high
Enables integrated VccLAN1_05 and VccCL1_05 VRM's when sampled high
PCI Express Lane Reversal. Rising Edge of PWROK. No Reboot. Rising Edge of PWROK.
Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8)
TP3
XOR Chain Entrance. Rising Edge of PWROK.
This signal should not be pull low unless using XOR Chain testing.
GPIO33/ HDA_DOCK _EN#
This signal has a weak internal pull-up. Flash Descriptor Security Override Strap Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be Rising Edge of PWROK in effect.This should only be used in manufacturing environments.
SATALED# SPKR
ICH7M Integrated Pull-up and Pull-down Resistors
Allows entrance to XOR Chain testing when TP3 XOR Chain Entrance/ PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: Rising Edge of PWROK offset 224h)
HDA_SYNC
D
If sampled high, the system is strapped to the "No Reboot" mode(ICH8 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.
ICH8-M EDS 21762
SIGNAL
E
Crestline Strapping Signals and Crestline EDS 20954 Configuration page 7 2.0V1
Resistor Type/Value
Pin Name
Strap Description
CFG[2:0]
FSB Frequency Select
HDA_BIT_CLK
PULL-DOWN 20K
HDA_RST#
NONE
HDA_SDIN[3:0]
PULL-DOWN 20K
CFG[4:3]
Reserved
HDA_SDOUT
PULL-DOWN 20K
CFG5
DMI x2 Select
HDA_SYNC
PULL-DOWN 20K
CFG[8:6]
Reserved
GNT[3:0]
PULL-UP 20K
GPIO[20]
PULL-DOWN 20K
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
LAN_RXD[2:0]
PULL-UP 10K
LDRQ[0]
PULL-UP 20K
LDRQ[1]/GPIO23
PULL-UP 20K
PME#
PULL-UP 20K
PWRBTN#
PULL-UP 20K
SATALED#
PULL-UP 15K
SPI_CS1#
PULL-UP 20K
SPI_CLK
PULL-UP 20K
SPI_MOSI
PULL-UP 20K
SPI_MISO
PULL-UP 20K
TACH_[3:0]
PULL-UP 20K
SPKR
PULL-DOWN 20K
TP[3]
PULL-UP 20K
USB[9:0][P,N]
PULL-DOWN 15K
CL_RST#
PULL-UP 13K
1.0
Configuration 001 = FSB533 011 = FSB667 010 = FSB800 others = Reserved
4
0 = DMI x2 1 = DMI x4 (Default)
Low Power PCI Express
0 = Normal mode 1 = Low Power mode
CFG9
PCI Express Graphics Lane Reversal
0 = Reverse Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane Numbered in order
CFG[11:10]
Reserved
CFG[13:12]
XOR/ALL Z test straps
CFG[15:14]
Reserved
CFG16
FSB Dynamic ODT
00 01 10 11
= = = =
(Default)
Reserved XOR mode enabled All Z mode enabled Normal Operation (Default)
Reserved 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default)
CFG[18:17]
Reserved
CFG19
DMI Lane Reversal
3
0 = Normal operation (Default):lane Numbered in order 1 =Reverse Lane,4->0,3->1 ect...
CFG20
SDVO/PCIE Concurrent
0 = Only SDVO or PCIE x1 is operational (Default) 1 =SDVO and PCIE x1 are operating simultaneously via the PEG port
SDVOCRTL _DATA
SDVO Present
0 = No SDVO Card present (Default) 1= SDVO Card present
NOTE: All strap signals are sampled with respect to the leading edge of the Crestline GMCH PWORK in signal.
History
2
2
ICH7M IDE Integrated Series Termination Resistors DD[15:0], DIOW#, DIOR#, DREQ, approximately 33 ohm DDACK#,
IORDY, DA[2:0], DCS1#,
DCS3#, IDEIRQ
PCIE Routing
USB Table
LAN BCM5787M
USB ports definition
LANE2
MiniCard WLAN
Pair
LANE3
NewCard WLAN
LANE1
1
Device
0
USB1
1
USB3
2
USB2
3
USB4
4
PCI Routing IDSEL OZ129 AD22
page 16
INT
REQ
GNT
INT_PIRQG#
PCI_REQ#0
PCI_GNT#0
1
UMA
Wistron Corporation
MINICARD
5
BlueTooth
6
CCD
7
NewCard
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Reference Size A3
Document Number
Date: Wednesday, April 18, 2007
A
B
C
D
Rev
-1
Volvi Sheet
E
2
of
42
B
2
1
1
1
1 2
2
2
1
1 2
1 2
1 2
1 2
H/L: 100/96MHz 1
PCLK_KBC
2 R328
1 33R2J-2-GP
PCLKKBC
PCLK_PCM
2 R331
1 33R2J-2-GP
PCLKPCM
56 3 4 5
1 33R2J-2-GP
SS_SEL PCLKICH
9 8
2
24
-1 0411 Del R321 2 R329
CLK_ICHPCI
PCI_2/REQ_SEL PCI_3 PCI_4 PCI_5 PCIF_1/DOT96SS_SEL# PCIF_0/ITP_EN
1
16
2
R327 10KR2J-3-GP
CL=20pF±0.2pF C188 SC27P50V2JN-2-GP 1 2
7 7
X2
46 47
SCLK SDATA
DREFCLK_1 DREFCLK#_1
14 15
DOT96 DOT96#
GEN_XTAL_IN GEN_XTAL_OUT
50 49
X1 X2
0R0402-PAD
52 39
REF_0 IREF
10
VTT_POWER_GOOD#/PWRDWN
1 R119
2
PCI_STOP#
X-14D31818M-44GP 2
PCLK_PCM
2
11,18 SMBC_ICH 11,18 SMBD_ICH
RN31 SRN33J-5-GP-U 3 UMA 2 4 1
DREFCLK DREFCLK#
82.30005.951 1
16 PM_STPPCI#
55
-1 0413
1
SB 0313 for EMI
16
CLK_ICH14
GEN_XTAL_OUT_R
C189 SC27P50V2JN-2-GP
35
CLK_EN#
GEN_REF 2 R320 1 22R2J-2-GP GEN_IREF 2 R311 1 475R2F-L1-GP R319 2 1 0R2J-2-GP
3D3V_S0
DY
1
2
2
R323 10KR2J-3-GP EC129 SC22P50V2JN-4GP
1
RN27 SRN33J-5-GP-U 3 4
CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7
CLK_PCIE_ICH_1 2 CLK_PCIE_ICH_1# 1
RN25 SRN33J-5-GP-U 3 4
CLK_PCIE_ICH 16 CLK_PCIE_ICH# 16
CLK_PCIE_NEW_R 2 CLK_PCIE_NEW#_R 1
RN23 SRN33J-5-GP-U 3 4
CLK_PCIE_NEW 27 CLK_PCIE_NEW# 27
CLK_PCIE_SATA_1 2 CLK_PCIE_SATA_1#1
RN21 SRN33J-5-GP-U 3 4
CLK_PCIE_SATA 15 CLK_PCIE_SATA# 15
4
RN22
SRN33J-5-GP-U 4 CLK_PCIE_LAN 22 3 CLK_PCIE_LAN# 22
RN24
SRN33J-5-GP-U 4 CLK_PCIE_MINI1 27 3 CLK_PCIE_MINI1# 27
RN26
SRN33J-5-GP-U 4 CLK_PCIE_PEG 26 3 CLK_PCIE_PEG# 26
U10 30
SS_SEL
2
CLK_MCH_3GPLL_1 2 CLK_MCH_3GPLL_1# 1
CLK_PCIE_LAN_R 1 CLK_PCIE_LAN#_R 2
R325 10KR2J-3-GP
DY
DREFSSCLK 7 DREFSSCLK# 7
C412
3D3V_S0
3
RN29 SRN33J-5-GP-U UMA 3 4
C396 SCD1U16V2ZY-2GP
1
C425 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
C408
2 1
DREFSSCLK_1 DREFSSCLK#_1
SCD1U16V2ZY-2GP
SC4D7U6D3V3KX-GP
C392 SC1U16V3ZY-GP
C393
C399 SCD1U16V2ZY-2GP
3D3V_S0 R291 0R0603-PAD 1 2
C430 SCD1U16V2ZY-2GP
-1 0412
3D3V_CLKPLL_S0
DY
C416 SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
4
E
3D3V_S0 R297 0R0603-PAD 1 2
3D3V_CLKGEN_S0
C422 SC1U16V3ZY-GP
C426
D
2
3D3V_S0 R318 0R3-0-U-GP 2 1
3D3V_48MPWR_S0
DY
C
-1 0412
1
-1 0413
2
A
RN58 SRN49D9F-GP 4 3
DREFSSCLK# DREFSSCLK
1 2
DREFCLK# DREFCLK
RN60 SRN49D9F-GP 1 4 2 3
CLK_CPU_BCLK# CLK_CPU_BCLK
RN59 SRN49D9F-GP 1 4 2 3
CLK_MCH_BCLK CLK_MCH_BCLK#
1 2
RN57 SRN49D9F-GP 4 3
CLK_PCIE_SATA CLK_PCIE_SATA#
2 1
RN49 SRN49D9F-GP 3 4
CLK_MCH_3GPLL 2 CLK_MCH_3GPLL# 1
RN56 SRN49D9F-GP 3 4
CLK_PCIE_ICH CLK_PCIE_ICH#
2 1
RN54 SRN49D9F-GP 3 4
CLK_PCIE_MINI1 CLK_PCIE_MINI1#
RN53 SRN49D9F-GP 1 4 2 3
2 6 51 45 38 13 29
GND_PCI GND_PCI GND_REF GND_CPU GND_CORE GND_48 GND_SRC
SRC_0/DOT96SS SRC_0#/DOT96SS#
17 18
DREFSSCLK_1 DREFSSCLK#_1
SRC_1 SRC_1# SRC_2 SRC_2# SRC_3 SRC_3# SRC_4_SATA SRC_4_SATA# SRC_5 SRC_5# SRC_6/PCIE_REQ_1# SRC_6#/PCIE_REQ_2#
19 20 22 23 24 25 26 27 31 30 33 32
CLK_MCH_3GPLL_1 CLK_MCH_3GPLL_1# CLK_PCIE_ICH_1 CLK_PCIE_ICH_1# CLK_PCIE_NEW_R CLK_PCIE_NEW#_R CLK_PCIE_SATA_1 CLK_PCIE_SATA_1# CLK_PCIE_LAN_R CLK_PCIE_LAN#_R CLK_PCIE_MINI_1 CLK_PCIE_MINI_1#
CPU_2_ITP/SRC_7 CPU_2_ITP#/SRC_7#
36 35
CLK_PCIE_PEG_1 CLK_PCIE_PEG_1#
CPU_0 CPU_0# CPU_1 CPU1_#
44 43 41 40
CLK_CPU_BCLK_1 CLK_CPU_BCLK_1# CLK_MCH_BCLK_1 CLK_MCH_BCLK_1#
CPU_STOP# FSC/TEST_SEL/REF_1 FSB/TEST_MODE USB48MHZ/FSA
54 53 16 12
VDD_3.3_SRC VDD_3.3_SRC
34 21
VDD_3.3_PCI VDD_3.3_PCI
7 1
VDD_3.3_REF VDD_3.3_CPU VDD_3.3_CORE VDD_3.3_48M VDD_3.3_SRC
48 42 37 11 28
CLK_PCIE_MINI_1 1 CLK_PCIE_MINI_1# 2
CLK_PCIE_PEG_1 1 CLK_PCIE_PEG_1# 2
MXM RN30
SRN33J-5-GP-U 4 CLK_CPU_BCLK 4 3 CLK_CPU_BCLK# 4
RN28
SRN33J-5-GP-U 4 CLK_MCH_BCLK 6 3 CLK_MCH_BCLK# 6
CLK_CPU_BCLK_1 1 CLK_CPU_BCLK_1# 2
CLK_MCH_BCLK_1 1 CLK_MCH_BCLK_1# 2
3
PM_STPCPU# 16
CPU_SEL2_R CPU_SEL1_R CLK48
2 R324 1 2K2R2J-2-GP 2 R314 1 2K2R2J-2-GP 2 R317 1 22R2J-2-GP 2 R316 1 2K2R2J-2-GP
CPU_SEL2 4,7 CPU_SEL1 4,7 CLK48_ICH 16 2
CPU_SEL0 4,7
3D3V_CLKPLL_S0 3D3V_48MPWR_S0 3D3V_CLKGEN_S0
RTM865T-433-GP CLK_PCIE_NEW CLK_PCIE_NEW#
RN52 SRN49D9F-GP 2 3 1 4
71.00865.B0W
RN51 SRN49D9F-GP CLK_PCIE_LAN# 2 3 CLK_PCIE_LAN 1 4
FSC
FSB
FSA
CPU
FSB
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
266M 133M 200M 166M 333M 100M 400M Reserved
X 533M X 667M X X X X
EMI 1
CLK_ICH14
EC19 1
DY 2 SC10P50V2JN-4GP
SB 0313 for EMI PCLK_KBC
EC86 1
2 SC22P50V2JN-4GP
CLK_ICHPCI
EC21 1
DY 2 SC10P50V2JN-4GP
CLK48_ICH
EC15 1
DY 2 SC10P50V2JN-4GP
CLK_PCIE_PEG CLK_PCIE_PEG#
RN55 SRN49D9F-GP 1 4 2 MXM 3
UMA
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Clock Generator Size
Document Number
Rev
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
-1 Sheet E
3
of
42
A
B
C
D
E
H_DINV#[3..0] TP5
TPAD30
U39A
D21 A24 A25
THERMTRIP#
H_TRDY# 6
1D05V_S0 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#
TP23 TP18 TP22 TP21 TP19 TP6
A22 A21
RSVD[12]
T22
RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17] RSVD[18] RSVD[19] RSVD[20]
D2 F6 D3 C1 AF1 D22 C23 C24
TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30
CPU_PROCHOT#_R H_THERMDA 19 H_THERMDC 19
C7
BCLK[0] BCLK[1]
6 6
6 6 6
R280 56R2J-4-GP
H_THERMDC
C362 SC2200P50V2KX-2GP
1D05V_S0
R330 1KR2J-1-GP
6 6 6
R332 2KR2F-3-GP
2nd source: 62.10053.401
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#
N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26
D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
AD26
GTLREF
C173
DY
2
62.10079.001
H_DSTBN#1 H_DSTBP#1 H_DINV#1
CPU_GTLREF0 SC1KP50V2KX-1GP
RSVD[11]
PM_THRMTRIP# should connect to ICH7 and Calistoga without T-ing ( No stub)
BGA479-SKT6-GPU3
2
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
H_THERMDA
PM_THRMTRIP-A# 7,33
CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3
H_DSTBN#0 H_DSTBP#0 H_DINV#0
E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 H23 G22 J26
Layout Note: 0.5" max length.
TEST1 C26 1KR2J-1-GP TEST2 D25 51R2F-2-GP
1 R61 1 R270
DY
3,7 3,7 3,7
CPU_SEL0 CPU_SEL1 CPU_SEL2
2 2
B22 B23 C21
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]#
AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#
AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
DATA GRP 2
PROCHOT# THERMDA THERMDC
XDP/ITP SIGNALS
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
U39B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
6
DATA GRP 3
CONTROL
G6 E4
THERM
ADDR GROUP 1
B25
HIT# HITM#
Place testpoint on H_IERR# with a GND 0.1" away
1
RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]
B1 F3 F4 G3 G2
H_INIT# 15
2
AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3
RESET# RS[0]# RS[1]# RS[2]# TRDY#
H_LOCK# 6 H_CPURST# 6,31 H_RS#[2..0]
1
STPCLK# LINT0 LINT1 SMI#
H4
2
D5 C6 B4 A3
LOCK#
BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
4
2
15 H_STPCLK# 15 H_INTR 15 H_NMI 15 H_SMI#
H_IERR#
H_HIT# H_HITM#
6
R80 56R2J-4-GP
1
A20M# FERR# IGNNE#
IERR# INIT#
D20 B3
H_RS#0 H_RS#1 H_RS#2
H_D#[63..0]
1D05V_S0
1
15 H_A20M# 15 H_FERR# 15 H_IGNNE#
A6 A5 C4
3
A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]#
H_BREQ#0 6
6
1
6 H_ADSTB#1
Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4
F1
6
H_DSTBP#[3..0]
2
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
H_DEFER# 6 H_DRDY# 6 H_DBSY# 6
2
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#
H5 F21 E1
6 6 6
1
K3 H2 K2 J3 L5
H_ADSTB#0 H_REQ#[4..0]
BR0#
H CLK
6 6
DEFER# DRDY# DBSY#
H_ADS# H_BNR# H_BPRI#
DATA GRP 1
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
4
ADS# BNR# BPRI#
H1 E2 G5
DATA GRP 0
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
H_A#[31..3]
ADDR GROUP 0
J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2
RESERVED
6
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
6
H_DSTBN#[3..0]
MISC
TEST1 TEST2 BSEL[0] BSEL[1] BSEL[2]
COMP[0] COMP[1] COMP[2] COMP[3]
R26 U26 U1 V1
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
E5 B5 D24 D6 D7 AE6
H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 3
H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3
R287 R309 R96 R102
1 1 1 1
2 2 2 2
27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP
H_DPRSTP# 15,35 H_DPSLP# 15 H_DPWR# 6 H_PWRGD 15,31,33 H_CPUSLP# 6,15 PSI# 35
2
BGA479-SKT6-GPU3 Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .
62.10079.001
2nd source: 62.10053.401 1D05V_S0
R111 1
DY
2 39D2R3F-2-GP
XDP_TDO
R110 1
DY
2 54D9R2F-L1-GP
H_CPURST#
R54
1
XDP_DBRESET# R64
1
2 54D9R2F-L1-GP 3D3V_S0
1
DY
2 150R2F-1-GP
XDP_TCK
R112 1
2 27D4R2F-L1-GP
XDP_TRST#
R113 1
2 680R3F-GP
H_INIT# 1
XDP_TMS
2 150R2F-1-GP
DY 2
R107 1
C66 SC4700P50V2KX
XDP_TDI
UMA
1
All place within 2" to CPU
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (1 of 2) Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
4
of
42
A
B
C
D
E
U39D A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VCC_CORE_S0
VCC_CORE_S0 U39C
SCD1U10V2KX-4GP
1D5V_VCCA_S0
1D5V_S0
2
2
1 2
1
C127
2
1
C126
2
1 2
1 2
1 2
1 2
1
C96
SC4D7U6D3V3KX-GP
VCC_CORE_S0
1 2
1
C54 SC10U10V5ZY-1GP
2
1
C169 SC10U10V5ZY-1GP
2
1
C167 SC10U10V5ZY-1GP
2
1
C164 SCD1U10V2KX-4GP
2
C85 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.
C165
DY
2
C84
2
VCCSENSE and VSSSENSE lines should be of equal length.
2
R118 100R2F-L1-GP-U
1
Layout Note:
1
62.10079.001
C162
SC4D7U6D3V3KX-GP
VSS_SENSE 35
C142
SCD1U10V2KX-4GP
AE7
C154
SCD1U10V2KX-4GP
VSSSENSE
C104
SCD1U10V2KX-4GP
VCC_SENSE 35
C99
68.00230.041
SCD1U10V2KX-4GP
AF7
35 VCC_CORE_S0 35 35 35 35 R117 35 100R2F-L1-GP-U 35
SCD1U10V2KX-4GP
VCCSENSE
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
SCD1U10V2KX-4GP
AD6 AF5 AE5 AF4 AE3 AF2 AE2
2 HCB1608KF121T30-GP
C370
2
C372
1
1 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
BGA479-SKT6-GPU3
1D05V_S0
L19
2
B26
1 R95 2 0R0402-PAD C161
1
VCCA
1D05V_CPU_V6
1
V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
1
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
Layout Note 1D05V_S0
SC4D7U6D3V3KX-GP
2
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
1
3
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
2
4
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
SCD01U16V2KX-3GP
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24
4
3
2
BGA479-SKT6-GPU3
62.10079.001
1
C129
DY 2
1
DY 2
1 2
1
C177
C170 SC10U10V5ZY-1GP
DY
SC10U10V5ZY-1GP
2
1
C151
SC10U10V5ZY-1GP
DY
SC10U10V5ZY-1GP
2
1
C183 SC10U10V5ZY-1GP
2
1
C108 SC10U10V5ZY-1GP
2
1
C184 SC10U10V5ZY-1GP
2
1
C128 SC10U10V5ZY-1GP
2
1
C182 SC10U10V5ZY-1GP
2
1
C152 SC10U10V5ZY-1GP
2
1
C168 SC10U10V5ZY-1GP
2
1
C109 SC10U10V5ZY-1GP
2
1
C53 SC10U10V5ZY-1GP
2
C73 SC10U10V5ZY-1GP
1
C72 SC10U10V5ZY-1GP
2
1
VCC_CORE_S0
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (2 of 2) Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
5
of
42
A
B
C
D
E
1
H_XRCOMP
R272 24D9R2F-L-GP
2
2
3
C355 SCD1U16V2ZY-2GP
1
1
H_XSWING R248 100R2F-L1-GP-U
1
H_YRCOMP
2
R281 24D9R2F-L-GP
2
1D05V_S0
R275 54D9R2F-L1-GP 1
2
H_YSCOMP
1
1D05V_S0
H_XRCOMP H_XSCOMP H_XSWING
H_YRCOMP H_YSCOMP H_YSWING
Y1 U1 W1
H_YRCOMP H_YSCOMP H_YSWING
3 CLK_MCH_BCLK 3 CLK_MCH_BCLK#
AG2 AG1
H_CLKIN H_CLKIN#
1
2
2
C374
CALISTOGA
SCD1U16V2ZY-2GP
R279 100R2F-L1-GP-U
1
E1 E2 E4
H_YSWING
1
2
R277 221R2F-2-GP
H_XRCOMP H_XSCOMP H_XSWING
71.CALIS.00U
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF_0 H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# H_VREF_1
E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13
1D05V_S0
H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4
R70 100R2F-L1-GP-U H_VREF
3
H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_CPURST# 4,31 H_DBSY# 4 H_DEFER# 4 H_DPWR# 4 H_DRDY# 4
J7 W8 U3 AB10
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
K4 T7 Y5 AC4
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
K3 T6 AA5 AC5
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_HIT# H_HITM# H_LOCK#
D3 D4 B3
H_HIT# 4 H_HITM# 4 H_LOCK# 4
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
D8 G8 B8 F8 A8
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#_0 H_RS#_1 H_RS#_2
B4 E6 D6
H_RS#0 H_RS#1 H_RS#2
H_SLPCPU# H_TRDY#
E3 E7
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
4
1
2
R263 221R2F-2-GP
4
2
1
1D05V_S0
H_A#[31..3]
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
H_DINV#[3..0]
4
H_DSTBN#[3..0]
4
H_DSTBP#[3..0]
4
C74
1
H_XSCOMP
H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14
R65 200R2F-L-GP 2
1
R59 54D9R2F-L1-GP
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31
2
2
1D05V_S0
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
1
4
F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8
SCD1U16V2ZY-2GP
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
HOST
U38A
H_D#[63..0]
2
4
2
H_REQ#[4..0]
H_RS#[2..0]
4
4
H_CPUSLP# 4,15 H_TRDY# 4
DIS :PM945 KI.94501.006 UMA :GM945 KI.94501.005
Place them near to the chip ( < 0.5")
UMA
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Document Number
GMCH (1 of 5)
Date: Wednesday, April 18, 2007 A
B
C
D
Volvi
Rev
-1 Sheet E
6
of
42
A
B
C
D
E
U38B
AU20 AT20 BA29 AY29
SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3
11,12 11,12 11,12 11,12
M_CS0# M_CS1# M_CS2# M_CS3#
AW13 AW12 AY21 AW21
SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3
BA13 BA12 AY20 AU21
SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3
1
SM_OCDCOMP_0 SM_OCDCOMP_1
DY
2
2
R106 R92 40D2R2F-GP 40D2R2F-GP
DY
11,12 11,12 11,12 11,12
M_RCOMPN M_RCOMPP
1 2
C419 3 CLK_MCH_3GPLL# 3 CLK_MCH_3GPLL 3 DREFCLK# 3 DREFCLK 3 DREFSSCLK# 3 DREFSSCLK
AV9 AT9
SM_RCOMP# SM_RCOMP
AK1 AK41
SM_VREF_0 SM_VREF_1
AF33 AG33 A27 A26 C40 D41
G_CLKIN# G_CLKIN D_REFCLKIN# D_REFCLKIN D_REFSSCLKIN# D_REFSSCLKIN
3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
16 16 16 16
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
AE37 AF41 AG37 AH41
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
16 16 16 16
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
AC37 AE41 AF37 AG41
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
SDVO_CTRLCLK SDVO_CTRLDATA LT_RESET# NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18
DMI
AC35 AE39 AF35 AG39
PM_EXTTS#0 PM_EXTTS#1 CALISTOGA
1D8V_S3
13 GMCH_LCDVDD_ON
1 2
CPU_SEL0 3,4 CPU_SEL1 3,4 CPU_SEL2 3,4
UMA
-1 0411 CFG9
4 3 13 13 13 13
RN15 SRN0J-6-GP
GMCH_TXACLKGMCH_TXACLK+ GMCH_TXBCLKGMCH_TXBCLK+
13 GMCH_TXAOUT013 GMCH_TXAOUT113 GMCH_TXAOUT2-
R504 1 2 0R0402-PAD
-1 0411
LA_CLK# LA_CLK LB_CLK# LB_CLK
C37 B35 A37
LA_DATA#_0 LA_DATA#_1 LA_DATA#_2
B37 B34 A36
LA_DATA_0 LA_DATA_1 LA_DATA_2
13 GMCH_TXBOUT013 GMCH_TXBOUT113 GMCH_TXBOUT2-
G30 D30 F29
LB_DATA#_0 LB_DATA#_1 LB_DATA#_2
F30 D29 F28
LB_DATA_0 LB_DATA_1 LB_DATA_2
G28 PM_BMBUSY# 16 F25 PM_EXTTS#0 13 GMCH_TXBOUT0+ R305 0R2J-2-GP H26 PM_EXTTS#1 13 GMCH_TXBOUT1+ G6 PM_THRMTRIP-A# 4,33 13 GMCH_TXBOUT2+ 1 2 AH33 PWROK_GD DY VGATE_PWRGD 16,35 R298 0R0402-PAD AH34 RSTIN# 1 2 PWROK 16,19 R93 1 2 PLT_RST1# 16,26,30 TP8 TPAD30 100R2J-2-GP H28 CTRLCLK 14 TV_DACA TP7 TPAD30 C157 H27 CTRLDATA 14 TV_DACB K28 DY MCH_ICH_SYNC# 16 14 TV_DACC D1 C41 C1 BA41 BA40 BA39 BA3 BA2 BA1 B41 B2 AY41 AY1 AW41 AW1 A40 A4 A39 A3
A33 A32 E27 E26
13 GMCH_TXAOUT0+ 13 GMCH_TXAOUT1+ 13 GMCH_TXAOUT2+
A16 C18 A19
SC100P50V2JN-3GP
R69 1 1 4K99R2F-L-GP UMA 1 R43 0R2J-2-GP UMA 1 R45 0R2J-2-GP UMA R44 0R2J-2-GP UMA
2 2 2 2
TV_IREF J20 TV_IRTNA B16 TV_IRTNB B18 TV_IRTNC B19
TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC
3D3V_S0
E23 D23 C22 B22 A21 GMCH_RGB# B21
14 GMCH_BLUE 14 GMCH_GREEN RN10 SRN10KJ-5-GP
14 GMCH_RED 2 1D05V_S0
1
MXM
R262 0R2J-2-GP
14 GMCH_DDCCLK 14 GMCH_DDCDATA 14 GMCH_HSYNC
CRT_IREF
14 GMCH_VSYNC
71.CALIS.00U
C26 C25 G23 J22 H23
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC
1
2
LIBG L_LVBG
TPAD30 TP3
L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL
VGA
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
13 CLK_DDC_EDID 13 DAT_DDC_EDID
D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32
TV
16 16 16 16
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
NC
RN11 SRN10KJ-5-GP 1 4 2 3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
MISC
3D3V_S0
16 16 16 16
AE35 AF39 AG35 AH39
PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 PM_THRMTRIP# PWROK RSTIN#
PM
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
1
DDR_VREF_S3
C415
M_ODT0 M_ODT1 M_ODT2 M_ODT3
CFG
AL20 AF10
LCTLA_CLK LCTLB_DATA
LVDS
1
M_OCDCOMP0 M_OCDCOMP1
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26
L_BKLTCTL GMCH_BL_ON
GRAPHICS
M_CKE0 M_CKE1 M_CKE2 M_CKE3
13 30
R77
PCI-EXPRESS
11,12 11,12 11,12 11,12
1D05V_S0 U38C L_BKLTCTL
1
SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3
2
AW35 AT1 AY7 AY40
for calistoga configuration
3 4
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
H32 T32 R32 F3 F7 AG11 AF11 H7 J19 K30 J29 A41 A35 A34 D28 D27
2 1
11 11 11 11
RSVD_0 RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15
MUXING
SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3
DDR
AY35 AR1 AW7 AW40
CLK
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
RSVD
4
11 11 11 11
2
R114 80D6R2F-L-GP
PEG_CMP 2
1 24D9R2F-L-GP
EXP_A_COMPI EXP_A_COMPO
D40 D38
EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8 EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15
F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38
PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0
EXP_A_RXP_0 EXP_A_RXP_1 EXP_A_RXP_2 EXP_A_RXP_3 EXP_A_RXP_4 EXP_A_RXP_5 EXP_A_RXP_6 EXP_A_RXP_7 EXP_A_RXP_8 EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15
D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38
PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0
EXP_A_TXN_0 EXP_A_TXN_1 EXP_A_TXN_2 EXP_A_TXN_3 EXP_A_TXN_4 EXP_A_TXN_5 EXP_A_TXN_6 EXP_A_TXN_7 EXP_A_TXN_8 EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12 EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15
F36 GTXN0 G40 GTXN1 H36 GTXN2 J40 GTXN3 L36 GTXN4 M40 GTXN5 N36 GTXN6 P40 GTXN7 R36 GTXN8 T40 GTXN9 V36 GTXN10 W40 GTXN11 Y36 GTXN12 AA40 GTXN13 AB36 GTXN14 AC40 GTXN15
1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C45 C57 C43 C58 C60 C67 C83 C90 C94 C102 C113 C120 C130 C136 C145 C150
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
EXP_A_TXP_0 EXP_A_TXP_1 EXP_A_TXP_2 EXP_A_TXP_3 EXP_A_TXP_4 EXP_A_TXP_5 EXP_A_TXP_6 EXP_A_TXP_7 EXP_A_TXP_8 EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15
D36 GTXP0 F40 GTXP1 G36 GTXP2 H40 GTXP3 J36 GTXP4 L40 GTXP5 M36 GTXP6 N40 GTXP7 P36 GTXP8 R40 GTXP9 T36 GTXP10 V40 GTXP11 W36 GTXP12 Y40 GTXP13 AA36 GTXP14 AB40 GTXP15
1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM 1 MXM
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C39 C50 C37 C51 C52 C65 C76 C87 C89 C98 C110 C114 C121 C131 C138 C144
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
PEG_RXN[15..0]
26 4
PEG_RXP[15..0] 26
PEG_TXN[15..0] 26 3
PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TXP[15..0] 26
PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
2
CALISTOGA
71.CALIS.00U
M_RCOMPN LCTLA_CLK LCTLB_DATA
1 2
RN12 SRN10KJ-5-GP 4 UMA 3
GMCH_HSYNC GMCH_VSYNC
1 2
RN19 SRN0J-6-GP 4 MXM 3
M_RCOMPP
1
R57 150R2F-1-GP R109 80D6R2F-L-GP
GMCH_BLUE
1
UMA
2
RN20 SRN100KJ-6-GP GMCH_BL_ON GMCH_LCDVDD_ON
2
R56 150R2F-1-GP GMCH_GREEN
1
UMA
2
2 1
1
UMA
2
LIBG
1
1
UMA
2
TV_DACB
1
UMA
1
UMA
R249 0R2J-2-GP UMA 2
CRT_IREF
R76 255R2F-L-GP 1 UMA 2
GMCH_GREEN GMCH_BLUE
RN18 SRN0J-6-GP 2 3 1 MXM 4
CRT_IREF
R264 0R2J-2-GP 1 MXM 2 R75 0R2J-2-GP 1 MXM 2
TV_DACA TV_DACB
1 2
TV_IREF TV_DACC
RN17 SRN0J-6-GP 1 4 2 MXM 3
TV_IRTNA
R259 0R2J-2-GP 1 MXM 2
TV_IRTNB
R260 0R2J-2-GP 1 MXM 2
TV_IRTNC
R261 0R2J-2-GP 1 MXM 2
GMCH_RED
2
R47 150R2F-1-GP TV_DACC
2
1
R48 150R2F-1-GP
1
UMA
GMCH_RGB#
R49 150R2F-1-GP TV_DACA
UMA
R53 1K5R2F-2-GP
R256 150R2F-1-GP GMCH_RED
3 4
2
1D05V_S0
RN16 SRN0J-6-GP 4 MXM 3
1D5V_S0
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
GMCH (2 of 5) Size
B
C
Document Number
Rev
-1
Volvi Date:
A
3D3V_S0
D
Wednesday, April 18, 2007
Sheet E
7
of
42
A
B
C
D
E
4
4
2
SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13
AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13
SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE#
AW14 AK23 AK24 AY14
SA_RCVENIN# SA_RCVENOUT#
M_A_BS#0 11,12 M_A_BS#1 11,12 M_A_BS#2 11,12 M_A_CAS# 11,12 M_A_DM[7..0] 11
M_A_DQS[7..0]
M_A_DQS#[7..0]
11
11
M_A_A[13..0] 11,12
M_A_RAS# 11,12
TP15 TPAD30 TP14 TPAD30
M_A_WE# 11,12
Place Test PAD Near to Chip as could as possible
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
B
AU12 AV14 BA20
MEMORY
SA_BS_0 SA_BS_1 SA_BS_2
AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3
SYSTEM
A
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
MEMORY
3
AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8
SYSTEM
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
DDR
11 M_A_DQ[63..0]
U38E M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
DDR
11 M_B_DQ[63..0] U38D
SB_BS_0 SB_BS_1 SB_BS_2
AT24 AV23 AY28
SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13
AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23
SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE#
AU23 AK16 AK18 AR27
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 SB_RCVENIN# SB_RCVENOUT#
M_B_BS#0 11,12 M_B_BS#1 11,12 M_B_BS#2 11,12 M_B_CAS# 11,12 M_B_DM[7..0] 11
M_B_DQS[7..0] 11
M_B_DQS#[7..0]
3
11
M_B_A[13..0] 11,12
2
M_B_RAS# 11,12
TP16 TPAD30 TP17 TPAD30
M_B_WE# 11,12
Place Test PAD Near to Chip ascould as possible
CALISTOGA
71.CALIS.00U
CALISTOGA
71.CALIS.00U 1
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
GMCH (3 of 5) Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
8
of
42
B
C
D
VCCD_QTVDAC
1
2 2
1
1
UMA
UMA
C61
2
SC10U10V5ZY-1GP
C38
1
1
C158
2
C134
1
C139
2
2
2
V_DACC
1
1 2
2
2
SCD1U10V2KX-4GP
R245 0R3-0-U-GP V_TVBG 2 UMA 1
UMA C353
SCD1U10V2KX-4GP
C149 SCD1U10V2KX-4GP
UMA
SCD1U10V2KX-4GP
1
UMA C46
1
V_DACB
2
1
1D5V_S0
SCD1U10V2KX-4GP
2
L17 HCB1608KF121T30-GP 68.00230.041
C86
C64 SCD1U10V2KX-4GP
R246 0R3-0-U-GP 2 UMA 1
2
V_DACA
1
2
1
C63
2
1 2
VCCP_GMCH_CAP2 VCCP_GMCH_CAP1 C375
C40
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
SCD1U10V2KX-4GP
GMCH (4 of 5)
CALISTOGA
SCD1U10V2KX-4GP
C356
SCD22U16V3ZY-GP
R42
DY 10R2J-2-GP
1D5V_QTVDAC_S0
2 1 R78 0R0603-PAD
VCCP_GMCH_CAP3
SCD47U10V3ZY-GP
R242 0R3-0-U-GP UMA 1
1D5V_S0 1D05V_S0
SCD1U10V2KX-4GP
R41 0R5J-6-GP
2
2
VCCA_CRTDAC R240 0R3-0-U-GP 1 MXM 2 1
1
VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40
SCD47U10V3ZY-GP
UMA
C34 SCD1U10V2KX-4GP
2
C30
SCD1U10V2KX-4GP
2
1
1
2
2
AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12
1
H19 3D3V_S0_VCC_HV
1
VCC_HV0 VCC_HV1 VCC_HV2
C35 SCD1U10V2KX-4GP
4
3
2
VCCD_TVDAC
A23 B23 B25
1D5V_TVDAC_S0
1
1
2
C101
2
2
D21
VCCD_LVDS 1 R265 0R3-0-U-GP
POWER
C137
1
2
2
UMA
1
3D3V_S0
R247 0R3-0-U-GP 2 UMA 1
Divide by Trace (Layout Rule approve)
VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2
V_DACC
R258 0R0603-PAD
1D5V_3D3V_S0
UMA
A28 B28 C28
2 0R2J-2-GP
C92
2
1
1D5V_S0
2
1
VCCD_HMPLL0 VCCD_HMPLL1
MXM
1D5V_MPLL_S0
3D3V_TVDAC
3D3V_S0
AH1 AH2
MXM MXM
R253 1
2
2D5V_CRTDAC
2
VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1
V_DACA V_DACB
R257 0R3-0-U-GP 2 MXM 1
D3 DY BAT54-4-GP 1
1
E19 F19 C20 D20 E20 F20
2 0R2J-2-GP 2 0R2J-2-GP
R239
3
VCCA_TVBG VSSA_TVBG
1D5V_S0
L4 HCB1608KF121T30-GP 68.00230.041
1D5V_S0
VCCA_MPLL
H20 G20
R251 1 R250 1
DY 10R2J-2-GP
2D5V_S0
VCCA_LVDS VSSA_LVDS
1D5V_MPLL_S0 AF2
2
1D5V_HPLL_S0
C147
UMA
A38 B39
UMA 1 VSSA_LVDS
V_TVBG
1D5V_2D5V_S0
1
VCCA_DPLLA VCCA_DPLLB VCCA_HPLL
2 0R2J-2-GP
R46 0R0603-PAD
2
B26 C39 AF1
MXM
R252 1
1D5V_S0
D25 DY BAT54-4-GP 1 3
VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC
1
1 2 1 2 1
1
1 2 1 2
2
1 2 1 2 1 2 1 2
2
2 1 2 1
1 2 1 2 1 2 1 2
UMA
VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG
AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1
SC4D7U10V5ZY-3GP
R269 0R2J-2-GP 2 MXM 1
R52 2 C361 0R2J-2-GP SCD1U10V2KX-4GP
VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76
VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2
F21 E21 G21
VCCA_CRTDAC
SC10U10V5ZY-1GP
1D5V_S0
2D5V_3GBG_S0
2D5V_S0_LVDS
SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
-1 0411
C414
AJ41 AB41 Y41 V41 R41 N41 L41 AC33 G41 H41
VCCSYNC
SC2D2U6D3V3MX-1-GP
C397
C30 B30 A30
2D5V_VCC
1D5V_DPLLA 1D5V_DPLLB 1D5V_HPLL_S0
C148 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
R289 0R0603-PAD 1 2
C367
2
1D05V_S0
U38H H22
SCD1U10V2KX-4GP
C376
VCCSYNC C103 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R285 0R0603-PAD 1 2
SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
3
1D5V_DPLLB
C32
UMA
2
SC4D7U6D3V3KX-GP
C29
UMA
2D5V_S0
R271 0R3-0-U-GP 1 UMA 2
C378 SC4D7U6D3V3KX-GP
UMA
UMA
C123
SC4D7U6D3V3KX-GP
R55 0R3-0-U-GP 1 2
C44 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
UMA
R243
UMA 0R3-0-U-GP
1 MXM R51 0R2J-2-GP
C373
SCD1U10V2KX-4GP
1D5V_DPLLA C33
C141 SC4D7U6D3V3KX-GP
R50 0R3-0-U-GP 1 2
R66
UMA 0R3-0-U-GP
UMA
1D5V_3GPLL_S0 R89 0R0603-PAD 2 1
1D5V_S0
UMA
R85 0R2J-2-GP 1 MXM
1D5V_PCIE_S0 R310 0R0805-PAD 1 2
1D5V_S0
1D5V_S0
2
C47 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
4
C365
C31 SC4D7U6D3V3KX-GP
R273 0R0603-PAD 2 1
1
2D5V_3GBG_S0
2
1
2D5V_VCC 2D5V_S0
E
2D5V_S0 1
2D5V_S0
2
A
Size
71.CALIS.00U
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
9
of
42
A
D
71.CALIS.00U VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72
E
U38I
NCTF
VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12
AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17
VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57
AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15
AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34
1D5V_S0
TC2 ST220U2D5VBM-2GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
1
C93
2
1
C111
2
1
C95
2
1
C112
2
1
C117 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
2
1
C122
2
C68
1
Place these Caps close VCC_0 ~ VCC_110
-1 0409
1
VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96
U38J
VSS
VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179
AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23
AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21 AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11
VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272
VSS
VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360
J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1
3
2
CALISTOGA
71.CALIS.00U
CALISTOGA
71.CALIS.00U 1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
CALISTOGA
71.CALIS.00U
4
C159 SCD1U16V2ZY-2GP
2
1
C175 SCD1U16V2ZY-2GP
2
1
C166 SCD1U16V2ZY-2GP
2
1
C172 SCD1U16V2ZY-2GP
DY 2
1
C176 SCD1U10V2KX-4GP
2
1
C181 SCD1U10V2KX-4GP
2
1
C171 SCD1U10V2KX-4GP
2
1
C174 SCD1U10V2KX-4GP
2
1
C163 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
ST220U2D5VBM-2GP
DY
C156
2
TC11
1
1D8V_S3
2
VCC
VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99 VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107
SC10U10V5ZY-1GP
1
C
U38F CALISTOGA
AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18
1
2
1D05V_S0
AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1
2
3
VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110
1
4
AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19 M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16
2
1D05V_S0
B
U38G
-1 0409
Title
GMCH (5 of 5) Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
10
of
42
A
B
C
D
E
DM1
8 M_B_DQS#[7..0]
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
13 31 51 70 131 148 169 188
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
8 M_B_DQS[7..0]
DDR_VREF_S3
A
1
C223 SCD1U16V2ZY-2GP
1
DY
2
C228
SDA SCL
195 197
VDDSPD
199
SA0 SA1
198 200
NC#50 NC#69 NC#83 NC#120 NC#163/TEST
50 69 83 120 163
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
VREF VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
202
GND
GND
201
MH1
MH1
MH2
MH2
114 119
M_ODT2 M_ODT3
2
7,12 7,12
SC4D7U6D3V3KX-GP
1
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
10 26 52 67 130 147 170 185
M_CLK_DDR2 7 M_CLK_DDR#2 7 M_B_DM[7..0] 8
1 2
OTD0 OTD1
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
8,12
TPAD30 TP25 TPAD30 TP24 M_A_BS#2
8,12 8,12
M_A_BS#0 M_A_BS#1 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
8 M_A_DQ[63..0] SMBD_ICH 3,18 SMBC_ICH 3,18 3D3V_S0
DDRB_SA02 R139
1
10KR2J-3-GP C231
1D8V_S3
7,12 7,12 7,12 7,12 8,12 8,12 8,12
M_CS0# M_CS1# M_CKE0 M_CKE1 M_A_RAS# M_A_CAS# M_A_WE# SMBC_ICH SMBD_ICH
DDR_VREF_S3 7,12 7,12
DY
M_ODT0 M_ODT1
C454
C202
DDR2-200P-23-GP-U1
62.10017.A71
High 9.2mm B
C
MH1
MH2
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2
107 106
BA0 BA1
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
50 69 83 120 163
NC#50 NC#69 NC#83 NC#120 NC#163/TEST
110 115 79 80 108 113 109
CS0# CS1# CKE0 CKE1 RAS# CAS# WE#
197 195
SCL SDA
114 119
ODT0 ODT1
1 201
MH2
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
10 26 52 67 130 147 170 185
CK0 CK0# CK1 CK1#
30 32 164 166
SA0 SA1
198 200
VDD_SPD
199
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
81 82 87 88 95 96 103 104 111 112 117 118
VREF
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
GND
GND
202
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS[7..0]
M_A_DQS#[7..0]
8
8 4
M_A_DM[7..0] 8
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_CLK_DDR0 7 M_CLK_DDR#0 7 M_CLK_DDR1 7 M_CLK_DDR#1 7 3D3V_S0
C208
1
11 29 49 68 129 146 167 186
2
CK1 CK1#
164 166
0122 swap CLK2 and CLK3
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
2
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
3
M_CLK_DDR3 7 M_CLK_DDR#3 7
1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
30 32
2
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
8 M_B_DQ[63..0]
M_CKE2 7,12 M_CKE3 7,12
CK0 CK0#
SCD1U16V2ZY-2GP
BA0 BA1
79 80
1
M_B_BS#0 M_B_BS#1
M_CS2# 7,12 M_CS3# 7,12
CKE0 CKE1
2
8,12 8,12
CS0# CS1#
110 115
SC4D7U6D3V3KX-GP
TPAD30 TP26 TPAD30 TP27 M_B_BS#2
M_B_RAS# 8,12 M_B_WE# 8,12 M_B_CAS# 8,12
1
8,12
108 109 113
2
107 106
4
MH1 8,12 M_A_A[13..0]
RAS# WE# CAS#
SCD1U16V2ZY-2GP
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
SCD1U16V2ZY-2GP
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85
REVERSE TYPE
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
REVERSE TYPE
DM2 8,12 M_B_A[13..0]
3
1D8V_S3
2
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
SKT-SODIMM20022U2GP
62.10017.691
Title
High 5.2mm Size Date: D
Document Number
DDR2 Socket
Wednesday, April 18, 2007
Rev
-1
Volvi
Sheet E
11
of
42
A
B
D
PARALLEL TERMINATION
1
1 2
2
1 2
2
2
2
1
1
1
1 2
SCD1U16V2ZY-2GP
2
C230
SCD1U16V2ZY-2GP
DY
C218
SCD1U16V2ZY-2GP
2
C235
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
1
1
1
1
C207
1
1
2
1
2
SCD1U16V2ZY-2GP
2
C453
SCD1U16V2ZY-2GP
DY
C241
SCD1U16V2ZY-2GP
DY
C243
2
C199 SCD1U16V2ZY-2GP
2
1
1
1
1
C220 SCD1U16V2ZY-2GP
2
C211 SCD1U16V2ZY-2GP
DY
C234 SCD1U16V2ZY-2GP
2
C210
2
C242
2
C217
1
1
1
M_B_A[13..0] 8,11 SCD1U16V2ZY-2GP
SRN56J-5-GP
C219
M_A_A[13..0] 8,11
C452
M_ODT2 7,11 M_ODT3 7,11 M_B_RAS# 8,11
C221
SCD1U16V2ZY-2GP
M_B_WE# 8,11
C216
SCD1U16V2ZY-2GP
M_B_A[13..0]
SCD1U16V2ZY-2GP
8 7 6 5
SRN56J-5-GP RN45 1 M_B_A13 2 3 4
M_A_A[13..0]
M_B_A3 M_B_A1 M_B_A10
DY
C206
SCD1U16V2ZY-2GP
SRN56J-5-GP RN41 1 2 3 4
C229
SCD1U16V2ZY-2GP
8 7 6 5
DY
M_CKE2 7,11 M_CKE3 7,11 M_B_BS#2 8,11
C240 SCD1U16V2ZY-2GP
SRN56J-5-GP RN39 1 2 3 4 M_B_A12
4
C198
SCD1U16V2ZY-2GP
8 7 6 5
Put decap near power(0.9V) and pull-up resistor
DDR_VREF_S0
SCD1U16V2ZY-2GP
8 7 6 5
2
M_A_A12
SRN56J-5-GP RN40 M_B_A8 1 2 M_B_A9 3 M_B_A5 4
M_CKE0 7,11 M_CKE1 7,11 M_A_BS#2 8,11
1
1 2 3 4
2
8 7 6 5
E
Decoupling Capacitor
Put decap near power(0.9V) and pull-up resistor
RN32
2
DDR_VREF_S0
4
C
RN44 M_B_BS#1 8,11
1
1
2
2 1
2
DY
2
2 SRN56J-5-GP
2
DY
DY
SCD1U16V2ZY-2GP
DY M_ODT0 7,11 M_CS0# 7,11 M_A_RAS# 8,11
C212
SCD1U16V2ZY-2GP
M_A_A13
C209
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN38 1 2 3 4
C205
2
C197
SRN56J-5-GP
8 7 6 5
1
2 1
M_B_BS#0 8,11 M_B_CAS# 8,11 M_CS3# 7,11 M_CS2# 7,11
SC2D2U6D3V3MX-1-GP
1 2 3 4
C446
SC2D2U6D3V3MX-1-GP
RN42 8 7 6 5
C214
SC2D2U6D3V3MX-1-GP
SRN56J-5-GP
C448
SC2D2U6D3V3MX-1-GP
M_B_A6 M_B_A7 M_B_A11
C213
SC2D2U6D3V3MX-1-GP
1 2 3 4
1
C447
RN43 8 7 6 5
1
1
SRN56J-5-GP
3
Place these Caps near DM1
1D8V_S3
1
M_B_A2 M_B_A0 M_B_A4
2
1 2 3 4
2
8 7 6 5
3
2
RN37 8 7 6 5
1 2 3 4
M_A_A0 M_A_A2 M_A_A4
M_A_BS#1 8,11
Place these Caps near DM2
1D8V_S3
SRN56J-5-GP
DY
1 2
1 2 1
1 2 1
1
DY
2
2
DY
C222
DY
SCD1U16V2ZY-2GP
M_A_A6 M_A_A7 M_A_A11
C239 SCD1U16V2ZY-2GP
1 2 3 4
SCD1U16V2ZY-2GP
1
SCD1U16V2ZY-2GP
RN36 8 7 6 5
C224
2
C238
SRN56J-5-GP
2
2 1
M_A_A9 M_A_A8 M_A_A5 M_A_A3
C246 SC2D2U6D3V3MX-1-GP
1 2 3 4
C236 SC2D2U6D3V3MX-1-GP
RN33 8 7 6 5
C227 SC2D2U6D3V3MX-1-GP
M_CS1# 7,11 M_ODT1 7,11
SRN56J-5-GP
C245 SC2D2U6D3V3MX-1-GP
M_A_CAS# 8,11
SC2D2U6D3V3MX-1-GP
1 2 3 4
1
C226
RN35 8 7 6 5
2
1
SRN56J-5-GP
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
RN34 8 7 6 5
1 2 3 4
M_A_A1 M_A_A10 Title
M_A_BS#0 8,11 M_A_WE# 8,11
DDR2 Termination Resistor Size
SRN56J-5-GP
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
12
of
42
LCDVDD
3D3V_S0 Q15 GND 2
U35
R224 0R2J-2-GP
MXM
GND IN#8 IN#7 IN#6 IN#5
C339
3 OUT
R2
G5281RC1U-GP
74.05281.093
30
1
IN#1 OUT EN GND
IN
PWR_G_LED
R1
1
CHDTC143ZUPT-GP
C337
3D3V_S0
84.00143.B1K
2
C338
SCD1U16V2ZY-2GP 2 1
2
0R2J-2-GP
2
SC1U16V3ZY-GP
2LCDVDD_ON_1
1
R226
UMA 1
7 GMCH_LCDVDD_ON
9 8 7 6 5
SC1U16V3ZY-GP
1 2 3 4
LED1 31 PWRLED#_DB
1 2FRONT_PWRLED#_R R500 100R2J-2-GP
3
STDBY_LED#_DB
STDBY_LED#_R 1 2 R499 100R2J-2-GP
4
1
31 STDBY_LED#_DB
PWRLED#_DB
3D3V_S5
1 2 LED-GY-14-GP
Q14
83.00195.I70
GND 2
26 NV_LCDVDD_ON
3 OUT
R2 IN
PWR_O_LED
R1
1
CHDTC143ZUPT-GP
84.00143.B1K
R333
1 2 33R2J-2-GP
27 WLAN_LED#_MC
WLAN_LED# 31
Q10
LCD/INVERTER CONN
D
30
2N7002-11-GP
G
30 WLAN_TEST_LED
S
84.27002.W31
LCDVDD
DCBATOUT
1 1
F1
1 2 FUSE-3A32V-8-GP
69.43001.111 SCD1U50V3ZY-GP
SC10U35V0ZY-GP
2 2
EC1
1 2 3 4
UMA 8 7 6 5
GMCH_TXBOUT1GMCH_TXBOUT1+ GMCH_TXBOUT0GMCH_TXBOUT0+
30
IN
BT_LED
R1
1
84.00143.B1K
CHDTC143ZUPT-GP
ODD CHANNEL
RN3 LCD_TXBCLKLCD_TXBCLK+ LCD_TXBOUT2LCD_TXBOUT2+
1 2 3 4
EVEN CHANNEL
GND 2
8 7 6 5
GMCH_TXBCLK- 7 GMCH_TXBCLK+ 7 GMCH_TXBOUT2- 7 GMCH_TXBOUT2+ 7
RN9
1 2 3 4
IN
30 CHARGE_LED
R1
1
GMCH_TXACLKGMCH_TXACLK+ GMCH_TXAOUT2GMCH_TXAOUT2+
7 7 7 7
GMCH_TXAOUT1GMCH_TXAOUT1+ GMCH_TXAOUT0GMCH_TXAOUT0+
7 7 7 7
IN
30 DC_BATFULL
1
LCD_TXAOUT1LCD_TXAOUT1+ LCD_TXAOUT0LCD_TXAOUT0+
1 2 3 4
RN6 LCD_TXBOUT0+ LCD_TXBOUT0LCD_TXBOUT1+ LCD_TXBOUT1-
F2
2
1 2 3 4
84.00143.B1K
8 7 6 5
RN5 SRN2K2J-1-GP
R35 2 0R2J-2-GP 1 R29 2 0R2J-2-GP R34
26 26 26 26
1
7 DAT_DDC_EDID
LVDS_TXBOUT2+ 26 LVDS_TXBOUT2- 26 LVDS_TXBCLK+ 26 LVDS_TXBCLK- 26
LCD_TXAOUT0+ LCD_TXAOUT0LCD_TXAOUT1+ LCD_TXAOUT1-
1 2 3 4
8 7 6 5
LVDS_TXAOUT2+ LVDS_TXAOUT2LVDS_TXACLK+ LVDS_TXACLK-
26 26 26 26
LVDS_TXAOUT0+ LVDS_TXAOUT0LVDS_TXAOUT1+ LVDS_TXAOUT1-
26 26 26 26
LCD_TXBCLKLCD_TXBOUT2+
2 R2
DY 330R2J-3-GP
2 1
LCD_TXAOUT2LCD_TXAOUT1+ R7
R3
DY 330R2J-3-GP LCD_TXBOUT1LCD_TXBOUT0+
DY 330R2J-3-GP LCD_TXAOUT1LCD_TXAOUT0+
2 1
SRN0J-7-GP
R8
1
BRIGHTNESS 30 BLON_OUT 30
R6 LCD_TXBOUT2LCD_TXBOUT1+
LCD_TXBOUT0-
UMA
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
R4
DY 330R2J-3-GP 1
L_BKLTCTL 7
8 7 6 5
DY 330R2J-3-GP LCD_TXACLKLCD_TXAOUT2+
DY 330R2J-3-GP
MXM
R1
2
SC100P50V2JN-3GP 2 1
SC100P50V2JN-3GP 2 1
C4
10KR2J-3-GP
C340
RN13
R5
DY 330R2J-3-GP
SRN0J-7-GP 16 16
LCD_TXACLK+ R9
MXM
2 1
1 2 3 4
2 1
LCD_TXAOUT2+ LCD_TXAOUT2LCD_TXACLK+ LCD_TXACLK-
EC4 DY SCD1U16V2ZY-2GP
EMI LCD_TXBCLK+
2 1
SB 0226
-1 0416
EC3 DY SCD1U16V2ZY-2GP
DY 330R2J-3-GP LCD_TXAOUT0-
Title
1
8 7 6 5
RN8
BRIGHTNESS_CN BLON_OUT
NV_EDID_DAT
MXM
2
1 2 3 4
SRN0J-7-GP
1 0R2J-2-GP R227 1 2 0R0402-PAD
UMA
2 0R2J-2-GP
1 R28 2 0R2J-2-GP
26 NV_EDID_DAT_1
2 1
1
RN4 LCD_TXBOUT2+ LCD_TXBOUT2LCD_TXBCLK+ LCD_TXBCLK-
DY
NV_EDID_CLK
MXM
MXM
2
2
1
LVDS_TXBOUT0+ LVDS_TXBOUT0LVDS_TXBOUT1+ LVDS_TXBOUT1-
UMA
1
69.50007.721 C2 SCD1U16V2ZY-2GP
83.00195.I70 3D3V_S0
UMA
SRN0J-7-GP
FUSE-1A6V-2-GP
R2252
2 DC_BATFULL#_R 100R2J-2-GP
MXM 8 7 6 5
1
CHDTC143ZUPT-GP
26 NV_EDID_CLK_1
USBPN6 USBPP6
1
R1
7 CLK_DDC_EDID
2 2
3 OUT
R2
2
LED-GY-14-GP
R498
UMA
4 3
CHDTC143ZUPT-GP Q27 GND 2
8 7 6 5
RN14
0R0402-PAD 1 R11 0R0402-PAD 1 R10
R497 CHARGE_LED#_R 1 2 100R2J-2-GP
84.00143.B1K
SRN0J-7-GP
USB_6USB_6+
3 OUT
R2
SRN0J-7-GP LCD_TXACLKLCD_TXACLK+ LCD_TXAOUT2LCD_TXAOUT2+
LED2
UMA
SRN0J-7-GP
3D3V_S0
C1 SC4D7U10V5ZY-3GP
3D3V_S5
Q8
20.F0993.040
CCD_PWR
2nd 84.00143.D1K
SRN0J-7-GP
ACES-CONN40A-2GP
1
3 OUT
R2
7 7 7 7
1
BRIGHTNESS_CN BLON_OUT
RN7 LCD_TXBOUT1LCD_TXBOUT1+ LCD_TXBOUT0LCD_TXBOUT0+
2
CCD_PWR
LCD_TXAOUT2LCD_TXAOUT2+ LCD_TXAOUT1LCD_TXAOUT1+ LCD_TXAOUT0LCD_TXAOUT0+ LCD_TXACLKLCD_TXACLK+ LCD_TXBOUT2LCD_TXBOUT2+ LCD_TXBOUT1LCD_TXBOUT1+ LCD_TXBOUT0LCD_TXBOUT0+ LCD_TXBCLKLCD_TXBCLK+
2 1
3D3V_S0 NV_EDID_CLK NV_EDID_DAT
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Q9 GND 2
SCD1U25V3ZY-1GP
3 4
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
C5
1
2
USB_6USB_6+
DY
1
BT_LED#
BT_LED#
2
41 2
C3
31
1
LCD1
LCD CONN & LED Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007
Sheet
13
of
42
A
B
C
3
CRT_VSYNC1
14
C16
MH2
1CRT_DEC_R 1
2
CRT_DEC#
2
2
3
BAV99-5-GP
5V_CRT_S0
2 1
C341 SCD1U16V2ZY-2GP
2nd 83.R3004.A8F CH751H-40PT D1 3D3V_S0
3D3V_S0 RN1 SRN2K2J-1-GP
1
14
SRN10KJ-6-GP RN2
7
4
14
CRT_HSYNC1_R 1 2CRT_HSYNC1 0R2J-2-GP 26 NV_DDCDAT
3
CRT_VSYNC 0R2J-2-GP
1
C352DY
2
2C
C354 354
DY
SC18P50V2JN-1-GP 7
5
1
SC18P50V2JN-1-GP
2
6
MXM
U2A TSAHCT125PW-GP
CRT_VSYNC1_R
1 R13 R12 1
7 GMCH_DDCDATA
Q1
2
0R2J-2-GP 2 0R2J-2-GP
NV_DDCDAT_1
CRT_DEC#
4
3
5
2
6
1
DAT_DDC1_5
UMA
1 2CRT_VSYNC1 0R2J-2-GP
U2B TSAHCT125PW-GP
1 2 3 4
2
3 4
CRT_HSYNC 0R2J-2-GP
2
1 R237
NV_VSYNC
5V_S0
1
SC100P50V2JN-3GP
3D3V_S0
R26
MXM 26
DY
3
C6
1 2 2
UMA
R2381 2 0R2J-2-GP
7 GMCH_VSYNC
SC100P50V2JN-3GP
R27
MXM 1 R236
C7
5V_S0
D2
UMA
NV_HSYNC
SC18P50V2JN-1-GP
SCD01U16V2KX-3GP
20.20334.015
5V_S0
26
C17
VIDEO-15-21-U4-GP
Hsync & Vsync level shift
7 GMCH_HSYNC
CLK_DDC1_5
15 5 16
470R2J-2-GP
R2351 2 0R2J-2-GP
C10
10
SC18P50V2JN-1-GP
R15
3
5V_CRT_S0
4
C15 to 18P C12 to 27P C9 to 27P For ATI MXM M66M R,G,B 30
9
1
2
SC100P50V2JN-3GP CRT_B
C9
2
1
C12
CRT_HSYNC1
1
MXM
Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
1
CRT_B C15
CRT_G
13
2
MXM
68.00230.021
1
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
MXM
2 FCB1608CF-GP
4
2 8
2
R18
C8
2
R20
C11
C13
SC6D8P50V2DN-GP
R23
1 C14
SC22P50V2JN-4GP
0R2J-2-GP
1
CRT_B_1 0R2J-2-GP
SC22P50V2JN-4GP
2
1
2
UMA
1
SC22P50V2JN-4GP
R17
1
2
R19
1
NV_BLUE GMCH_BLUE
12
2
L1
2
26 7
1
68.00230.021
0R2J-2-GP
2
2
MXM
SC6D8P50V2DN-GP
UMA
1
SC6D8P50V2DN-GP
R21
7 DAT_DDC1_5
1
7 GMCH_GREEN
0R2J-2-GP
1
CRT_G
2 FCB1608CF-GP
2
R22
1
NV_GREEN
1
11
CRT_R
L2 CRT_G_1
2
26 4
2
MH1 6
8 7 6 5
0R2J-2-GP
MXM 1
17
CRT_R
2 FCB1608CF-GP
68.00230.021
1
2
1
2
UMA
1
CRT1
L3
CRT_R_1 0R2J-2-GP
1
R24
2
2
GMCH_RED
1
2
7
R25
Ferrite bead impedance: 10 ohm@100MHz
1
MXM NV_RED
E
CRT I/F & CONNECTOR
Layout Note: Place these resistors close to the CRT-out connector 26
D
MXM 1 R16 R14 1
26 NV_DDCCLK 7 GMCH_DDCCLK
0R2J-2-GP 2 0R2J-2-GP
2N7002DW-1-GP
84.27002.D3F
2
NV_DDCCLK_1
UMA
CLK_DDC1_5
2
DDC_CLK & DATA level shift C194
R124 150R2F-1-GP
TVOUT1
1 2 IND-1D2UH-5-GP
68.1R220.10A
LUMA_1 1
1
LUMA_1_1
C193
C195
SC150P50V2JN-3GP
2
TV_DACB
L11
L9 1 2 IND-1D2UH-5-GP
68.1R220.10A
1 3 8 9
5V_S0
1
3
1 BAV99-5-GP D23
2
3
68.1R220.10A
COMP_1 C190
2
C192
SC150P50V2JN-3GP
SC270P50V2JN-2GP
3
2 CRT_G 3
DY
SC270P50V2JN-2GP
COMP_1 1
1 R121 150R2F-1-GP
L10 1 2 IND-1D2UH-5-GP
2
TV_DACA
1
DY
1
1
BAV99-5-GP D6
BAV99-5-GP D22
2
2 CRT_B 3
DY
1
Wistron Corporation
DY
1
1
BAV99-5-GP
BAV99-5-GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
2
7
R122 UMA 0R2J-2-GP 1 2
COMP_1_1 1
26 NV_TV_COMP
DY
BAV99-5-GP D5
2 SC33P50V2JN-3GP
1
2 CRT_R 3
DY
2 CRMA_1
C185
C191 R123 MXM 0R2J-2-GP 1 2
D24 2
LUMA_1
C187
SC150P50V2JN-3GP
5V_S0
D7
CRMA_1 1
1 R115 150R2F-1-GP
NC#5
2
GND GND GND GND
22.10021.H61
2 SC33P50V2JN-3GP
2
TV_DACC
R116 UMA 0R2J-2-GP 1 2
CRMA_1_1
5
NC#2
2
7
R120 MXM 0R2J-2-GP 1 2
1
26 NV_TV_CRMA
LUMA CRMA COMP
MINDIN7-19-GP-U2
C186 1
4 6 7
SC270P50V2JN-2GP
2
7
R125 UMA 0R2J-2-GP 1 2
2 SC33P50V2JN-3GP
1
2
26 NV_TV_LUMA
R126 MXM 0R2J-2-GP 1 2
1
TV CONN
CRT/TV Connector
Document Number
Date: Wednesday, April 18, 2007 A
B
C
D
Volvi
Rev
-1 Sheet E
14
of
42
A
B
C
D
E
SB 0305
4
4
1
AA3
RTCRST#
R373 1
2 1MR2J-1-GP
INTRUDER# INTVRMEN
Y5 W4
INTRUDER#
3
SC1U10V3ZY-6GP
19
C520
R393 0R2J-2-GP 2 DY 1 LAN_RSTYNC
SB 0313 for EMI
2 R407 1 22R2J-2-GP
28 ACZ_SDATAIN0 21 ACZ_SDATAIN1
1
ACZ_BTCLK_MDC 2 1
EC132
2 R406 1 22R2J-2-GP1 R379 1 R385
ACZ_BITCLK 21,28 ACZ_SYNC 21,28 ACZ_RST#
R358 10KR2J-3-GP
R397 1 39R2J-L-GP
21,28 ACZ_SDATAOUT
DY
ACZ_BIT_CLK ACZ_SYNC_R 2 39R2J-L-GP ACZ_RST#_R 2 33R2J-2-GP
SATA_LED#
20 20 20 20
SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0
1 1 1 1
2 2 2 2
SC3900P50V3KX-GP SC3900P50V3KX-GP SC3900P50V3KX-GP SC3900P50V3KX-GP
SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C
3 CLK_PCIE_SATA# 3 CLK_PCIE_SATA
RTC_AUX_S5 1
SATARBIAS 1 R372 2 24D9R2F-L-GP R386 300KR2J-GP
2
P.H. for internal VCCSUS1_05
INTVRMEN 1
Place within 500 mils of ICH7ball
20 20 20 20 20 20
IDE_PDIOR# IDE_PDIOW# IDE_PDDACK# INT_IRQ14 IDE_PDIORDY IDE_PDDREQ
R395
2
V3
LAN_CLK
U3
LAN_RSTSYNC
U5 V4 T5
LAN_RXD0 LAN_RXD1 LAN_RXD2
U7 V6 V7
LAN_TXD0 LAN_TXD1 LAN_TXD2
U1 R6
ACZ_BIT_CLK ACZ_SYNC
R5
ACZ_RST# ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2
AA6 AB5 AC4 Y6
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LDRQ0# 30
30 30 30 30
AC3 AA5 3D3V_LDRQ1_S0 1 R377 2 10KR2J-3-GP
LFRAME#
AB3
LPC_LFRAME# 30
A20GATE A20M#
AE22 AH28
KA20GATE 30 H_A20M# 4
CPUSLP#
AG27
TP1/DPRSTP# TP2/DPSLP#
AF24 AH25
1D05V_S0
H_CPUSLP#_2
AF7 AE7 AG6 AH6
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
AF1 AE1
SATA_CLKN SATA_CLKP
AH10 AG10
SATARBIASN SATARBIASP
AF15 AH15 AF16 AH16 AG16 AE15
DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ
IDE
3
R339 56R2J-4-GP
H_CPUSLP# 4,6
H_DPRSTP# 4,35 H_DPSLP# 4
FERR# GPIO49/CPUPWRGD
AG24
H_PWRGD 4,31,33
IGNNE# INIT3_3V# INIT# INTR
AG22 AG21 AF22 AF25
H_IGNNE# 4
RCIN#
AG23
KBRCIN# 30
NMI SMI#
AH24 AF23
H_NMI 4 H_SMI# 4
STPCLK#
AH22
H_STPCLK# 4
THERMTRIP#
AF26
H_THERMTRIP_R
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15
IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15
DA0 DA1 DA2
AH17 AE17 AF17
IDE_PDA0 20 IDE_PDA1 20 IDE_PDA2 20
DCS1# DCS3#
AE16 AD16
IDE_PDCS1# 20 IDE_PDCS3# 20
H_FERR# 4
-1 0411 TP64 TPAD30
FWH_INIT#
H_INIT# 4 H_INTR 4
H_PWRGD 1D05V_S0
R342 200R2F-L-GP 1 DY 2
1D05V_S0
R335 56R2J-4-GP
Layout Note: R568 needs to placed within 2" of ICH7, R568 must be placed within 2" of R169 w/o stub.
SATALED# SATA0RXN SATA0RXP SATA0TXN SATA0TXP
3D3V_S0
R334 0R2J-2-GP 1 DY 2
AG26
ACZ_SDOUT
AF3 AE3 AG2 AH2
Open R for Dothan A step Shunt for Dothan B step & all Yonah
20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
2
ICH7-M-GP
71.ICH7M.00U
INTVRMEN
DY 0R2J-2-GP
1
EE_CS EE_SHCLK EE_DOUT EE_DIN
AF18 C515 C518 C509 C500
LDRQ0# LDRQ1#/GPIO23
W1 Y1 Y2 W3
T2 T3 ACZ_SDIN2 T1 TPAD30 TP58 ACZ_SDATAOUT_R T4 2
31 SATA_LED#
2
ACZ_BITCLK EC131
SC22P50V2JN-4GP
2
28
3D3V_S0
SC22P50V2JN-4GP
1
2
21 ACZ_BTCLK_MDC
0130
INTRUDER# INTVRMEN
LAD0 LAD1 LAD2 LAD3
1
RTXC1 RTCX2
RTC_RST#
2
2 20KR2J-L2-GP
1
1
R374 1
2
AB1 AB2
RTC LPC
U15A RCT_X1 RCT_X2
LAN CPU
2 SC10P50V2JN-4GP
AC-97/AZALIA
C247 1
2
20.F1000.003
C225 SC1U10V3ZY-6GP
SATA
MLX-CON3-10-GP
C590
1
1
5
1 2
2
DY
3 BAT_D
SCD1U16V2ZY-2GP
2 3
2
R376 1KR2J-1-GP 1 2
BAT
1
RTC_AUX_S5
2
RTC1 4
R145 10MR2J-L-GP
82.30001.691 1
RTC circuitry
X3 X-32D768KHZ-38GPU
D11 BAS40CW-GP
2
3D3V_AUX_S5
4
2 SC10P50V2JN-4GP
3
C250 1
Enable
1
Disable
0
Change to KI.80101.017 UMA
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Placement Note: Diatance between the ICH-7 M and cap on the "P" signal should be identical distance between the ICH-7 M and cap on the "N" signal for same pair.
Title Size
Document Number
ICH7-M (1 of 4)
Date: Wednesday, April 18, 2007 A
B
C
D
Volvi
Rev
-1 Sheet E
15
of
42
C
E
7
SMB_ALERT# B23
24 24 24 24
3 3
R354 A7 PCI_IRDY# 24 47R2J-2-GP E10 PCI_PAR 24 PCIRST# 1 B18 2 A12 PCI_DEVSEL# 24 C9 PCI_PERR# E11 PCI_LOCK# B10 PCI_SERR# F15 PCI_STOP# 24 F14 PCI_TRDY# 24 F16 PCI_FRAME# 24
G8 F7 F8 G7
RSVD[6] RSVD[7] RSVD[8] RSVD[9] MCH_SYNC#
SRN8K2J-2-GP-U 10 PCI_IRDY# 9 PCI_PERR# 8 INT_PIRQE# 7 PCI_DEVSEL# 6
3D3V_S0
RP2 PCI_STOP# PCI_REQ#2 PCI_TRDY# PCI_REQ#3
SRN8K2J-2-GP-U 10 PCI_REQ#1 9 PCI_FRAME# 8 PCI_REQ#4 7 PCI_LOCK# 6
1 2 3 4 5
3D3V_S0
RP4 INT_PIRQF# INT_PIRQC# INT_SERIRQ MCH_ICH_SYNC# 3D3V_S0
SRN8K2J-2-GP-U 10 PCI_SERR# 9 INT_PIRQD# 8 INT_PIRQB# 7 INT_PIRQA# 6
1 2 3 4 5
R360 1
ACZ_SPKR
R353 1
INT_PIRQG# 24
AE9 AG8 AH8 F21 AH20
ECSCI#_1
R359 1
2 10KR2J-3-GP
PWROK
R390 2
1 10KR2J-3-GP
2 1KR2J-1-GP
GPIO26
B21 E23
GPIO27 GPIO28
AG18
GPIO32/CLKRUN#
AC19 U2
GPIO33/AZ_DOCK_EN# GPIO34/AZ_DOCK_RST#
F20 AH21 AF20
WAKE# SERIRQ THRM#
AC21 AC18 ECSMI# E21
TPAD30 TP49
GPIO18/STPPCI# GPIO20/STPCPU#
A21
AD22
ECSCI#_1
GPIO11/SMBALERT#
PWROK GPIO16/DPRSLPVR TP0/BATLOW# PWRBTN# LAN_RST# RSMRST# GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35 GPIO38 GPIO39
VRMPWRGD GPIO6 GPIO7 GPIO8
GPIO
AA4
E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20
MCH_ICH_SYNC#
7
TXN1 TXP1
PERn1 PERp1 PETn1 PETp1
1 1
TXN2 TXP2
H26 H25 G28 G27
PERn2 PERp2 PETn2 PETp2
1 1
TXN3 TXP3
K26 K25 J28 J27
PERn3 PERp3 PETn3 PETp3
M26 M25 L28 L27
PERn4 PERp4 PETn4 PETp4
PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1
C438 SCD1U10V2KX-5GP 2 C439 SCD1U10V2KX-5GP 2
1 1
27 27 27 27
PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2
C436 SCD1U10V2KX-5GP 2 C437 SCD1U10V2KX-5GP 2
27 27 27 27
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
C434 SCD1U10V2KX-5GP 2 C435 SCD1U10V2KX-5GP 2
LAN
MINI CARD 3D3V_S0
NEW CARD RP1 3D3V_S0
ICH7_GPI12 1 PM_BATLOW#_R 2 DBRESET# 3 SMB_LINK_ALERT# 4 5 3D3V_S5 RP5
3D3V_S0
USB_OC#3 USB_OC#1 USB_OC#4 USB_OC#0
1 2 3 4 5
3D3V_S5
SRN10KJ-L3-GP 3D3V_S5 10 9 PCIE_WAKE# 8 PSW_CLR# 7 SMB_ALERT# 6 PM_RI# SRN10KJ-L3-GP 10 9 8 7 6
3D3V_S5 USB_OC#2 USB_OC#7 USB_OC#6 USB_OC#5 TPAD30 TP59
3D3V_S5
ECSWI# ECSMI#
SMLINK0 SMLINK1
3 4
21 21
USB_OC#0 USB_OC#1
RN67 SRN100KJ-6-GP 2 1
SPI_ARB
USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7
RN66 SRN10KJ-5-GP 3 2 4 1
P26 P25 N28 N27
PERn5 PERp5 PETn5 PETp5
H
PCI
H
L
SPI
L
H
T25 T24 R28 R27
PERn6 PERp6 PETn6 PETp6
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
7 7 7 7
DMI1RXN DMI1RXP DMI1TXN DMI1TXP
Y26 Y25 W28 W27
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
7 7 7 7
DMI2RXN DMI2RXP DMI2TXN DMI2TXP
AB26 AB25 AA28 AA27
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
7 7 7 7
DMI3RXN DMI3RXP DMI3TXN DMI3TXP
AD25 AD24 AC28 AC27
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
7 7 7 7
DMI_CLKN DMI_CLKP
AE28 AE27
CLK_PCIE_ICH# 3 CLK_PCIE_ICH 3
C25 D25
DMI_IRCOMP_R
R2 P6 P1
SPI_CLK SPI_CS# SPI_ARB
P5 P2
SPI_MOSI SPI_MISO
D3 C4 D5 D4 E5 C3 A2 B3
OC0# OC1# OC2# OC3# OC4# OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P
F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3
USBRBIAS# USBRBIAS
D2 D1
USBPN0 USBPP0 USBPN1 USBPP1 USBPN2 USBPP2 USBPN3 USBPP3 USBPN4 USBPP4 USBPN5 USBPP5 USBPN6 USBPP6 USBPN7 USBPP7
PM_DPRSLPVR 35
PM_PWRBTN# 30,31
3D3V_S0
L:UMA
H:IDTCV125 L:RTM865-433
R349 10KR2J-3-GP
IDT CLKGNT_SEL R350 10KR2J-3-GP
R345 10KR2J-3-GP
RTL
3
Layout Note: PCIE AC coupling caps need to be within 250 mils of the driver.
1D5V_S0 Place within 500 mils of ICH R341 24D9R2F-L-GP
21 21 21 21 21 21 21 21 27 27 21 21 13 13 27 27
2
USB ports definition Pair
Device
0
USB1
1
USB3
2
USB2
USB_RBIAS_PN
3
USB4
4
MINICARD
5
BlueTooth
6
CCD
7
NewCard
R404 22D6R2F-L1-GP
71.ICH7M.00U
UMA 1 R411 2K2R2J-2-GP
GAP放在Dimm Door打開可量測處
D13 BAT54PT-GP 1
G68 PSW_CLR#
1
2 30 RSMRST#_KBC GAP-OPEN
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
3
RSMRST#_SB Title R401 100KR2D-1-GP
2
Size
2 A
H:MXM
R352 10KR2J-3-GP
MXM UMA_DIS_SEL
V26 V25 U28 U27
ICH7-M-GP
2
H
30
3D3V_S0
UMA
1
GNT5# GNT4#
ECSWI# ICH7_GPI12
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
DMI_ZCOMP DMI_IRCOMP
4
7,19
PM_DPRSLPVR_R
U15D
F26 F25 E28 E27
22 22 22 22
Default:H LPC
PWROK
R346 2 1100R2J-2-GP 1 2 R348 DY C21 PM_BATLOW#_R 100KR2J-1-GP PWRBTN#_ICH 1 D9 C23 R355 BAS16-1-GP 10KR2J-3-GP 3 LAN_RST# 1 C19 2 2 RSMRST#_SB Y4 AC22
3D3V_S5
1
PM_SLP_S3# 19,26,27,30,33,36,37,38,39 PM_SLP_S4# 27,30,37,39 TP47 TPAD30
ICH7-M-GP
2 8K2R2J-3-GP
DY
22,27 PCIE_WAKE# 30 INT_SERIRQ 19 THRM#
30
3D3V_S0 PM_CLKRUN#
PCB_VER0 PCB_VER1
GPIO0/BM_BUSY#
B24 D23 F22 SLPS5#
1
RP3
30 30
7,35 VGATE_PWRGD
71.ICH7M.00U
1 2 3 4 5
SB 0314
TP50 TPAD30
ICH7-M-GP
PCI_REQ#0 INT_PIRQG# INT_PIRQH# PCI_REQ#5
PSW_CLR#
24,30 PM_CLKRUN#
PLT_RST1# 7,26,30 CLK_ICHPCI 3
INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#
AC20 AF21
PM_STPPCI# PM_STPCPU#
PCIRST1# 20,22,24,27
-1 0416
R340 1 C26 PLTRST# 2 0R0402-PAD A9 B19 ICH_PME#
AB18
PM_BMBUSY#
PM_SUS_CLK 19
SLP_S3# SLP_S4# SLP_S5#
1
TPAD30
C20
2
TP55
DBRESET#
CLK_ICH14 3 CLK48_ICH 3
SUSCLK
1
TPAD30 TP45
SPKR SUS_STAT# SYS_RST#
2
TPAD30
A19 A27 A22
AC1 B2
3D3V_S0 RN68 SRN10KJ-6-GP 8 7 6 5
2
RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]
TP53
ACZ_SPKR
CLK14 CLK48
71.ICH7M.00U
MISC
AE5 AD5 AG4 AH4 AD9
28
RI#
Direct Media Interface
3
GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH#
TPAD30
A28
PCI-Express
PIRQA# PIRQB# PIRQC# PIRQD#
TP54
PM_RI#
1 2 3 4
1
Interrupt I/F
A3 B4 C5 B5
TPAD30
SATA0_R1 SATA0_R3 SATA0_R0 SATA0_R2
2
PLTRST# PCICLK PME#
TPAD30
TP51
SATA0_R0 SATA0_R1 SATA0_R2 SATA0_R3
1
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3
TP52
AF19 AH18 AH19 AE19
2
C/BE0# C/BE1# C/BE2# C/BE3#
B15 C12 D12 C15
PCI_REQ#0 24 PCI_GNT#0 24
PCI_REQ#1 PCI_GNT#1 PCI_REQ#2 PCI_GNT#2 PCI_REQ#3 PCI_GNT#3 PCI_REQ#4 PCI_GNT#4 PCI_REQ#5 PCI_GNT#5
GPIO21/SATA0GP GPIO19/SATA1GP GPIO36/SATA2GP GPIO37/SATA3GP
Clocks
D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8
SMB
REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ4#/GPIO22 GNT4#/GPIO48 GPIO1/REQ5# GPIO17/GNT5#
PCI
SPI
INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1
USB
4
E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6
C22 B22 SMB_LINK_ALERT# A26 SMLINK0 B25 SMLINK1 A25
18,22,27 SMB_CLK 18,22,27 SMB_DATA
SYS GPIO Power MGT
U15B PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
SATA GPIO
U15C
24 PCI_AD[31..0]
2
D
1
B
2
A
B
C
Document Number
ICH7-M (2 of 4)
Date: Wednesday, April 18, 2007
D
Volvi
Rev
-1 Sheet
E
16
of
42
1
A
B
C
D
E
Layout Note: Place near pin AA19
1D05V_S0
1
2
1
1 2
2
1 2
2 1
TP56 TPAD28 TP44 TPAD28 TP48 TPAD28
1 2
B
1
2
3D3V_S5 R375 0R0603-PAD 1 2
2 1
1D5V_S0
2
C458
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
1D5V_S0
ICH7-M (3 of 4) Size
71.ICH7M.00U
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007
A
2
1 2
1
Layout Note: Place near AB3 C501
1
2
1
RTC_AUX_S5
DY C498
1
2
1
C508
2 VccSus1_05[1]
2
1 2
1 2
1
1 2
1 2
2
1
2 1 2 2
SCD1U10V2KX-4GP
C459
C28 VccSus1_05[2] G20 VccSus1_05[3] A1 H6 H7 J6 J7
C490
C466
AB8 AC8 K7
1
1 2
1
1
2
2
1 2
1
2 1 2 1 2
1
IDE PCI
2
CORE
ICH7-M-GP
1
1 2
1
1 2
2 1 2
VccSus1_05[2] VccSus1_05[3] VccSus1_05/VccLAN1_05[1] VccSus1_05/VccLAN1_05[2]Vcc1_5_A[26] Vcc1_5_A[27] Vcc1_5_A[28] Vcc1_5_A[29] Vcc1_5_A[30]
2
1 2
1 2
1
1 2
2
1 2
1 2
USB
1 2 1
2
VccSus1_05[1]
USB CORE
1 2
1
1 2
2
2
1
1 2
1 2
2
1
1
2
2 1 1 2 2 1 1 2 1 2
Vcc1_5_A[24] Vcc1_5_A[25]
C477
DY
SC10U10V5ZY-1GP
VccLan1_05[1] AA2 Y7
T7 F17 G17
DY
C487 SC10U10V5ZY-1GP
VccUSBPLL
Vcc1_5_A[21] Vcc1_5_A[22] Vcc1_5_A[23]
C483
SCD1U10V2KX-4GP
VccSus3_3[19]
C1
AB17 AC17
C502
C467
SCD1U10V2KX-4GP
E3
Vcc1_5_A[19] Vcc1_5_A[20]
SCD1U10V2KX-4GP
Vcc1_5_A[10] Vcc1_5_A[11] Vcc1_5_A[12] Vcc1_5_A[13] Vcc1_5_A[14] Vcc1_5_A[15] Vcc1_5_A[16] Vcc1_5_A[17] Vcc1_5_A[18]
C506
C476
3D3V_S0
3D3V_S5 V3D3A_VCCPSUS R343 0R0603-PAD 2 1
3D3V_ICH_S5
3
3D3V_S0
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
TP57 TPAD28
Vcc3_3[2]
AB10 AB9 AC10 AD10 AE10 AF10 AF9 AG9 AH9
K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7
C481
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C511
VccSATAPLL
VccSus3_3[7] VccSus3_3[8] VccSus3_3[9] VccSus3_3[10] VccSus3_3[11] VccSus3_3[12] VccSus3_3[13] VccSus3_3[14] VccSus3_3[15] VccSus3_3[16] VccSus3_3[17] VccSus3_3[18]
C440
C492
SCD1U10V2KX-4GP
C517
SCD01U16V2KX-3GP
C473
AD2 AH11
A24 C24 D19 D22 G19
C488
SCD1U10V2KX-4GP
1D5V_S0
Vcc1_5_A[1] Vcc1_5_A[2] Vcc1_5_A[3] Vcc1_5_A[4] Vcc1_5_A[5] Vcc1_5_A[6] Vcc1_5_A[7] Vcc1_5_A[8] Vcc1_5_A[9]
VccSus3_3[2] VccSus3_3[3] VccSus3_3[4] VccSus3_3[5] VccSus3_3[6]
C471
SCD1U10V2KX-4GP
DY C495 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
3D3V_ICH_S5
AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5
P7
C494
SCD1U10V2KX-4GP
C461
VccDMIPLL
ATX
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0 C482
AG28
VccSus3_3[1]
3D3V_S0
SC4D7U10V5ZY-3GP
C442
Vcc3_3[1]
ARX
3D3V_S0
C465
B27
SCD1U10V2KX-4GP
C516
1D5V_S0
DY
1D5V_S0
1
R396 0R0603-PAD
1
C441
VccRTC
W5
C521
1D05V_S0
SCD1U10V2KX-4GP
68.1R220.10A
Vcc3_3[12] Vcc3_3[13] Vcc3_3[14] Vcc3_3[15] Vcc3_3[16] Vcc3_3[17] Vcc3_3[18] Vcc3_3[19] Vcc3_3[20] Vcc3_3[21]
A5 B13 B16 B7 C10 D15 F9 G11 G12 G16
3D3V_S5
SCD1U10V2KX-4GP
2 IND-1D2UH-5-GP
SCD1U10V2KX-4GP
2
1 C196
SCD01U16V2KX-3GP
1D5V_ICH_S0
1D5V_GPLL_ICH_S0
L12
SC10U10V5ZY-1GP
1D5V_S0
SCD1U10V2KX-4GP
1D5V_S0
Vcc3_3[3] Vcc3_3[4] Vcc3_3[5] Vcc3_3[6] Vcc3_3[7] Vcc3_3[8] Vcc3_3[9] Vcc3_3[10] Vcc3_3[11]
AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19
4
SCD1U10V2KX-4GP SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C512
AE23 AE26 AH26
C451
3D3V_S5
C496
3D3V_S0
C475
C472
DY
SCD1U10V2KX-4GP
C510 SCD1U16V2ZY-2GP
2
3D3V_S0
V_CPU_IO[1] V_CPU_IO[2] V_CPU_IO[3]
C474
SCD1U10V2KX-4GP
V5REF_S5
R394 100R2J-2-GP
R7
C479
SCD1U10V2KX-4GP
D12 CH751H-40PT
2nd 83.R3004.A8F
U6
C486
SCD1U10V2KX-4GP
5V_S5
Vcc3_3/VccHDA VccSus3_3/VccSusHDA
C480
SCD1U10V2KX-4GP
3D3V_S5
V5 V1 W2 W7
VCCA3GP
SCD1U16V2ZY-2GP
Layout Note: Place near ICH7
C478
VccSus3_3/VccLAN3_3[1] VccSus3_3/VccLAN3_3[2] VccSus3_3/VccLAN3_3[3] VccSus3_3/VccLAN3_3[4]
C489
SCD1U10V2KX-4GP
V5REF_S0 3
R363 100R2J-2-GP
Vcc1_5_B[1] Vcc1_5_B[2] Vcc1_5_B[3] Vcc1_5_B[4] Vcc1_5_B[5] Vcc1_5_B[6] Vcc1_5_B[7] Vcc1_5_B[8] Vcc1_5_B[9] Vcc1_5_B[10] Vcc1_5_B[11] Vcc1_5_B[12] Vcc1_5_B[13] Vcc1_5_B[14] Vcc1_5_B[15] Vcc1_5_B[16] Vcc1_5_B[17] Vcc1_5_B[18] Vcc1_5_B[19] Vcc1_5_B[20] Vcc1_5_B[21] Vcc1_5_B[22] Vcc1_5_B[23] Vcc1_5_B[24] Vcc1_5_B[25] Vcc1_5_B[26] Vcc1_5_B[27] Vcc1_5_B[28] Vcc1_5_B[29] Vcc1_5_B[30] Vcc1_5_B[31] Vcc1_5_B[32] Vcc1_5_B[33] Vcc1_5_B[34] Vcc1_5_B[35] Vcc1_5_B[36] Vcc1_5_B[37] Vcc1_5_B[38] Vcc1_5_B[39] Vcc1_5_B[40] Vcc1_5_B[41] Vcc1_5_B[42] Vcc1_5_B[43] Vcc1_5_B[44] Vcc1_5_B[45] Vcc1_5_B[46] Vcc1_5_B[47] Vcc1_5_B[48] Vcc1_5_B[49] Vcc1_5_B[50] Vcc1_5_B[51] Vcc1_5_B[52] Vcc1_5_B[53]
SCD1U10V2KX-4GP
5V_S0
D10 CH751H-40PT
2nd 83.R3004.A8F
C443 SCD1U10V2KX-4GP
3D3V_S0
C484 SCD1U10V2KX-4GP
*Within a given well, 5VREF needs to be up before the corresponding 3.3V rail
C524 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
2
C460
C491
SC10U10V5ZY-1GP
C457
AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28 D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 R25 R26 T22 T23 T26 T27 T28 U22 U23 V22 V23 W22 W23 Y22 Y23
V5REF_Sus
SCD1U10V2KX-4GP
C497
V5REF[2]
F6
SCD1U10V2KX-4GP
C507
AD17
V5REF_S5
L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
SCD1U10V2KX-4GP
C444
V5REF_S0
Vcc1_05[1] Vcc1_05[2] Vcc1_05[3] Vcc1_05[4] Vcc1_05[5] Vcc1_05[6] Vcc1_05[7] Vcc1_05[8] Vcc1_05[9] Vcc1_05[10] Vcc1_05[11] Vcc1_05[12] Vcc1_05[13] Vcc1_05[14] Vcc1_05[15] Vcc1_05[16] Vcc1_05[17] Vcc1_05[18] Vcc1_05[19] VCC PAUX Vcc1_05[20]
SCD1U10V2KX-4GP
1D5V_S0
V5REF[1]
SCD1U10V2KX-4GP
4
G10
1
U15F
C
D
Sheet E
17
of
42
A
B
C
D
E
U15E
2
1
P28 R1 R11 R12 R13 R14 R15 R16 R17 R18 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U14 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V27 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA24 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB27 AB28 AC2 AC5 AC9 AC11 AD1 AD3 AD4 AD7 AD8 AD11 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27
4
3
3D3V_S5
3D3V_S0
8 7 6 5
3
VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194]
RN64
1 2 3 4
4
VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97]
SRN4K7J-10-GP
A4 A23 B1 B8 B11 B14 B17 B20 B26 B28 C2 C6 C27 D10 D13 D18 D21 D24 E1 E2 E4 E8 E15 F3 F4 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G18 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J1 J2 J5 J24 J25 J26 K24 K27 K28 L13 L15 L24 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M17 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N14 N15 N16 N17 N18 N24 N25 N26 P3 P4 P12 P13 P14 P15 P16 P17 P24 P27
5V_S0
Q11 16,22,27 SMB_CLK
3
4
2
5
1
6 2N7002DW-1-GP
SMBC_ICH 3,11 2
84.27002.D3F 16,22,27 SMB_DATA SMBD_ICH 3,11
Q13 & Q14 connect SMLINK and SMBUS in S) for SMBus 2.0 compliance
SMBUS
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
ICH7-M-GP
71.ICH7M.00U Title
ICH7-M (4 of 4) Size
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007 A
B
C
D
Sheet E
18
of
42
Digital Output Data Bits TEMP. Sign
MSB
LSB
EXT
+127.875
0
111
1111
111
+126.375
0
111
1110
011
+25.5
0
001
1001
100
+1.75
0
000
0001
110
SB 0306 Test Point FAN1_VCC FAN1_FG1 PURE_HW_SHUTDOWN#
5V_S0
TP172 TPAD30 TP100 TPAD30 TP101 TPAD30
FAN1_VCC
111
-1.125
1
111
1110
111
-25.5
1
110
0110
100
-55.25
1
100
1000
110
001
2
4
1
3
C343 SC2200P50V2KX-2GP
2
2
1
FAN1
1 D21
1
5
*Layout* 15 mil
2
C385 SC1KP50V2KX-1GP
2
1
BAS16-1-GP
3D3V_S0
U36
ALERT# THERM# THERM_SET RESET#
V_DEGREE
5 17 8 10 12
G792_DXN2 G792_DXN3 GAP-CLOSE
DGND DGND SGND1 SGND2 SGND3
1
ALERT#
R233 2
DY 0R2J-2-GP
R230 49K9R2F-L-GP G792SFUF-GP
74.00792.A79
G63
1
2
33 PURE_HW_SHUTDOWN#
C346
G1
C348
Q19 MMBT3904-3-GP B C360 SC470P50V3JN-2GP
Q5 MMBT3904-3-GP B C116 SC470P50V3JN-2GP
SC2200P50V2KX-2GP SC2200P50V2KX-2GP
3.System Sensor, Put between CPU and NB.
H_THERMDA 4
Place near chip as close as possible
2
DXP1:108 Degree (CPU) DXP2:H/W Setting 100(System) DXP3:105 Degree (SYSTEM)
C347 SC2200P50V2KX-2GP H_THERMDC 4
1 R231 2 G792_RESET# 4K7R2F-GP
1
7,16 PWROK
1.For CPU Sensor
2
R229 10KR2F-2-GP
1
D18 R444 0R0402-PAD
1
2
PURE_HW_SHUTDOWN#
3D3V_AUX_S5
R443 DY 0R2J-2-GP 2 1
DY
INTRUDER#
15
1
2
2
3
BAW56PT-U
R446 10KR2J-3-GP
RSMRST# 30
D17 BAT54-7-F-GP
2004/11/10 CHANGE
DY 3
1
-1 0411 2
1
(dummy, KBC already delay) C569 DY SCD1U16V2ZY-2GP
2
3D3V_S5
32K suspend clock output U16
1 2 3
OE A GND
DY
VCC
5
Y
4
R399 10R2J-2-GP 1 2
32KHZ
G792_32K
1
16,26,27,30,33,36,37,38,39 PM_SLP_S3# 16 PM_SUS_CLK
NC7SZ126P5X-GP
R400 240KR3-GP
RUN_POWER_ON
D
20060810
2
73.7S126.AAH
G
V_DEGREE =(((Degree-72)*0.02)+0.34)*VCC
G792_DXP2 G792_DXP3
2
2
1
THRM#
2.HW T8 sensor
SMBD_G792 26,30 SMBC_G792 26,30
C
15 13 3 2
G792_32K
C
DXP1 DXP2 DXP3
1 4 14 16 18 19
2
7 9 11
FAN1 FG1 CLK SDA SCL NC#19
1
2
C351 C349 C350 SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
1
16
Setting T8 as 90 Degree
VCC DVCC
1
1 R234 10KR2J-3-GP
2
1
1 R232 21KR2F-GP
6 20
2
SC1U16V3ZY-GP
1
5V_G792_S0 C344
MLX-CON3-10-GP
20.F1000.003
5V_S0
*Layout* 30 mil
R228
1 2 10R3J-3-GP
2
5V_S0
2 3
FAN1_FG1
000
1111
GAP-CLOSE 2
011
C342 SC4D7U6D3V3KX-GP
1
1
1
C345 SCD1U16V2ZY-2GP
-65.000
R290 10KR2J-3-GP
FAN1_VCC
*Layout* 15 mil
E
1111
E
0000
111
1
0000
000
1
2
000
0
-0.125
1
100
0
+0.125
2
+0.5
Q13
S
2N7002-11-GP
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Thermal/Fan Controllor
Document Number
Date: Wednesday, April 18, 2007
Volvi
Rev
-1 Sheet
19
of
42
ODD Connector
SATA HD Connector SATA1
5V_S0
1
C551 SCD1U16V2ZY-2GP
DEVICE_CONFIG(CSEL)
IDE_PDCS1# IDE_PDCS3#
35 36
CSIFX# CS3FX#
IDE_PDA0 IDE_PDA1 IDE_PDA2
33 31 34
DA0 DA1 DA2
2
47 15 15
2
2
RN70
SCD1U16V2ZY-2GP
5 6 7 8
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NP2 24
ODD1
SC10U10V5ZY-1GP
3D3V_S0
5V_S0
41 42
+5V(LOGIC) +5V(LOGIC)
38 39 40
+5V(MOTOR) +5V(MOTOR) +5V(MOTOR)
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
21 19 17 15 13 11 9 7 6 8 10 12 14 16 18 20
VENDER_UNIQUE#50 VENDER_UNIQUE#49
50 49
AUDIO_GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND
3 4 23 26 43 44 45 46 48
GND GND
51 52
4 3 2 1
SRN10KJ-6-GP
ODD_LED# PDIAG
15
IDE_PDIORDY 15 INT_IRQ14
TYCO-CON22-GP
20.80392.022 31
15 15 15
15
IDE_PDDREQ
27 29 22
IORDY INTRQ DMARQ
15 15
IDE_PDIOR# IDE_PDIOW#
24 25
DIOR# DIOW#
37 32 28 5 30
DASP# PDIAG# DMACK# RESET# IOCS16#
ODD_LED# 15 IDE_PDDACK# 2
3D3V_S0
R430 1 10KR2J-3-GP
PDIAG IDE_PDDACK# HDDDRV#_5
DY
1 2
AUDIO_L_CH AUDIO_R_CH
IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15
SPD-CONN50-4R-13GP-U1 5V_S0
20.80640.050
-1 0411 13
R244 12
11
2
1
HDDDRV#_5
0R0402-PAD
U2D TSAHCT125PW-GP 1
16,22,24,27 PCIRST1#
R241 10KR2J-3-GP 2
2
2
C549
DY
14
A
SC10U10V5ZY-1GP
SSM24PT-GP
DY
C578 SCD1U16V2ZY-2GP
D31
TC15
1
1
K
5V_S0
C546
7
15 SATA_RXN0 15 SATA_RXP0
1
2 3 4 5 6 7
15 SATA_TXP0 15 SATA_TXN0
1
23 NP1 1
UMA
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
HDD and CDROM
Document Number
Rev
-1
Volvi Date: Wednesday, April 18, 2007
Sheet
20
of
42
SB 0226 5V_USB1_S0
USBCN1
5V_S5
1
SB 0306 Test Point 3D3V_S0
U56
EC114 DY SCD1U16V2ZY-2GP
1 2 3
OUT GND NC#3
IN
5
EN
4
1
C589 SC4D7U10V5ZY-3GP 2
BLUETOOTH_EN 30
USB_5+
TP102 TPAD30
USB_5-
TP103 TPAD30
2
TP104 TPAD30
USBPP1
TP105 TPAD30
USBPN3
TP106 TPAD30
USBPP3
TP107 TPAD30
USB_OC#1
TP108 TPAD30
USB_PWR_EN#
TP109 TPAD30
21.D0214.115
EC103
DY
74.05240.A7F
30
EC142 SC220P50V2JN-3GP
5V_S5 C505
-1 0412 for EMI
5V_USB1_S0 0R0402-PAD
2
1 R138 USB2 6 1 USB_2USB_2+
USBPN2 USBPP2
2 3 4 5
-1 0412 Test Point
SKT-USB-97-UGP
22.10218.H01
-1 0410 change to 0 ohm pad Remove TR1, TR2
G5240B1T1U-GP
EC21 put near BLUE1 / all USB put one choke near connector by EMI request
USBPN1
USB_OC#1 16 USB_PWR_EN#
DY 1 2 R465 0R3-0-U-GP
3D3V_BT_S0
TP175 TPAD30
16 16
BLUETOOTH MODULE 3D3V_BT_S0
TP176 TPAD30
5V_S5
R378 1
SC1U16V3ZY-GP
SCD1U16V2ZY-2GP
17 5V_S5
2
-1 0411
JST-CON15-1-GP
2nd:74.09711.073 (RT9711-BPQW-GP)
1
0R0402-PAD
2
SB 0226
1
DY
16 16
USBPN3 16 USBPP3 16
1
74.00545.073
DY
USBPN1 USBPP1
2
G545B2RD1U-GP
1
1
1
-1 0409
1 9
GND GND
2
OC#
2
EN/EN#
5
2 3 4 5 6 7 8 9 10 11 12 13 14 15
EC30
1
1 2
DY
SCD1U16V2ZY-2GP
EC105
4
EC23
SC1000P50V3JN-GP
USB_OC#0
TC13
SCD1U16V2ZY-2GP
16
100 mil
6 7 8
OUT#6 OUT#7 OUT#8
ST100U10VDM-6GP
USB_PWR_EN#
C541
IN#2 IN#3
2
2 3
2
U47 SCD1U16V3KX-3GP 2 1
16
5V_USB1_S0
0R0402-PAD
2
1 R137
0R0402-PAD
2
1 R136
5V_USB1_S0
USB1
BLUE1 6
6 1
3D3V_BT_S0
4 3 2 1
USB_5+
R482 2
1 0R0402-PAD
USBPP5
16
USB_5-
R481 2
1 0R0402-PAD
USBPN5
16
16 16
USB_0USB_0+
USBPN0 USBPP0
2 3 4 5 SKT-USB-97-UGP
5
22.10218.H01
ACES-CON4-GP
20.F0714.004
0R0402-PAD
-1 0411
2
1 R135
3 5 7 9 11
4 6 8 10 12
18
16
C581
R464 0R0603-PAD
-1 3D3V_S5 U53 1 2 3
ACZ_BTCLK_MDC 15
1
DY
2
C579 DUMMY-C2 2
100KR2J-1-GP
1
1 1 R463
2
SC4D7U10V5ZY-3GP
20.F0757.012
2
17 AMP-CONN12A-2GP
C583
IN GND EN
OUT
5
NC#4
4
DY
ME615ASN5A15-GP
74.00615.D3F
SC1U16V3ZY-GP
NP2
C580
SC1U16V3ZY-GP
C575 SC22P50V2JN-4GP
1D5V_S5
3D3V_S5
UMA 1
2
1
15
1
DY
C585
Wistron Corporation
2
ACZ_SYNC 1 2ACSDATAIN1_A R461 39R2J-L-GP ACZ_RST#
13
1D5V_S5
1
15,28 ACZ_SYNC 15 ACZ_SDATAIN1 15,28 ACZ_RST#
ACZ_SDATAOUT
2
15,28 ACZ_SDATAOUT
14
2
MDC1 NP1
SC4D7U10V5ZY-3GP 1 2
MDC 1.5 CONN
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
USB / MDC / BLUETOOTH
Document Number
Volvi
Date: Wednesday, April 18, 2007
Rev
-1 Sheet
21
of
42
5
4
3
2
1
1 2
GPIO2
PCIE_RXDP PCIE_RXDN
26 25 31 32 12 10 29 28
UART_MODE GPIO1_SERIALDI GPIO0_SERIALDO
9 7 4
UART_MODE EE_WP GPIO0
3D3V_LAN_S5
Q4 BCP69T1-1-GP
-1 0411
C56
1 2
1 2
1 2 1 2 1 2
1
1
1
2
2
68.00217.241
GPHY_PLLVDD 1
1
1
2
C48
2
PCIE_PLLVDD C62
2 R286 1 0R0402-PAD
1
2 R62 1 0R0402-PAD
2
R313 C420 SC4D7U10V5ZY-3GP FCM1608K-601T03GP C381 68.00217.241
2
1
1
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