Acer Aspire 5750_5755G Compal LA-6901P Rev2.0 schematic

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Compal Confidential 1

Model Name : JE50-HR/SJV50-HR Compal Project Name : P5WE0/P5WS0 File Name : LA-6901P

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Compal Confidential 2

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JE50-HR/SJV50-HR(P5WE0/P5WS0) M/B Schematics Document Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH Nvidia N12P GS/GV

2011-02-08

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3

REV:2.0

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Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Cover Page Rev

JE50-HR/SJV50-HR M/B SchematicsE

Date:

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Wednesday, June 08, 2011 E

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Fan Control

page 42

1

1

PEG(DIS)

100MHz

PCI-E 2.0x16 5GT/s PER LANE

Nvidia N12P GS/GV

Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual Channel

Intel Sandy Bridge

133MHz

page 11,12

BANK 0, 1, 2, 3 1.5V DDRIII 1066/1333

Processor

page22~30

rPGA989 page 4~10

HDMI(DIS)

CRT(DIS)

HDMI Conn. page 33

CRT Conn.

LVDS(DIS)

FDI x8

LVDS Conn.

page 32

page 31

2

DMI x4

100MHz

100MHz

2.7GT/s

1GB/s x4

LVDS(UMA/OPTIMUS) CRT(UMA/OPTIMUS) TMDS(UMA/OPTIMUS)

Intel Cougar Point-M

USB 2.0 conn x2

Bluetooth Conn

CMOS Camera

USB port 0,1 on USB/B page 38

USB port 13

USB port 10

page 38

USBx14

3.3V 48MHz

HD Audio

3.3V 24MHz

3G connector USB port 9,12 on 3G/B page 37

page 31

2

PCH HDA Codec

100MHz PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz

port 5

port 2,3

USB 3.0 conn x1 NEC uPD720200AF1 with USB3.0 Conn. page 45

port 1

WLAN, WWAN USB port 12,13 page 37

BCM57785

SPI ROM x1

page 35,36

port 0

Card Reader Conn. page 35,36

RJ45 page 36

34

SATA CDROM Conn. page 34

page 40

LPC BUS

4

page 43,44

3

page 39

page 38

LF-6901P

Int.KBD

Touch Pad

FPC for USB3.0

page 40

page 40

page 38

USB 3.0 /B 1 port as USB3.0 1 port as USB2.0

page 38

DC/DC Interface CKT.

page 41

ENE KB930

LS-6904P Power On/Off CKT.

page 41

Phone Jack x 2

33MHz

USB 2.0/B 2Port USB Port0,1 page 13

Int. Speaker

page 13

port 1

SATA HDD Conn. page

Sub-board LS-6901P RTC CKT.

page 41

SPI

page 13~21

LAN(GbE) & Card Reader

MINI Card x2

3

ALC271X/277X

989pin BGA

BIOS ROM page 40

LS-6903P 4

3G/B page 37

Power Circuit DC/DC page 46~59

LS-6902P + LS-6905P

Issued Date

A

2011/02/08

2012/02/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 40

WWW.AliSaler.Com

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PWR/B

Block Diagrams Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

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D

Sheet

Wednesday, June 08, 2011 E

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Voltage Rails Power Plane

1

2

Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

N/A

N/A

N/A

Full ON

ON

ON

ON

LOW

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

OFF

+VGFX_CORE

Core voltage for UMA graphic

ON

OFF

OFF

+0.75VS

+0.75VP to +0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.05VSDGPU

+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU

ON

OFF

OFF

+1.05VS_VTT

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

ON

OFF

OFF

+1.05VS_PCH

+1.05VS_VCCP to +1.05VS_PCH power for PCH

ON

OFF

OFF

+1.5V

+1.5VP to +1.5V power rail for DDRIII

ON

ON

OFF

+1.5VS

+1.5V to +1.5VS switched power rail

ON

OFF

OFF

Vcc Ra/Rc/Re

+1.5VSDGPU

+1.5VS to +1.5VSDGPU switched power rail for GPU

ON

OFF

OFF

Board ID

+1.8VS

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON

OFF

OFF

+1.8VSDGPU

+1.8VS to +1.8VSDGPU switched power rail for GPU

OFF

OFF

0 1 2 3 4 5 6 7

ON*

+3V_LAN

+3VALW to +3V_LAN power rail for LAN

ON

ON

ON*

+3VALW_PCH

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

ON

ON

ON*

+3VS

+3VALW to +3VS power rail

ON

OFF

OFF

+5VALW

+5VALWP to +5VALW power rail

ON

ON

ON*

+5VALW_PCH

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

ON

ON

ON*

+5VS

+5VALW to +5VS switched power rail

ON

OFF

OFF

+VSB

+VSBP to +VSB always on power rail for sequence control

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

Device

Address

Smart Battery

0001 011X b

3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC

V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V

V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V

BOARD ID Table Board ID 0 1 2 3 4 5 6 7

EC SM Bus2 address Device

Address

Device

PCB Revision 0.1 0.2 0.3 0.4 1.0

Address

Clock Generator (9LVS3199AKLFT, RTM890N-631-VB-GRT)

1101 0010b

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

USB Port Table USB 2.0 USB 1.1 Port UHCI0

4

3G & BT & USB30 & USB20 Config 3G SKU: 3G@ USB30 SKU: USB30@ OPTMIUS SKU: OPT@ BT SKU: BT@ USB20 SKU: USB20@ Non-OPTMIUS SKU: NOPT@ LAN Chip A0 version: A0@ N12P-GS: GS@ LAN chip B0 Version: B0@ N12P-GV: GV@ BOM Config BT@/3G@/USB30@/UMA@/UMAO@/NOPT@/A0@ UMA Only: OPTIMUS(N12P-GS): BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@/GS@ DIS Only(N12P-GS): BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@/GS@ OPTIMUS(N12P-GV): BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@/GV@ DIS Only(N12P-GV): BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@/GV@ VRAM P/N : 64*16 Samsung : SA000035700 Hynix : SA000032400/SA0000324C0 128*16 Samsung : SA00003MQ40 Hynix : SA00003VS00

UHCI1 EHCI1 UHCI2 UHCI3 UHCI4 EHCI2

UHCI5 UHCI6

0 1 2 3 4 5 6 7 8 9 10 11 12 13

2011/02/08

EVT EVT2 DVT PVT Pre-MP 2

3 External USB Port USB/B (Right Side) USB/B (Right Side) USB3.0 colay USB2.0 Conn. USB/B Colay USB3.0

BTO Item UMA Only UMA with OPTIMUS Dis with OPTIMUS DIS Only OPTIMUS Non-OPTIMUS 3G Blue Tooth USB2.0 USB3.0 VRAM Connector Unpop LAN Chip A0 version LAN Chip B0 version N12P-GS N12P-GV

BOM Structure UMAO@ UMA@ DIS@ DISO@ OPT@ NOPT@ 3G@ BT@ USB20@ USB30@ X76@ CONN@ @ A0@ B0@ GS@ GV@

3

Mini Card 1(WLAN) 3G/B(WWAN) Camera Mini Card 2(Reserved) 3G/B(SIM Card) BlueTooth

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification Issued Date

V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V

BTO Option Table

PCH SM Bus address 3

1

Board ID / SKU ID Table for AD channel

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

ON

HIGH

OFF

ON*

Clock

HIGH

ON

ON

ON

HIGH

Core voltage for GPU

ON

ON

HIGH

+VGA_CORE

ON

ON

LOW

OFF

ON

HIGH

HIGH

N/A

OFF

+3VALW always on power rail

+VS

HIGH

LOW

N/A

ON

+3VALW always to KBC

+V

HIGH

LOW

N/A

Core voltage for CPU

+3VALW_EC

+VALW

HIGH

S1(Power On Suspend)

AC or battery power rail for power circuit.

+3VALW

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

S3 (Suspend to RAM)

B+ +CPU_CORE

ON

SIGNAL

STATE

E

2012/02/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Notes List Rev

JE50-HR/SJV50-HR M/B Schematics E

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2

+1.05VS_VTT

1

ZZZ DA60000KC10 R517 24.9_0402_1%

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

B28 B26 A24 B23

DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]

15 15 15 15

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

G21 E22 F21 D21

DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]

15 15 15 15

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

G22 D22 F20 C21

DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

15 15 15 15 15 15 15 15

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

A21 H19 E19 F18 B21 C20 D18 E17

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]

15 15 15 15 15 15 15 15

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

A22 G19 E20 G18 B20 C19 D19 F17

FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3]

15 FDI_FSYNC0 15 FDI_FSYNC1

J18 J17

FDI0_FSYNC FDI1_FSYNC

15 FDI_INT

H20

R145 24.9_0402_1%

FDI_INT

15 FDI_LSYNC0 15 FDI_LSYNC1

J19 H17

FDI0_LSYNC FDI1_LSYNC

A18 A17 B16

eDP_COMPIO eDP_ICOMPO eDP_HPD

C15 D15

eDP_AUX eDP_AUX#

C17 F16 C16 G15

eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

C18 E16 D16 F15

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

PCI EXPRESS* - GRAPHICS

15 15 15 15

DMI

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]

EDP_COMP

B

eDP

2

eDP_COMPIO and ICOMPO signals should be shorted near balls, Trace Width for EDP_COMPIO=4mils, EDP_ICOMPO=12mils, and both length less than 500 mils... should not be left floating ,even if disable eDP function...

B27 B25 A25 B24

1

+1.05VS_VTT

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

Intel(R) FDI

C

15 15 15 15

2

JCPU1A D

PEG_COMP

1

PEG_ICOMPI and PEG_RCOMPO signals should be shorted and routed, max length = 500 mils,trace width=4mils PEG_ICOMPO signals should be routed with - max length = 500 mils,trace width=12mils spacing =15mils

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

J22 J21 H22

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

PEG_GTX_C_HRX_N15 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0

C46 C49 C51 C53 C60 C71 C75 C82 C92 C93 C102 C111 C113 C125 C129 C144

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K

PEG_GTX_HRX_N15 PEG_GTX_HRX_N14 PEG_GTX_HRX_N13 PEG_GTX_HRX_N12 PEG_GTX_HRX_N11 PEG_GTX_HRX_N10 PEG_GTX_HRX_N9 PEG_GTX_HRX_N8 PEG_GTX_HRX_N7 PEG_GTX_HRX_N6 PEG_GTX_HRX_N5 PEG_GTX_HRX_N4 PEG_GTX_HRX_N3 PEG_GTX_HRX_N2 PEG_GTX_HRX_N1 PEG_GTX_HRX_N0

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0

C47 C50 C52 C56 C66 C68 C81 C86 C89 C100 C105 C106 C117 C119 C135 C138

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K

PEG_GTX_HRX_P15 PEG_GTX_HRX_P14 PEG_GTX_HRX_P13 PEG_GTX_HRX_P12 PEG_GTX_HRX_P11 PEG_GTX_HRX_P10 PEG_GTX_HRX_P9 PEG_GTX_HRX_P8 PEG_GTX_HRX_P7 PEG_GTX_HRX_P6 PEG_GTX_HRX_P5 PEG_GTX_HRX_P4 PEG_GTX_HRX_P3 PEG_GTX_HRX_P2 PEG_GTX_HRX_P1 PEG_GTX_HRX_P0

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

PEG_HTX_GRX_N15 PEG_HTX_GRX_N14 PEG_HTX_GRX_N13 PEG_HTX_GRX_N12 PEG_HTX_GRX_N11 PEG_HTX_GRX_N10 PEG_HTX_GRX_N9 PEG_HTX_GRX_N8 PEG_HTX_GRX_N7 PEG_HTX_GRX_N6 PEG_HTX_GRX_N5 PEG_HTX_GRX_N4 PEG_HTX_GRX_N3 PEG_HTX_GRX_N2 PEG_HTX_GRX_N1 PEG_HTX_GRX_N0

C516 C520 C529 C534 C538 C540 C542 C544 C546 C548 C550 C552 C554 C556 C558 C560

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K

PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N0

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_HTX_GRX_P15 PEG_HTX_GRX_P14 PEG_HTX_GRX_P13 PEG_HTX_GRX_P12 PEG_HTX_GRX_P11 PEG_HTX_GRX_P10 PEG_HTX_GRX_P9 PEG_HTX_GRX_P8 PEG_HTX_GRX_P7 PEG_HTX_GRX_P6 PEG_HTX_GRX_P5 PEG_HTX_GRX_P4 PEG_HTX_GRX_P3 PEG_HTX_GRX_P2 PEG_HTX_GRX_P1 PEG_HTX_GRX_P0

C515 C528 C533 C536 C539 C541 C543 C545 C547 C549 C551 C553 C555 C557 C559 C561

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K

PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P0

D

PEG_GTX_HRX_N[0..15] 22 PEG_GTX_HRX_P[0..15] 22 PEG_HTX_C_GRX_N[0..15] 22 PEG_HTX_C_GRX_P[0..15] 22

C

B

Sandy Bridge_rPGA_Rev0p61 CONN@

Typ- suggest 220nF. The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s)

A

A

Compal Secret Data

Security Classification Issued Date

WWW.AliSaler.Com 5

2011/02/08

Deciphered Date

2012/02/08

Title

PROCESSOR(1/7) DMI,FDI,PEG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Wednesday, June 08, 2011

Sheet 1

4

of

61

5

4

3

2

1

Buffered reset to CPU +3VS

D

D

+3VALW

15 SYS_PWROK

2

15 PM_DRAM_PWRGD

R88 0_0402_5% @

1

B

2

A

2

200_0402_1%

4

O

PM_SYS_PWRGD_BUF

1 R204

2 130_0402_5%

PM_DRAM_PWRGD_R 1

SN74LVC1G07DCKR_SC70-5

U11 74AHC1G09GW_TSSOP5

5

BUFO_CPU_RST#

R205

2

P

A

4

1

1 R87 43_0402_1% 1 2 BUF_CPU_RST#

2

U7

G

2

R90 75_0402_1%

1

R203 39_0402_1%

3

PLT_RST#

C307 0.1U_0402_16V4Z

2

1

PLT_RST#

Y

+1.5V_CPU_VDDQ

3

17

NC

G

1

+1.05VS_VTT C162 0.1U_0402_16V4Z

P

5

1

2

RESET#:都ok後請CPU做reset

+1.05VS_VTT

18,40 2 R91

H_PECI

1 62_0402_5% H_PROCHOT#

40,50 H_PROCHOT#

18 H_THRMTRIP#

R92 56_0402_5% 1 2

SKTOCC#

AL33

CATERR#

H_PECI

AN33

PECI

H_PROCHOT#_R AL32

H_THEMTRIP#

AN32

PROCHOT#

CLOCKS

AN34

H_CATERR# @

Processor Pullups

SNB_IVB#

BCLK BCLK#

A28 A27

DPLL_REF_SSCLK DPLL_REF_SSCLK#

A16 A15

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

AP33

UNCOREPWRGOOD

1 10K_0402_5% H_CPUPWRGD

18 H_CPUPWRGD

UNCOREPWRGOOD:非CORE外的電OK PM_DRAM_PWRGD_R

V8

SM_DRAMPWROK

SM_DRAMPWROK:DRAM power ok BUF_CPU_RST# AR33

RESET#

1 1K_0402_5% 1 1K_0402_5%

2 2

SM_DRAMRST#

AK1 A5 A4

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

+1.05VS_VTT

If use External Graphic or use integrated without eDP DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT SM_DRAMRST# 6

R231 R566 R571

1 140_0402_1% 1 25.5_0402_1% 1 200_0402_1%

2 2 2

R03 modify

PRDY# PREQ#

AP29 AP27

TCK TMS TRST#

AR26 AR27 AP30

TCK TMS TRST#

PAD PAD PAD

T66 T67 T68

TDI TDO

AR28 AP26

TDI TDO

PAD PAD

T69 T70

DBR#

AL35

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

@ @ @

+3VS

@ @

B

R40 1K_0402_5% 2

PM_SYNC

CLK_CPU_DMI 14 CLK_CPU_DMI# 14

DDR3 Compensation Signals

JTAG & BPM

AM34

PWR MANAGEMENT

R84 2

H_PM_SYNC

R516 R518

R8

THERMTRIP#

B

15 H_PM_SYNC

CLK_CPU_DMI CLK_CPU_DMI#

1

PAD

C26

DDR3 MISC

T6

C

MISC

17 H_SNB_IVB#

JCPU1B

THERMAL

SNB_IVB# had changed the name to PROC_SELCT#,function for future platform, connect to the DF_TVS strap on the PCH

C

@

XDP_DBRESET#

XDP_DBRESET# 15

Sandy Bridge_rPGA_Rev0p61 CONN@

A

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PROCESSOR(2/7) PM,XDP,CLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

5

of

61

5

4

3

2

JCPU1D

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

D

C

C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

AE10 AF10 V6

SA_BS[0] SA_BS[1] SA_BS[2]

AE8 AD9 AF9

SA_CAS# SA_RAS# SA_WE#

11 DDR_A_BS0 11 DDR_A_BS1 11 DDR_A_BS2

B

11 DDR_A_CAS# 11 DDR_A_RAS# 11 DDR_A_WE#

DDR SYSTEM MEMORY A

11 DDR_A_D[0..63]

SA_CLK[0] SA_CLK#[0] SA_CKE[0]

AB6 AA6 V9

SA_CLK_DDR0 11 12 DDR_B_D[0..63] SA_CLK_DDR#0 11 DDRA_CKE0_DIMMA 11

SA_CLK[1] SA_CLK#[1] SA_CKE[1]

AA5 AB5 V10

SA_CLK_DDR1 11 SA_CLK_DDR#1 11 DDRA_CKE1_DIMMA 11

SA_CLK[2] SA_CLK#[2] SA_CKE[2]

AB4 AA4 W9

SA_CLK[3] SA_CLK#[3] SA_CKE[3]

AB3 AA3 W10

SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3]

AK3 AL3 AG1 AH1

DDRA_CS0_DIMMA# 11 DDRA_CS1_DIMMA# 11

SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3]

AH3 AG3 AG2 AH2

SA_ODT0 11 SA_ODT1 11

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

C4 G6 J3 M6 AL6 AM8 AR12 AM15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

D4 F6 K3 N6 AL5 AM9 AR11 AM14

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

11

11

11

12 DDR_B_BS0 12 DDR_B_BS1 12 DDR_B_BS2

12 DDR_B_CAS# 12 DDR_B_RAS# 12 DDR_B_WE#

Sandy Bridge_rPGA_Rev0p61 CONN@

2 DIMM_DRAMRST#_R 1 Q12 BSS138_NL_SOT23-3

2

3

2

1

A

G

R186 4.99K_0402_1%

11,12,14 RST_GATE 1

2

C293 0.047U_0402_16V7K

WWW.AliSaler.Com 5

AA9 AA7 R6

SB_BS[0] SB_BS[1] SB_BS[2]

AA10 AB8 AB9

SB_CAS# SB_RAS# SB_WE#

SB_CLK[0] SB_CLK#[0] SB_CKE[0]

AE2 AD2 R9

SB_CLK_DDR0 12 SB_CLK_DDR#0 12 DDRB_CKE0_DIMMB 12

SB_CLK[1] SB_CLK#[1] SB_CKE[1]

AE1 AD1 R10

SB_CLK_DDR1 12 SB_CLK_DDR#1 12 DDRB_CKE1_DIMMB 12

SB_CLK[2] SB_CLK#[2] SB_CKE[2]

AB2 AA2 T9

SB_CLK[3] SB_CLK#[3] SB_CKE[3]

AA1 AB1 T10

SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3]

AD3 AE3 AD6 AE6

DDRB_CS0_DIMMB# 12 DDRB_CS1_DIMMB# 12

SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3]

AE4 AD4 AD5 AE5

SB_ODT0 12 SB_ODT1 12

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

D7 F3 K6 N3 AN5 AP9 AK12 AP15

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

C7 G3 J6 M3 AN6 AP8 AK11 AP14

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

D

12

C

12

12

B

Sandy Bridge_rPGA_Rev0p61 CONN@

R217 1K_0402_5%

D

S

SM_DRAMRST#

5 SM_DRAMRST#

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

1

@R184 @ R184 0_0402_5% 1 2

C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

+1.5V

Follow CRB1.0

CPU通知DIMM做reset

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR SYSTEM MEMORY B

JCPU1C

1

1

R155 1K_0402_5% 2

DIMM_DRAMRST# 11,12

S0 RST_GATE hgih ,MOS ON SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH Dimm not reset S3 RST_GATE Low ,MOS OFF SM_DRAMRST# lo,DIMM_DRAMRST# HIGH Dimm not reset S4,5 RST_GATE Low ,MOS OFF SM_DRAMRST# lo,DIMM_DRAMRST# low Dimm reset

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PROCESSOR(3/7) DDRIII

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Wednesday, June 08, 2011

Sheet 1

6

of

61

5

4

3

2

1

CFG Straps for Processor

1

CFG2

2

R112 1K_0402_5% D

JCPU1E

RSVD5

B4 D1

RSVD6 RSVD7

RSVD6 and RSVD7 had changed to SA_DIMM_VREFDQ and SB_DIMMVREFDQ SA_DIMM_VREFDQ SB_DIMM_VREFDQ 1

SA_DIMM_VREFDQ SB_DIMM_VREFDQ For Future CPU M3 support, Sandey bridge not supportM3, Check list1.0&CRB say can NC

1

11 SA_DIMM_VREFDQ 12 SB_DIMM_VREFDQ

R164 1K_0402_5% 2

2

R154 1K_0402_5%

1

VCCIO_SEL B

R513 10K_0402_5% 2

@

*

J20 B18 A19

RSVD24 RSVD25 RSVD26

J15

RSVD27

RSVD37 RSVD38 RSVD39 RSVD40

T8 J16 H16 G16

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

AR35 AT34 AT33 AP35 AR34

RSVD46 RSVD47 RSVD48 RSVD49 RSVD50

B34 A33 A34 B35 C35

1/NC : (Default) +1.05VS_VTT

*

CFG4

C

1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6 CFG5

RSVD51 RSVD52

AJ32 AK32

RSVD53

AH27

RSVD54 RSVD55

AN35 AM35

R107 1K_0402_5% @

@

R108 1K_0402_5%

AH27 change to VCC_DIE_SENSE PAD

T7

@

PCIE Port Bifurcation Straps

RSVD56 RSVD57 RSVD58

KEY

RSVD54 and RSVD55 had changed to BCLK_ITP and BCLK_ITP#

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]

*10: x8, x8 - Device 1 function 1 enabled ; function 2

B

disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

AT2 AT1 AR1

B1

CFG7

0: +1.0VS_VTT

1

A19

For 2012 CPU support

RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23

@

RSVD26 had changed the name to VCCIO_SEL Need PH +3VALW 10K at +1.05VS_VTT source for 2012 processor +1.05V and +1.0V select

R102 1K_0402_5%

@ Sandy Bridge_rPGA_Rev0p61

2

VCCIO_SEL

VCCIO_SEL

F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29

0:Lane Reversed CFG4

1

AJ26

*

definition matches

Display Port Presence Strap

RESERVED

RSVD1 RSVD2 RSVD3 RSVD4

RSVD33 RSVD34 RSVD35

AT26 AM33 AJ27

1: Normal Operation; Lane # socket pin map definition

CFG2

R109 1K_0402_5%

C

AJ31 AH31 AJ33 AH33

RSVD28 RSVD29 RSVD30 RSVD31 RSVD32

2

CFG4 CFG5 CFG6 CFG7

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]

1

CFG2

AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29

2

CFG0 @

1

PAD

PEG Static Lane Reversal - CFG2 is for the 16x L7 AG7 AE7 AK2 W8

2

T8

D

CONN@

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

A

Compal Electronics, Inc. PROCESSOR(4/7) RSVD,CFG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

7

of

61

3

JCPU1F

QC 94A DC 53A

PEG AND DDR CORE SUPPLY

2

2

D

R02 modify @

ME interefer,not pop!!

1

1

+1.05VS_VTT

2

SVID

+

2

C641 22U_0805_6.3V6M

1

@

C291 22U_0805_6.3V6M

+

2

1

C

R450 130_0402_5%

AJ29 AJ30 AJ28

2

1

1

INTEL Recommend 2*330uF,12*22uF from PDDG 1.0

+1.05VS_VTT

VIDALERT# VIDSCLK VIDSOUT

+

2

C292 22U_0805_6.3V6M

R447 75_0402_1%

R448 43_0402_1% 1 2 R446 1 2 0_0402_5% R449 1 2 0_0402_5%

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

VR_SVID_ALRT# 55 VR_SVID_CLK 55 VR_SVID_DAT 55

Place the PU resistors close to VR

B

Place the PU resistors close to CPU

1

+CPU_CORE

R445 100_0402_1% AJ35 VCCSENSE_R AJ34 VSSSENSE_R

R444 1 R443 1

2 2

0_0402_5% 0_0402_5%

VCCSENSE 55 VSSSENSE 55 1

VCC_SENSE VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

B10 A10

R442 100_0402_1%

VCCIO_SENSE 53

VSSIO_SENSE

VSSIO_SENSE change to VSS_SENSE_VCCIO

R163 10_0402_5% 2

SENSE LINES

C151 330U_D2_2V_Y

2

1

2

1

C816 220U_B2_2.5VM_R35

C626 330U_D2_2V_Y

2

1 @

2

1

C229 22U_0805_6.3V6M

C233 330U_D2_2V_Y

2

1 @

2

C638 330U_D2_2V_Y

DC@

2

1

2

1

C232 22U_0805_6.3V6M

DC@

1

2

1

C616 330U_D2_2V_Y

C152 330U_D2_2V_Y

DC@

J23

2

1

C288 22U_0805_6.3V6M

DC@

VCCIO40

2

1

C648 22U_0805_6.3V6M

B

2

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

1

C289 22U_0805_6.3V6M

QC@

+

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

+1.05VS_VTT 1

C649 22U_0805_6.3V6M

2 3

1

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

C652 22U_0805_6.3V6M

QC@

+

2

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

C650 22U_0805_6.3V6M

2 3

1

1

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100

C647 22U_0805_6.3V6M

QC@

+

2

2

C606 22U_0805_6.3V6M

2 3

1

C562 330U_D2_2V_Y

QC@

+

C151 470U_D2_2VM_R4M

2 3

1

C626 470U_D2_2VM_R4M

+

C233 470U_D2_2VM_R4M

1

C152 470U_D2_2VM_R4M

PAW00 use 470uF*2 330uF*3

1

1

C160 22U_0805_6.3V6M

Follow Power Suggestion , place 3-pin Cap for CPU_CORE

2

C607 22U_0805_6.3V6M

+CPU_CORE

1

C171 22U_0805_6.3V6M

2

C608 22U_0805_6.3V6M

1

C172 22U_0805_6.3V6M

2

2

C609 22U_0805_6.3V6M

1

1

C575 22U_0805_6.3V6M

2

2

C610 22U_0805_6.3V6M

1

1

C635 22U_0805_6.3V6M

2

2

C226 22U_0805_6.3V6M

2

1

1

C627 22U_0805_6.3V6M

2

1

2

C225 22U_0805_6.3V6M

1

1

C574 22U_0805_6.3V6M

INTEL Recommend 4*470uF,16*22uF and 10*10uF from PDDG 1.0

2

C224 22U_0805_6.3V6M

C

C622 22U_0805_6.3V6M

2

1

+1.05VS_VTT

8.5A

C651 22U_0805_6.3V6M

+CPU_CORE

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26

C290 22U_0805_6.3V6M

2

C222 10U_0805_10V4Z

1

C202 10U_0805_10V4Z

2

2

C207 10U_0805_10V4Z

1

1

C203 10U_0805_10V4Z

2

2

C218 10U_0805_10V4Z

2

1

C223 10U_0805_10V4Z

2

1

C227 10U_0805_10V4Z

1

2

1

C204 10U_0805_10V4Z

D

2

1

C205 10U_0805_10V4Z

2

1

C206 10U_0805_10V4Z

1

1

POWER

2

+CPU_CORE

1

2

SV type CPU

2

2

4

1

5

Should change to connect form power cirucit & layout differential with VCCIO_SENSE.

A

A

Sandy Bridge_rPGA_Rev0p61

Compal Secret Data

Security Classification CONN@

Issued Date

WWW.AliSaler.Com 5

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PROCESSOR(5/7) PWR,BYPASS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

8

of

61

5

4

3

2

1

D

D

1 2 1

1

2

1

2

1

2

1

2

1

2

1

2

1 + 2

+1.5VS J5 1

Short for +1.5VS to +1.5V_1

INTEL Recommend 1*330uF,6*10uF from PDDG 1.0

+VCCSA

2

1

2

1

2

@

1

2

H23

1

2

1

2

1 +

C221 220U_B2_2.5VM_R35

1

C829 10U_0603_6.3V6M

M27 M26 L26 J26 J25 J24 H26 H25

R1371

@

2

R1411

2 0_0402_5%

VSSSA_SENSE 52

VCCSA_SENSE 52

C22 VCCSA_VID0 C24

FC_C22 change to VCCSA_VID0

Sandy Bridge_rPGA_Rev0p61

VCCSA_VID1

VCCSA_VID1 52

VID0

VID1

Vout

2011CPU

2012CPU

0

0

0.9V

V

V

0

1

0.8V

V

V

1

0

0.725V

X

V

1

1

0.675V

X

V

R138 @ 0_0402_5%

2

1

R143 10K_0402_5%

Compal Secret Data

Security Classification Issued Date

VCCSA_SENSE

2 0_0402_5%

If possible,use os-con cap if not,use the D2 size

VCCSA FC_C22 VCCSA_VID1

CONN@

INTEL Recommend 1*330uF,1*10uF and 2*1uF(0402) from PDDG 1.0

B

+VCCSA

R06 Modify

6A

VCCSA_SENSE

2

PAD-OPEN 4x4m @

INTEL Recommend 1*330uF,3*10uF from PDDG 1.0 VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

2

PAD-OPEN 4x4m @

C355 330U_D2_2V_Y

1

C361 10U_0805_10V4Z

VCCPLL1 VCCPLL2 VCCPLL3

J4

10A

C828 10U_0603_6.3V6M

2

B6 A6 A2

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

C213 10U_0603_6.3V6M

2

2

1

C653 1U_0402_6.3V6K

2

1

C654 1U_0402_6.3V6K

+

1

C655 10U_0805_10V4Z

@

1

C664 220U_B2_2.5VM_R35

2

C830 10U_0603_6.3V6M

C831 10U_0603_6.3V6M

2

1

+1.5V VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

C219 10U_0805_10V4Z

+1.8VS_VCCPLL 1

A

1.2A

R06 Modify

R575 100_0402_1%

+1.5V_CPU_VDDQ

C605 10U_0805_10V4Z

R528 0_0805_5% 1 2

1

2

C214 10U_0805_10V4Z

+1.8VS

C688 0.1U_0402_16V4Z

C365 10U_0805_10V4Z

‧ Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed in a common motherboard design, ‧ VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed

+V_SM_VREF

AL1

C341 10U_0805_10V4Z

Vaxg B

SM_VREF

C

R582 100_0402_1%

C362 10U_0805_10V4Z

UMA@ 2

+V_SM_VREF should have 20 mil trace width

C364 10U_0805_10V4Z

UMA@ 2

1

+1.5V_CPU_VDDQ

C363 10U_0805_10V4Z

2

2

C599 22U_0805_6.3V6M

@

1

UMA@ 1

C275 22U_0805_6.3V6M

2

2

C600 22U_0805_6.3V6M

@

1

UMA@ 1

C242 22U_0805_6.3V6M

UMA@

2

C273 22U_0805_6.3V6M

1

UMA@ 1

C271 22U_0805_6.3V6M

2

2

C208 22U_0805_6.3V6M

2

+

UMA@ 1

C274 22U_0805_6.3V6M

+

1

2

C645 330U_D2_2V_Y

@

C646 330U_D2_2V_Y

1

UMA@ 1

C209 22U_0805_6.3V6M

2

C210 22U_0805_6.3V6M

UMA@ 1

VCC_AXG_SENSE 55 VSS_AXG_SENSE 55

2

C

AK35 AK34

1

2

VAXG_SENSE VSSAXG_SENSE

2

2

SENSE LINES

2

VREF

2

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

DDR3 -1.5V RAILS

2

AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17

SA RAIL

2

POWER

JCPU1G

MISC

2

UMA@ 1

C231 22U_0805_6.3V6M

UMA@ 1

C211 22U_0805_6.3V6M

UMA@ 1

C272 22U_0805_6.3V6M

UMA@ 1

C212 22U_0805_6.3V6M

UMA@ 1

C625 22U_0805_6.3V6M

UMA@ 1

C611 22U_0805_6.3V6M

R151 0_0402_5% DISO@

QC 33A DC 26A

GRAPHICS

1

+VGFX_CORE

1.8V RAIL

INTEL Recommend 2*470uF,12*22uF from PDDG 1.0

2011/02/08

2012/02/08

Deciphered Date

Title

A

Compal Electronics, Inc. PROCESSOR(6/7) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

9

of

61

5

4

3

2

JCPU1H D

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25

C

B

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

1

JCPU1I

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

D

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

C

B

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

CONN@

CONN@

A

A

Compal Secret Data

Security Classification Issued Date

WWW.AliSaler.Com 5

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PROCESSOR(7/7) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

10

of

61

5

4

3

2

1

1

+1.5V

R320 1K_0402_5%

+1.5V

DDR_A0_DM0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9

6

DDR_A_DQS[0..7]

6

DDR_A_D[0..63]

6

DDR_A_MA[0..15]

6

DDR_A_DQS#1 DDR_A_DQS1

All VREF traces should have 10 mil trace width

DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17

Layout Note: Place near JDIMM1

DDR_A_DQS#2 DDR_A_DQS2

+1.5V DDR_A_D18 DDR_A_D19

1

2

1

2

C409 1U_0402_6.3V6K

2

C410 1U_0402_6.3V6K

1

C385 1U_0402_6.3V6K

2

C371 1U_0402_6.3V6K

1

DDR_A_D24 DDR_A_D25 DDR_A0_DM3 DDR_A_D26 DDR_A_D27

DDRA_CKE0_DIMMA

6 DDRA_CKE0_DIMMA

+1.5V

DDR_A_BS2

6 DDR_A_BS2

2

1

2

C414 10U_0603_6.3V6M

2

1

C415 10U_0603_6.3V6M

2

1

C378 10U_0603_6.3V6M

1

C384 10U_0603_6.3V6M

C

DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 SA_CLK_DDR0 SA_CLK_DDR#0

6 SA_CLK_DDR0 6 SA_CLK_DDR#0 +1.5V

R05 modify

2

@

1 + 2

6 DDR_A_WE# 6 DDR_A_CAS#

DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDRA_CS1_DIMMA#

6 DDRA_CS1_DIMMA#

@

DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41

+0.75VS

DDR_A0_DM5

2

1

2

C388 1U_0402_6.3V6K

2

1

C394 1U_0402_6.3V6K

2

1

C395 1U_0402_6.3V6K

1

C393 1U_0402_6.3V6K

B

DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51

Layout Note: Place near JDIMM1.203,204

DDR_A_D56 DDR_A_D57 DDR_A0_DM7

DDR_A0_DM0 DDR_A0_DM1 DDR_A0_DM2 DDR_A0_DM3 DDR_A0_DM4 DDR_A0_DM5 DDR_A0_DM6 DDR_A0_DM7

DDR_A_D58 DDR_A_D59

+3VS

2 1

2

R301 10K_0402_5%

2

R302 10K_0402_5%

2

1

C416 2.2U_0603_6.3V6K

1

C404 0.1U_0402_16V4Z

R05 modify

1

+0.75VS

205

G1

CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

G2

206

DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7

D

DDR_A_D12 DDR_A_D13 DDR_A0_DM1 DDR3_DRAMRST#

DIMM_DRAMRST# 6,12

DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A0_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31

DDRA_CKE1_DIMMA

DDRA_CKE1_DIMMA

6

DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7

C

DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 SA_CLK_DDR1 SA_CLK_DDR#1

SA_CLK_DDR1 6 SA_CLK_DDR#1 6

DDR_A_BS1 DDR_A_RAS#

DDR_A_BS1 6 DDR_A_RAS# 6

DDRA_CS0_DIMMA# SA_ODT0

DDRA_CS0_DIMMA# SA_ODT0 6

SA_ODT1

SA_ODT1 6

+1.5V

6

R267 1K_0402_5%

+VREF_CA DDR_A_D36 DDR_A_D37 1

DDR_A0_DM4 DDR_A_D38 DDR_A_D39

2

1

2

DDR_A_D44 DDR_A_D45

C373 0.1U_0402_16V4Z

DDR_A_D32 DDR_A_D33

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

DDR_A_D4 DDR_A_D5

C372 2.2U_0603_6.3V6K

C407 330U_D2_2V_Y

2

1

C383 10U_0603_6.3V6M

1

C412 10U_0603_6.3V6M

2

C413 10U_0603_6.3V6M

1

6 DDR_A_BS0

DDR_A_MA10 DDR_A_BS0

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

1

6,12,14 RST_GATE DDR_A_DQS#[0..7]

2

VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26

2

2

2

DDR_A_D0 DDR_A_D1

VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25

1

G

D

1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

R266 1K_0402_5% 2

2

BSS138_NL_SOT23-3

1

C411 0.1U_0402_16V4Z

R319 1K_0402_5%

1 Q46 @

C408 2.2U_0603_6.3V6K

D

S

3

+1.5V JDIMM1

+V_DDR_REFA

1

7 SA_DIMM_VREFDQ

@ R133 0_0402_5% 1 2

2

M3 support

DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47

B

DDR_A_D52 DDR_A_D53 DDR_A0_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 D_CK_SDATA D_CK_SCLK

D_CK_SDATA 12,14 D_CK_SCLK 12,14

+0.75VS

FOX_AS0A626-U8SN-7F CONN@



DIMM_1 Reserve H:8mm A

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

Deciphered Date

2012/02/08

Title

Compal Electronics, Inc. DDRIII DIMMA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Wednesday, June 08, 2011 1

Sheet

11

of

61

5

4

3

2

1

1

+1.5V

+1.5V

2

DDR_B0_DM0 DDR_B_D2 DDR_B_D3

2

G

DDR_B_D8 DDR_B_D9

6,11,14 RST_GATE D

DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#[0..7] DDR_B_DQS[0..7] DDR_B_D[0..63]

All VREF traces should have 10 mil trace width

6 6

DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17

6

DDR_B_MA[0..15]

6

DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19

Layout Note: Place near JDIMM2

DDR_B_D24 DDR_B_D25

+1.5V

DDR_B0_DM3

1

2

1

2

C429 1U_0402_6.3V6K

2

C430 1U_0402_6.3V6K

1

C444 1U_0402_6.3V6K

2

C445 1U_0402_6.3V6K

1

DDR_B_D26 DDR_B_D27

DDRB_CKE0_DIMMB

6 DDRB_CKE0_DIMMB

DDR_B_BS2

6 DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

+1.5V

DDR_B_MA8 DDR_B_MA5

2

1

2

C449 10U_0603_6.3V6M

2

1

C450 10U_0603_6.3V6M

2

1

C425 10U_0603_6.3V6M

1

C424 10U_0603_6.3V6M

C

DDR_B_MA3 DDR_B_MA1 6 SB_CLK_DDR0 6 SB_CLK_DDR#0

SB_CLK_DDR0 SB_CLK_DDR#0

6 DDR_B_BS0

DDR_B_MA10 DDR_B_BS0 DDR_B_WE# DDR_B_CAS#

6 DDR_B_WE# 6 DDR_B_CAS#

+1.5V

DDR_B_MA13 DDRB_CS1_DIMMB#

6 DDRB_CS1_DIMMB#

2

DDR_B_D32 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35

@ DDR_B_D40 DDR_B_D41 DDR_B0_DM5 DDR_B_D42 DDR_B_D43

+0.75VS

2

1

2

C428 1U_0402_6.3V6K

2

1

C439 1U_0402_6.3V6K

2

1

C427 1U_0402_6.3V6K

1

C440 1U_0402_6.3V6K

B

DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57

+3VS

DDR_B0_DM7 2 1

DDR_B0_DM0 DDR_B0_DM1 DDR_B0_DM2 DDR_B0_DM3 DDR_B0_DM4 DDR_B0_DM5 DDR_B0_DM6 DDR_B0_DM7

R344 10K_0402_5%

Layout Note: Place near JDIMM2.203,204

DDR_B_D58 DDR_B_D59

+3VS

2

2

R345 10K_0402_5%

R05 modify

1

C436 2.2U_0603_6.3V6K

2

C435 0.1U_0402_16V4Z

1

1

+0.75VS

205

G1

CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

G2

206

DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 DDR_B0_DM1 DDR3_DRAMRST#

D

DIMM_DRAMRST# 6,11

DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B0_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31

DDRB_CKE1_DIMMB

DDRB_CKE1_DIMMB

6

DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 C

DDR_B_MA2 DDR_B_MA0 SB_CLK_DDR1 SB_CLK_DDR#1

SB_CLK_DDR1 6 SB_CLK_DDR#1 6

DDR_B_BS1 DDR_B_RAS#

DDR_B_BS1 6 DDR_B_RAS# 6

DDRB_CS0_DIMMB# SB_ODT0

DDRB_CS0_DIMMB# SB_ODT0 6

SB_ODT1

SB_ODT1 6

+1.5V

6

R351 1K_0402_5%

+VREF_CC DDR_B_D36 DDR_B_D37 1

DDR_B0_DM4 DDR_B_D38 DDR_B_D39

2

1

2

DDR_B_D44 DDR_B_D45

C446 0.1U_0402_16V4Z

+

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

C451 2.2U_0603_6.3V6K

2

1

C359 330U_D2_2V_Y

2

1

C426 10U_0603_6.3V6M

1

C447 10U_0603_6.3V6M

2

C448 10U_0603_6.3V6M

1

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26

1

2

2

BSS138_NL_SOT23-3

DDR_B_D0 DDR_B_D1

VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25

2

R340 1K_0402_5%

1 Q47 @

1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

1

2 1

1

C437 0.1U_0402_16V4Z

D

S

3

+1.5V JDIMM2

+V_DDR_REFC C438 2.2U_0603_6.3V6K

7 SB_DIMM_VREFDQ

@ R346 0_0402_5% 1 2

R350 1K_0402_5% 2

R341 1K_0402_5%

M3 support

DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 B

DDR_B0_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 D_CK_SDATA D_CK_SCLK

D_CK_SDATA 11,14 D_CK_SCLK 11,14

+0.75VS

FOX_AS0A626-U4RN-7F CONN@



DIMM_2 Reserve H:4mm

A

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

Deciphered Date

2012/02/08

Title

Compal Electronics, Inc. DDRIII DIMMB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

WWW.AliSaler.Com

4

3

2

Wednesday, June 08, 2011 1

Sheet

12

of

61

5

4

3

2

1

PCH_RTCX1

+RTCVCC

1

+RTCBATT

1

C686 18P_0402_50V8J

JBATT2

+

4 OSC

OSC

NC

NC 2

C682

2

3

18P_0402_50V8J

1

R05 modify

32.768KHZ_12.5PF_Q13MC14610002

Y3

D

PCH_RTCX2

2 10M_0402_5%

1

1 R568

2

D

2 1M_0402_5%

SM_INTRUDER#

R585 1

2 330K_0402_5%

PCH_INTVRMEN

CONN@

2

-

R567 1

SUYIN_060003HA002G202ZL

INTVRMEN

*

H：Integrated VRM enable L：Integrated VRM disable

(INTVRMEN should always be pull high.)

RTCRST close RAM door +3VS

C

HDA_SDO

C360 1U_0603_10V6K 1 2 R248 20K_0402_1% 1 2 R243 20K_0402_1%

HDA_SDOUT_PCH

C356 1U_0603_10V6K

2

1

J2 0_0603_5% @

2

A20

RTCX1

PCH_RTCX2

C20

RTCX2

PCH_RTCRST#

D20

RTCRST#

PCH_SRTCRST#

G22

SRTCRST#

SM_INTRUDER#

K22

INTRUDER#

PCH_INTVRMEN

C17

INTVRMEN

HDA_BITCLK_PCH

N34

HDA_BCLK

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

C38 A38 B37 C37

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

FWH4 / LFRAME#

D36

LPC_FRAME#

LDRQ0# LDRQ1# / GPIO23

E36 K36

SERIRQ

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

+3VS

LPC_FRAME# 40

SERIRQ

V5

40 40 40 40

SERIRQ

This signal has a weak internal pull-down 42

*

On Die PLL VR Select is supplied by 1.5V when smapled high 1.8V when sampled low Needs to be pulled High for Huron River platfrom

HDA_SDIN0

HDA_SYNC_PCH

L34

HDA_SYNC

PCH_SPKR

T10

SPKR

HDA_RST_PCH#

K34

HDA_RST#

HDA_SDIN0

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

Prevent back drive issue.

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

+3VS

1

42 HDA_SDOUT_AUDIO

1

+3VALW_PCH

Q36 BSS138_NL_SOT23-3 1HDA_SYNC_PCH

R674 51_0402_5% 2 1

2 @ R540 0_0402_5%

R03 modify R792 1M_0402_5%

+3VALW_PCH

PCH_JTAG_TCK

J3

JTAG_TCK

PCH_JTAG_TMS

H7

JTAG_TMS

PCH_JTAG_TDI

K5

JTAG_TDI

PCH_JTAG_TDO

H1

JTAG_TDO

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

AM3 AM1 AP7 AP5

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

AM10 SATA_PRX_DTX_N1 AM8 SATA_PRX_DTX_P1 AP11 SATA_PTX_DRX_N1 AP10 SATA_PTX_DRX_P1

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

AD7 AD5 AH5 AH4

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

AB8 AB10 AF3 AF1

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

Y7 Y5 AD3 AD1

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

Y3 Y1 AB3 AB1

SATAICOMPO

Y11

SATAICOMPI

Y10

SATA3RCOMPO

AB12

SATA3COMPI

AB13

PCH_SPI_CS0#_1 1 R651

PCH_JTAG_TDI

2 PCH_SPI_CLK 0_0402_5% 2 PCH_SPI_CS0# 0_0402_5%

PCH_SPI_MOSI_1 1 R684 PCH_SPI_MISO_1 1 R652

2

2

T3 Y14 T1

R648 100_0402_1%

R636 100_0402_1%

2

PCH_SPI_CLK_1 1 R681

2 PCH_SPI_MOSI 0_0402_5% 2 PCH_SPI_MISO 0_0402_5%

SPI_CLK

SATA3RBIAS

AH1

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0

34 34 34 34

PCH_SATALED#

R640

2

1 10K_0402_5%

R624 1

2 4.7K_0402_5%

SPI_CS1#

R02 modify

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

34 34 34 34

ODD

R20 modify

change to port1 cause by intel SATA II issue (20110201)

+3VS

R260 37.4_0402_1% 1 2

SATA_COMP

R241 49.9_0402_1% 1 2

SATA3_COMP RBIAS_SATA3 R625

1

R259 10K_0402_5%

+1.05VS_PCH SGEN#

P3

PCH_SATALED#

V4

SPI_MOSI

SATA0GP / GPIO21

V14

SGEN#

U3

SPI_MISO

SATA1GP / GPIO19

P1

PCH_GPIO19

B

R258 10K_0402_5% @

+1.05VS_PCH

GPIO21

2 750_0402_1%

SGEN#

Switchable GPU * Non-Switchable



SATALED#

C

HDD

SPI_CS0#

SPI

R671 100_0402_1%

2

PCH_JTAG_TMS

1

PCH_JTAG_TDO

R646 200_0402_1%

1

2

R637 200_0402_1%

1

2

R666 200_0402_1%

1

1

1

2

+3VALW_PCH

HDA_SDOUT_PCH

D

B

42 HDA_RST_AUDIO#

3 S

42 HDA_SYNC_AUDIO

G

42 HDA_BITCLK_AUDIO

2

R544 33_0402_5% 1 2 HDA_BITCLK_PCH R542 33_0402_5% 1 2 HDA_SYNC_PCH_R R545 33_0402_5% 1 2 HDA_RST_PCH# R555 33_0402_5% 1 2 HDA_SDOUT_PCH

1 10K_0402_5%

1

2

HDA_SYNC_PCH

2

2

1 1K_0402_5%

PCH_SPKR

SATA 6G

R539

42

SATA

SRTCRST close RAM door

+3VALW_PCH

R275

PCH_GPIO19

IHDA

ME debug mode,this signal has a weak internal PD Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide]

JTAG

*

SERIRQ

40

2

HDA_SDO as Capella ME override (GPIO33)

PCH_RTCX1

LPC

R556 1K_0402_5% @ 1 R557 0_0402_5% 2 1

U33A

J1 0_0603_5% @

1

12

2

40

+RTCVCC

RTC

+3VALW_PCH

R05 modify

PCH_SPKR

1

2 1K_0402_5%

2

*

@

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

1

R294 1

PCH_SATALED# 41

0 1

COUGARPOINT_FCBGA989~D +RTCBATT

Boot BIOS Strap Boot BIOS GPIO51 GPIO19 0 0 LPC 0 1 Reserved 1 0 1 1 * SPI

+3VS

+RTCBATT U36

2

+CHGRTC

+3VS

1 +

R375 1K_0402_5%

JBATT1

R654 1 R667 1

2 3.3K_0402_5% 2 3.3K_0402_5%

PCH_SPI_CS0#_1 SPI_WP1# SPI_HOLD1#

2

3 1

A

D13

1 3 7 4

CS# WP# HOLD# GND

VCC SCLK SI SO

8 6 5 2

PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MISO_1

EN25F32-100HIP SOP 8P SA00003IN00

+RTCBATT_R

20mil

SPI ROM FOR ME (4MB) Footprint 200mil

A

+RTCVCC

20mil

2

CONN@

2

-

CHN202UPT_SC70-3 C471

Compal Secret Data

Security Classification

1 1

SUYIN_060003HA002G202ZL

0.1U_0402_16V4Z

20100416 add

Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

Compal Electronics, Inc. PCH (1/8) SATA,HDA,SPI, LPC, XDP

3

2

Wednesday, June 08, 2011

Sheet 1

13

of

61

5

4

3

2

1

+3VALW_PCH

U33B

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

BG36 BJ36 AV34 AU34

PERN3 PERP3 PETN3 PETP3

C663 C665

1 1

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

C661 C660

1 1

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

BF36 BE36 AY34 BB34

PERN4 PERP4 PETN4 PETP4

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

BG37 BH37 AY36 BB36

PERN5 PERP5 PETN5 PETP5

BJ38 BG38 AU36 AV36

PERN6 PERP6 PETN6 PETP6

BG40 BJ40 AY40 BB40

PERN7 PERP7 PETN7 PETP7

BE38 BC38 AW38 AY38

PERN8 PERP8 PETN8 PETP8

2

1 10K_0402_5%

MINI1_CLKREQ#

R273

2

1 10K_0402_5%

USB30_CLKREQ#

+3VALW_PCH

C

R05 modify

R618

2

1 10K_0402_5%

PCH_GPIO73

R630

2

1 10K_0402_5%

LAN_CLKREQ#

R653

2

1 10K_0402_5%

MINI2_CLKREQ#

R238

2

1 10K_0402_5%

USB30_CLKREQ#_L

R293

2

1 10K_0402_5%

PCH_GPIO45

R295

2

1 10K_0402_5%

PCH_GPIO46

Y40 Y39 PCH_GPIO73 CLK_PCIE_MINI1# CLK_PCIE_MINI1

38 CLK_PCIE_MINI1# 38 CLK_PCIE_MINI1

Mini Card 1

MINI1_CLKREQ#

38 MINI1_CLKREQ#

AB49 AB47 M1

CLK_PCIE_USB30# AA48 CLK_PCIE_USB30 AA47

39 CLK_PCIE_USB30# 39 CLK_PCIE_USB30

USB3.0

J2

39 USB30_CLKREQ#

H14

PCH_SMBCLK

C9

PCH_SMBDATA

SMBDATA

SML0ALERT# / GPIO60 SML0CLK

PCH_SMBDATA 38

RST_GATE 6,11,12

2

RST_GATE

R608

2

1 1K_0402_5%

PCH_SMBCLK

R677

1

2

2.2K_0402_5%

PCH_SMBDATA

R662

1

2

2.2K_0402_5%

PCH_GPIO74

R647

1

2

10K_0402_5%

PCH_SML1CLK

R642

1

2

2.2K_0402_5%

PCH_SML1DATA

R643

1

2

2.2K_0402_5%

PCH_GPIO47

R280

1

2

10K_0402_5%

D

SML1ALERT# / PCHHOT# / GPIO74

C13

PCH_GPIO74

SML1CLK / GPIO58

E14

PCH_SML1CLK

SML1DATA / GPIO75

M16

PCH_SML1DATA

CL_DATA1 CL_RST1#

M7

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

P10

3

Mini Card 2

PCIECLKRQ2# / GPIO20

CLK_PCIE_LAN# CLK_PCIE_LAN

Y37 Y36

CLKOUT_PCIE3N CLKOUT_PCIE3P

USB3.0 Left

A8 Y43 Y45

MINI2_CLKREQ#

38 MINI2_CLKREQ#

L12

CLK_PCIE_USB30_L# V45 CLK_PCIE_USB30_L V46

46 CLK_PCIE_USB30_L# 46 CLK_PCIE_USB30_L

USB30_CLKREQ#_L L14

46 USB30_CLKREQ#_L

D_CK_SCLK

4

D_CK_SCLK 11,12

Q40B DMN66D0LDW-7_SOT363-6

PCH_GPIO47

M10

D_CK_SDATA 11,12

R670 4.7K_0402_5% 1 2 +3VS

AB37 AB38

C

Pull up at EC side. For VGA,EC

+3VS CLK_CPU_DMI# CLK_CPU_DMI

CLKOUT_DMI_N CLKOUT_DMI_P

AV22 AU22

CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P

AM12 AM13

CLKOUT_PCIE2N CLKOUT_PCIE2P

V10

38 CLK_PCIE_MINI2# 38 CLK_PCIE_MINI2

D_CK_SDATA

1

Q40A DMN66D0LDW-7_SOT363-6

PCH_SMBCLK

PCIECLKRQ1# / GPIO18

USB30_CLKREQ#

LAN_CLKREQ#

35 LAN_CLKREQ#

R669 4.7K_0402_5% 1 2 +3VS

PCH_SMBDATA 6

T11

CLK_CPU_DMI# 5 CLK_CPU_DMI 5

PCH_SML1DATA 6

CLKIN_DMI_N CLKIN_DMI_P

BF18 BE18

CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI

R2331 R2341

2 10K_0402_5% 2 10K_0402_5%

CLKIN_DMI2_N CLKIN_DMI2_P

BJ30 BG30

CLKIN_GND1# CLKIN_GND1

R5631 R5611

2 10K_0402_5% 2 10K_0402_5%

CLKIN_DOT_96N CLKIN_DOT_96P

G24 E24

CLK_BUF_DREF_96M# CLK_BUF_DREF_96M

R2201 R2211

2 10K_0402_5% 2 10K_0402_5%

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

AK7 AK5

CLK_BUF_PCIE_SATA# CLK_BUF_PCIE_SATA

R2641 R2651

2 10K_0402_5% 2 10K_0402_5%

REFCLK14IN

K45

CLK_BUF_ICH_14M

R1751

2 10K_0402_5%

CLKIN_PCILOOPBACK

H45

CLK_PCI_LPBACK

XTAL25_IN XTAL25_OUT

V47 V49

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

Y47

XCLK_RCOMP

PCIECLKRQ3# / GPIO25 CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P PCIECLKRQ5# / GPIO44

EC_SMB_DA2

1

Q38A DMN66D0LDW-7_SOT363-6 PCH_SML1CLK

35 CLK_PCIE_LAN# 35 CLK_PCIE_LAN

PCIE LAN

For DDR

+3VS

CL_CLK1

10K_0402_5%

C8 G12

CLKOUT_PCIE0N CLKOUT_PCIE0P

CLKOUT_PCIE1N CLKOUT_PCIE1P

1

PCH_SMBCLK 38

RST_GATE

A12

SML0DATA

PEG_A_CLKRQ# / GPIO47

PCIECLKRQ0# / GPIO73

EC_LID_OUT# 40

R240

EC_SMB_DA2 22,40

5

1 1

R05 modify R638

PERN2 PERP2 PETN2 PETP2

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

C813 C814

+3VS

BE34 BF34 BB32 AY32

SMBCLK

EC_LID_OUT#

2

USB3.0 Left

46 PCIE_PRX_DTX_N5 46 PCIE_PRX_DTX_P5 46 PCIE_PTX_C_DRX_N5 46 PCIE_PTX_C_DRX_P5

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

EC_LID_OUT#

5

39 PCIE_PRX_DTX_N4 39 PCIE_PRX_DTX_P4 39 PCIE_PTX_C_DRX_N4 39 PCIE_PTX_C_DRX_P4

1 1

SMBALERT# / GPIO11

E12

2

USB3.0 Right

C675 C677

SMBUS

38 PCIE_PRX_DTX_N3 38 PCIE_PRX_DTX_P3 38 PCIE_PTX_C_DRX_N3 38 PCIE_PTX_C_DRX_P3

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

PERN1 PERP1 PETN1 PETP1

Link

Mini Card 2

1 1

BG34 BJ34 AV32 AU32

Controller

D

38 PCIE_PRX_DTX_N2 38 PCIE_PRX_DTX_P2 38 PCIE_PTX_C_DRX_N2 38 PCIE_PTX_C_DRX_P2

C672 C669

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

CLOCKS

Mini Card 1

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1

PCI-E*

PCIE LAN

35 35 35 35

3

EC_SMB_CK2

4

EC_SMB_CK2 22,40

Q38B DMN66D0LDW-7_SOT363-6

Pull down 10K ohm for using internal Clock

CLK_PCI_LPBACK 17

B

B

PEG_CLKREQ#_R

PCH_GPIO45

PCH_GPIO46

AB42 AB40 E6

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

CLKOUT_PCIE6N CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38 V37

CLKOUT_PCIE7N CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14 AK13

CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P

XTAL25_IN XTAL25_OUT @

CLK_FLEX0

CLKOUTFLEX0 / GPIO64

K43

CLKOUTFLEX1 / GPIO65

F47

CLK_FLEX1

@

CLKOUTFLEX2 / GPIO66

H47 CLK_FLEX2

@

CLKOUTFLEX3 / GPIO67

K49

T9

PAD

T73

PAD

T29

PAD

DGPU_PRSNT#

R05 modify

1

C631 27P_0402_50V8J

R530 33_0402_5% 2 1 @

C642 22P_0402_50V8J 1 2

A

@

Reserve for EMI please close to UH4

1

PEG_CLKREQ# 22

WWW.AliSaler.Com

Compal Secret Data

Security Classification Issued Date

2

S

2

2

Pull high @ VGA side

0 1

CLK_PCI_LPBACK

1

2

DIS,OPTIMUS UMA

2 G

Q39 2N7002H_SOT23-3 R631 3 1 2 0_0402_5% DIS@ R668 R644 @ @ 2.2K_0402_5% 2.2K_0402_5% D

1 2

R160 10K_0402_5% DIS@

DGPU_PRSNT#

1

for safe

C630 27P_0402_50V8J

2

DGPU_PRSNT#

GPIO67

2 PEG_CLKREQ#_R

1

25MHZ_20PF_7A25000012 1

R159 10K_0402_5% UMAO@

1 1 10K_0402_5%

5

2 1

2

R632 DIS@ 10K_0402_5%

R663

2 1M_0402_5% Y2

DGPU_PWR_EN 17,45

+3VALW_PCH

1 R527

R04 modify

+3VS

COUGARPOINT_FCBGA989~D

A

+1.05VS_VTT

R526 90.9_0402_1% 1 2

PEG_B_CLKRQ# / GPIO56

V40 V42

FLEX CLOCKS

CLK_PEG_VGA# CLK_PEG_VGA

22 CLK_PEG_VGA# 22 CLK_PEG_VGA

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PCH (2/8) PCIE, SMBUS, CLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

14

of

61

5

4

3

2

1

+3VS

R607

2

1 10K_0402_5%

SUS_PWR_DN_ACK

R218

2

1 200K_0402_5%

PCH_ACIN

R247

2

1 10K_0402_5%

PCH_GPIO72

R610

2

1 10K_0402_5%

RI#

R597

2

1 200_0402_1%

PM_DRAM_PWRGD

R559

2

1 10K_0402_5%

PCH_RSMRST#

D

4 4 4 4

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

BC24 BE20 BG18 BG20

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

4 4 4 4

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

BE24 BC20 BJ18 BJ20

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

4 4 4 4

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

AW24 AW20 BB18 AV18

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

4 4 4 4

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

AY24 AY20 AY18 AU18

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

+1.05VS_PCH DMI_IRCOMP 2 49.9_0402_1% RBIAS_CPY 2 750_0402_1%

5 XDP_DBRESET#

R678

1

2 SUSACK#_R 0_0402_5%

1

2 XDP_DBRESET#_R 0_0402_5% SYS_PWROK

not support AMT APWROK can mux with PWROK (check list1.0 P.40)

C

PCH_PWROK R635

1

2

5 PM_DRAM_PWRGD

PCH_PWROK_R 0_0402_5%

40 SUS_PWR_DN_ACK

22,40,44,45,48 ACIN

D9

1

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

4 4 4 4 4 4 4 4

FDI_INT FDI_FSYNC0

BG25

DMI_IRCOMP

FDI_FSYNC1

BC10

FDI_FSYNC1

BH21

DMI2RBIAS

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC1

BB10

FDI_LSYNC1

DSWVRMEN

A18

DSWODVREN

DPWROK

E22

PCH_RSMRST#

WAKE#

B9

PCH_PCIE_WAKE#

CLKRUN# / GPIO32

N3

PCH_GPIO32

C12 K3 P12

SUSACK# SYS_RESET# SYS_PWROK

L22

PWROK

L10

APWROK

B13

PCH_RSMRST#

C21

RSMRST#

SUS_PWR_DN_ACK

K16

PCH_ACIN 2 CH751H-40PT_SOD323-2

4 4 4 4 4 4 4 4

AV12

PM_DRAM_PWRGD

PBTN_OUT#

40 PBTN_OUT#

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_INT

SUS_STAT# / GPIO61

FDI_INT 4

SUSCLK / GPIO62

SUS_STAT#

N14

SUSCLK

F4

PM_SLP_S3#

E20

PWRBTN#

SLP_A#

G10

H20

ACPRESENT / GPIO31

SLP_SUS#

G16

Ring Indicator CRB1.0 PH 10K +3VALW

SLP_S5# / GPIO63

35,38,39,46 +3VALW_PCH

@ @

PMSYNCH SLP_LAN# / GPIO29

1

2 10K_0402_5%

PCH_GPIO29

R235

1

2 10K_0402_5%

PCH_GPIO32

R622

1

2 10K_0402_5%

PAD

T23

PAD

T21

PAD

+3VS

T20

PAD

PM_SLP_S5# 40 PM_SLP_S4# 40 PM_SLP_S3# 40

@ PAD

R613

T47

@

AP14

H_PM_SYNC

K14

PCH_GPIO29

@

Can be left NC when IAMT is not support on the platfrom not support Deep S4,S5 can NC PCH EDS1.2 P.74

PAD H_PM_SYNC 5

COUGARPOINT_FCBGA989~D

B

5

ALL power OK

Y

SYS_PWROK

4

3

SYS_PWROK 5 1

MC74VHC1G08DFT2G_SC70-5

R629 10K_0402_5% 2

A

2

R645 10K_0402_5%

*

1 330K_0402_5%

@

DSWODVREN - On Die DSW VR Enable H：Enable L：Disable

G

1

1

VGATE

4

1 330K_0402_5%

P

U35 2 B 40,55

4

FDI_LSYNC1

2

+3VS

tell PCH all power ok but cpu core 40 PCH_PWROK

BATLOW# / GPIO72 RI#

FDI_LSYNC0

PCH_PCIE_WAKE#

T16

B

4

2

R581

SUSCLK 40

SLP_S4#

A10

FDI_FSYNC1

R577

@

SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#

E10

4

not support Deep S4,S5 DPWROK mux with PWROK check list1.0 P.42

T22

PM_SLP_S4#

RI#

DSWODVREN

FDI_FSYNC0

C

G8

D10

PCH_GPIO72

+RTCVCC

PCH_PCIE_WAKE#

H4

DRAMPWROK

D

R05 modify

PM_SLP_S5#

R05 modify 40 PCH_RSMRST#

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_FSYNC0

System Power Management

SUS_PWR_DN_ACK R599

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

DMI_ZCOMP

4mil width and place within 500mil of the PCH not support Deep S4,S5 mux with SUS_PWR_DN_ACK

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

AW16

BJ24

1 R223 1 R578

DMI

+3VALW_PCH

FDI

U33C

A

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PCH (3/8) DMI,FDI,PM,

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Wednesday, June 08, 2011

Sheet 1

15

of

61

5

4

3

2

1

Pull high at LVDS conn side. U33D 22,40

ENBKL

ENBKL

R532

1 0_0402_5%

2

IGPU_BKLT_EN

IGPU_BKLT_EN

UMA@

31 PCH_LCD_CLK 31 PCH_LCD_DATA

1

1 C193

0.01U_0402_16V7K D

2 @

31

PCH_ENVDD

J47 M45

L_BKLTEN L_VDD_EN

31

DPST_PWM

P45

L_BKLTCTL

T40 K47

L_DDC_CLK L_DDC_DATA

T45 P39

L_CTRL_CLK L_CTRL_DATA

CTRL_CLK CTRL_DATA

0.01U_0402_16V7K C191

2 @

R189

For RF request R177

2.37K_0402_1% 2 1 UMA@

LVDS_IBG

AF37 AF36

LVD_IBG LVD_VBG

LVD_VREF

AE48 AE47

LVD_VREFH LVD_VREFL

PCH_TXCLKPCH_TXCLK+

AK39 AK40

LVDSA_CLK# LVDSA_CLK

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

AN48 AM47 AK47 AJ48

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+

AN47 AM49 AK49 AJ47

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

AF40 AF39

LVDSB_CLK# LVDSB_CLK

AH45 AH47 AF49 AF45

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

AH43 AH49 AF47 AF43

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

0_0402_5% 2 1 UMA@

1 UMA@ 2 2.2K_0402_5%

CTRL_DATA

R156

1 UMA@ 2 2.2K_0402_5%

PCH_LCD_CLK

R157

1 UMA@ 2 2.2K_0402_5%

PCH_LCD_DATA

31 PCH_TXOUT031 PCH_TXOUT131 PCH_TXOUT231 PCH_TXOUT0+ 31 PCH_TXOUT1+ 31 PCH_TXOUT2+

+3VS R521

1 UMA@ 2 2.2K_0402_5%

PCH_CRT_CLK

R522

1 UMA@ 2 2.2K_0402_5%

PCH_CRT_DATA

C

R534

1 UMA@ 2 150_0402_1%

PCH_CRT_B

R533

1 UMA@ 2 150_0402_1%

PCH_CRT_G

R535

1 UMA@ 2 150_0402_1%

PCH_CRT_R

32 PCH_CRT_B 32 PCH_CRT_G 32 PCH_CRT_R 32 PCH_CRT_CLK 32 PCH_CRT_DATA

PCH_CRT_B PCH_CRT_G PCH_CRT_R

N48 P49 T49

CRT_BLUE CRT_GREEN CRT_RED

PCH_CRT_CLK PCH_CRT_DATA

T39 M40

CRT_DDC_CLK CRT_DDC_DATA

M47 M49

CRT_HSYNC CRT_VSYNC

T43 T42

DAC_IREF CRT_IRTN

32 PCH_CRT_HSYNC 32 PCH_CRT_VSYNC

AM42 AM40

SDVO_INTN SDVO_INTP

AP39 AP40

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA

SDVO_CTRLDATA strap pull high at level shift page SDVO_SCLK SDVO_SDATA

P38 M39

AT49 AT47 AT40 PCH_DPB_HPD PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

D

SDVO_SCLK 33 SDVO_SDATA 33

PCH_DPB_HPD 33 PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3

33 33 33 33 33 33 33 33

HDMI D2 HDMI D1 HDMI D0 HDMI CLK

P46 P42

DDPC_AUXN DDPC_AUXP DDPC_HPD

AP47 AP49 AT38

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

DDPD_CTRLCLK DDPD_CTRLDATA

1

CRT_IREF

Digital Display Interface

R158

31 PCH_TXCLK31 PCH_TXCLK+

LVDS

CTRL_CLK

SDVO_STALLN SDVO_STALLP

DDPB_AUXN DDPB_AUXP DDPB_HPD

CRT

1 UMA@ 2 2.2K_0402_5%

AP43 AP45

SDVO_CTRLCLK SDVO_CTRLDATA

+3VS R174

SDVO_TVCLKINN SDVO_TVCLKINP

C

M43 M36

DDPD_AUXN DDPD_AUXP DDPD_HPD

AT45 AT43 BH41

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

COUGARPOINT_FCBGA989~D

2

R178 1K_0402_0.5%

B

B

A

A

Compal Secret Data

Security Classification Issued Date

WWW.AliSaler.Com 5

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PCH (4/9) LVDS,CRT,DP,HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

16

of

61

5

4

3

R166 R169 R170 R172

1 1 1 1

2 2 2 2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

PCH_GPIO2 DGPU_PWR_EN PCH_GPIO4 ODD_DA#

R165

1

2 8.2K_0402_5%

R03 modify

1

2 8.2K_0402_5%

PCH_GPIO53

C

GPIO51 Internal pull high 14,45 DGPU_PWR_EN

Boot BIOS Strap bit1 BBS1 Boot BIOS Bit11 Bit10 Destination

B

1

1

0

PCI

1

1

SPI

0

0

LPC

Reserved 34

ODD_DA#

PAD 5

14 CLK_PCI_LPBACK 40 CLK_PCI_LPC

TP21 TP22 TP23 TP24

BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30

DGPU_HOLD_RST#

0

B21 M20 AY16 BG46

CLK_PCI_LPBACK CLK_PCI_LPC

2

1 @

2

2 1

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

C46 C44 E40

REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54

PCH_GPIO51 PCH_GPIO53 PCH_GPIO55

D47 E42 F46

GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55

PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5

G42 G40 C42 D44

PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5

K10

PME#

CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4

H49 H43 J48 K42 H40

C632 22P_0402_50V8J

AV5 AY1

D

DF_TVS

DMI Termination Voltage AV10

Set to Vcc when HIGH AT8

NV_RE#_WRB0 NV_RE#_WRB1

AY5 BA2

DF_TVS Set to Vss when LOW

DG 1.2 CRB1.0 PH 2.2K series 1K AT12 BF3 +1.8VS

DGPU_HOLD_RST# PCH_GPIO52 DGPU_PWR_EN

C6

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_RB#

NV_WE#_CK0 NV_WE#_CK1

PIRQA# PIRQB# PIRQC# PIRQD#

1 22_0402_5% 2 22_0402_5% T30 @ T10 @ T12 @

PAD PAD PAD

NV_RCOMP

K40 K38 H38 G38

PLT_RST#

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 NV_ALE NV_CLE

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

@

PLT_RST# R531 R529

1 C633 22P_0402_50V8J @

T18

AT10 BC8

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

USBRBIAS#

C33

USBRBIAS

USBRBIAS

B33

PLTRST#

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

A14 K20 B17 C16 L16 A16 D14 C14

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

USB/B (Right side)

C

R633 2.2K_0402_5%

USB Conn. Colay USB3.0 USB/B (Right side) DF_TVS

USB/B (Right side) ,colay USB3.0

R626

2

1 1K_0402_5%

H_SNB_IVB# 5

CLOSE TO THE BRANCHING POINT

Some PCH config not support USB port 6 & 7. USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13

USB20_N8 38 USB20_P8 38 USB20_N9 38 USB20_P9 38 USB20_N10 31 USB20_P10 31 USB20_N11 38 USB20_P11 38 USB20_N12 38 USB20_P12 38 USB20_N13 39 USB20_P13 39

Mini Card 1 (WLAN) +3VALW_PCH

3G/B (WWAN) CMOS Camera (LVDS) Mini2 Card 2 (Reserved) 3G/B(SIM Card )

USB_OC0# USB_OC2# USB_OC7# USB_OC5#

R596 R588 R595 R590

1 1 1 1

2 2 2 2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

USB_OC1# USB_OC4# USB_OC3# USB_OC6#

R773 R612 R592 R616

1 1 1 1

2 2 2 2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

BlueTooth

Within 500 mils 1 R558

2 22.6_0402_1%

R03 modify

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

B

USB_OC1# 46

COUGARPOINT_FCBGA989~D R282 0_0402_5% 2 1 @

For RF request

PLT_RST#

PLTRST_VGA# 22

R281 100K_0402_5% DIS@

IN1

2

IN2

MC74VHC1G08DFT2G_SC70-5

2

DIS@

1

U15

OUT

4

PLT_RST_BUF# 35,38,39,40,46 R297 100K_0402_5% 2

A

NC7SZ08P5X_NL_SC70-5

R296 100_0402_1% 1 2 DIS@

4

5

U14 Y

1

1

B

G

2

DGPU_HOLD_RST#

3

PLT_RST#

+3VS

P

5

+3VS

R03 modify

39 39 46 46 39 39 39 39

1

PCH_GPIO55 PCH_GPIO51 PCH_GPIO5 PCH_GPIO52

NV_DQS0 NV_DQS1

2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

AY7 AV7 AU3 BG4

1

2 2 2 2

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

VCC

1 1 1 1

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

GND

R152 R153 R161 R162

D

BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45

3

PCI_PIRQA# PCI_PIRQD# PCI_PIRQC# PCI_PIRQB#

NVRAM

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

USB

2 2 2 2

RSVD

1 1 1 1

PCI

R173 R180 R181 R183

GNT1#/ GPIO51

1

U33E

+3VS

R188

2

A

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PCH (5/9) PCI, USB, NVRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

17

of

61

5

4

3

2

1

HDA_SYNC PH(PLL =+1.5VS)

GPIO28

On-Die PLL Voltage Regulator This signal has a weak internal pull up

*

H：On-Die voltage regulator enable L：On-Die PLL Voltage Regulator disable R272

D

+3VALW_PCH

R768

1

2 1K_0402_5% PCH_GPIO28

@

+3VS

2 4.7K_0402_5%

1

ODD_EN#

R771

1

2 10K_0402_5%

EC_KBRST#

R279

1

2 10K_0402_5%

D

U33F PCH_GPIO0

H36

TACH2 / GPIO6

TACH6 / GPIO70

C41

PCH_GPIO70

+3VS

EC_SCI#

E38

TACH3 / GPIO7

TACH7 / GPIO71

A40

PCH_GPIO71

40

EC_SMI#

EC_SMI#

C10

GPIO8

T5

SCLOCK / GPIO22

PCH_GPIO24

E8

GPIO24 / MEM_LED

PCH_GPIO27

E16

GPIO27

PCH_GPIO28

P8

GPIO28

BT_ON#

OPTIMUS Non-OPTIMUS

0 1

R03 modify

GPIO35

38 WWAN_OFF#

M5

SATA3GP / GPIO37

OPTIMUS_EN#

N2

SLOAD / GPIO38

PCH_GPIO39

M3

SDATAOUT0 / GPIO39

PCH_GPIO48

V13

WL_OFF#

WL_OFF# PCH_GPIO57

T61

@

THRMTRIP#

AY10

INIT3_3V#

T14

NC_1

AH8

NC_2

AK11

NC_3

AH10

NC_4

AK10

NC_5

P37

SATA2GP / GPIO36

SDATAOUT1 / GPIO48

VSS_NCTF_15

BG2

V3

SATA5GP / GPIO49

VSS_NCTF_16

BG48

D6

GPIO57

VSS_NCTF_17

BH3

VSS_NCTF_18

BH47

A4

VSS_NCTF_1

VSS_NCTF_19

BJ4

PAD

T46

@

A44

VSS_NCTF_2

VSS_NCTF_20

BJ44

1

2 200K_0402_5% WWAN_OFF#

PAD

T44

@

A45

VSS_NCTF_3

VSS_NCTF_21

BJ45

R276

1

2 10K_0402_5%

PCH_GPIO0

PAD

T41

@

A46

VSS_NCTF_4

VSS_NCTF_22

BJ46

R546

1

2 10K_0402_5%

WL_EN#

PAD

T52

@

A5

VSS_NCTF_5

VSS_NCTF_23

BJ5

R191

1

2 10K_0402_5%

DGPU_HPD_INT#

PAD

T51

@

A6

VSS_NCTF_6

VSS_NCTF_24

BJ6

R641

1

2 10K_0402_5%

PCH_GPIO16

PAD

T64

@

B3

VSS_NCTF_7

VSS_NCTF_25

C2

R194

1

2 10K_0402_5%

DGPU_PWROK

PAD

T37

@

B47

VSS_NCTF_8

VSS_NCTF_26

C48

1

2 10K_0402_5%

PCH_GPIO22

BD1

VSS_NCTF_9

VSS_NCTF_27

D1

R290

R649

1

2 10K_0402_5%

PAD

PCH_GPIO39

R291

T34

@

BD49

VSS_NCTF_10

VSS_NCTF_28

D49

PAD

T56

@

BE1

VSS_NCTF_11

VSS_NCTF_29

E1

BE49

VSS_NCTF_12

VSS_NCTF_30

E49

BF1

VSS_NCTF_13

VSS_NCTF_31

F1

VSS_NCTF_14

VSS_NCTF_32

F49

1

2 200K_0402_5% ODD_DETECT#

PAD

R619

1

2 10K_0402_5%

BT_ON#

PAD

R292

1

2 10K_0402_5%

PCH_GPIO48

1

2 10K_0402_5%

WL_OFF#

R274

@

PAD

PAD

R04 modify

T55

NCTF

R04 modify

R277

B

T35 T57 T36

@ @ @

BF49

H_CPUPWRGD

CTRL+ALT+DEL

PCH_THRMTRIP#_R 1 R627

non CPU power ok

5

H_THRMTRIP# 2 390_0402_5%

H_THRMTRIP# 5

130 degree shut sown

Checklist1.0 P.59

This signal has weak internal PU, can't pull low,leave NC

TS_VSS1~4 PD to GND

T58

PAD

T39

PAD

T59

PAD

T40

PAD

T60

PAD

T45

PAD

T43

PAD

T42

PAD

T50

PAD

T49

PAD

T65

PAD

T38

PAD

T63

PAD

T32

PAD

T54

PAD

T33

PAD

T53

PAD

T31

PAD

@ @

R02 modify

@

+3VS

+3VS

+3VS

@ @ R554 10K_0402_5%

@

R548 10K_0402_5% @

@ PCH_GPIO69

@ R553 10K_0402_5%

@

R550 10K_0402_5% @

PCH_GPIO70

X76@ PCH_GPIO71

R549 10K_0402_5%

B

R551 10K_0402_5% X76@

@ @ @ @

Project ID * P5WE0 P7YE0 x x

@ @ @ @

GPIO69 GPIO70 0 0 0 0 1 0 1 1

GPIO71 PCH_GPIO71

*VRAM 800 MHz VRAM 900 MHz

0 1

@

COUGARPOINT_FCBGA989~D

GPIO24 Unmultiplexed NOTE: GPIO24 configuration register bits are not cleared by CF9h reset event.

+3VALW_PCH

A

STP_PCI# / GPIO34

K4

WWAN_OFF#

PAD +3VS

K1

V8

38

AY11

C

ODD_DETECT#

OPTIMUS_EN#

*

PROCPWRGD

PECI CPU-EC

5,40

EC_KBRST# 40

INIT3_3V

34 ODD_DETECT#

GPIO38

EC_KBRST#

H_PECI

1

R03 modify

PCH_GPIO22

P5

1 2 0_0402_5% @ R239

2

BT_ON#

TACH0 / GPIO17

PCH_PECI_R

2

38,39

2 10K_0402_5%

D40

GATEA20 40

AU16

1

1 OPT@

DGPU_PWROK

RCIN#

P4

1

2 0_0402_5%

SATA4GP / GPIO16

PECI

2

DIS@

U2

A20GATE

1

1

GPIO15

1

PCH_GPIO16 R193

G2

1

R639

SMIB

2

PCH_GPIO27

LAN_PHY_PWR_CTRL / GPIO12

2

SMIB

R278 10K_0402_5%

C4

1

39,46

OPTIMUS_EN#

ODD_EN# 34

DGPU_HPD_INT#

+3VS

1 NOPT@ 2 10K_0402_5%

PCH_GPIO69

EC_SCI#

R05 modify

R623

B41

PCH_GPIO12

54 VGA_PWROK

C

ODD_EN#

TACH5 / GPIO69

CPU/MISC

2 10K_0402_5%

1

C40

TACH1 / GPIO1

GPIO

R661

TACH4 / GPIO68

A42

40

33 DGPU_HPD_INT#

Deep S4,S5 wake event signal RTC alarm,Power BTN,GPIO27 PCH_GPIO27 (Have internal Pull-High) Deep S4,S5 wake event signal No use PD to GND Check list1.0 P.70

BMBUSY# / GPIO0

WL_EN#

2

39 WL_EN#

2

R05 modify

T7

R262

1

2 10K_0402_5%

PCH_GPIO24

R620

1

2 10K_0402_5%

PCH_GPIO12

R672

1

2 1K_0402_5%

SMIB

R263

1

2 10K_0402_5%

PCH_GPIO57

CRB1.0 PH10K to +3VALW A

Compal Secret Data

Security Classification Issued Date

WWW.AliSaler.Com 5

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PCH (6/9) GPIO, CPU, MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

18

of

61

5

4

3

2

1

+VCCADAC should be powered up during S0 system state.Note that Thermal Sensor shares the same power supply rail with DAC

BJ22

VCCAPLLEXP

+VCCAPLLEXP

T48 @

+1.05VS_PCH C

AN17

VCCIO[16]

AN21

VCCIO[17]

2

1

2

C332 1U_0402_6.3V6K

2

1

C342 1U_0402_6.3V6K

1

C325 1U_0402_6.3V6K

2

C353 1U_0402_6.3V6K

C314 10U_0805_10V4Z

2

1

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

VCCIO[22]

AP26

VCCIO[23]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29 1

T19 @

+VCCAFDI_VRM

AP16

+1.05VS_VCCAPLL_FDI

BG6

1 VSSALVDS

AK37

VCCTX_LVDS[1]

AM37

VCCTX_LVDS[2]

AM38

VCCTX_LVDS[3]

AP36

VCCTX_LVDS[4]

AP37

1

1

C310 0.01U_0402_16V7K 2 UMA@

2

C300 22U_0805_6.3V6M UMA@

0.1uH inductor, 200mA

+3VS

DISO@ 0_0402_5%

PCH Power Rail Table

V33

I/O Buffer Voltage Voltage Rail C313 0.1U_0402_10V7K

V34 2

V_PROC_IO

VCCVRM[3]

AT16

VCCDMI[1]

AT20

VCCIO[1]

AB36

V5REF_Sus

+1.05VS_PCH

AU20

1

VCCVRM[2] VCCFDIPLL

VCCDMI[2]

20mA

2

1

2

VCCPNAND[1]

AG16

VCCPNAND[2]

AG17

VCCPNAND[3]

AJ16

VCCPNAND[4]

AJ17

C344 1U_0402_6.3V6K

0.001

Processor I/F

5

0.001

PCH Core Well Reference Voltage

5

0.001

Suspend Well Reference Voltag

Vcc3_3

3.3

0.266

I/O Buffer Voltage

VccADAC

3.3

0.001

Display DAC Analog Power. This power is supplied by the core well.

VccADPLLA

1.05

0.08

Display PLL A power

VccADPLLB

1.05

0.08

Display PLL B power

VccCore

1.05

1.3

Internal Logic Voltage

VccDMI

1.05

0.042

DMI Buffer Voltage

VccIO

1.05

2.925

Core Well I/O buffers

VccASW

1.05

1.01

1.05 V Supply for Intel R Management Engine and Integrated LAN

VccSPI

3.3

0.02

3.3 V Supply for SPI Controller Logic

VccDSW

3.3

0.003

3.3v supply for Deep S4/S5 well

VccpNAND

1.8

0.19

1.8V power supply for DF_TVS

VccRTC

3.3

6 uA

Battery Voltage

3.3

0.266

Suspend Well I/O Buffer Voltage

place near AT20

C308 1U_0402_6.3V6K

Core Well I/O Buffer

place near AB36

+1.8VS

1

VccDFTERM should PH +1.8VS or +3VS C349 0.1U_0402_10V7K

2

+3VS

20mA

VCCSPI

V1

For SPI control logi

1

C347 B

1.05

DMI buffer logic

1

190mA

FDI

Trace 20mil

S0 Iccmax Current(A)

C

VCC3_3[3]

VCCIO[27]

Voltage

+VCCAFDI_VRM

+1.05VS_PCH AP17

COUGARPOINT_FCBGA989~D 2 1U_0402_6.3V6K

2

C703 1U_0402_6.3V6K

GPIO28

VccSus3_3

On-Die PLL Voltage Regulator

H：On-Die PLL voltage regulator enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2

VccSusHDA

3.3 / 1.5 0.01

VccVRM

1.8 / 1.5 0.16

+VCCAFDI_VRM +1.5VS R257

2

1

D

R210

1 VCC3_3[7]

2

R06 Modify

2 VCC3_3[6]

2

1 C615 @ 22U_0805_6.3V6M @

+1.8VS L16 UMA@ 0.1UH_MLF1608DR10KT_10%_1608 2 1 1

C305 0.01U_0402_16V7K 2 UMA@

2

1

R05 modify

R176 0_0402_5% DISO@

+VCCTX_LVDS 1

1 C276 22U_0805_6.3V6M

Internal PLL and VRM(+1.5VS)

C322 0.1U_0402_10V7K

2

PAD

VCCIO[24]

VCCALVDS

2

+3VS

R149 0_0805_5% 1 2 UMA@

+VCCA_LVDS

2

1

V5REF

VCCIO[21]

AP24

AT24

+3VS

2925mA

AN26

AP23 1

VCCIO[15]

NAND / SPI

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

2

266mA

VCCIO

AN16

U47

2

1

1

CRT LVDS

60mA

On-Die PLL Voltage Regulator

H：On-Die PLL voltage regulator enable

VSSADAC

2

1

2

VCCIO[28]

VCCADAC

AK36

HVCMOS

PAD

AN19

1mA

1mA

DMI

+1.05VS_PCH

VCC CORE

2

1 R523 0_0402_5% @

C833 10P_0402_50V8J

2

1

VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17]

1 U48

C629 22U_0805_6.3V6M

2

1

C320 1U_0402_6.3V6K

1

C319 1U_0402_6.3V6K

2

D

C346 1U_0402_6.3V6K

@

C334 10U_0805_10V4Z

PAD-OPEN 4x4m 1

AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31

C644 0.1U_0402_10V7K

+1.05VS_PCH

1

C640 0.01U_0402_16V7K

2

C777 0.1U_0402_10V7K

1300mA

C710 12P_0402_50V8J

POWER

U33G J3

2

+1.05VS_VTT

+3VS L31 MBK1608221YZF_2P 2 1

R05 modify

+VCCADAC

0_0603_5%

B

High Definition Audio Controller Suspend Voltage 1.8 V Internal PLL and VRMs (1.8 V for Desktop)

+VCCAFDI_VRM

VccCLKDMI

VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP VCCVRM = 160mA detal waiting for newest spec 配HDA_SYNC PH(PLL =+1.5VS)

1.05

0.02

DMI Clock Buffer Voltage

VccSSC

1.05

0.095

Spread Modulators Power Supply

VccDIFFCLKN

1.05

0.055

Differential Clock Buffers Power Supply

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

Analog power supply for LVDS (Mobile Only) Analog power supply for LVDS (Mobile Only)

A

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PCH (7/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

19

of

61

5

4

3

2

1

Have internal VRM R167 0_0603_5% 2 1

PAD

GPIO28

T11 @

V12

DCPSUSBYP

+3VS_VCC_CLKF33

T38

VCC3_3[5]

+VCCAPLL_CPY_PCH

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

119mA

H：On-Die PLL voltage regulator enable +VCCSUS1

AL24

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA +1.05VS_PCH R06 Modify

C

2

2

1

2

C316 1U_0402_6.3V6K

2

1

C327 1U_0402_6.3V6K

2

2

C326 1U_0402_6.3V6K

1

1

2

@

C295 1U_0402_6.3V6K

1 +

SGA00001700 220U 2.5V M B2 ESR 35mohm@100Khz

2

2 R808 0_0603_5%

+1.05VS_VCCA_B_DPL C278 220U_B2_2.5VM_R35

2 L11 10UH_LB2012T100MR_20%

1

C296 1U_0402_6.3V6K

2

C279 220U_B2_2.5VM_R35

+

1

C335 22U_0805_6.3V6M

+1.05VS_VCCA_A_DPL 1

1

1

C336 22U_0805_6.3V6M

L12 10UH_LB2012T100MR_20% 1 2

1

+1.05VS_PCH

C348 0.1U_0402_10V7K

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

+VCCRTCEXT

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16 Y49

P28

VCCIO[32]

T27

VCCIO[33]

T29

VCCSUS3_3[7]

T23

VCCSUS3_3[8]

T24

VCCSUS3_3[9]

V23

1

VCCSUS3_3[10]

V24

VCCSUS3_3[6]

P24

C321 1U_0402_6.3V6K

2

D

+3VALW_PCH

1

1

C330 0.1U_0402_10V7K

Place near 2 P24

2

+5VALW_PCH

C333 0.1U_0402_10V7K

Place near P24

1mA

+PCH_V5REF_SUS

VCCIO[34]

T26

V5REF_SUS

M26

+PCH_V5REF_SUS

DCPSUS[4]

AN23

+VCCA_USBSUS +3VALW_PCH

VCCSUS3_3[1]

AN24

1010mA

+3VALW_PCH

R202 100_0402_1% +1.05VS_PCH

VCCASW[12]

AD31

1 +VCCAFDI_VRM

DCPSUS[3]

D8 CH751H-40PT_SOD323-2

1

2 @ T14

V5REF

P34

+PCH_V5REF_RUN

VCCSUS3_3[2]

N20

+3V_VCCPSUS

VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5]

P22

1mA

suppied by internal 1.05V VR Must NC +3VS

+3VALW_PCH

1

R148 100_0402_1% C352 1U_0402_6.3V6K +PCH_V5REF_RUN

2

1

2 VCC3_3[1]

AA16

VCC3_3[8]

W16

VCC3_3[4]

T34

Place near 2 AJ2

AJ2

+1.05VS_PCH

VCC3_3[2] VCCIO[5]

AF13

VCCIO[12]

AH13

VCCIO[13]

AH14

VCCIO[6]

AF14

DCPRTC VCCVRM[4]

1

C704 0.1U_0402_10V7K

C

D7 CH751H-40PT_SOD323-2

+3VS

1

C318 0.1U_0603_25V7K

PAD

+5VS

PCI/GPIO/LPC

T13 @

Clock and Miscellaneous

PAD

P26

VCCIO[31]

3mA

+PCH_VCCDSW

+1.05VS_PCH

On-Die PLL Voltage Regulator

VCCIO[30] VCCDSW3_3

2

suppied by internal 1.05V VR must NC

VCCIO[29]

VCCACLK

1

T17 @

T16

2

PAD

C340 0.1U_0402_10V7K

N26

1

2

VCCDMI = 42mA detal waiting for newest spec

+1.05VS_PCH

1

AD49

1

Not support Deep S4,S5 connect to +3VALW

POWER

U33J

1

2

VCC3_3 = 266mA detal waiting for newest spec

+3VALW_PCH C304 1U_0402_6.3V6K

2 D

+3VS_VCC_CLKF33 1

C277 10U_0805_10V4Z

1

+VCCACLK

@

2

+1.05VS_PCH

+1.05V analog internal clock PLL Can NC

2

R150 0_0805_5% 2 @ L14 10UH_LB2012T100MR_20% 1 2 1

USB

+3VS

1

C343 0.1U_0402_10V7K

Place near 2 AA16,W16

2

C244 1U_0603_10V6K

C309 0.1U_0402_10V7K

Place near T34

1 C350 1U_0402_6.3V6K

2

2

+1.05VS_VCCA_B_DPL

2

Place near AG33

1 C317 1U_0402_6.3V6K 2

Place near AF33, AF34,AG34

PAD

suppied by internal 1.05V VR Must NC

AG33 1

+VCCSST 2 C354 0.1U_0402_10V7K +1.05VM_VCCSUS

T15 @

VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[11] VCCIO[10] DCPSST

T17 V19

DCPSUS[1] DCPSUS[2]

2

2

1

2

C687 0.1U_0402_10V7K

1

C685 0.1U_0402_10V7K

2

Place near BJ8

H：On-Die PLL voltage regulator enable +VCCAFDI_VRM

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

+VCCAFDI_VRM

VCCIO[2]

AC16

+1.05VS_PCH

VCCIO[3]

AC17

1

VCCIO[4]

AD17

C351 1U_0402_6.3V6K

2 +1.05VS_PCH

VCCASW[22]

T21

+VCCME_22

R237

2

1 0_0603_5%

VCCASW[23]

V21

+VCCME_23

R224

2

1 0_0603_5%

VCCASW[21]

T19

+VCCME_21

R236

2

1 0_0603_5%

VCCRTC

10mAVCCSUSHDA

P32

+VCCSUSHDA

R206

2

1 0_0603_5%

1

COUGARPOINT_FCBGA989~D

2

Issued Date

5

On-Die PLL Voltage Regulator

PAD

AF11

Need +3VALW and 0.1U close PCH

C315 0.1U_0402_16V4Z

A

Close P32

Compal Secret Data

Security Classification

WWW.AliSaler.Com

@ T62

+3VALW_PCH A22

1

B

GPIO28 +VCCSATAPLL

+RTCVCC

C331 1U_0402_6.3V6K

C693 0.1U_0402_10V7K

2

1

C694 0.1U_0402_10V7K

C700 4.7U_0603_6.3V6K

2

1

1mA V_PROC_IO

AK1

VCCVRM[1]

95mA

+1.05VS_PCH

1

VCCAPLLSATA

55mA

V16

BJ8

A

VCCADPLLB

CPU

Place near AF17

AF17 AF33 AF34 AG34

80mA 80mA

RTC

2

1 C312 1U_0402_6.3V6K

BF47

VCCADPLLA

HDA

+1.05VS_PCH

1 C311 1U_0402_6.3V6K

BD47

MISC

+1.05VS_VCCA_A_DPL

SATA

B

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PCH (8/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

20

of

61

5

4

3

2

1

U33I

D

U33H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3

C

B

VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79]

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

COUGARPOINT_FCBGA989~D

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3

VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

D

C

B

A

A

COUGARPOINT_FCBGA989~D

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PCH (9/9) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

21

of

61

A

B

C

D

E

U27A

17 PLTRST_VGA#

1

2

1

2

1

2

DIS@ C184 0.1U_0402_16V4Z

2

DIS@ C186 0.1U_0402_16V4Z

1

DIS@ C180 0.1U_0402_16V4Z

2

DIS@ C146 0.1U_0402_16V4Z

2

AM16 AG21 1 DIS@ 2.49K_0402_1%

+GPU_PLLVDD

@ C187 4700P_0402_25V7K

2

FBMA-L10-160808-300LMT 0603 DIS@ 150mA 2 1 L9 1 1 DIS@ C190 10U_0603_6.3V6M

1

DIS@ C189 22U_0805_6.3V6M

+1.05VSDGPU

2 R67

@

AE9

XTALIN XTALOUT

I2CS_SCL I2CS_SDA 31 VGA_LCD_CLK 31 VGA_LCD_DATA

+3VSDGPU 2

For RF

I2CS_SCL

1

6

VGA_LCD_CLK VGA_LCD_DATA 1 @ request C197 0.01U_0402_16V7K 2

EC_SMB_CK2 14,40

CRT

1

@ C195 0.01U_0402_16V7K

2 32 VGA_DDC_CLK 32 VGA_DDC_DATA

PLLVDD SP_PLLVDD

AD9

VID_PLLVDD

B1 B2

XTAL_IN XTAL_OUT

I2CS_SCL I2CS_SDA

E3 E4

I2CC_SCL I2CC_SDA

G3 G2

I2CB_SCL I2CB_SDA

VGA_DDC_CLK G1 VGA_DDC_DATA G4

I2CA_SCL I2CA_SDA

I2CB_SCL I2CB_SDA

F6 G6

MIOB_DE_NC MIOB_CTL3_NC MIOB_VREF_NC

Y5 W3 AF1

OUT

N/A

GPIO3

OUT

N/A

GPIO4

OUT

N/A

GPIO5

OUT GPU Core VID0

GPIO6 15,40,44,45,48

OUT GPU Core VID1

N/A HPD_IFPC

ENVDD VGA_BKL_EN

VGA_BKL_EN

1 10K_0402_5%

4

P ACIN_BUF

1 10K_0402_5%

B

2

G

VGA_PNL_PWM

U42

DIS@ R118 2 DIS@ R117 2 DIS@ R72 2 DIS@ R115 2

A

1

Y

DIS@

1 10K_0402_5%

3

VGA_HDMI_DET

5

DIS@

ACIN

NC7SZ08P5X_NL_SC70-5

ENBKL

ENBKL

16,40

+3VSDGPU I2CS_SCL I2CS_SDA I2CH_SCL I2CH_SDA I2CB_SCL I2CB_SDA VGA_LCD_CLK VGA_LCD_DATA

R495 R494 R122 R121 R120 R119 R502 R497

1 1 1 1 1 1 1 1

VGA_DDC_CLK R123 1 VGA_DDC_DATA R124 1 VGA_CRT_R VGA_CRT_G VGA_CRT_B

R45 R48 R49

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

2 2 2 2 2 2 2 2

2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% XTALOUT

DIS@ 2 2.2K_0402_5% DIS@ 2 2.2K_0402_5%

R479 1 DIS@

2 10K_0402_5%

MIOB_CLKIN_NC MIOB_CLKOUT_NC

AE1 V4

R465 1 DIS@

2 10K_0402_5%

OUT

GPIO8

IN

OVERT

GPIO9

OUT

ALERT

GPIO10

OUT

N/A

GPIO11

OUT

N/A

GPIO12

IN

GPIO13

OUT

N/A

GPIO14

OUT

N/A

1 DIS@ 1 DIS@ 1 DIS@

2 2 2

150_0402_1% 150_0402_1% 150_0402_1%

MIOACAL_PD_VDDQ_NC MIOACAL_PU_GND_NC

U5 T5

R458 1 DIS@

2 10K_0402_5%

MIOBCAL_PD_VDDQ_NC MIOBCAL_PU_GND_NC

AA7 AA6

R462 1 DIS@

2 10K_0402_5%

PWR_LEVEL

I2CH_SCL I2CH_SDA

AM15 AM14 AL14

DACA_HSYNC DACA_VSYNC

AM13 AL13

DACA_VDD DACA_VREF DACA_RSET

AJ12 AK12 AK13

DACB_RED DACB_GREEN DACB_BLUE

AK4 AL4 AJ4

DACB_HSYNC DACB_VSYNC

AM1 AM2

DACB_VDD DACB_VREF DACB_RSET

AG7 AK6 AH7

2

1M_0402_5%

2

1

1

Y1 DIS@ 1 27MHZ_16PF_X5H027000FG1H

2

2

External Spread Spectrum

DIS@ C577 18P_0402_50V8J

OSC_OUT

R477 1

@

22_0402_5%

2

U29

T4 W4

N/A

XTALIN

@ R474

DIS@ C576 18P_0402_50V8J

N4 R4

GPIO7

1 10K_0402_5%

2 DISO@ 1 R116 0_0402_5%

MIOA_CLKIN_NC MIOA_CLKOUT_NC

DACA_RED DACA_GREEN DACA_BLUE

1

XTAL_OUTBUFF 1

N2 P5 N5

GPIO2

+3VSDGPU

R03 modify

MIOA_CLKOUT_NC_N MIOB_CLKOUT_NC_N

XTAL_OUTBUFF XTAL_SSIN

E2 E1

I2CH_SCL I2CH_SDA

DMN66D0LDW-7_SOT363-6 Q31A DIS@

4

PEX_RST_N PEX_TERMP

AF9

XTAL_OUTBUFFD1 XTAL_SSIN D2

under GPU

PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N

MIOA_DE_NC MIOA_CTL3_NC MIOA_VREF_NC

IN

1

VSS

6

REFOUT

2

XOUT

MODOUT

5

3

XIN/CLKIN

R455 10K_0402_5% DIS@

OSC_SPREAD

3

2

3

AJ17 AJ18 1 200_0402_1%

W1 W2

IN

GPIO1

OSC_OUT

VDD

4

+3VSDGPU 1

@ ASM3P2872AF-06OR_TSOT-23-6 2

OSC_SPREAD R476 1

@ C581 0.1U_0402_16V4Z

@

2 22_0402_5%

XTAL_SSIN 1

R44

2

MIOB_HSYNC_NC MIOB_VSYNC_NC

GPIO0

USAGE

2

14 PEG_CLKREQ#

N3 L3

+3VSDGPU

R454 10K_0402_5% DIS@

If External Spread Spectrum not stuff then stuff resistor

VGA_CRT_R 32 VGA_CRT_G 32 VGA_CRT_B 32 VGA_CRT_HSYNC 32 VGA_CRT_VSYNC 32 +DACA_VDD

120 mA

DIS@ R466 2 1 10K_0402_5% @C154 @ C154 0.1U_0402_16V4Z 1 2 @R467 @ R467 1 2 124_0402_1%

1

2

1

2

1

2

1

2

1

2

2 1 OPT@ R113 10K_0402_5%

14 CLK_PEG_VGA 14 CLK_PEG_VGA#

MIOA_HSYNC_NC MIOA_VSYNC_NC

I/O

ACIN_BUF 1 CH751H-40PT_SOD323-2

2

D31

1 10K_0402_5%

DISO@ C176 4.7U_0603_6.3V6K

2 10K_0402_5%

CLK

1 DIS@

Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6

2 DIS@

DISO@ C132 1U_0402_6.3V6K

PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N

R418

MIOB_D0_NC MIOB_D1_NC MIOB_D2_NC MIOB_D3_NC MIOB_D4_NC MIOB_D5_NC MIOB_D6_NC MIOB_D7_NC MIOB_D8_NC MIOB_D9_NC MIOBD_10_NC MIOB_D11_NC MIOB_D12_NC MIOB_D13_NC MIOB_D14_NC

R74

DISO@ C136 0.1U_0402_16V4Z

AR16 AR17 AR13

+3VSDGPU

I2C DACs

2

N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6

VGA_ACIN

GPIO

R05 modify

DISO@ C140 0.1U_0402_16V4Z

PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N

MIOA_D0_NC MIOA_D1_NC MIOA_D2_NC MIOA_D3_NC MIOA_D4_NC MIOA_D5_NC MIOA_D6_NC MIOA_D7_NC MIOA_D8_NC MIOA_D9_NC MIOA_D10_NC MIOA_D11_NC MIOA_D12_NC MIOA_D13_NC MIOA_D14_NC

VGA_HDMI_DET VGA_HDMI_DET 33 VGA_PNL_PWM VGA_PNL_PWM 31 ENVDD ENVDD 31 VGA_BKL_EN GPU_VID0 GPU_VID0 54 GPU_VID1 GPU_VID1 54 GPU_VID2 GPU_VID2 54 R78 2 DIS@ 1 10K_0402_5% +3VSDGPU R70 2 DIS@ 1 10K_0402_5%

DIS@ C124 0.1U_0402_16V4Z

AL17 AM17 AM18 AM19 AL19 AK19 AL20 AM20 AM21 AM22 AL22 AK22 AL23 AM23 AM24 AM25 AL25 AK25 AL26 AM26 AM27 AM28 AL28 AK28 AK29 AL29 AM29 AM30 AM31 AM32 AN32 AP32

K1 K2 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6 M7

1

PEG_GTX_HRX_P0 PEG_GTX_HRX_N0 PEG_GTX_HRX_P1 PEG_GTX_HRX_N1 PEG_GTX_HRX_P2 PEG_GTX_HRX_N2 PEG_GTX_HRX_P3 PEG_GTX_HRX_N3 PEG_GTX_HRX_P4 PEG_GTX_HRX_N4 PEG_GTX_HRX_P5 PEG_GTX_HRX_N5 PEG_GTX_HRX_P6 PEG_GTX_HRX_N6 PEG_GTX_HRX_P7 PEG_GTX_HRX_N7 PEG_GTX_HRX_P8 PEG_GTX_HRX_N8 PEG_GTX_HRX_P9 PEG_GTX_HRX_N9 PEG_GTX_HRX_P10 PEG_GTX_HRX_N10 PEG_GTX_HRX_P11 PEG_GTX_HRX_N11 PEG_GTX_HRX_P12 PEG_GTX_HRX_N12 PEG_GTX_HRX_P13 PEG_GTX_HRX_N13 PEG_GTX_HRX_P14 PEG_GTX_HRX_N14 PEG_GTX_HRX_P15 PEG_GTX_HRX_N15

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24

2

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

1

Part 1 of 7

DIS@ R65 124_0402_1%

PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N

GPIO

AP17 AN17 AN19 AP19 AR19 AR20 AP20 AN20 AN22 AP22 AR22 AR23 AP23 AN23 AN25 AP25 AR25 AR26 AP26 AN26 AN28 AP28 AR28 AR29 AP29 AN29 AN31 AP31 AR31 AR32 AR34 AP34

PCI EXPRESS DVO

4 4 4 4 4 4 4 4 4 4 4 4

4 PEG_HTX_C_GRX_P0 4 PEG_HTX_C_GRX_N0 4 PEG_HTX_C_GRX_P1 4 PEG_HTX_C_GRX_N1 4 PEG_HTX_C_GRX_P2 4 PEG_HTX_C_GRX_N2 4 PEG_HTX_C_GRX_P3 4 PEG_HTX_C_GRX_N3 4 PEG_HTX_C_GRX_P4 4 PEG_HTX_C_GRX_N4 4 PEG_HTX_C_GRX_P5 4 PEG_HTX_C_GRX_N5 4 PEG_HTX_C_GRX_P6 4 PEG_HTX_C_GRX_N6 4 PEG_HTX_C_GRX_P7 4 PEG_HTX_C_GRX_N7 4 PEG_HTX_C_GRX_P8 4 PEG_HTX_C_GRX_N8 4 PEG_HTX_C_GRX_P9 4 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_N15

1 2 +3VSDGPU L5 FBMA-L10-160808-301LMT_2P DISO@

Under GPU

4

5

+3VSDGPU

I2CS_SDA

4

N12P-GV1-A1_BGA973 3

DIS@

EC_SMB_DA2 14,40

WWW.AliSaler.Com A

Compal Secret Data

Security Classification

DMN66D0LDW-7_SOT363-6 Q31B DIS@

Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

N12P PEG 1/9 Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

B

C

D

Sheet

Wednesday, June 08, 2011 E

22

of

61

A

MDA[15..0]

27

MDA[15..0]

27

MDA[31..16]

28 28

MDA[47..32] MDA[63..48]

MDA[31..16]

29

MDC[15..0]

MDA[47..32]

29

MDC[31..16]

MDA[63..48]

30

MDC[47..32]

30

MDC[63..48]

U27B

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

+FB_PLLAVDD_0

AG27 AF27

FB_DLLAVDD_0 FB_PLLAVDD_0

+FB_PLLAVDD_1

J19 J18

FB_DLLAVDD_1 FB_PLLAVDD_1

CMDA0 CMDA1 CMDA2 CMDA3 CMDA4 CMDA5 CMDA6 CMDA7 CMDA8 CMDA9 CMDA10 CMDA11 CMDA12 CMDA13 CMDA14 CMDA15 CMDA16 CMDA17 CMDA18 CMDA19 CMDA20 CMDA21 CMDA22 CMDA23 CMDA24 CMDA25 CMDA26 CMDA27 CMDA28 CMDA29 CMDA30

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

P32 H34 J30 P30 AF32 AL32 AL34 AF35

DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

L35 G35 H31 N32 AD32 AJ31 AJ35 AC34

DQSA#0 DQSA#1 DQSA#2 DQSA#3 DQSA#4 DQSA#5 DQSA#6 DQSA#7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

L34 H35 J32 N31 AE31 AJ32 AJ34 AC33

DQSA0 DQSA1 DQSA2 DQSA3 DQSA4 DQSA5 DQSA6 DQSA7

FBA_WCK0 FBA_WCK0_N FBA_WCK1 FBA_WCK1_N FBA_WCK2 FBA_WCK2_N FBA_WCK3 FBA_WCK3_N

P29 R29 L29 M29 AG29 AH29 AD29 AE29

FB_VREF_NC FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0 FBA_CLK0_N

T32 T31

FBA_CLK1 FBA_CLK1_N

AC31 AC30

MDC[47..32] MDC[63..48]

CMDC[30..0] Part 3 of 7

MDC0 MDC1 MDC2 MDC3 MDC4 MDC5 MDC6 MDC7 MDC8 MDC9 MDC10 MDC11 MDC12 MDC13 MDC14 MDC15 MDC16 MDC17 MDC18 MDC19 MDC20 MDC21 MDC22 MDC23 MDC24 MDC25 MDC26 MDC27 MDC28 MDC29 MDC30 MDC31 MDC32 MDC33 MDC34 MDC35 MDC36 MDC37 MDC38 MDC39 MDC40 MDC41 MDC42 MDC43 MDC44 MDC45 MDC46 MDC47 MDC48 MDC49 MDC50 MDC51 MDC52 MDC53 MDC54 MDC55 MDC56 MDC57 MDC58 MDC59 MDC60 MDC61 MDC62 MDC63

DQMA[3..0] 27

DQMA[7..4] 28

DQSA#[3..0] 27

DQSA#[7..4] 28

DQSA[3..0] 27

DQSA[7..4] 28

B13 D13 A13 A14 C16 B16 A17 D16 C13 B11 C11 A11 C10 C8 B8 A8 E8 F8 F10 F9 F12 D8 D11 E11 D12 E13 F13 F14 F15 E16 F16 F17 D29 F27 F28 E28 D26 F25 D24 E25 E32 F32 D33 E31 C33 F29 D30 E29 B29 C31 C29 B31 C32 B32 B35 B34 A29 B28 A28 C28 C26 D25 B25 A25

FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8 FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 FBC_CMD31

F18 E19 D18 C17 F19 C19 B17 E20 B19 D20 A19 D19 C20 F20 B20 G21 F22 F24 F23 C25 C23 F21 E22 D21 A23 D22 B23 C22 B22 A22 A20 G20

CMDC0 CMDC1 CMDC2 CMDC3 CMDC4 CMDC5 CMDC6 CMDC7 CMDC8 CMDC9 CMDC10 CMDC11 CMDC12 CMDC13 CMDC14 CMDC15 CMDC16 CMDC17 CMDC18 CMDC19 CMDC20 CMDC21 CMDC22 CMDC23 CMDC24 CMDC25 CMDC26 CMDC27 CMDC28 CMDC29 CMDC30

FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7

A16 D10 F11 D15 D27 D34 A34 D28

DQMC0 DQMC1 DQMC2 DQMC3 DQMC4 DQMC5 DQMC6 DQMC7

FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7

B14 B10 D9 E14 F26 D31 A31 A26

DQSC#0 DQSC#1 DQSC#2 DQSC#3 DQSC#4 DQSC#5 DQSC#6 DQSC#7

FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7

C14 A10 E10 D14 E26 D32 A32 B26

DQSC0 DQSC1 DQSC2 DQSC3 DQSC4 DQSC5 DQSC6 DQSC7

FBC_WCK0 FBC_WCK0_N FBC_WCK1 FBC_WCK1_N FBC_WCK2 FBC_WCK2_N FBC_WCK3 FBC_WCK3_N

G14 G15 G11 G12 G27 G28 G24 G25

FBC_CLK0 FBC_CLK0_N

E17 D17

CLKC0 CLKC0#

29 29

FBC_CLK1 FBC_CLK1_N

D23 E23

CLKC1 CLKC1#

30 30

+1.5VSDGPU

CLKA0 CLKA0# CLKA1 CLKA1#

DIS@ 1 K27 2 40.2_0402_1% R36 DIS@ 1 L27 2 40.2_0402_1% R42 DIS@ 1 M27 2 60.4_0402_1% R41 FBB_DEBUG0 G19 FBB_DEBUG1 G16

27 27 28 28

FBCAL_PD_VDDQ FBCAL_PU_GND FBCAL_TERM_GND FBC_DEBUG0 FBB_DEBUG1

29,30

DQMC[3..0] 29

DQMC[7..4] 30

DQSC#[3..0] 29

DQSC#[7..4] 30

DQSC[3..0]

29

DQSC[7..4]

30

1

N12P-GV1-A1_BGA973 DIS@

DIS@

2 10K_0402_5% 10K_0402_5%

2 2

DIS@ 1

FBA_DEBUG1 R34 DIS@ 1 FBB_DEBUG1 R478

1

2

1

2

1

2

1

2

DIS@ 1 +1.05VSDGPU L25 BLM18PG330SN1_2P

2

100mA 1

2

1

2

1

2

1

2

1

2

DIS@ 1 +1.05VSDGPU L26 BLM18PG330SN1_2P

2

Compal Secret Data

Security Classification Issued Date

+FB_PLLAVDD_1 DIS@ C578 10U_0805_10V4Z

1

DIS@ C584 1U_0603_10V6K

100mA

DIS@ C582 0.1U_0402_16V4Z

FBA_DEBUG0 R38 FBB_DEBUG0 DIS@ 1 R43

DIS@ C501 10U_0805_10V4Z

2

DIS@ 1

DIS@ C504 1U_0603_10V6K

60.4_0402_1%

2

DIS@ C55 0.1U_0402_16V4Z

+FB_PLLAVDD_0 60.4_0402_1%

DIS@ C101 0.1U_0402_16V4Z

+1.5VSDGPU

DIS@ C583 0.1U_0402_16V4Z

N12P-GV1-A1_BGA973

DIS@ C54 0.1U_0402_16V4Z

J27 FBA_DEBUG0 T30 FBA_DEBUG1 T29

MEMORY INTERFACE A

L32 N33 L33 N34 N35 P35 P33 P34 K35 K33 K34 H33 G34 G33 E34 E33 G31 F30 G30 G32 K30 K32 H30 K31 L31 L30 M32 N30 M30 P31 R32 R30 AG30 AG32 AH31 AF31 AF30 AE30 AC32 AD30 AN33 AL31 AM33 AL33 AK30 AK32 AJ30 AH30 AH33 AH35 AH34 AH32 AJ33 AL35 AM34 AM35 AF33 AE32 AF34 AE35 AE34 AE33 AB32 AC35

U30 V30 U31 V32 T35 U33 W32 W33 W31 W34 U34 U35 U32 T34 T33 W30 AB30 AA30 AB31 AA32 AB33 Y32 Y33 AB34 AB35 Y35 W35 Y34 Y31 Y30 W29 Y29

DIS@ C505 0.1U_0402_16V4Z

1

MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

MDC[31..16]

U27C

CMDA[30..0] 27,28 Part 2 of 7

MDC[15..0]

MEMORY INTERFACE C

VRAM Interface

2011/02/08

Deciphered Date

2012/02/08

Title

Compal Electronics, Inc. N12P VRAM 2/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

A

Wednesday, June 08, 2011

Sheet

23

of

61

5

4

3

2

1

For GB2-128 & GB2b-128 colayout.... +3VSDGPU

U27D

C

1

1

+3VSDGPU

AL2 AL3 AJ3 AJ2 AJ1 AH1 R89 AH2 4.7K_0402_5% AH3 DIS@

AP2 AN3

33 VGA_HDMI_SCLK 33 VGA_HDMI_SDATA B

IFPF_L0 IFPF_L0_N IFPF_L1 IFPF_L1_N IFPF_L2 IFPF_L2_N IFPF_L3 IFPF_L3_N

1

2 1 X76@ R128 10K_0402_1%

X76@ R125 15K_0402_1% 2 1 X76@ R126 15K_0402_1%

R04 modify R777 15K_0402_5% X76@

2 1 X76@ R127 10K_0402_1%

STRAP3

2 1 X76@ R475 15K_0402_1%

2 R776 10K_0402_5% @

ROM_SI ROM_SO ROM_SCLK

1

STRAP0 STRAP1 STRAP2

2

+3VSDGPU

GV@

+3VSDGPU

X76@ R453 20K_0402_1%

1

40.2K_0402_1%

2 1 X76@ R480 15K_0402_1%

2 1

+3VSDGPU @ R482 34.8K_0402_1%

IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N

2 R779

R775 20K_0402_5% X76@

2 1 X76@ R459 24.9K_0402_1%

AH6 AH5 AH4 AG4 AF4 AF5 AE6 AE5

STRAP_REF2

Straps MULTI LEVEL STRAPS

2 1 DIS@ R461 34.8K_0402_1%

IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N

2 R778 1 GV@ 10K_0402_5%

R04 modify

2 1 DIS@ R481 45.3K_0402_1%

AR8 AR7 AP7 AN7 AN5 AP5 AR5 AR4

PGOOD

D

STRAP4

R04 modify STRAP3

2 1 @ R460 45.3K_0402_1%

IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N

STRAP4

1

AM7 AM6 AL5 AM5 AM3 AM4 AP1 AR2

R774 10K_0402_5% @

2

IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N

A2 A7 B7 C5 C7 D5 D6 D7 E5 E7 F4 G5 H32 J25 J26 P6 U7 V6 Y4 AA4 AB4 AB7 AC5 AD6 AF6 AG6 AG20 AJ5 AK15 AL7

C

For N12P-GS strap table Memory Size

Memory Config

strap0

strap1

strap2

800 MHz

64M* 16* 8 1GB

Hynix SA000032420

R481 PU 45K

R461 PD 35K

R459 PD 25K

900 MHz

64M* 16* 8 1GB

Hynix SA000041S40

R481 PU 45K

R461 PD 35K

R459 PD 25K

900 MHz

64M* 16* 8 1GB

Samsung SA00004GS10

R481 PU 45K

R461 PD 35K

R459 PD 25K

N12P-GS

800 MHz

128M* 16* 8 2GB

Samsung SA00003MQ60

R481 PU 45K

R461 PD 35K

R459 PD 25K

N12P-GS

800 MHz

128M* 16* 8 2GB

Hynix SA00003VS10

R481 PU 45K

R461 PD 35K

R459 PD 25K

GPU N12P-GS

N12P-GS

N12P-GS VDD_SENSE_0 VDD_SENSE_1 VDD_SENSE_2

D35 P7 AD20

R484 1 DIS@ R485 1 DIS@ R483 1 DIS@

2 0_0402_5% 2 0_0402_5% 2 0_0402_5%

GND_SENSE_0 GND_SENSE_1 GND_SENSE_2

AD19 E35 R7

R488 1 DIS@ R487 1 DIS@ R486 1 DIS@

2 0_0402_5% 2 0_0402_5% 2 0_0402_5%

Frenq.

GCORE_SEN 54

FB_GND

strap3

strap4

ROM_SI

ROM_SO

NC

NC

R453 PD 5K

R127 PD 10K

ROM_SCLK R125 PU 15K

NC

NC

R453 PD 15K

R127 PD 10K

R125 PU 15K

NC

NC

R453 PD 20K

R127 PD 10K

R125 PU 15K

NC

NC

R453 PD 45K

R127 PD 10K

R125 PU 15K

NC

NC

R453 PD 35K

R127 PD 10K

R125 PU 15K

ROM_SCLK

54

For N12P-GV (ES) strap table

2

2

R94 4.7K_0402_5% DIS@

AP13 AN13 AN8 AP8 AP10 AN10 AR11 AR10 AN11 AP11

NC_0 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 NC_27 NC_28 NC_29

1

33 VGA_HDMI_TXD2+ 33 VGA_HDMI_TXD233 VGA_HDMI_TXD1+ 33 VGA_HDMI_TXD133 VGA_HDMI_TXD0+ 33 VGA_HDMI_TXD033 VGA_HDMI_TXC+ 33 VGA_HDMI_TXC-

IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N

NC

D

AM11 AM12 AM8 AL8 AM10 AM9 AK10 AL10 AK11 AL11

LVDS/TMDS

31 VGA_TXCLK+ 31 VGA_TXCLK31 VGA_TXOUT0+ 31 VGA_TXOUT031 VGA_TXOUT1+ 31 VGA_TXOUT131 VGA_TXOUT2+ 31 VGA_TXOUT2-

2

Part 4 of 7

AP4 AN4

IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N

AE4 AD4

IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N

Memory Config

strap0

strap1

strap2

strap3

strap4

ROM_SI

ROM_SO

64M* 16* 4 512MB

Hynix SA000032420

R481 PU 45K

R461 PD 35K

R480 PU 45K

R777 PD 15K

R775 PD 20K

R453 PD 5K

R128 PU 10K

R125 PU 15K

N12P-GV(ES)

900 MHz

64M* 16* 4 512MB

Hynix SA000041S40

R481 PU 45K

R461 PD 35K

R480 PU 45K

R777 PD 15K

R775 PD 20K

R453 PD 15K

R128 PU 10K

R125 PU 15K

N12P-GV(ES)

900 MHz

64M* 16* 4 512MB

Samsung SA00004GS10

R481 PU 45K

R461 PD 35K

R480 PU 45K

R777 PD 15K

R775 PD 20K

R453 PD 20K

R128 PU 10K

R125 PU 15K

N12P-GV(ES)

800 MHz

128M* 16* 4 1GB

Samsung SA00003MQ60

R481 PU 45K

R461 PD 35K

R480 PU 45K

R777 PD 15K

R775 PD 20K

R453 PD 45K

R128 PU 10K

R125 PU 15K

N12P-GV(ES)

800 MHz

128M* 16* 4 1GB

Hynix SA00003VS10

R481 PU 45K

R461 PD 35K

R480 PU 45K

R777 PD 15K

R775 PD 20K

R453 PD 35K

R128 PU 10K

R125 PU 15K

ROM_SCLK

Frenq.

TEST TESTMODE JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N

AP35 AP14 AN14 AN16 AR14 AP16

R403 1

N12P-GV(ES)

DIS@

IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N

B

2 10K_0402_5% JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST

R417 2 DIS@ AF3 AF2

Memory Size

800 MHz

GPU

IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA_N

PAD PAD PAD PAD PAD

T27 T1 T24 T26 T25

@ @ @ @ @

110K_0402_5%

R04 modify

SERIAL ROM_CS_N ROM_SI ROM_SO ROM_SCLK

C3 D3 C4 D4

ROM_CS# R129 1 ROM_SI ROM_SO ROM_SCLK

NC/SPDIF_NC

A5

R130

MULTI_STRAP_REF0_GND

N9

R457 2 DIS@

1 40.2K_0402_1%

MULTI_STRAP_REF1_GND

M9

R456 2 DIS@

1 40.2K_0402_1%

DIS@ 2 10K_0402_5%

+3VSDGPU

if unuse this pin , pull down 36k

GENERAL

+3VSDGPU A4 @ 1 R463

AB5 2 10K_0402_5% STRAP0 W5 STRAP1 W7 STRAP2 V7

BUFRST_N CEC STRAP0 STRAP1 STRAP2

THERMDP THERMDN

2 DIS@

For N12P-GV-OP-B-A1 strap table

1 36K_0402_1%

B5 B4

N12P-GV1-A1_BGA973 A

Memory Size

Memory Config

strap0

strap1

strap2

strap3

strap4

ROM_SI

ROM_SO

800 MHz

64M* 16* 4 512MB

Hynix SA000032420

R481 PU 45K

R461 PD 35K

R459 PD 5K

R777 PD 15K

R775 PD 10K

R453 PD 5K

R128 PU 10K

R125 PU 5K

N12P-GV OP-B-A1

900 MHz

64M* 16* 4 512MB

Hynix SA000041S40

R481 PU 45K

R461 PD 35K

R459 PD 5K

R777 PD 15K

R775 PD 10K

R453 PD 15K

R128 PU 10K

R125 PU 5K

N12P-GV OP-B-A1

GPU N12P-GV OP-B-A1

900 MHz

64M* 16* 4 512MB

Samsung SA00004GS10

R481 PU 45K

R461 PD 35K

R459 PD 5K

R777 PD 15K

R775 PD 10K

R453 PD 20K

R128 PU 10K

R125 PU 5K

N12P-GV OP-B-A1

800 MHz

128M* 16* 4 1GB

Samsung SA00003MQ60

R481 PU 45K

R461 PD 35K

R459 PD 5K

R777 PD 15K

R775 PD 10K

R453 PD 45K

R128 PU 10K

R125 PU 5K

N12P-GV OP-B-A1

800 MHz

128M* 16* 4 1GB

Hynix SA00003VS10

R481 PU 45K

R461 PD 35K

R459 PD 5K

R777 PD 15K

R775 PD 10K

R453 PD 35K

R128 PU 10K

R125 PU 5K

A

DIS@

Issued Date

5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

WWW.AliSaler.Com

Frenq.

2011/02/08

2012/02/08

Deciphered Date

Title

N12P LVDS 3/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

4

3

2

Wednesday, June 08, 2011

Sheet 1

24

of

61

5

4

3

2

1

D

D

U27E +1.5VSDGPU

+IFPAB_IOVDD R114 10K_0402_5% OPT@ 1K_0402_5% 2 DIS@

+IFPC_PLLVDD 1 R76 +IFPC_IOVDD

1K_0402_5% 2

Under GPU

440 mA

+3VSDGPU

+IFPC_PLLVDD DIS@ 1 R464 +IFPC_IOVDD

DISO@

1 R131 10K_0402_5% OPT@

IFPC_PLLVDD IFPC_RSET

AJ8

IFPC_IOVDD

AC6 AB6

IFPD_PLLVDD IFPD_RSET

AK8

IFPD_IOVDD

1 R468 1 R469

AJ6 AL1

IFPEF_PLLVDD IFPEF_RSET

10K_0402_5%1 DIS@

2 R68

AE7 AD7

IFPE_IOVDD IFPF_IOVDD

DIS@ C85 0.1U_0402_16V4Z

DIS@ C90 0.1U_0402_16V4Z

DIS@ C126 1U_0402_6.3V6K

DIS@ C91 1U_0402_6.3V6K

2

1

2

1

2

DIS@ C98 0.1U_0402_16V4Z

2

1

DIS@ C73 0.1U_0402_16V4Z

1

DIS@ C79 1U_0402_6.3V6K

DIS@ C84 1U_0402_6.3V6K

2

2

1

2

DIS@ C115 1U_0402_6.3V6K

1

DIS@ C179 4.7U_0603_6.3V6K

2

DIS@ C120 0.1U_0402_16V4Z

2500 mA

Under GPU

2

1 L6 MBC1608121YZF_0603 DIS@

NV recommand 0720

Under GPU

2

1

2

1

2

+3VSDGPU

2 DIS@ 1 R82 0_0603_5%

DIS@ C99 1U_0402_6.3V6K

1

R04 modify

DIS@ C147 0.1U_0402_16V4Z

PEX_SVDD_3V3 PEX_SVDD_3V3_NC

120mA

+1.05VSDGPU

2 @ 1 R98 0_0603_5%

B

120mA

+VDD33

Under GPU

1

AA9 AB9 W9 Y9

1

DIS@ C116 4.7U_0603_6.3V6K

2

1

+PEX_SVDD_3V3

MIOB_VDDQ_NC_0 MIOB_VDDQ_NC_1 MIOB_VDDQ_NC_2 MIOB_VDDQ_NC_3

Under GPU

+1.05VSDGPU

AG19 F7

MIOA_VDDQ_NC_0 MIOA_VDDQ_NC_1 MIOA_VDDQ_NC_2 MIOA_VDDQ_NC_3

DIS@ C108 4.7U_0603_6.3V6K

DIS@ C103 10U_0603_6.3V6M

DIS@ C183 22U_0805_6.3V6M

1

DIS@ C63 10U_0603_6.3V6M

2

120mA

P9 R9 T9 U9

2

2

R04 modify R800 10K_0402_5% DIS@

1

2

1

2

+3VSDGPU

1

2

1

2

2 DIS@

1

R63 0_0603_5%

Under GPU

R801 10K_0402_5% DIS@ 2

2

AJ9 AK7

1

+PEX_PLLVDD

J10 J11 J12 J13 J9

2

1

C

AG14

VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4

2

1

+1.05VSDGPU

PEX_PLLVDD

2

2

1

DISO@ C158 0.1U_0402_16V4Z

2

1

DISO@ C181 0.1U_0402_16V4Z

2

1

DISO@ C185 0.1U_0402_16V4Z

1

DISO@ C188 4.7U_0603_6.3V6K

2

DISO@ C153 1U_0402_6.3V6K

1

IFPA_IOVDD IFPB_IOVDD

10K_0402_5%2 DIS@ 1K_0402_5% 2 DIS@

+IFPC_PLLVDD

2 1 L8 BLM18PG181SN1D_0603

AG9 AG10

1

DIS@ C137 4.7U_0603_6.3V6K

2

IFPAB_PLLVDD IFPAB_RSET

2

DIS@ C148 4.7U_0603_6.3V6K

1

1 C178

1 R71

AK9 AJ11

2

1

DIS@ C141 1U_0402_6.3V6K

2

+IFPAB_PLLVDD 1K_0402_5% 2 DIS@

2

1 C177

DISO@

2

0.1U_0402_16V4Z

1 C150

DISO@

C182 DISO@ 2

0.1U_0402_16V4Z

1

+IFPAB_IOVDD

DISO@

L7 BLM18PG181SN1D_0603

1U_0402_6.3V6K

2

300 mA 4.7U_0603_6.3V6K

B

DISO@ 1

AK16 AK17 AK21 AK24 AK27

2

1

DIS@ C134 0.1U_0402_16V4Z

+1.8VSDGPU

PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4

2

1

DIS@ C122 0.1U_0402_16V4Z

2

2

R103 10K_0402_5% OPT@

1

DIS@ C62 22U_0805_6.3V6M

DIS@ C87 0.1U_0402_16V4Z

DIS@ C104 0.1U_0402_16V4Z

DIS@ C64 0.1U_0402_16V4Z

2

1

C174 1 DISO@

2

DISO@

C173 1

DISO@

2

2

1

+IFPAB_PLLVDD 0.1U_0402_16V4Z

C149 1

2

1

under GPU

220mA

4.7U_0603_6.3V6K

1U_0402_6.3V6K

1 C175 DISO@ 2

BLM18PG181SN1D_0603 1 DISO@L4 DISO@ L4

4.7U_0603_6.3V6K

2

2

1

+1.05VSDGPU

2500mA

DIS@ C118 0.1U_0402_16V4Z

+1.05VSDGPU

2

1

DIS@ C76 0.1U_0402_16V4Z

2

1

DIS@ C65 1U_0402_6.3V6K

1

DIS@ C61 4.7U_0603_6.3V6K

under GPU

AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16

1

C

PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24

2

2

FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37

1

2

1

DIS@ C70 0.1U_0402_16V4Z

2

1

DIS@ C67 0.1U_0402_16V4Z

2

1

DIS@ C58 0.1U_0402_16V4Z

2

1

DIS@ C109 0.1U_0402_16V4Z

1

DIS@ C80 1U_0402_6.3V6K

2

DIS@ C69 4.7U_0603_6.3V6K

1

J23 J24 J29 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27 AJ28 B18 E21 G17 G18 G22 G8 G9 H29 J14 J15 J16 J17 J20 J21 J22 N27 P27 R27 T27 U27 U29 V27 V29 V34 W27 Y27

POWER

Part 5 of 7

7200mA

N12P-GV1-A1_BGA973

Under GPU DIS@ A

A

+1.05VSDGPU

570 mA

DISO@

2

1

Compal Secret Data

Security Classification

R77 10K_0402_5% OPT@

Issued Date

2

2

1

DISO@ C155 0.1U_0402_16V4Z

2

1

DISO@ C156 0.1U_0402_16V4Z

1

DISO@ C159 4.7U_0603_6.3V6K

2

+IFPC_IOVDD DISO@ C157 1U_0402_6.3V6K

2 1 L3 BLM18PG181SN1D_0603 1

2011/02/08

2012/02/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Under GPU

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

Compal Electronics, Inc. N12P POWER & GND 4/9

4

3

2

Sheet

Wednesday, June 08, 2011 1

25

of

61

5

4

D

3

2

1

D

U27F

B

A

V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13 AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AK14 AK31 AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30 AP33

+VGA_CORE

2

1

2

2

2

1

2

1

2

2

1

2

DIS@ C72 0.01U_0402_16V7K

DIS@ C121 0.01U_0402_16V7K

DIS@ C114 0.01U_0402_16V7K

2

1

DIS@ C130 0.1U_0402_16V4Z

2

2

1

DIS@ C78 0.1U_0402_16V4Z

1

DIS@ C110 0.01U_0402_16V7K

2

1

DIS@ C77 0.047U_0402_16V7K

2

DIS@ C107 0.01U_0402_16V7K

DIS@ C94 0.01U_0402_16V7K 1

1

1

DIS@ C96 0.047U_0402_16V7K

2

2

DIS@ C74 0.047U_0402_16V7K

1

DIS@ C97 0.022U_0402_16V7K

DIS@ C88 0.01U_0402_16V7K 1

2

1

Put Under GPU DIS@

DIS@

DIS@

DIS@

+VGA_CORE

GV@

2

2

1

2

1

2

1

2

1

2

DIS@ C593 47U_0805_4V6

2

1

+

DIS@ C591 22U_0805_6.3V6M

1 GS@ C604 470U_V_2.5VM

DIS@ C592 4.7U_0603_6.3V6K

+

DIS@ C595 10U_0603_6.3V6M

1 GS@ C1 470U_V_2.5VM

DIS@ C594 10U_0603_6.3V6M

R03 modify

VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55

Part 7 of 7

POWER

1

2

1

AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M12 M14 M16 M18 M20 M22 M24 P11 P13 P15 P17 P19

C139 10U_0603_6.3V6M

2

1

DIS@C112 0.022U_0402_16V7K

1

2

DIS@ C95 0.022U_0402_16V7K

2

1

C133 10U_0603_6.3V6M

DIS@ C83 0.01U_0402_16V7K

1

VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85 VDD_86 VDD_87 VDD_88 VDD_89 VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98 VDD_99 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110

P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24

C

B

GV@

N12P-GV1-A1_BGA973 C1 330U_V_2.5VM

DIS@

C604 330U_V_2.5VM

For Cost Down 2/21

A

Compal Secret Data

Security Classification Issued Date

DIS@

5

U27G

41020mA

N12P-GV1-A1_BGA973

WWW.AliSaler.Com

+VGA_CORE

Under GPU

C131 10U_0603_6.3V6M

GND_97 GND_98 GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192

C123 10U_0603_6.3V6M

C

GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96

Part 6 of 7

GND

B3 B6 B9 B12 B15 B21 B24 B27 B30 B33 C2 C34 E6 E9 E12 E15 E18 E24 E27 E30 F2 F31 F34 F5 J2 J5 J31 J34 K9 L9 M2 M5 M11 M13 M15 M17 M19 M21 M23 M25 M31 M34 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R5 R31 R34 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V2 V5 V9 V12 V14 V16

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. N12P POWER & GND 5/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

26

of

61

5

4

3

2

1

VRAM DDR3 chips (1GB)

Mode D Address

0..31

64Mx16 DDR3 *8==>1GB

D

D

CMD1 ODT_L

CMD2

DQSA[7..0]

23,28 DQSA[7..0]

U23 +MEM_VREF0

M8 H1

VREFCA VREFDQ

CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

DQMA[7..0] MDA[63..0]

23,28 MDA[63..0]

CMDA[30..0]

23,28 CMDA[30..0]

+1.5VSDGPU

DIS@ R391 240_0402_1%

C

1

DIS@ R392 240_0402_1%

2

C495 DIS@ 0.1U_0402_16V4Z

+MEM_VREF0

+1.5VSDGPU

DIS@ R23 240_0402_1%

2

C25 DIS@ 0.1U_0402_16V4Z

1

CLKA0 CLKA0# CMDA3

J7 K7 K9

CK CK CKE/CKE0

CMDA2 CMDA0 CMDA30 CMDA15 CMDA13

K1 L2 J3 K3 L3

ODT/ODT0 CS/CS0 RAS CAS WE

F3 C7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

B1 B9 D1 D8 E2 E8 F9 G1 G9

G3 B7

DQSL DQSU

T2

RESET

X76@

ZQ/ZQ0

J1 L1 J9 L9

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

DIS@ R395 243_0402_1%

2

R11 @ 80.6_0402_1%

Group2

Group1

+1.5VSDGPU

1

2

VREFCA VREFDQ

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

M2 N8 M3

BA0 BA1 BA2

CLKA0 CLKA0# CMDA3

J7 K7 K9

CK CK CKE/CKE0

CMDA2 CMDA0 CMDA30 CMDA15 CMDA13

K1 L2 J3 K3 L3

ODT/ODT0 CS/CS0 RAS CAS WE

F3 C7

DQSL DQSU

DQMA0 DQMA3

E7 D3

DML DMU

DQSA#0 DQSA#3

G3 B7

DQSL DQSU

CMDA5 ZQ1

B2 D9 G7 K2 K8 N1 N9 R1 R9

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ VDDQ

A1 A8 C1 C9 D2 E9 F1 H2 H9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

B1 B9 D1 D8 E2 E8 F9 G1 G9

RESET

L8

ZQ/ZQ0

J1 L1 J9 L9

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

MDA29 MDA26 MDA31 MDA28 MDA27 MDA25 MDA30 MDA24

D7 C3 C8 C2 A7 A2 B8 A3

VDD VDD VDD VDD VDD VDD VDD VDD VDD

T2

Group0

Group3

+1.5VSDGPU

CMDA12 CMDA27 CMDA26

DQSA0 DQSA3

MDA3 MDA4 MDA2 MDA7 MDA0 MDA5 MDA1 MDA6

E3 F7 F2 F8 H3 H8 G2 H7

CMD3

CKE

CMD4

A14

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

CMD16

A14

CAS* CS0_H# C

CMD17 CMD18

ODT_H CKE_H

CMD19

+1.5VSDGPU

CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

Not Available

B

1

L8

CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14

1

CLKA0 1 2 R12 @ 80.6_0402_1% DIS@ R15 160_0402_1%

2

1 2

A1 A8 C1 C9 D2 E9 F1 H2 H9

DQSA#2 DQSA#1

ZQ0

CLKA0# 1

VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ DQSL VDDQ DQSU VDDQ DML DMU

CMDA5

CLKA0#

B2 D9 G7 K2 K8 N1 N9 R1 R9

E7 D3

+MEM_VREF1 M8 H1

MDA12 MDA11 MDA14 MDA8 MDA13 MDA10 MDA15 MDA9

D7 C3 C8 C2 A7 A2 B8 A3

VDD VDD VDD VDD VDD VDD VDD VDD VDD

DQMA2 DQMA1

MDA18 MDA19 MDA23 MDA17 MDA21 MDA16 MDA20 MDA22

E3 F7 F2 F8 H3 H8 G2 H7

+1.5VSDGPU

BA0 BA1 BA2

B

23

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

M2 N8 M3

+MEM_VREF1 DIS@ R25 240_0402_1%

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

CMDA12 CMDA27 CMDA26

DQSA2 DQSA1

CLKA0

U4

@ C4 0.01U_0402_16V7K

DIS@ R390 243_0402_1% 2

23,28 DQMA[7..0]

23

X76@

DQSA#[7..0]

23,28 DQSA#[7..0]

32..63

CS0_L#

CMD0

96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96

CMDA2 CMDA3 CMDA5 CMDA18 CMDA19

R397 R398 R399 R401 R400

1 1 1 1 1

DIS@ DIS@ DIS@ DIS@ DIS@

2 2 2 2 2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

Command Bit

Default Pull-down

ODTx

10k 10k

CKEx

DDR3

RST CS*

10k No Termination

96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96

NV recommand 0720 +1.5VSDGPU

+1.5VSDGPU

2

1

2

Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )

DIS@ C35 0.1U_0402_16V4Z

2

1

DIS@ C34 0.1U_0402_16V4Z

2

1

DIS@ C33 0.1U_0402_16V4Z

2

1

DIS@ C31 0.1U_0402_16V4Z

2

1

DIS@ C27 0.1U_0402_16V4Z

2

1

DIS@ C18 1U_0603_10V6K

2

1

DIS@ C22 1U_0603_10V6K

2

1

DIS@ C21 1U_0603_10V6K

2

1

DIS@ C19 1U_0603_10V6K

2

1

DIS@ C497 0.1U_0402_16V4Z

2

1

DIS@ C502 0.1U_0402_16V4Z

2

1

DIS@ C506 0.1U_0402_16V4Z

2

1

DIS@ C508 0.1U_0402_16V4Z

2

1

DIS@ C511 0.1U_0402_16V4Z

2

1

DIS@ C512 0.1U_0402_16V4Z

2

1

DIS@ C487 1U_0603_10V6K

2

1

DIS@ C493 1U_0603_10V6K

2

1

DIS@ C488 1U_0603_10V6K

1

DIS@ C486 1U_0603_10V6K

Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P) AMD :SA00003PF10 (S IC D3 64M16/800 23EY2387MB-12 PG-TFBGA 96P 1.5V)

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

N12P DDR3 6/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

27

of

61

5

4

3

2

1

VRAM DDR3 chips (1GB)

Mode D Address

64Mx16 DDR3 *8==>1GB

CMD0

0..31

32..63

CS0_L#

CMD1 D

U3 +MEM_VREF2 DQMA[7..0] CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14

CMDA[30..0]

23,27 CMDA[30..0]

DQSA#[7..0]

23,27 DQSA#[7..0]

DQSA[7..0]

23,27 DQSA[7..0]

MDA[63..0]

23,27 MDA[63..0]

+1.5VSDGPU DIS@ R21 240_0402_1%

CMDA12 CMDA27 CMDA26

M8 H1

VREFCA VREFDQ

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

M2 N8 M3

U24 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

1

2

C23 DIS@ 0.1U_0402_16V4Z

DIS@ R22 240_0402_1%

CLKA1 CLKA1# CMDA19

J7 K7 K9

CMDA18 CMDA16 CMDA30 CMDA15 CMDA13

K1 L2 J3 K3 L3

DQSA4 DQSA5

F3 C7

+1.5VSDGPU DIS@ R393 240_0402_1%

DQMA4 DQMA5

2

CMDA5

T2

ZQ2

L8

DIS@ R24 243_0402_1% CLKA1

2 23

2

R10 @ DIS@ 80.6_0402_1% R14 160_0402_1% CLKA1# 1

2 R9 @ 80.6_0402_1%

CLKA1#

J1 L1 J9 L9

2

23

1

B

CLKA1 1

CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14

Group4

Group5

BA0 BA1 BA2

CK CK CKE/CKE0

VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ DQSL VDDQ DQSU VDDQ

A1 A8 C1 C9 D2 E9 F1 H2 H9

DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

B1 B9 D1 D8 E2 E8 F9 G1 G9

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

RESET ZQ/ZQ0

CMDA12 CMDA27 CMDA26

B2 D9 G7 K2 K8 N1 N9 R1 R9

VDD VDD VDD VDD VDD VDD VDD VDD VDD

CLKA1 CLKA1# CMDA19

+1.5VSDGPU

1

2

X76@

M8 H1

VREFCA VREFDQ

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

M2 N8 M3

J7 K7 K9

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

BA0 BA1 BA2

VDD VDD VDD VDD VDD VDD VDD VDD VDD

CK CK CKE/CKE0

K1 L2 J3 K3 L3

ODT/ODT0 CS/CS0 RAS CAS WE

DQSA7 DQSA6

F3 C7

DQSL DQSU

DQSA#7 DQSA#6

CMDA5 ZQ3

E7 D3 G3 B7

T2 L8

MDA58 MDA59 MDA56 MDA63 MDA57 MDA61 MDA60 MDA62

D7 C3 C8 C2 A7 A2 B8 A3

MDA49 MDA53 MDA51 MDA55 MDA48 MDA54 MDA50 MDA52

Group7

Group6

+1.5VSDGPU

CMDA18 CMDA16 CMDA30 CMDA15 CMDA13

DQMA7 DQMA6

E3 F7 F2 F8 H3 H8 G2 H7

B2 D9 G7 K2 K8 N1 N9 R1 R9

VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ VDDQ VDDQ

A1 A8 C1 C9 D2 E9 F1 H2 H9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

B1 B9 D1 D8 E2 E8 F9 G1 G9

DML DMU DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

DIS@ R389 243_0402_1%

J1 L1 J9 L9

96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

D

CMD2

ODT_L

CMD3

CKE

CMD4

A14

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

A14

CAS* CS0_H#

CMD16 CMD17 +1.5VSDGPU

CMD18

ODT_H

CMD19

CKE_H

CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

C

Not Available

1

1

G3 B7

D7 C3 C8 C2 A7 A2 B8 A3

MDA42 MDA45 MDA40 MDA44 MDA41 MDA47 MDA43 MDA46

+MEM_VREF3

1

DIS@ R396 240_0402_1%

DQSA#4 DQSA#5

C503 DIS@ 0.1U_0402_16V4Z

+MEM_VREF3

E7 D3

MDA39 MDA35 MDA37 MDA33 MDA38 MDA32 MDA36 MDA34

+1.5VSDGPU

+MEM_VREF2

C

E3 F7 F2 F8 H3 H8 G2 H7

2

23,27 DQMA[7..0]

X76@

B

96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96

@ C3 0.01U_0402_16V7K

NV recommand 0720

2

1

2

2

1

DIS@ C494 0.1U_0402_16V4Z

2

1

DIS@ C496 0.1U_0402_16V4Z

2

1

DIS@ C510 0.1U_0402_16V4Z

2

1

DIS@ C507 0.1U_0402_16V4Z

2

1

DIS@ C509 0.1U_0402_16V4Z

2

1

DIS@ C489 1U_0603_10V6K

2

1

DIS@ C492 1U_0603_10V6K

2

1

DIS@ C491 1U_0603_10V6K

2

1

DIS@ C490 1U_0603_10V6K

2

1

DIS@ C20 0.1U_0402_16V4Z

2

1

DIS@ C32 0.1U_0402_16V4Z

2

1

DIS@ C30 0.1U_0402_16V4Z

2

1

DIS@ C28 0.1U_0402_16V4Z

2

1

DIS@ C26 0.1U_0402_16V4Z

2

1

DIS@ C24 0.1U_0402_16V4Z

2

1

DIS@ C17 1U_0603_10V6K

1

DIS@ C14 1U_0603_10V6K

2

+1.5VSDGPU

DIS@ C15 1U_0603_10V6K

1

DIS@ C16 1U_0603_10V6K

+1.5VSDGPU

A

A

Issued Date

WWW.AliSaler.Com 5

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

N12P DDR3 7/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

28

of

61

5

4

3

2

1

Mode D Address

VRAM DDR3 chips (1GB)

32..63

0..31 CS0_L#

CMD0 CMD1

64Mx16 DDR3 *8==>1GB

DQSC[7..0] DQSC#[7..0] DQMC[7..0]

+MEM_VREF4

CMDC[30..0]

+1.5VSDGPU

GS@ R435 240_0402_1%

+1.5VSDGPU

C165 GS@ 0.1U_0402_16V4Z

A1 A8 C1 C9 D2 E9 F1 H2 H9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

B1 B9 D1 D8 E2 E8 F9 G1 G9

J7 K7 K9

CK CK CKE/CKE0

CMDC2 CMDC0 CMDC30 CMDC15 CMDC13

K1 L2 J3 K3 L3

ODT/ODT0 CS/CS0 RAS CAS WE DQSL DQSU

E7 D3

DML DMU

DQSC#2 DQSC#1

G3 B7

CMDC5

T2

RESET

ZQ4

L8

ZQ/ZQ0

J1 L1 J9 L9

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

A1 A8 C1 C9 D2 E9 F1 H2 H9

DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

B1 B9 D1 D8 E2 E8 F9 G1 G9

BA0 BA1 BA2

CLKC0 CLKC0# CMDC3

J7 K7 K9

CK CK CKE/CKE0

CMDC2 CMDC0 CMDC30 CMDC15 CMDC13

K1 L2 J3 K3 L3

ODT/ODT0 CS/CS0 RAS CAS WE

DQMC0 DQMC3

F3 C7 E7 D3

DQSC#0 DQSC#3

G3 B7

CMDC5

T2

RESET

L8

ZQ/ZQ0

J1 L1 J9 L9

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

ZQ5

Group3

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

A14

CAS* CS0_H#

CMD16

+1.5VSDGPU

DQSL DQSU

A14

CMD17 ODT_H

CMD18

+1.5VSDGPU

C

CKE_H

CMD19 CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

Not Available

GS@ R50 243_0402_1%

B

CMDC2 CMDC3 CMDC5 CMDC18 CMDC19

R415 R416 R414 R413 R412

1 1 1 1 1

GS@ GS@ GS@ GS@ GS@

2 2 2 2 2

Command Bit

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

DDR3

Default Pull-down

ODTx

10k

CKEx

10k

RST CS*

10k No Termination

96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

GS@ C566 0.1U_0402_16V4Z

2

1

GS@ C567 0.1U_0402_16V4Z

2

1

GS@ C571 0.1U_0402_16V4Z

2

1

GS@ C163 0.1U_0402_16V4Z

2

1

GS@ C164 0.1U_0402_16V4Z

2

1

GS@ C166 0.1U_0402_16V4Z

2

1

GS@ C167 0.1U_0402_16V4Z

2

1

GS@ C168 0.1U_0402_16V4Z

1

GS@ C169 1U_0603_10V6K

+1.5VSDGPU @ C145 0.01U_0402_16V7K

GS@ C170 1U_0603_10V6K

2 NV recommand 0720

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ DQSL VDDQ DQSU VDDQ

M2 N8 M3

Group0

CKE

CMD4

+1.5VSDGPU 1

GS@ C161 1U_0603_10V6K

2 R60 @ 80.6_0402_1%

B2 D9 G7 K2 K8 N1 N9 R1 R9

CMDC12 CMDC27 CMDC26

DQSC0 DQSC3

CLKC0# 1

CLKC0#

VDD VDD VDD VDD VDD VDD VDD VDD VDD

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96

GS@ C127 1U_0603_10V6K

1

2

R61 @ GS@ 80.6_0402_1% R69 160_0402_1%

2 23

MDC28 MDC24 MDC31 MDC25 MDC29 MDC27 MDC30 MDC26

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

GS@ C568 0.1U_0402_16V4Z

CLKC0 1

CLKC0

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14

2

2

GS@ R437 243_0402_1%

23

MDC3 MDC7 MDC1 MDC4 MDC2 MDC6 MDC0 MDC5

D

CMD3

1

DQSL DQSU

+1.5VSDGPU

1

B

Group1

+1.5VSDGPU

CLKC0 CLKC0# CMDC3

F3 C7

Group2

E3 F7 F2 F8 H3 H8 G2 H7

GS@ C569 0.1U_0402_16V4Z

2

VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ VDDQ VDDQ

BA0 BA1 BA2

DQMC2 DQMC1

1

B2 D9 G7 K2 K8 N1 N9 R1 R9

M2 N8 M3

+MEM_VREF5 GS@ R85 240_0402_1%

VDD VDD VDD VDD VDD VDD VDD VDD VDD

CMDC12 CMDC27 CMDC26

DQSC2 DQSC1

GS@ R86 240_0402_1%

MDC13 MDC10 MDC14 MDC9 MDC12 MDC8 MDC15 MDC11

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

VREFCA VREFDQ

GS@ C572 0.1U_0402_16V4Z

2

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

+MEM_VREF5 M8 H1

GS@ C563 1U_0603_10V6K

C

C570 GS@ 0.1U_0402_16V4Z

GS@ R436 240_0402_1%

MDC22 MDC16 MDC18 MDC19 MDC23 MDC17 MDC20 MDC21

CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14

+MEM_VREF4 1

E3 F7 F2 F8 H3 H8 G2 H7

VREFCA VREFDQ

X76@

GS@ C573 1U_0603_10V6K

23,30 MDC[63..0]

U6 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

M8 H1

MDC[63..0]

23,30 CMDC[30..0]

X76@

GS@ C565 1U_0603_10V6K

23,30 DQMC[7..0]

U28

GS@ C564 1U_0603_10V6K

23,30 DQSC[7..0] 23,30 DQSC#[7..0]

ODT_L

CMD2

D

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

N12P DDR3 8/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

29

of

61

5

4

3

2

1

VRAM DDR3 chips (1GB) 64Mx16 DDR3 *8==>1GB D

D

DQMC[7..0]

23,29 DQMC[7..0]

CMDC[30..0]

23,29 CMDC[30..0]

DQSC#[7..0]

23,29 DQSC#[7..0]

U5

DQSC[7..0]

23,29 DQSC[7..0]

+MEM_VREF6

MDC[63..0]

23,29 MDC[63..0]

CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14

+1.5VSDGPU GS@ R32 240_0402_1%

GS@ R31 240_0402_1%

C

1

2

C44 GS@ 0.1U_0402_16V4Z

+MEM_VREF6 CMDC12 CMDC27 CMDC26

+1.5VSDGPU GS@ R407 240_0402_1%

M8 H1

VREFCA VREFDQ

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

M2 N8 M3

CLKC1 CLKC1# CMDC19

J7 K7 K9

CMDC18 CMDC16 CMDC30 CMDC15 CMDC13

K1 L2 J3 K3 L3

DQSC4 DQSC5

X76@

F3 C7

U26 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

MDC39 MDC33 MDC38 MDC32 MDC36 MDC34 MDC37 MDC35

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

MDC42 MDC43 MDC41 MDC46 MDC40 MDC45 MDC44 MDC47

+MEM_VREF7 CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14

Group4

Group5

+1.5VSDGPU VDD VDD VDD VDD VDD VDD VDD VDD VDD

B2 D9 G7 K2 K8 N1 N9 R1 R9

VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ DQSL VDDQ DQSU VDDQ

A1 A8 C1 C9 D2 E9 F1 H2 H9

DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

B1 B9 D1 D8 E2 E8 F9 G1 G9

BA0 BA1 BA2

CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE

CMDC12 CMDC27 CMDC26

+1.5VSDGPU

M8 H1

VREFCA VREFDQ

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

M2 N8 M3

CLKC1 CLKC1# CMDC19

J7 K7 K9

CMDC18 CMDC16 CMDC30 CMDC15 CMDC13

K1 L2 J3 K3 L3

Mode D Address

X76@ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

MDC56 MDC63 MDC57 MDC60 MDC59 MDC61 MDC58 MDC62

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

MDC48 MDC55 MDC49 MDC52 MDC51 MDC54 MDC50 MDC53

CMD0

VDD VDD VDD VDD VDD VDD VDD VDD VDD

B2 D9 G7 K2 K8 N1 N9 R1 R9

VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ DQSL VDDQ DQSU VDDQ

A1 A8 C1 C9 D2 E9 F1 H2 H9

DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

B1 B9 D1 D8 E2 E8 F9 G1 G9

CK CK CKE/CKE0

CMD2

Group6

+1.5VSDGPU

2

DQMC4 DQMC5

C524 GS@ 0.1U_0402_16V4Z

1

E7 D3

DQSC#4 DQSC#5

G3 B7

CMDC5

T2

ZQ6

L8

RESET ZQ/ZQ0

DQSC7 DQSC6

F3 C7

DQMC7 DQMC6

E7 D3

DQSC#7 DQSC#6

G3 B7

CMDC5

T2

ZQ7

1 2

L8

DQSL DQSU

RESET ZQ/ZQ0

CLKC1# 1

CMD5

RST

RST

CMD6

A9

A9

CMD7

A7

A7

CMD8

A2

A2

CMD9

A0

A0

CMD10

A4

A4

CMD11

A1

A1

CMD12

BA0

BA0

CMD13

WE*

WE*

CMD14

A15

A15

CMD15

CAS*

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

A14

C

CAS* CS0_H# ODT_H CKE_H

CMD19 CMD20

A13

A13

CMD21

A8

A8

CMD22

A6

A6

CMD23

A11

A11

CMD24

A5

A5

CMD25

A3

A3

CMD26

BA2

BA2

CMD27

BA1

BA1

CMD28

A12

A12

CMD29

A10

A10

CMD30

RAS*

RAS*

LOW

HIGH

B

Not Available

96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96

+1.5VSDGPU

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

GS@ C521 0.1U_0402_16V4Z

1

GS@ C522 0.1U_0402_16V4Z

2

GS@ C523 0.1U_0402_16V4Z

1

GS@ C525 0.1U_0402_16V4Z

2

GS@ C526 0.1U_0402_16V4Z

1

GS@ C519 1U_0603_10V6K

2

GS@ C517 1U_0603_10V6K

1

GS@ C518 1U_0603_10V6K

2

GS@ C39 0.1U_0402_16V4Z

1

GS@ C40 0.1U_0402_16V4Z

2

GS@ C41 0.1U_0402_16V4Z

1

GS@ C42 0.1U_0402_16V4Z

+1.5VSDGPU

GS@ C43 0.1U_0402_16V4Z

2

J1 L1 J9 L9

96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 @ C57 0.01U_0402_16V7K

GS@ C45 0.1U_0402_16V4Z

NV recommand 0720

1

GS@ C36 1U_0603_10V6K

2 R37 @ 80.6_0402_1%

GS@ C37 1U_0603_10V6K

CLKC1#

GS@ C38 1U_0603_10V6K

23

GS@ C48 1U_0603_10V6K

2

GS@ R35 160_0402_1%

GS@ R411 243_0402_1%

GS@ C532 1U_0603_10V6K

2 R33 @ 80.6_0402_1%

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

2

GS@ R30 243_0402_1%

CLKC1 1

CLKC1 1

23

J1 L1 J9 L9

A14

CMD18

1

B

DQSL DQSU

CKE

CMD4

CMD17

+MEM_VREF7 GS@ R408 240_0402_1%

ODT_L

CMD3

CMD16 ODT/ODT0 CS/CS0 RAS CAS WE

32..63

CMD1 Group7

+1.5VSDGPU

BA0 BA1 BA2

0..31 CS0_L#

A

A

Issued Date

WWW.AliSaler.Com 5

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

N12P DDR3 9/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

30

of

61

5

4

3

2

1

D

D

LCD POWER CIRCUIT

+LCDVDD

+3VS

+3VALW 1

W=60mils R6 10K_0402_5%

1

2

2

R5 300_0603_5%

Place closed to JLVDS1

+LCDVDD

C479 4.7U_0603_6.3V6K

+INVPWR_B+ B+ L2 FBMA-L11-201209-221LMA30T_0805 2 1 L1 FBMA-L11-201209-221LMA30T_0805 2 1

W=60mils

+3VS

2

2 G

1

3

S

PCH_ENVDD

1 UMA@ 2 LCDVDD_ON 0_0402_5%

R1

22

Q1 SSM3K7002F_SC59-3

2

Q28 +LCDVDD

1

1

C484 0.1U_0402_16V4Z

2

1

C485 10U_0805_10V4Z

2

C11 C9 680P_0402_50V7K

0.1U_0402_16V4Z

W=60mils

1

1

2

2

1

1

C483 4.7U_0805_10V4Z

2

2

SM010014520 3000ma 220ohm@100mhz DCR 0.04

C10 0.1U_0402_16V4Z

LCD/LED PANEL Conn.

R4

C

C6 68P_0402_50V8J

2

S

1

1 DISO@ 2 R3 0_0402_5%

ENVDD

C2 0.047U_0402_16V7K

D

2 G 3

16

1

AP2301GN-HF_SOT23-3

2

1

Q2 SSM3K7002F_SC59-3

3

R2 1K_0402_5% 2 1

1

1

D

C

100K_0402_5% 2

W=60mils +INVPWR_B+

40

BKOFF#

DAC_BRIG

220P_0402_50V7K 1

2 C482

INVTPWM

220P_0402_50V7K 1

2

C5

BKOFF#

220P_0402_50V7K 1

2

C8

R18

R05 modify

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

BKOFF# INVTPWM TXCLK+ TXCLKTXOUT2+ TXOUT2-

2 10K_0402_5%

1

JLVDS1

TXOUT1+ TXOUT1TXOUT0+ TXOUT0I2CC_SDA I2CC_SCL

UMA Only / Optimus

40

TXOUT0+ TXOUT0-

0_0402_5% 2 UMA@ 1 R471 0_0402_5% 2 UMA@ 1 R473

PCH_TXOUT0+ PCH_TXOUT0-

17 17

TXOUT1+ TXOUT1-

0_0402_5% 2 UMA@ 1 R441 0_0402_5% 2 UMA@ 1 R452

PCH_TXOUT1+ PCH_TXOUT1-

TXOUT2+ TXOUT2-

0_0402_5% 2 UMA@ 1 R434 0_0402_5% 2 UMA@ 1 R439

PCH_TXOUT2+ PCH_TXOUT2-

TXCLK+ TXCLK-

0_0402_5% 2 UMA@ 1 R432 0_0402_5% 2 UMA@ 1 R430

PCH_TXCLK+ PCH_TXCLK-

I2CC_SCL I2CC_SDA

0_0402_5% 2 UMA@ 1 R504 0_0402_5% 2 UMA@ 1 R499

PCH_LCD_CLK PCH_LCD_DATA

PCH_TXOUT0+ 16 PCH_TXOUT0- 16

PCH_TXCLK+ 16 PCH_TXCLK- 16

DPST_PWM

1 2

Discrete ONLY

TXOUT1+ TXOUT1-

0_0402_5% 2 DISO@ 1 R440 0_0402_5% 2 DISO@ 1 R451

VGA_TXOUT1+ VGA_TXOUT1-

TXOUT2+ TXOUT2-

0_0402_5% 2 DISO@ 1 R433 0_0402_5% 2 DISO@ 1 R438

VGA_TXOUT2+ VGA_TXOUT2-

TXCLK+ TXCLK-

0_0402_5% 2 DISO@ 1 R431 0_0402_5% 2 DISO@ 1 R429

VGA_TXCLK+ VGA_TXCLK-

I2CC_SCL I2CC_SDA

0_0402_5% 2 DISO@ 1 R503 0_0402_5% 2 DISO@ 1 R498

A

VGA_LCD_CLK VGA_LCD_DATA

C481 22P_0402_50V8J 2 @

ACES_88341-3000B001 CONN@

OE# VCC

5

OUT

4

Reserved for UMA Only and OPTIMA

IN DPST_PWM_1

GND

INVTPWM 1 UMA@ 2 R20 0_0402_5%

74AHC1G125GW_SOT353-5 UMA@

D15

VGA_TXOUT0+ 24 VGA_TXOUT0- 24 VGA_TXOUT1+ 24 VGA_TXOUT1- 24 VGA_TXOUT2+ 24 VGA_TXOUT2- 24

40

INVT_PWM

INVT_PWM

1 DISO@ 2 R19 0_0402_5%

USB20_CMOS_P10

1

I/O1

I/O4

6

2

REF1 REF2

5

3

I/O2

4

I/O3

+3VS USB20_CMOS_N10

PJUSB208H_SOT23-6 VGA_PNL_PWM 1 R17

22 VGA_PNL_PWM

@

2 0_0402_5%

VGA_TXCLK+ 24 VGA_TXCLK- 24

1

VGA_TXOUT0+ VGA_TXOUT0-

2

B

+3VS

U1 1 R783 2 100K_0402_5%

PCH_LCD_CLK 16 PCH_LCD_DATA 16

R388 20_0402_5% +3VS_CAMERA 1 USB20_CMOS_P10 2 0_0402_5% USB20_CMOS_N10 2 0_0402_5% 1 1 C480 22P_0402_50V8J @

R02 modify

PCH_TXOUT2+ 16 PCH_TXOUT2- 16

3

0_0402_5% 2 DISO@ 1 R470 0_0402_5% 2 DISO@ 1 R472

DAC_BRIG R387 1 R386 1

PCH_TXOUT1+ 16 PCH_TXOUT1- 16

16

TXOUT0+ TXOUT0-

DAC_BRIG +3VS USB20_P10 USB20_N10

A

R16 10K_0402_5%

VGA_LCD_CLK 22 VGA_LCD_DATA 22

2

B

+3VS +LCDVDD

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

LVDS Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

31

of

61

A

B

C

DISO@

DISO@

DISO@

L32 0_0805_5%

L29 0_0805_5%

L27 0_0805_5%

D

E

EMI Cost request

1

1

For DISO only L22,L24,L26 use 0 Ohm

1

1

2

UMA@ 2

1

UMA@ 2

1

UMA@ 2

2

3

1

CRT_B_2

1

2

1

2

1

2

C597 10P_0402_50V8J

1

1

2

SM010012010 300ma 120ohm@100mhz DCR 0.4 +CRT_VCC

P CRT_HSYNC

A

1 10K_0402_5%

U10 Y

1 L13

2 MBC1608121YZF_0603

CRT_HSYNC_2

1 L10

2 MBC1608121YZF_0603

CRT_VSYNC_2 1 1

C230 10P_0402_50V8J CRT_HSYNC_1

4

C589 100P_0402_50V8J

3

JCRT1 6 JCRT1.11 11 @ T71 1 7 12 2 8 13 3 9 14 G 16 4 G 17 10 15 JCRT1.5 5 @ T72 C-H_13-12201513CP PAD CONN@

2

DSUB_12

2

2

1

C220 10P_0402_50V8J

DSUB_15

C623 2 68P_0402_50V8J 1

G

2

1

R147 2 5

2 0.1U_0402_16V4Z

OE#

C243 1

CRT Connector

PAD

CRT_G_2

C614 10P_0402_50V8J

2

CRT_B_1

1

C215 0.1U_0402_16V4Z

CRT_R_2

C637 10P_0402_50V8J

2

CRT_G_1

C588 22P_0402_50V8J

2

CRT_R_1

CH491DPT_SOT23-3

2

L33 BLM18BA470SN1D_2P 1 2 L30 BLM18BA470SN1D_2P 1 2 L28 BLM18BA470SN1D_2P 1 2

C601 22P_0402_50V8J

2

1

@

1

+CRT_VCC F1 1.1A_6V_SMD1812P110TFW=40mils 1 2

1

D18 PJDLC05C_SOT23-3 @

C621 22P_0402_50V8J

2 2

1

C596 10P_0402_50V8J

1

R510 150_0402_1%

C613 10P_0402_50V8J

R524 R520 150_0402_1% 150_0402_1%

C636 10P_0402_50V8J

1

CRT_B

+R_CRT_VCC

2 D17 PJDLC05C_SOT23-3

L32 BLM18BA470SN1D_2P 1 2 L29 BLM18BA470SN1D_2P 1 2 L27 BLM18BA470SN1D_2P 1 2

CRT_G

+5VS D5

CRB1.0 use 47ohm@100Mhz Bead

CRT_R

2

3

W=40mils

74AHCT1G125GW_SOT353-5

2

C586 68P_0402_50V8J

+CRT_VCC

P 2

A

U9 Y

4

CRT_VSYNC_1

3

G

CRT_VSYNC

1

5

2 0.1U_0402_16V4Z

OE#

C228 1

74AHCT1G125GW_SOT353-5 +CRT_VCC

3

3

UMA Only / OPTIMUS 16 PCH_CRT_G 16 PCH_CRT_B 16 PCH_CRT_HSYNC 16 PCH_CRT_VSYNC 16 PCH_CRT_CLK

R424 2 UMA@ 1 0_0402_5%

CRT_G

PCH_CRT_B

R422 2 UMA@ 1 0_0402_5%

PCH_CRT_HSYNC

R428 2 UMA@ 1 33_0402_5%

CRT_HSYNC

PCH_CRT_VSYNC

R426 2 UMA@ 1 33_0402_5%

CRT_VSYNC

PCH_CRT_CLK

R506 2 UMA@ 1 0_0402_5% CRT_DDC_CLK

CRT_B

CRT_DDC_DATA

1

CRT_DDC_CLK

4

R142 4.7K_0402_5% 2

PCH_CRT_G

2

CRT_R 2

R420 2 UMA@ 1 0_0402_5%

PCH_CRT_DATA

16 PCH_CRT_DATA

R146 4.7K_0402_5%

PCH_CRT_R

5

16 PCH_CRT_R

1

1

+3VS

DSUB_12

6 Q11A DMN66D0LDW-7_SOT363-6

DSUB_15

3

Q11B DMN66D0LDW-7_SOT363-6

R501 2 UMA@ 1 0_0402_5% CRT_DDC_DATA

Discrete only 22 VGA_CRT_R 4

22 VGA_CRT_G 22 VGA_CRT_B 22 VGA_CRT_HSYNC 22 VGA_CRT_VSYNC 22 VGA_DDC_CLK 22 VGA_DDC_DATA

VGA_CRT_R

R419 2 DISO@ 1 0_0402_5%

CRT_R

VGA_CRT_G

R423 2 DISO@ 1 0_0402_5%

CRT_G

VGA_CRT_B

R421 2 DISO@ 1 0_0402_5%

CRT_B

VGA_CRT_HSYNC

R427 2 DISO@ 1 0_0402_5% CRT_HSYNC

VGA_CRT_VSYNC

R425 2 DISO@ 1 0_0402_5% CRT_VSYNC

VGA_DDC_CLK

R505 2 DISO@ 1 0_0402_5% CRT_DDC_CLK

VGA_DDC_DATA

R500 2 DISO@ 1 0_0402_5% CRT_DDC_DATA

4

WWW.AliSaler.Com A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

CRT Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

B

C

D

Sheet

Wednesday, June 08, 2011 E

32

of

61

5

4

@R242 @ R242 0_0603_5% 1 2

D

3

2

1

SM070001310 400ma 90ohm@100mhz DCR 0.3

W=40mils

HDMI_CLK-

+HDMI_5V_OUT D10 2

+5VS

R574 1

F2 1 +HDMI_5V

CH491DPT_SOT23-3

1

1

L38 WCM-2012-900T_0805 @ 4

2

1.1A_6V_SMD1812P110TF

1

2

C345 0.1U_0402_16V4Z

1

2

4

3

HDMI_CLK+

R579 1

2

HDMI_TX0-

R565 1

2

D

HDMI_R_CK-

0_0402_5%

2

2 3 0_0402_5%

HDMI_R_CK+

0_0402_5%

HDMI_R_D0-

+3VS

1

1

2 G HDMI_HPD

16 PCH_DPB_N1 16 PCH_DPB_P1

C283 UMA@ 2 C282 UMA@ 2

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

HDMI_TX1HDMI_TX1+

16 PCH_DPB_N2 16 PCH_DPB_P2

C287 UMA@ 2 C286 UMA@ 2

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

HDMI_TX0HDMI_TX0+

16 PCH_DPB_N3 16 PCH_DPB_P3

C285 UMA@ 2 C284 UMA@ 2

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

HDMI_CLKHDMI_CLK+

1

2

1

3

S

2

HDMI_TX2HDMI_TX2+ D

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

1

C280 UMA@ 2 C281 UMA@ 2

PCH_DPB_HPD 16

Q14 SSM3K7002F_SC59-3 UMA@ UMA@ R219 100K_0402_5%

HDMI_TX1-

R584 1

2

HDMI_TX1+

R586

HDMI_TX2-

R591

24 VGA_HDMI_TXD024 VGA_HDMI_TXD0+

C241 DISO@2 C240 DISO@2

1 0.1U_0402_10V7K HDMI_TX01 0.1U_0402_10V7K HDMI_TX0+

24 VGA_HDMI_TXC24 VGA_HDMI_TXC+

C239 DISO@2 C238 DISO@2

1 0.1U_0402_10V7K HDMI_CLK1 0.1U_0402_10V7K HDMI_CLK+

HDMI_TX2+

100K_0402_5% R552 DISO@

3 3

2

1

2

4

3

1

2

1

2

1 4

3 0_0402_5%

HDMI_R_D0+

0_0402_5%

HDMI_R_D1-

2 3 0_0402_5%

HDMI_R_D1+

0_0402_5%

HDMI_R_D2C

2 3

R593 1

2

2

2 3 0_0402_5%

HDMI_R_D2+

R03 modify

DISO@ D20 BAV99_SOT23-3

2

1 0.1U_0402_10V7K HDMI_TX11 0.1U_0402_10V7K HDMI_TX1+

HDMI_HPD

1

C237 DISO@2 C236 DISO@2

1

24 VGA_HDMI_TXD124 VGA_HDMI_TXD1+

22 VGA_HDMI_DET

HDMI_TX2- R589 1 UMA@ 2 680_0402_5% HDMI_TX2+ R594 1 UMA@ 2 680_0402_5% 1

DGPU_HPD_INT# 18

D

1 0.1U_0402_10V7K HDMI_TX21 0.1U_0402_10V7K HDMI_TX2+

S

C234 DISO@2 C235 DISO@2

L19 DISO@ BLM18PG181SN1D_0603 2 1

3 2

1 L40 WCM-2012-900T_0805 @ 4

G

24 VGA_HDMI_TXD224 VGA_HDMI_TXD2+

2

DIS

R547 DISO@ 10K_0402_5% 1 2

4

R569 1

C

NVIDA Recommand 05/10

2

HDMI_TX0+

1 L39 WCM-2012-900T_0805 @ 4

2

16 PCH_DPB_N0 16 PCH_DPB_P0

C324 220P_0402_50V7K

UMA

L36 WCM-2012-900T_0805 @ 4

R198 1M_0402_5% UMA@

1

SSM3K7002F_SC59-3 Q13 DISO@

+3VSDGPU

HDMI_GND

HDMI_TX1- R583 1 UMA@ 2 680_0402_5% HDMI_TX1+ R587 1 UMA@ 2 680_0402_5% HDMI_TX0- R564 1 UMA@ 2 680_0402_5% HDMI_TX0+ R570 1 UMA@ 2 680_0402_5%

+3VS

INTEL use 680 Ohm for terminationn in DG 1.5 2

+HDMI_5V_OUT

1

HDMI_CLK- R573 1 UMA@ 2 680_0402_5% HDMI_CLK+ R580 1 UMA@ 2 680_0402_5%

D Q37

+3VS

RB751V40_SC76-2 R785 0_0402_5% UMA@

DISO@

1

R784 0_0402_5%

D12

G

2

Pull high at VGA side 1 UMA@ 2 0_0402_5% 1 DISO@ 2 0_0402_5%

HDMI_SCLK_R

16 SDVO_SDATA 24 VGA_HDMI_SDATA

R252 R254

1 UMA@ 2 0_0402_5% 1 DISO@ 2 0_0402_5%

HDMI_SDATA_R

3

D11 RB751V40_SC76-2 +HDMI_5V_OUT

1

HDMI_SDATA HDMI_SCLK HDMI_R_CKHDMI_SCLK

2

1 HDMI_SDATA

D

S Q17

SSM3K7002F_SC59-3

1

1

SSM3K7002F_SC59-3

Place closed to JHDMI1

HDMI_R_CK+ HDMI_R_D0-

1109 RF request

G

Q16 3

3

JHDMI1 HDMI_HPD

D

R249 R244

S

16 SDVO_SCLK 24 VGA_HDMI_SCLK

HDMI connector

2

R03 modify

1 2 1 R255 2.2K_0402_5%

SDVO_SDATA

2

1 UMA@ 2 2.2K_0402_5%

1 2 1 R256 2.2K_0402_5%

R253 B

+3VSDGPU +3VS 2

SDVO_SCLK

2

1 UMA@ 2 2.2K_0402_5%

1

R250

G SSM3K7002F_SC59-3 S

2

HDMI_R_D0+ HDMI_R_D1-

C357 47P_0402_50V8J @

HDMI_R_D1+ HDMI_R_D2-

C358 47P_0402_50V8J 2 @

HDMI_R_D2+

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

B

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

NV use 499 Ohm for terminationn

20 21 22 23

DISO@

DISO@

DISO@

DISO@

R589 499_0402_5%

R594 499_0402_5%

R583 499_0402_5%

R587 499_0402_5%

DISO@

DISO@

DISO@

DISO@

R564 499_0402_5%

R570 499_0402_5%

R573 499_0402_5%

R580 499_0402_5%

ACON_HMR2E-AK120D CONN@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

HDMI Conn

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

E JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

33

of

61

5

4

3

2

1

D

D

SATA HDD1 Conn. CL 4.0 mm JHDD1 13 SATA_PTX_DRX_P0 13 SATA_PTX_DRX_N0 13 SATA_PRX_DTX_N0 13 SATA_PRX_DTX_P0

SATA_PTX_DRX_P0 SATA_PTX_DRX_N0

C708 1 C711 1

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0

C712 1 C713 1

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0

+3VS

+5VS

R05 modify C

+3VS 1

2

0.1U_0402_16V4Z

+5VS

R05 modify C

100mils 1

2

OCTEK_SAT-22DD1G CONN@

change to port1 cause by intel SATA II issue (20110201)

C453

1

2

1

2

1

2

C742 1000P_0402_50V7K

3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND Rsv GND 12V 12V 12V GND GND

C743 0.1U_0402_16V4Z

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C740 1U_0402_6.3V6K

GND RX+ RXGND TXTX+ GND

C744 10U_0805_10V4Z

1 2 3 4 5 6 7

SATA ODD Conn. JODD1

R20 modify

13 SATA_PTX_DRX_P1 13 SATA_PTX_DRX_N1

C643 1 C639 1

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P2 SATA_PTX_C_DRX_N2

13 SATA_PRX_DTX_N1 13 SATA_PRX_DTX_P1

C628 1 C624 1

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

SATA_PRX_C_DTX_N2 SATA_PRX_C_DTX_P2

R763

1 @

2

0_0402_5%

+5VS_ODD

+5VS R765 0_0805_5% 1 2

GND GND GND GND

17 16 15 14

OCTEK_SLS-13SB1G_RV CONN@

2

1

2

1

2

1

2

B

1

S Q55 SI3456BDV-T1-E3 1N TSOP6

@ 1

3

18

@

R764 1.5M_0402_5%

1

ODD_EN D

Q56 2 ODD_EN# G SSM3K7002F_SC59-3 S @

4

G

2

6 5 2 1 3

@

C812 1U_0402_6.3V6K

1

R760 470K_0402_5% @

2

2

D

+VSB

ODD_DA#_R

80mils 1

C192 1000P_0402_50V7K

ODD_DA#

DP +5V +5V MD GND GND

C200 0.1U_0402_16V4Z

17

8 9 10 11 12 13

+5VS_ODD

C201 1U_0402_6.3V6K

B

+5VS_ODD

GND A+ AGND BB+ GND

C199 10U_0805_10V4Z

1 @ R139 2 0_0402_5% +5VS_ODD

18 ODD_DETECT#

1 2 3 4 5 6 7

2

1

C811 0.1U_0402_16V4Z @

A

A

Issued Date

WWW.AliSaler.Com 5

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

HDD & ODD Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

34

of

61

5

4

3

2

1

+1.2V_LAN 0.1U_0402_16V4Z C678

1

C302

0.1U_0402_16V4Z 1 1 1 C674 C301

C671

1

U32

0.1U_0402_16V4Z +3VALW 1 1 C298 C668 +1.2V_LAN

4.7U_0603_6.3V6K 2

2 2 0.1U_0402_16V4Z

2 2 0.1U_0402_16V4Z

2 2 0.1U_0402_16V4Z

20

VDDO_CR

35 61

VDDC VDDC

+3VALW 7 56 62

+3VALW

D

1

C683

4.7U_0603_6.3V6K 2

C690

+LAN_AVDDL

2 0.1U_0402_16V4Z

37

+LAN_BIASVDDH

XTALVDDH

17

+LAN_XTALVDDH

AVDDH AVDDH

48 42

VDDO VDDO VDDO

39 45 51

+3VALW

60mil

+LAN_AVDDH

1

C662

AVDDL AVDDL AVDDL

+LAN_GPHYPLLVDDL

36

GPHY_PLLVDDL

+LAN_PCIEPLLVDD

32

PCIE_PLLVDDL

29

PCIE_PLLVDDL

TRD3_N TRD3_P

49 50

LAN_MIDI3LAN_MIDI3+

TRD2_N TRD2_P

47 46

LAN_MIDI2LAN_MIDI2+

TRD1_N TRD1_P

43 44

LAN_MIDI1LAN_MIDI1+

TRD0_N TRD0_P

41 40

LAN_MIDI0LAN_MIDI0+

20mil

LAN_MIDI1- 36 LAN_MIDI1+ 36

+LAN_XTALVDDH C323

LAN_MIDI0- 36 LAN_MIDI0+ 36

20mil

65

2

40

28 2 C670 PCIE_PRX_C_DTX_P1 2 C673 PCIE_PRX_C_DTX_N1 27 33 34

EC_PME#

R201 1

2 0_0402_5%

+3VALW

R209 1

2 4.7K_0402_5%

C

R213 1

15,38,39,46 PCH_PCIE_WAKE#

@

TRAFFICLED#_SERIALDI

67

17,38,39,40,46 PLT_RST_BUF# 14 CLK_PCIE_LAN 14 CLK_PCIE_LAN#

CR_DATA0 R199 CR_DATA1 R207 CR_DATA2 R211 CR_DATA3 R215 CR_DATA4 R168 CR_DATA5 R171 CR_DATA6 R179 CR_DATA7 R182

CR_DATA0 CR_DATA1 CR_DATA2 CR_DATA3 CR_DATA4 CR_DATA5 CR_DATA6 CR_DATA7

LAN_PME#

L15

+VDDO_CR_R

GPIO_0

5

CR_5IN1_LED#_R

PREST# PCIE_REFCLK_P PCIE_REFCLK_N

CR_DATA0_R CR_DATA1_R CR_DATA2_R CR_DATA3_R CR_DATA4_R CR_DATA5_R CR_DATA6_R CR_DATA7_R

25 24 23 22 52 53 54 55

CR_DATA0 CR_DATA1 CR_DATA2 CR_DATA3 CR_DATA4 CR_DATA5 CR_DATA6 CR_DATA7

R190 1

2 1K_0402_5%

R228

B

R208 2 R212 1

1

58

TEST1

10 1 2 R226 4.7K_0402_5% B0@ 1 0_0402_5% 4 2 10K_0402_5% A0@

TEST2

2

LAN_XTALO_R LAN_XTALI

LOW_PWR

19 18

2LAN_XTALO

2

CR_5IN1_LED#

0.1U_0402_16V4Z

CR_5IN1_LED# 41

CR_XD_WE#_SD_DETECT_R

R576

2

1 0_0402_5%

CR_XD_WE#_SD_DETECT

SR_DISABLE/XD_DETECT#

68

CR_XD_DETECT#_R

R572

2

1 0_0402_5%

CR_XD_DETECT#

MS_INS#/XD_CE#

59

CR_XD_CE#_MS_INS#_R

R192

1

2 0_0402_5%

CR_XD_CE#_MS_INS#

9

CR_XD_RE#_R

R227

2

1 0_0402_5%

CR_XD_RE#

CR_WP#/XD_WP#

57

CR_WP#_XD_WP#_R

R185

2

1 0_0402_5%

CR_WP#_XD_WP#

CR_LED_CR_BUS_PWR/XD_ALE

60

CR_PWR_XD_ALE_R

R196

2

A0@ 1 0_0402_5%

CR_PWR_XD_ALE

CR_CLK/XD_RY_BY#

21

CR_CLK_XD_RY_BY#_R

R216

1

2 0_0402_5%

CR_CMD_XD_CLE

26

CR_CMD_XD_CLE_R

R195

1

2 47_0402_5% CR_CMD_XD_CLE

14 LAN_CLKREQ#

SR_LX

16

SR_VFB

13

40mil

38

RDAC

12

CLK_REQ#

BCM57785XA0KMLG_QFN68_8X8

SR_VDDP SR_VDD

C689

C337

CR_XD_WE#_SD_DETECT 36 CR_XD_DETECT# 36

1

4.7U_0603_6.3V6K 2

CR_XD_CE#_MS_INS# 36

C676

1

C328

1 1

2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z

CR_XD_RE# 36 CR_WP#_XD_WP# 36 CR_PWR_XD_ALE 36 R222

CR_CLK_XD_RY_BY#

CR_CLK_XD_RY_BY#

36

C329

1

2 1 2 @ 22_0402_5% @ 0.01U_0402_16V7K

CR_CMD_XD_CLE 36

40mil +1.2V_LAN 1

1

2

2

EMI Request...2010/07/27

C691 10U_0805_10V4Z

B

SM010005500 500ma 600ohm@100mhz DCR 0.38

20mil

40mil

15 14

C

R232 2 B0@ 0_0805_5%

For EMI request

L37 +1.2V_LAN_OUT 1 2 4.7UH_PG031B-4R7MS_1.1A_20%

XTALO XTALI

15mil

2 LAN_RDAC 1.24K_0402_1%

25MHZ_20PF_7A250000121

C681 27P_0402_50V8J 2

2

R826 (+VDDO_CR) +VDDO_CR For B0 version

0.1U_0402_16V4Z

GND PLANE

1 1

2

+VDDO_CR

+3VALW 1 0.1U_0402_16V4Z C684

1

2

2

L18 1 2 BLM18AG601SN1D_2P

+LAN_PCIEPLLVDD

4.7U_0603_6.3V6K C692

C306 0.1U_0402_16V4Z

1

1

2

2

+1.2V_LAN

C303 4.7U_0603_6.3V6K

69

2 Y4

0_0402_5%

0.1U_0402_16V4Z

1 2 BLM18AG601SN1D_2P

R04 modify

R562 200_0402_1% 1 R541

modify

C294

1

SPROM_DOUT SPROM_CLK

64 63

VMAIN_PRSNT

6

LAN_XTALI LAN_XTALO_R

B0@ 1

4.7K_0402_5% 1

CR_PWR_XD_ALE

0_0603_5% R03 2

1 R229 2

LAN_ACTIVITY# 36

1

GPIO2_MEDIA_SENSE/XD_RE#

R05 modify

R824 (CP_PWR_XD_ALE) for B0 version

1 0_0402_5% R214

+3VS +3VALW

R200 2

1

WAKE#

11 31 30

47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5%

2 2 2 2 2 2 2 2

1 2 BLM18AG601SN1D_2P 0.1U_0402_16V4Z

2

20mil

8

SI_EEDATA CS#_EECLK

3

2 0_0402_5%

1 1 1 1 1 1 1 1

L34

+LAN_AVDDH

GPIO1_LR_OUT

SD_DETECT/XD_WE#

36 36 36 36 36 36 36 36

1

+3VALW

+XDPWR_SDPWR_MSPWR

2 0_0402_5%

R225 1

PCIE_TXD_P PCIE_TXD_N PCIE_RXD_P PCIE_RXD_N

L20 1 2 BLM18AG601SN1D_2P 0.1U_0402_16V4Z

2

C299 0.1U_0402_10V7K 1 0.1U_0402_10V7K 1

1

LAN_LINK# 36

66

SPD100LED#_SERIALDO

D

LAN_MIDI2- 36 LAN_MIDI2+ 36

C657

SCLK_SPD1000LED#

PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 PCIE_PTX_C_DRX_P1 PCIE_PTX_C_DRX_N1

C666

LAN_MIDI3- 36 LAN_MIDI3+ 36

+LAN_BIASVDDH SO_LINKLED#

14 14 14 14

1

4.7U_0603_6.3V6K 2 2 0.1U_0402_16V4Z

0.1U_0402_16V4Z 1 1 1 C680 C667

2 2 0.1U_0402_16V4Z

BIASVDDH

PLACE NEXT P14

C679 27P_0402_50V8J

20mil

L35 1 2 BLM18AG601SN1D_2P

+LAN_GPHYPLLVDDL C658 0.1U_0402_16V4Z

1

1

2

2

1

1

2

2

+1.2V_LAN

C659 4.7U_0603_6.3V6K

+3VALW

1

0

1

1

@

R537 4.7K_0402_5%

R536 4.7K_0402_5%

20mil

2

2

SPROM_CLK SPROM_DOUT

L17 1 2 BLM18AG601SN1D_2P

+LAN_AVDDL C656

+1.2V_LAN

C297

U31 @ 8 7 6 5

1

A

2 0.1U_0402_16V4Z @

1

AT24C02

C634 1 2

SPROM_DOUT (EEDATA) 2

On chip

SPROM_CLK (EECLK)

VCC WP SCL SDA

A0 A1 A2 GND

0.1U_0402_16V4Z

1 2 3 4

4.7U_0603_6.3V6K A

AT24C04BN-SH-T_SO8

R538 4.7K_0402_5% R525 @ 4.7K_0402_5% 1

2011/02/08

1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/02/08

Deciphered Date

Title

Broadcom BCM57785

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

35

of

61

5

4

3

2

1

T28

TCT1 TD1+ TD1-

MCT1 MX1+ MX1-

24 23 22

RJ45_MIDI3+ RJ45_MIDI3-

35 35

LAN_MIDI2LAN_MIDI2+

LAN_MIDI2LAN_MIDI2+

4 5 6

TCT2 TD2+ TD2-

MCT2 MX2+ MX2-

21 20 19

RJ45_MIDI2RJ45_MIDI2+

35 35

LAN_MIDI1+ LAN_MIDI1-

LAN_MIDI1+ LAN_MIDI1-

7 8 9

TCT3 TD3+ TD3-

MCT3 MX3+ MX3-

18 17 16

RJ45_MIDI1+ RJ45_MIDI1-

35 35

LAN_MIDI0LAN_MIDI0+

LAN_MIDI0LAN_MIDI0+

10 11 12

TCT4 TD4+ TD4-

MCT4 MX4+ MX4-

15 14 13

RJ45_MIDI0RJ45_MIDI0+

D

1

C474,C475 and D14 ME interefer,do not pop!!

+3VALW

2 R384

1 1K_0402_5%

R490 75_0603_1%

1

220P_0402_50V7K C473

0.1U_0402_16V4Z

2

C474 68P_0402_50V8J @ 2 1

RJ45_GND

Place close to TCT pin

LAN_LINK#

35 LAN_LINK#

BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00 TIMAG:S X'FORM_ IH-160 LAN , SP050006F00

+3VALW

2 1 R385 1K_0402_5% 1 220P_0402_50V7K C476

R05 modify

Card Reader Connector

10 9 12 15 17 14 7

MS_DATA0 MS_DATA1 MS_DATA2 MS_DATA3 MS_SCLK MS_INS MS_BS

4

PR3+

RJ45_MIDI2-

5

PR3-

RJ45_MIDI1-

6

PR2-

RJ45_MIDI3+

7

PR4+

RJ45_MIDI3-

8

PR4-

11

Yellow LED+

12

Yellow LEDSANTA_130451-K CONN@

1

40mil

CR_XD_RE# CR_PWR_XD_ALE

C478 1 2

RJ45_GND

LANGND

1000P_1206_2KV7K

1

R04 modify

40mil CR_XD_DETECT# 35 CR_CLK_XD_RY_BY# 35 CR_XD_RE# 35 CR_XD_CE#_MS_INS# 35 CR_CMD_XD_CLE 35 CR_PWR_XD_ALE 35 CR_XD_WE#_SD_DETECT 35 CR_WP#_XD_WP# 35

1 J10 JUMP_43X118 @

2

1

B88069X9231T203_4P5X3P2-2 JP2 @

JP3 @ B88069X9231T203_4P5X3P2-2

C832 @

2 100P_0402_50V8J

R04 modify

R04 modify

D36 PJDLC05C_SOT23-3 @

L53 100UH_SSC0301101MCF_0.18A_20% R06 Modify

TAITW_R013-P17-HM_NR CONN@

A

A

2011/02/08

Issued Date

5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

WWW.AliSaler.Com

B

R03 modify

2

6 13 5 20 30 40 41 42

PR2+

RJ45_MIDI2+

1

SD_GND SD_GND MS_GND MS_GND XD_GND XD_GND GND GND

2 @

1

22 23 24 25 26 27 28 29

PR1-

3

EMI Request CR_DATA0 35 CR_DATA1 35 CR_DATA2 35 CR_DATA3 35 CR_DATA4 35 CR_DATA5 35 CR_DATA6 35 CR_DATA7 35 CR_XD_DETECT#

1

XD_CD XD_R/B XD_RE XD_CE XD_CLE XD_ALE XD_WE XD_WP-IN

CR_DATA0 CR_DATA1 CR_DATA2 CR_DATA3 CR_DATA4 CR_DATA5 CR_DATA6 CR_DATA7

2

SD_CLK SD_CMD SD_CD SD_WP SD/MMC_DAT0 SD/MMC_DAT1 SD/MMC_DAT2 SD/MMC_DAT3

31 32 33 34 35 36 37 38

2

RJ45_MIDI1+

C

14 13

SHLD1 SHLD2

1

CR_DATA0 CR_DATA1 CR_DATA2 CR_DATA3 CR_CLK_XD_RY_BY# CR_XD_CE#_MS_INS# CR_CMD_XD_CLE

8 16 1 2 4 3 21 19

XD_D0 XD_D1 XD_D2 XD_D3 XD_D4 XD_D5 XD_D6 XD_D7

RJ45_MIDI0-

2

CR_CLK_XD_RY_BY# CR_CMD_XD_CLE CR_XD_WE#_SD_DETECT CR_WP#_XD_WP# CR_DATA0 CR_DATA1 CR_DATA2 CR_DATA3

SD_VCC MS_VCC XD_VCC

PR1+

C475 @ JP1 B88069X9231T203_4P5X3P2-2 2 1

JREAD1

11 18 39

Green LED-

1

68P_0402_50V8J

2

B

+XDPWR_SDPWR_MSPWR

10 RJ45_MIDI0+

LAN_ACTIVITY#

35 LAN_ACTIVITY#

Green LED+

3

C

JRJ1

9

2

R491 75_0603_1%

2

0.1U_0402_16V4Z 2

2

0.1U_0402_16V4Z

C620

R03 modify

LAN Connector

R03 modify

R492 75_0603_1%

1

0.1U_0402_16V4Z 2 2

R493 75_0603_1%

1

C619

1

2

C618

1

D14 PJDLC05C_SOT23-3 @

2

2

C617

1

2

1

1

1

IH-160 SP050006F00

R02 modify

2

LAN_MIDI3+ LAN_MIDI3-

35 35

3

D

LAN_ACTIVITY# LAN_LINK#

LAN_MIDI3+ LAN_MIDI3-

1 2 3

Deciphered Date

2012/02/08

Title

LAN Magnetic & RJ45

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

4

3

2

Wednesday, June 08, 2011

Sheet 1

36

of

61

A

B

C

D

E

1

1

2

2

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

RTS5138 Card Reader

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

A

B

C

D

Sheet

Wednesday, June 08, 2011 E

37

of

61

A

B

C

D

E

For Wireless LAN 1 +3VS

+3VS_WLAN J6

1

60mil

2

+1.5VS

C403 4.7U_0805_10V4Z

2

1

C735 0.1U_0402_16V4Z

2

1

+3VS_WLAN

C392 4.7U_0805_10V4Z

2

1

C734 0.1U_0402_16V4Z

2

1

1

C423 0.1U_0402_16V4Z

2

C387 0.1U_0402_16V4Z

2

PAD-OPEN 4x4m @

WLAN&BT Combo module circuits

Mini Card Power Rating

1

R05 modify +1.5VS +3VS_WLAN @ R702 0_0402_5% 1 2

14 CLK_PCIE_MINI1# 14 CLK_PCIE_MINI1

14 PCIE_PRX_DTX_N2 14 PCIE_PRX_DTX_P2

14 PCIE_PTX_C_DRX_N2 14 PCIE_PTX_C_DRX_P2

+3VS_WLAN

2 0_0402_5% 2 0_0402_5%

E51TXD_P80DATA_R E51RXD_P80CLK_R

Disable

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

H

L

L

H

53

GNDGND

54

BT_CTRL BT_ON#

WL_OFF# PLT_RST_BUF#

R05 modify MINI1_SMBCLK R337 1 MINI1_SMBDATA R335 1

@ @

WL_OFF# 18 PLT_RST_BUF# 17,35,39,40,46 +3VS

2 0_0402_5% 2 0_0402_5%

D32 SUSP#

40,44,52,53 SUSP#

BT_CTRL

2

CH751H-40PT_SOD323-2 @

PCH_SMBCLK 14 PCH_SMBDATA 14 18,39

BT_ON#

USB20_N8 17 USB20_P8 17

R05 modify

1

D

Q57 2 G SSM3K7002F_SC59-3 S

MINI1_LED# 40

(9~16mA) R305 100K_0402_5%

2

1

2

1

2

R299 1 R287 1

Enable

1

3

14 MINI1_CLKREQ#

40 E51TXD_P80DATA 40 E51RXD_P80CLK

BT on module

JMINI1

1

15,35,39,46 PCH_PCIE_WAKE#

BT on module

1

+3VS_WLAN

ACES_51711-0520W-001

R300 R288 100K_0402_5% 1K_0402_5%

+3VS_WLAN

2

2

CONN@

BT_CTRL

For 3G / GPS

Reserve +3VS_FULL

To 3G Module Connect

+1.5VS

+3VS_FULL

R03 modify +3VS_FULL

1

2

C455 4.7U_0805_10V4Z @

1

2

C467 0.1U_0402_16V4Z @

1

2

C443 4.7U_0805_10V4Z @

1

2

C442 0.1U_0402_16V4Z @

1

2

C441 0.1U_0402_16V4Z @

1

2

J3G1 C466 0.1U_0402_16V4Z @

22

+1.5VS +3VS_FULL

3

+3VALW

JMINI2

14 CLK_PCIE_MINI2# 14 CLK_PCIE_MINI2

14 PCIE_PRX_DTX_N3 14 PCIE_PRX_DTX_P3

14 PCIE_PTX_C_DRX_N3 14 PCIE_PTX_C_DRX_P3

+3VS_FULL

E51TXD_P80DATA_R E51RXD_P80CLK_R

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

GND1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

GND2

54

1

The same circuit with JMINI1, but different PCIE & USB....

+3VS_MINI1

R343 1

@

WL_OFF# PLT_RST_BUF# 2 0_0603_5%

21

R334 1 R333 1

@ @

2 0_0402_5% PCH_SMBCLK 2 0_0402_5% PCH_SMBDATA

R332 1 R331 1

@ @

2 0_0402_5% USB20_N11 2 0_0402_5% USB20_P11

2 0_0402_5%

+3VALW

+3VS

USB20_N11_R USB20_P11_R @

C531 3G@ 0.1U_0402_16V4Z

R03 modify

MINI2_SMBCLK MINI2_SMBDATA

R329 1

2

GND

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

+3VALW

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

+3VS

R405 100K_0402_5% WWAN_OFF# MINI2_LED# R404 0_0402_5% USB20_N9_R1 1 3G@ 2 USB20_P9_R1 1 3G@ 2 R402 0_0402_5%

3

WWAN_OFF# 18 MINI2_LED# 40 USB20_N9 17 USB20_P9 17 USB20_N12 17 USB20_P12 17

3G_GATE

ACES_87213-2000G CONN@

Peak: 2.75A Normal: 1.1A

R03 modify USB20_N11 17 USB20_P11 17

+

MINI2_LED#

3G@ C535 220U_6.3V_M_R17

1

2

1 C527 3G@

C537 3G@ 2 10U_0603_6.3V6M

20mil +VSB

R790 47K_0402_5% 2 1 3G@

47P_0402_50V8J

(9~16mA)

44,52,53 SUSP

SUSP

1 3G@ C820 0.1U_0603_25V7K

D Q58 3G@

2 G

2

S SSM3K7002F_SC59-3

3

14 MINI2_CLKREQ#

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

1

(WLAN_BT_DATA) (WLAN_BT_CLK)

2

@ R371 0_0402_5% PCH_PCIE_WAKE# 1 2

GND

R03 modify

2

60mil

1 0_1206_5%

1

2 R352 @

1

+3VS

Close to 3G CONN

4

4

BELLW_80003-1021 CONN@

Issued Date

WWW.AliSaler.Com A

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

MINI CARD (WLAN & TV-Tuner)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

B

C

D

Sheet

Wednesday, June 08, 2011 E

38

of

61

A

B

C

D

E

USB3.0 Conn.

18,46 SMIB 15,35,38,46 PCH_PCIE_WAKE# 40,44,46,51 SYSON +1.5V +5VALW

30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

USB/B Conn.

36 35 34 33 32 31

ACES_50050-03071-001_30P

GND GND GND GND GND GND

1

30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 CONN@

29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 JUSB3

29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

+5VALW

PCIE_PTX_C_DRX_P4 14 PCIE_PTX_C_DRX_N4 14 PCIE_PRX_DTX_P4 14 PCIE_PRX_DTX_N4 14 CLK_PCIE_USB30 14 CLK_PCIE_USB30# 14 USB20_N3 17 USB20_P3 17 PLT_RST_BUF# 17,35,38,40,46 USB30_CLKREQ# 14 +3VALW

JUSB1

(Port 0,1)

R03 modify

OD output

+5VALW

17 17

USB20_N2 USB20_P2

17 17

USB20_N0 USB20_P0

1 2 3 4 5 6 7 8 9 10 11 12

SYSON#

44,46 SYSON#

1

W=100mils

USB20_N2 USB20_P2 USB20_N0 USB20_P0

1 2 3 4 5 6 7 8 9 10 11 12

GND GND

13 14

ACES_85201-1205N CONN@

2

2

BT Conn. (Port 11) 10

9

+BT_VCC

JBT1

GND 8 7 6 5 4 3 2 GND 1

8 7 6 5 4 3 2 1

USB20_P13 17 USB20_N13 17

(WLAN_BT_DATA) (WLAN_BT_CLK)

R05 modify WL_EN# 18

ACES_87213-0800G CONN@

3

3

BT Wire Cable Note: Pin 3, Pin 4 NC

+3VALW +3VS 2

C736 BT@ 0.1U_0402_16V4Z BT_ON#

BT_ON#

3

1 1

1 BT@ 2 R710 10K_0402_5%

Q41

2

2

C731 BT@ 1U_0603_10V6K

AP2301GN-HF_SOT23-3

W=40mils

1

+BT_VCC 1

C738 BT@ 0.1U_0402_16V4Z

2

1

18,38

1

C729 BT@

R709 300_0603_5% BT@

2

1

0.1U_0402_16V4Z

2

4.7U_0603_6.3V6K

C730 BT@

D

Q42 2 G SSM3K7002F_SC59-3 S

4

3

4

BT@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

USB / BT / USBB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

A

B

C

D

Sheet

Wednesday, June 08, 2011 E

39

of

61

5

4

3

2

1

+3VALW

65W/90W#

R701

2

1 100K_0402_5%

3S/4S#

R700

2

1 100K_0402_5%

TP_CLK

R363

1

2

4.7K_0402_5%

TP_DATA

R364

1

2

4.7K_0402_5%

+5VS

C431 2

18 GATEA20 18 EC_KBRST# 13 SERIRQ 13 LPC_FRAME# 13 LPC_AD3 13 LPC_AD2 13 LPC_AD1 13 LPC_AD0

10/1 ENE Recommand 1

2 47K_0402_5%

KSO1

R339

1

2 47K_0402_5%

KSO2

R682

1

2 1K_0402_5%

EC_SMI#

R359

1

2 2.2K_0402_5%

EC_SMB_DA1

1

2 2.2K_0402_5%

EC_SMB_CK1

17 CLK_PCI_LPC 17,35,38,39,46 PLT_RST_BUF# 18

R358

EC_SCI#

C

@ C462 22P_0402_50V8J 2 1

@R357 @ R357 33_0402_5% 1 2

Reserve for EMI please close to U44

41

KSI[0..7]

41

KSO[0..17]

KSI[0..7] KSO[0..17]

+3VS R360

1

2 2.2K_0402_5% EC_SMB_CK2

R361

1

2 2.2K_0402_5% EC_SMB_DA2

R685

1

2 10K_0402_5% EC_SCI#

R679 1

2 100K_0402_5%

PLT_RST_BUF#

50 50 14,22 14,22

OSC

4

1 @ C721 2

15P_0402_50V8J

@

3

2

NC

2

EC_XCLK0

NC

OSC

1

@1 C723 15P_0402_50V8J

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

15 PM_SLP_S3# 15 PM_SLP_S5# 18 EC_SMI# 35 EC_PME# 38 MINI1_LED#

B

EC_XCLK1

GATEA20 EC_KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

1 2 3 4 5 7 8 10

GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC

CLK_PCI_LPC PLT_RST_BUF# EC_RST# EC_SCI#

12 13 37 20 38

PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

77 78 79 80

SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47

PM_SLP_S3# PM_SLP_S5# EC_SMI# EC_PME# MINI1_LED#

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A

E51TXD_P80DATA E51RXD_P80CLK ON/OFF PWR_SUSP_LED# WLAN_LED#

38 E51TXD_P80DATA 38 E51RXD_P80CLK 41 ON/OFF 41 PWR_SUSP_LED# 41 WLAN_LED#

DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F

68 70 71 72

DAC_BRIG EN_DFAN1 IREF CALIBRATE#

PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F

83 84 85 86 87 88

EC_MUTE# GFX_CORE_PWRGD WWAN_LED# H_PROCHOT#_EC TP_CLK TP_DATA

SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0

97 98 99 109

65W/90W# HDA_SDO LID_SW#

SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS#

119 120 126 128

EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS#/FSEL#

CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59

73 74 89 90 91 92 93 95 121 127

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11

100 101 102 103 104 105 106 107 108

PCH_RSMRST# EC_LID_OUT# EC_ON 3S/4S# PCH_PWROK BKOFF#

PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

110 112 114 115 116 117 118

PM_SLP_S4# ENBKL EAPD VGATE SUSP# PBTN_OUT#

V18R

124

+V18R

PS2 Interface

SPI Flash ROM

GPIO SM Bus

GPI

1 100K_0402_5%

ADP_I AD_BID0

ADP_I

IMON_R

R356 2

1 0_0402_5%

KB930QF A1 LQFP 128P

DAC_BRIG 31 EN_DFAN1 43 IREF 48 CALIBRATE# 48

55

R367 0_0402_5% 2 1

VR_HOT#

VR_HOT#

H_PROCHOT# 5,50 D

S

H_PROCHOT#_EC 2 G

Q26 SSM3K7002F_SC59-3

EC_MUTE# 42 GFX_CORE_PWRGD 55 WWAN_LED# 41

C

Latest design guide suggest change QE1 to 74LVC1G06.

TP_CLK 41 TP_DATA 41

65W/90W# 48,50 HDA_SDO 13 LID_SW# 41

+3VALW

EC_SI_SPI_SO 41 EC_SO_SPI_SI 41 EC_SPICLK 41 EC_SPICS#/FSEL# 41

2 43_0402_1% FSTCHG 48 BATT_GRN_LED# 41

BATT_AMB_LED# PWR_LED SYSON VR_ON EC_ACIN

BATT_AMB_LED# 41 PWR_LED 41 SYSON 39,44,46,51 VR_ON 55

SA_PGOOD

15,22,44,45,48

LID_SW#

H_PECI

R696

1 100K_0402_5%

2

5,18 R780

C815

EC_SPICLK 1

2 @ 22_0402_5%

1

2 @ 0.01U_0402_16V7K

For EMI request PCH_RSMRST# 15 EC_LID_OUT# 14 EC_ON 41,49 3S/4S# 48 PCH_PWROK 15 BKOFF# 31

B

SA_PGOOD 52

PM_SLP_S4# 15 ENBKL EAPD 42 VGATE 15,55 SUSP# 38,44,52,53 PBTN_OUT# 15

15mil

16,22

R691 100K_0402_5%

C398 4.7U_0603_6.3V6K

R06 modify

2

20mil

For EC Tools

L23 ECAGND 2 1 FBMA-L11-160808-800LMT_0603

+3VALW

Place on RAM door

JEC1 1 2 3 4

1 2 3 4

E51RXD_P80CLK E51TXD_P80DATA

A

ACES_85205-0400 @

AD_BID0

1

1

ACIN

1 100P_0402_50V8J

2

48,50

R354 100K_0402_5%

Ra

+3VALW

1 CH751H-40PT_SOD323-2

C719

IMVP_IMON 55

EC_PECI R355 1 FSTCHG BATT_GRN_LED#

1

EC_ACIN

Analog Board ID definition, Please see page 3.

2 A

AGND

XCLK1 XCLK0

Board ID

1 10K_0402_5%

1 200K_0402_5%

2 2

D23

47,48

1 100P_0402_50V8J ECAGND BATT_TEMP 50

SPI Device Interface

11 24 35 94 113

R769 2

ACOFF C452 2

BATT_TEMP

GND GND GND GND GND

122 123

MINI2_LED# 38 BEEP# 42

ACOFF

63 64 65 66 75 76

69

1 R697

15 SUSCLK

EC_XCLK1 EC_XCLK0 2 0_0402_5%

MINI2_LED# BEEP#

BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43

DA Output

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

SUS_PWR_DN_ACK INVT_PWM FAN_SPEED1

15 SUS_PWR_DN_ACK 31 INVT_PWM 43 FAN_SPEED1

21 23 26 27

PWM Output AD

1 100K_0402_5% @

R02 modify

INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13

X1 32.768KHZ_12.5PF_Q13MC14610002

+3VALW

2

R676

+3VALW

R336

2

R362

EC_RST#

0.1U_0402_16V4Z

1

R735

EC_MUTE#

2

1 47K_0402_5%

BKOFF#

1

R328 2

+3VALW

D

+3VS @

1

VCC VCC VCC VCC VCC VCC

U20

2

C457 0.1U_0402_16V4Z

3

1

1

ECAGND

1

2

C399 1000P_0402_50V7K

2

2

C400 1000P_0402_50V7K

2

1

C720 0.1U_0402_16V4Z

CLK_PCI_LPC

2

1

C728 0.1U_0402_16V4Z

2

1

C456 0.1U_0402_16V4Z

R675 33_0402_5% 2 1

C418 0.1U_0402_16V4Z

1 D

C714 22P_0402_50V8J 2 1

L21 FBMA-L11-160808-800LMT_0603 1 2 +EC_VCCA

+3VALW_EC

67

R311 0_0805_5% 2

AVCC

1

9 22 33 96 111 125

+3VALW

R353 100K_0402_5%

Rb

1

C454 0.1U_0402_16V4Z

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

WWW.AliSaler.Com

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R20 Modify

5

Compal Electronics, Inc. EC ENE-KB930

2

2

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

40

of

61

1

2

3

4

5

6

7

8

R05 modify +3VALW C722 1 VDD SCK SI SO

8 6 5 2

EC_SPICLK_R EC_SO_SPI_SI_R EC_SI_SPI_SO_R

R698 1 R699 1 R692 1

2 0_0402_5% 2 0_0402_5% 2 0_0402_5%

ON/OFFBTN#

EC_SPICLK 40 EC_SO_SPI_SI 40 EC_SI_SPI_SO 40

R144 100K_0402_5% 1

CE# WP# HOLD# VSS

MX25L1005AMC-12G_SOP8 EC_SPICLK_R

SW1 SMT1-05-A_4P 1 3

2

JKB1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

2

@ R695

0_0402_5%

2

4

KSI[0..7]

KSO[0..17]

40

@ C727

KSO[0..17] 40

@ 40,49

33P_0402_50V8K

EC_ON

EC_ON

1 27 28

JPWR1

R05 modify +3VS 2

100P_0402_50V8J

KSO17

C262 1

2

100P_0402_50V8J

KSO15

C260 1

2

100P_0402_50V8J

KSO7

C252 1

2

100P_0402_50V8J

KSO14

C259 1

2

100P_0402_50V8J

KSO6

C251 1

2

100P_0402_50V8J

KSO13

C258 1

2

100P_0402_50V8J

KSO5

C250 1

2

100P_0402_50V8J

KSO12

C257 1

2

100P_0402_50V8J

KSO4

C249 1

2

100P_0402_50V8J

KSI0

C263 1

2

100P_0402_50V8J

KSO3

C248 1

2

100P_0402_50V8J

KSO11

C256 1

2

100P_0402_50V8J

KSI4

C267 1

2

100P_0402_50V8J

KSO10

C255 1

2

100P_0402_50V8J

KSO2

C247 1

2

100P_0402_50V8J

KSI1

C264 1

2

100P_0402_50V8J

KSO1

C246 1

2

100P_0402_50V8J

KSI2

C265 1

2

100P_0402_50V8J

KSO0

C245 1

2

100P_0402_50V8J

KSO9

C254 1

2

100P_0402_50V8J

KSI5

C268 1

2

100P_0402_50V8J

KSI3

C266 1

2

100P_0402_50V8J

KSI6

C269 1

2

100P_0402_50V8J

KSO8

C253 1

2

100P_0402_50V8J

KSI7

C270 1

2

100P_0402_50V8J

U8

P 4

1

5

R496 10K_0402_5%

B

2

CR_5IN1_LED# 35

A

1

PCH_SATALED# 13

Y G

MEDIA_LED#

3

LED7 HT-191NB5_BLUE

1 2 R380 330_0402_5%

2

1

B

MEDIA_LED#

R05 modify

2

B

LED8 3G@ HT-191NB5_BLUE

R05 modify 1 2 R381 150_0402_5%

2

B

1

WWAN_LED#

1

WLAN_LED#

WWAN_LED# 40

3G@

1

1 C217

C

C216

2 2 100P_0402_50V8J 100P_0402_50V8J

TP_CLK

LEFT_BTN#

TP_DATA

RIGHT_BTN#

LED4

A

+5VS

HT-191UD5_AMBER

1 PWR_SUSP_LED#

1

R05 modify

PWR_SUSP_LED# 40

HT-191UD5_AMBER

+3VALW

1 R379

LED6 2 2 200_0402_5%

D4 PJDLC05C_SOT23-3

3

A

WLAN_LED# 40

D3 PJDLC05C_SOT23-3

C196 0.1U_0402_16V4Z

2

B

BATT_GRN_LED#

1

BATT_GRN_LED# 40

1

1

2 2 560_0402_5%

2

B

1 R377

+3VS

PWR_LED#

2

LED5

HT-191NB5_BLUE LED1 2 2 560_0402_5%

TP_CLK 40 TP_DATA 40

1

2 2 200_0402_5%

TP Conn.

+5VS

1 1 2 2 3 3 LEFT_BTN# 4 4 RIGHT_BTN# 5 5 6 6 7 GND 8 GND JTP1 CONN@ ACES_85201-0605N

1

C

R05 modify

B

+3VS

PWR_LED# ON/OFFBTN#

ACES_85201-0805N CONN@

LED3 HT-191NB5_BLUE

+3VS

+3VALW LID_SW# 40

LID_SW#

MC74VHC1G08DFT2G_SC70-5

R05 modify +3VS

1 2 3 4 5 6 7 8 9 10

1 2 3 4 5 6 7 8 GND GND

EMI request

2

1 R378

Q7 SSM3K7002F_SC59-3

PWR/B G1 G2

R03 modify

+3VALW

S

KB Conn.

C261 1

1 R374

47

A

10K_0402_5%

B

+3VALW

D

2 G

R104

ACES_85201-26051 CONN@

EC Request

51ON#

51ON#

3

+3VS

KSO16

40

D6 CHN202UPT_SC70-3

2

KSI[0..7]

ON/OFF

1

6 5

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

1

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

3

A

1

1 3 7 4

3

EC_SPICS#/FSEL# 2 4.7K_0402_5% SPI_WP# 2 4.7K_0402_5% SPI_HOLD#

R694 1 R690 1

+3VALW

2

U38 40 EC_SPICS#/FSEL#

+3VALW

ON/OFF BTN

2 0.1U_0402_16V4Z

HT-191NB5_BLUE LEFT_BTN#

SW2 SMT1-05-A_4P 1

BATT_AMB_LED#

1

BATT_AMB_LED# 40

4

2

S

SW3 SMT1-05-A_4P 1

4

2

SSM3K7002F_SC59-3 D

1

R512 100K_0402_5%

A

HT-191UD5_AMBER Q32

2 G 3

PWR_LED 2

40 D

2 2 560_0402_5%

3

5 6

1

1 R376 D

RIGHT_BTN#

5 6

3

LED2 PWR_LED#

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

BIOS, I/O Port & K/B Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

1

2

3

4

5

6

Wednesday, June 08, 2011

7

Sheet

41 8

of

61

5

+VDDA

D30 CH751H-40PT_SOD323-2

(output = 300 mA)

R725

+PVDD_HDA C759 1

BEEP#

2

2

1U_0402_6.3V6K 13

R713 0_0603_5%

C771 1

PCH_SPKR

2

1U_0402_6.3V6K

1

1

2 1U_0402_6.3V6K

D2 PJDLC05C_SOT23-3

2

2 B

R724

1 1U_0402_6.3V6K

1 R729

Q44 E

SPKL+ SPKL-

R8 R7

JSPK2

20mil

2 0_0603_5% 2 0_0603_5%

1 1

SPK_L+ SPK_L-

1

D1 PJDLC05C_SOT23-3

0.1U_0402_16V4Z 1 C749

+PVDD1_HDA

2

+AVDD_HDA

C752

2 0.1U_0402_16V4Z 9

MIC2_R

SPK_OUT_L-

41

SPKL-

23

LINE1_L

SPK_OUT_R+

45

SPKR+

24

LINE1_R SPK_OUT_R-

44

SPKR-

HPOUT_L

32

HP_LEFT

HPOUT_R

33

CBN CBP

29

MIC2_VREFO

SDATA_IN

8

SDATA_OUT

5

SINGA_2SJ2326-001111

1 Q43 BSS138_NL_SOT23-3 S

HDA_SDIN0_AUDIO 1 R721 2 33_0402_5% HDA_SDOUT_AUDIO

RESET#

11

HDA_SYNC_AUDIO

10U_0805_10V4Z

13

1 22K_0402_5%

HP_PLUG#

R720

R03 modify

2

6

HDA_BITCLK_AUDIO

D26 CH751H-40PT_SOD323-2

13

@ @ 1 2 1 R717 0_0402_5%

LDD_CAP

19

13

GPIO0/DMIC_DATA

2

GPIO1/DMIC_CLK

3

PD#

4

JDREF

2 C757 22P_0402_50V8J

For EMI

MIC1_L R707

EC_MUTE# 40

MIC1_R R706

SENSE_A SENSE_B 2 2 20K_0402_1% 0_0402_5%

34

PCBEEP

12

MONO_OUT AVSS2

20 37

CPVEE

10mil

13 18 47

SENSE A SENSE B EAPD

48

SPDIFO

7

DVSS

49

GND

VREF

27

AVSS1 PVSS2 PVSS1

26 43 42

R705 4.7K_0402_5% FBMA-L11-160808-800LMT_0603 L45 2 MIC1_L_1 1 2 1K_0603_5% L44 2 MIC1_R_1 1 2 1K_0603_5% FBMA-L11-160808-800LMT_0603

1 1

220P_0402_50V7K CODEC_VREF C767 1 C768 1

10mil

1 2

MIC1_R_R

3

@

2 0.1U_0402_16V4Z 2 10U_0805_10V4Z

1

1

2

2

MIC_PLUG# C733

5

220P_0402_50V7K D25 PJDLC05C_SOT23-3

6 SINGA_2SJ-A960-C01 CONN@

Place next pin27

R03 modify +INTMIC_VREFO

1

SM010004010 300ma 70ohm@100mhz DCR 0.3 R394 10K_0402_5%

15mil 2

3

2

INT_MIC_L

D16

1

@ A

PJDLC05C_SOT23-3

4

JMIC1 MIC1_L_R

4 C732

AGND

GND

MIC JACK

R708 4.7K_0402_5%

MONO_IN

ALC271X-GR_QFN48_7X7

DGND

WWW.AliSaler.Com

D27 CH751H-40PT_SOD323-2

1

1

2 2.2U_0402_6.3V6M

D28 PJDLC05C_SOT23-3

B

C758

5

+MIC1_VREFO

R791 22K_0402_5%

HDA_RST_AUDIO# 13

MIC1_VREFO_L

28

1 20K_0402_1%

10

BCLK

31

10mil

2 10U_0805_10V4Z

R730 2

1 R7181 R715

MIC_PLUG#

COM_MIC

2

C760 1

EAPD

C746

HDA_SDIN0 13

2

1

+MIC1_VREFO +INTMIC_VREFO

SYNC

MIC1_VREFO_R

10mil

External MIC

40

1

2

HP_RIGHT

2 G

1

10mil 30

B

2 1 R731 39.2K_0402_1% MIC_PLUG# 2 1 R727 20K_0402_1% MIC2JD

R722 2.2K_0402_5% D

1

+MIC2_VREFO

Internal MIC

HP_PLUG#

CONN@

1

Combo MIC

5

3

MIC1_R

36

2 4

+MIC2_VREFO

MIC2JD

MIC1_L

C

1

1

1 DVDD

DVDD_IO

46 PVDD2

38

39 PVDD1

SPK_OUT_L+

MIC2_L

2

2

C755 2.2U_0402_6.3V6M

SPKL+

17

35

1

35mA

16

22

3 6

3

C762 1

COM_MIC

HP_PLUG#

40

21

Headphone Out JHP1

C747

2

MIC1_C_L 4.7U_0603_6.3V6K MIC1_C_R 2 4.7U_0603_6.3V6K

2

2

2

C763 1

68mA 600mA

2 75_0603_5%

2

MIC1_R

C764 1

LINE2_R

HP_RIGHT R714 1

2

MIC1_L

External MIC

C765 1

LINE2_L

15

2 75_0603_5%

1

1 COM_MIC_R 1K_0402_5%

2 R719

14

HP_LEFT R716 1

2

330P_0402_50V7K 330P_0402_50V7K 1 1 FBMA-L11-160808-800LMT_0603 L49 HPOUT_L_1 HPOUT_L_2 1 2 L47 HPOUT_R_1 1 HPOUT_R_2 2 FBMA-L11-160808-800LMT_0603

1

COM_MIC

C769 1

C751

3

Combo MIC

INT_MIC 1 1K_0402_5%

2 R726

25

U41

LINE2_C_L 4.7U_0603_6.3V6K LINE2_C_R 2 4.7U_0603_6.3V6K MIC2_C_L 2 4.7U_0603_6.3V6K MIC2_C_R 2 4.7U_0603_6.3V6K

2

AVDD2

Internal MIC INT_MIC_R

+3VS

1 C753

Place near Pin1, 9

Place near Pin25, 38 C770 1

1 C761

0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z

AVDD1

2

L48 2 1 BLM18AG121SN1D_0603

10U_0603_6.3V6M

1 C754

1

C772

2

+3VS_DVDD

10mil

0.1U_0402_16V4Z 1 1

C756 10U_0805_10V4Z

C

Singatron 2SJ2326 DC021007151

SM010030010 200ma 120ohm@100mhz DCR 0.2

10mil

2

2

SM010030010 200ma 120ohm@100mhz DCR 0.2 L51 2 1 BLM18AG121SN1D_0603

G1 G2

HD Audio Codec

20mil

Place near Pin39

+VDDA

1 2

3 4

1

1

C750 10U_0805_10V4Z

1 2

ACES_88266-02001 CONN@

2

SM010014520 3000ma 220ohm@100mhz DCR 0.04 L50 2 1 FBMA-L11-201209-221LMA30T_0805

D

2 2.4K_0402_1%

2SC2411K_SOT23-3

D29 CH751H-40PT_SOD323-2

Place near Pin46

+VDDA

G1 G2

MONO_IN

2

2

560_0402_5%

1 2

3 4

ACES_88266-02001 CONN@

C

R723

560_0402_5%

3

40

1

1 2

1

20mil

SPK_R+ SPK_R-

C766

2 1

+PVDD_HDA

L46 2 0.1U_0402_16V4Z 1 FBMA-L11-201209-221LMA30T_0805 1 1 @ C748 C745 10U_0805_10V4Z 2 2 @

C739

2

2

SM010014520 3000ma 220ohm@100mhz DCR 0.04

JSPK1

20mil

2 0_0603_5% 2 0_0603_5%

1 1

R728 10K_0402_5%

10K_0402_5%

D

+VDDA

SPKR+ R46 SPKR- R47

3

R712 10K_0402_5%

+3VS

3

4.75V

2

GND

1 2 SHDN BYP 4 C741 G9191-475T1U_SOT23-5 0.01U_0402_16V7K @ @

1

5

1

OUT

2

3

2

Int. Speaker Conn.

40mil

IN

2

2

1

1

1

+VDDA

U40

1

0.1U_0402_16V4Z

2

2 0_0805_5%

60mil 1 C737

3

1

1 R711

+5VS

4

PJ2 @ JUMP_43X39 1 1 2 2

PJ3 @ JUMP_43X39 1 1 2 2

PJ4 @ JUMP_43X39 1 1 2 2

PJ5 @ JUMP_43X39 1 1 2 2

PJ6 @ JUMP_43X39 1 1 2 2

GNDA

GND

2

Issued Date

GNDA

2011/02/08

JMIC2 1 2

1 2

3 4

G1 G2

C500 220P_0402_50V7K

A

ACES_88266-02001 CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Int. MIC

15mil

L24 1 2 INT_MIC_L FBMA-L11-160808-800LMT_0603

1

PJ1 @ JUMP_43X39 1 1 2 2

INT_MIC_R

For EMI

Deciphered Date

2012/02/08

Title

HD Audio Codec ALC271X

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

3

2

Wednesday, June 08, 2011

Sheet 1

42

of

61

H19 H_4P0

1

1 @

H16 H_3P0 @

@

H17 H_3P0 @

H18 H_3P0 @

1

@

H15 H_3P0

@

1

@

H14 H_3P0

H7 H_3P4

1

@

H13 H_3P0

1

@

H12 H_3P0

@

1

1

H11 H_3P0

@

H6 H_3P4

@

H20 H_4P0 @

1

1

FAN1 Conn

@

@

H5 H_3P4

1

1

1

@

H10 H_3P0

H4 H_3P4

1

H9 H_3P0

1

H8 H_3P0

@

1

@

JUSB3 Stand-Off

H3 H_3P4

1

H2 H_3P4

1

1

H1 H_3P4

1

FAN Stand-Off

@

+5VS 10U_0805_10V4Z 2

@

H23 H_4P2 @

H24 H_4P2 @

1

H22 H_4P2

@

APL5607KI-TRG_SO8

+3VS

H25 H_7P0N

C587 1000P_0402_50V7K 1 2

H26 H_3P0N

@

H27 H_3P5X3P0N

@

1

C585 10U_0805_10V4Z 1 2

1

C598 0.1U_0402_16V4Z

1

1

@

R489 10K_0402_5%

40mil FAN_SPEED1 1

C579 1000P_0402_50V7K

JFAN1 1 2 3 ACES_85205-03001 CONN@

2

FD3 @

FIDUCIAL_C40M80

@

FIDUCIAL_C40M80

FD4 @

FIDUCIAL_C40M80

@

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification Issued Date

FD2

1

FD1

1

40

+VCC_FAN1

1

2

1

+VCC_FAN1 1 300_0402_5%

1

2 R509

H21 H_4P2

8 7 6 5

1

EN_DFAN1

GND GND GND GND

2

40

EN VIN VOUT VSET

1

U30 1 2 3 4

1

C580 1

2011/02/08

Deciphered Date

2012/02/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FAN & Screw Hole Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

Wednesday, June 08, 2011

Sheet

43

of

61

B

C

D

E

+5VALW

+5VALW TO +5VS

+1.5V

2

SUSP

1

6

SUSP

Q27A DMN66D0LDW-7_SOT363-6

2

38,40,52,53 SUSP#

4

ACIN

15,22,40,45,48 ACIN

1

4

2

5

Q15B DMN66D0LDW-7_SOT363-6

D

3

SUSP

2

1

@

3

Q19A DMN66D0LDW-7_SOT363-6

Q15A DMN66D0LDW-7_SOT363-6

1.5VS_GATE

S

2 G

2

R251 10K_0402_5%

SUSP

C380 0.1U_0603_25V7K

2

10mil

1

2 1 R269 200K_0402_5%

1

20mil

1

1

2

38,52,53

R245 470_0603_5% 1

1

6

2 4

2 1 6 1

3

2

1

C338 1U_0603_10V6K

C470 0.1U_0603_25V7K

1

C339 4.7U_0805_10V4Z

2

SUSP

2

5

Q19B DMN66D0LDW-7_SOT363-6

2

1

+VSB

5VS_GATE 1

2

1

1 2 3

R268 510K_0402_5%

SUSP

R382 470_0603_5%

1

R246 100K_0402_5%

8 7 6 5

C376 0.1U_0402_16V4Z

2 1 R372 20K_0402_1%

+VSB

@

C377 0.1U_0402_16V4Z

10mil

2

C469 1U_0603_10V6K

@

1

C374 4.7U_0805_10V4Z

2

1

C468 4.7U_0805_10V4Z

20mil

2

C464 10U_0805_10V4Z

2

1

C465 4.7U_0805_10V4Z

1

+5VS C375 10U_0805_10V4Z

1

U22 DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5 4

For Cost Down 2/21

+1.5VS U12 AO4430L_SO8

For Cost Down 2/21

+5VALW

2

+1.5V to +1.5VS

1

A

2

Q21 @ SSM3K7002F_SC59-3

+5VALW 2

2

2

1

R383 100K_0402_5%

+3VALW TO +3VS

39,46 SYSON#

+3VALW

3 3

3

C463 0.1U_0603_25V7K

DMN66D0LDW-7_SOT363-6

R373 100K_0402_5%

1

2

SUSP

Q25A DMN66D0LDW-7_SOT363-6

2

40mil

1

4

1

2

2

2

5

2

5

Q25B DMN66D0LDW-7_SOT363-6

+3VALW_PCH

R614

0_0805_5%

3VS_GATE 1

+3VALW

6 1

4

10mil

2

SYSON

3

4

SUSP

Q27B 39,40,46,51 SYSON

R369 470_0603_5%

C701 10U_0805_10V4Z

R368 47K_0402_5% 2 1

2

1

C458 1U_0603_10V6K

+VSB

2

@

+3VALW TO +3VALW_PCH(PCH AUX Power) 1

C461 4.7U_0805_10V4Z

20mil

1

C459 10U_0805_10V4Z

2

C460 4.7U_0805_10V4Z

1

+3VS U21 DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5

1

For Cost Down 2/21

+5VALW TO +5VALW_PCH(PCH AUX Power)

+5VALW

+5VALW_PCH R197 1

2 0_0603_5%

2 Q34 2 SUSP G SSM3K7002F_SC59-3

S

1 1

D

@ R365 470_0603_5%

D

S

3

S

Q5 SUSP 2 G SSM3K7002F_SC59-3

1 1

D

+1.5V

R508 470_0603_5%

3

3

S

Q23 SUSP 2 G SSM3K7002F_SC59-3

1 1

D

R29 470_0603_5%

3

4

1 2

R366 22_0603_5%

+1.8VS 2

2

+1.05VS_VTT

1

+0.75VS

4

Q24 @ SYSON# 2 G SSM3K7002F_SC59-3

Issued Date

WWW.AliSaler.Com A

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DC Interface Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

B

C

D

Sheet

Wednesday, June 08, 2011 E

44

of

61

A

B

C

D

E

+1.8VS to +1.8VSDGPU for GPU +1.05VS_VTT to +1.05VSDGPU for GPU R03 modify

10mil

R406 470_0603_5% DIS@

2 1

G +1.8VS_GATE

3

1

VGA_ON#

DIS@ Q29A DMN66D0LDW-7_SOT363-6

2

S

S TR DMN3033LDM-7 1N TSOP6

300mA

0.1U_0603_25V7K DISO@

VGA_ON#

Q9A DISO@

2

1

S SSM3K7002F_SC59-3 @

C194

1

R132

DMN66D0LDW-7_SOT363-6

D Q30

2 G

+1.8VSDGPU

DISO@ C198

1

2

C530 DIS@ 0.1U_0603_25V7K

3

VGA_ON#

DISO@ 2 10U_0805_10V4Z

DISO@ 470_0603_5%

Q9B DISO@

5

R140 2 0_0402_5%

14,17 DGPU_PWR_EN

DMN66D0LDW-7_SOT363-6 4

ACIN

15,22,40,44,48 ACIN

1 2

5

DIS@ Q29B DMN66D0LDW-7_SOT363-6

4

VGA_ON#

R410 510K_0402_5%

3

DIS@ 1

D Q10

R136 2 1 510K_0402_5% DISO@

+VSB

1.05VSDGPU_GATE @

1 2 5 6

2 DIS@

2

2

+VSB

2

3 1

DIS@ R409 510K_0402_5% 2 1

C825 DIS@ 220U_B2_2.5VM_R35

4

2

For Cost Down 2/21 20mil

1

C499 1U_0603_10V6K

+

DIS@

1

C498 4.7U_0805_10V4Z

2 DIS@

4A 1

1

6

1 2 3

6 1

1 C513 4.7U_0805_10V4Z

+1.8VS

+1.05VSDGPU

4

1

+1.05VS_VTT U25 AO4430L_SO8 8 7 6 5

DIS@

VGA_ON

1

2

2

2

+5VALW

DIS@ R134 100K_0402_5%

D

S

2 G

R03 modify

+

1 2

1

4

DIS@ C603 0.1U_0603_25V7K

AP2301GN-HF_SOT23-3 3VSdelay_gate

2

DIS@ R511 470_0603_5%

1

2

DIS@

C590 4.7U_0805_10V4Z

DIS@

R519 1K_0402_5%

DIS@ DMN66D0LDW-7_SOT363-6 Q35B

5

100mil(1.5A) 3

DIS@ R515 100K_0402_5%

DIS@ R514 1K_0402_5% 1 2

+1.5VSDGPUH

1

Q33

DIS@

1

VGA_ON

3

1

2VGA_ON# Q3A GV@ DMN66D0LDW-7_SOT363-6

2

DIS@

2

1

C602 4.7U_0805_10V4Z

1

1

+3VSDGPU

1

+3VALW

Q4 SSM3K7002F_SC59-3 @

Q8 SSM3K7002F_SC59-3 S DIS@

2

2 2

R05 modify

6 1

2

+ GV@

D

2 G

DIS@ Q35A DMN66D0LDW-7_SOT363-6 23VSdelay_gate

1 DIS@ C612 0.1U_0603_25V7K

1

ACIN

4

GV@ Q3B DMN66D0LDW-7_SOT363-6

2

5

C29 GV@ 0.1U_0603_25V7K

+ DIS@

3

@ VGA_ON#

1

1

2

1.5VSDGPU_GATE R28 510K_0402_5%

For Cost Down 2/21

2 1 R27 510K_0402_5% GV@

3

+VSB

3

VGA_ON R135 DIS@ 22K_0402_5%

+3VS

For Cost Down 2/21 R26 470_0603_5% GV@

C826 220U_B2_2.5VM_R35

10mil

2

DIS@

6

2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z

GV@

2

1

1

C7

DIS@

C514 330U_2.5V_M_R15

2 4.7U_0805_10V4Z

C819

1

2

C818

R03 modify 1 2 3

4

2

1

C823 1 0.1U_0402_10V7K GV@

+3VS to +3VSDGPU for GPU C12 1U_0603_10V6K

2

20mil

1

1

+1.5VSDGPU

C13 10U_0805_10V4Z

C824 1U_0402_6.3V6K

1

3

R03 modify

+1.5VSDGPUH U2 AO4430L_SO8 8 7 6 5 1 1 GV@ GV@

51,54

1

+1.5VSDGPUH to +1.5VSDGPU for GPU

3

VGA_ON#

54 VGA_ON#

1

2009/08/17 add VGA_ON#

2

2

GV@ PJ28 2 2 1 1

ME interefer,not pop!!

C817 220U_B2_2.5VM_R35 2 @

JUMP_43X118 +1.5V

R03 modify

GV@ PJ27 2 2 1 1 JUMP_43X118 C821 1U_0402_6.3V6K

+1.5VSDGPUH 1

1

2

2

C822 0.1U_0402_10V7K

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DC Interface Rev

JE50-HR/SJV50-HR M/B Schematics E

Date:

A

B

C

D

Sheet

Wednesday, June 08, 2011 E

45

of

61

4

3

+3V_USB3.0

C696

C368

C717

C718

C695

C389

C366

C367

1

1

1

1

1

1

1

1

1

1

1

1

1

1

U3TXDP2_L 3

2

2

2

2

2

2

2

2

2

2

2

2

2

2

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.1U_0402_10V7K

0.01U_0402_16V7K

0.1U_0402_10V7K

2

2

0.1U_0402_10V7K

2

USB30@ USB30@ USB30@

+1.05V_USB3.0

+1.05VR

+3V_USB3.0 SMI SMI#

USB30_CLKREQ#_L R603 1 USB30@2 10K_0402_5% @ R604 1 2 100_0402_1% R602 1 USB30@2 10K_0402_5% R605 1 USB30@2 0_0402_5% SMI_R R600 1 @ 2 0_0402_5% SMIB_R

R611 1 USB30@2 10K_0402_5%

+3V_USB3.0

1

USB30@ 2

C702 1U_0603_10V6K

1 2 D21 1 2 1SS355TE-17_SOD323-2

PERXP PERXN

H2 K1 K2

PERSTB PEWAKEB PECREQB

J2 J1 H1 P4

AUXDET PSEL SMI SMIB

SPI_CLK_USB_R SPI_CS_USB# USB_SO_SPI_SI USB_SI_SPI_SO

M2 N2 N1 M1

USB30@

2

2

D7

H11 K11 K12 L8 VDD10 VDD10 VDD10 VDD10

H3 H4 L5 VDD10 VDD10 VDD10

E11 E12 VDD10 VDD10

E3 E4 VDD10 VDD10

C8 C9 D8 D9 VDD10 VDD10 VDD10 VDD10

C4 C5 C6 C7 D5 VDD10 VDD10 VDD10 VDD10 VDD10

N4 N5 N6 P3 VDD33 VDD33 VDD33 VDD33

L13 L14 VDD33 VDD33

L9 L10

P13

A6 N8

U3TX_C_DN21 U2DN2_L

U2DP2 U3RXDP2

P8 B8

U2DP2_L U3RXDP2_L

U3RXDN2

A8

U3RXDN2_L

OCI2B OCI1B

@ R703 47K_0402_5%

33P_0402_50V8K

USB3_XT1 USB3_XT2 1

+3V_USB3.0 R665 100_0402_1% 2

USB30@ Y5 1

2

Place as close as possibile to U3.N14 and U3.M14

24MHZ_12PF_X5H024000DC1H USB30@ 1 1 C709 12P_0402_50V8J USB30@ 2 2

H14 J14

U3TXDP1

B10

U3TXDN1 U2DM1

A10 N10

U2DP1 U3RXDP1

P10 B12

U3RXDN1

A12

RREF U2AVSS

P12 N12

U2PVSS

N11

U3AVSS

D6

A

Pin compare table for support USB remote wakeup or not

Support USB remote wakeup

AUXDET(Pin J2)

CSEL(Pin P6)

CLK

pull high 10k to VDD33

Tied to GND

Must use 24MHz crystal: mount Y1,R19,C40,C41

WWW.AliSaler.Com Not support USB remote wakeup

Tied to GND 5

pull high to VDD33

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

C707 12P_0402_50V8J USB30@

5

3

I/O2

4

2 U3TXDN2_L USB30@ C7060.1U_0402_10V7K

U3TXDP2

1

10

U3TXDP2

U3TXDN2

2

9

U3TXDN2

U3RXDP2

4

7

U3RXDP2

U3RXDN2

5

6

U3RXDN2

+3V_USB3.0

I/O3

+USB3_VCCA U2DP2

+USB3_VCCA

1 +

3

+5VALW

2

USB30@ RCLAMP0524P.TCT~D

2

1

+USB3_VCCA

C432 0.1U_0402_10V7K 1 2

R03 modify 1 USB30@2 1 USB30@2 1 USB30@2 1 USB30@2

U17 1 2 3 4

39,44 SYSON#

W=60mils

GND VIN VIN EN

R786 0_0402_5% R787 0_0402_5% R788 0_0402_5% R789 0_0402_5%

R298 1.6K_0402_1% 1 2 USB30@

UPD720200AF1-DAP-A_FBGA176~D USB30@

8 7 6 5

VOUT VOUT VOUT FLG

1 @ 2 OCI2B 0_0402_5% R313

AP2301MPG-13_MSOP8

USB20@ R314 2 0_0402_5%

1 1 17

1 @ R687 L52 2 2

USB20_N1

U2DN2 2 0_0402_5% USB20@ 1 1

2

USB_OC1# 17

C417 @ 0.1U_0402_16V4Z

R03 modify 3

3

4

4

WCM-2012-900T_0805 U2DP2 1 @ 2 R686 0_0402_5%

USB20_P1

R06 modify

P14 P11 P9 P7 P2 P1 N13 N9 N7 N3 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 L12 L11 L7 L6

B

0_0402_5% R806 USB30@ 2 1

SMIB

18,39

SMI

Q59B DMN66D0LDW-7_SOT363-6 USB30@

5

+3V_USB3.0

R03 modify +USB3_VCCA

@R807 @ R807 10K_0402_5%

JUSB5 U2DN2 U2DP2

1 2 3 4 5 6 7 8

VCC DD+ GND

SMI#

1

6 Q59A DMN66D0LDW-7_SOT363-6 USB30@

GND1 GND2 GND3 GND4 SUYIN_020173GB004M25MZL CONN@

USB2.0 Conn A

PN: SP060004B00

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

USB3.0 PD720200

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Can use either 48MHz or 24MHz When use 48MHz clock: mount R22,R25

Date:

4

3

C

2

2 1

@

6

REF1 REF2

PJUSB208H_SOT23-6 @

CSEL

A1 A2 A3 A4 A5 A7 A9 A11 A13 A14 B3 B4 B5 B7 B9 B11 B13 B14 C1 C2 C3 C10 C11

I/O4

2

C12 C13 D3 D4 D11 D12 D13 D14 E1 E2 E13 E14 F4 F6 F7 F8 F9 F11 F12 G1 G2 G6 G7 G8 G9 G11 G12 G13 H6 H7 H8 H9 H12 J3 J4 J6 J7 J8 J9 J11 J12 K3 K4 L1 L2 L3 L4

EMI Request

USB30@

2

SPI_CS_USB# USB_SI_SPI_SO

MX25L5121EMC-20G_SO8 USB30@

R802 0_0402_5% @

1

1 2 3 4

1

2

CS# SO WP# GND

I/O1

D34

Resister overlap with L52

R634 0_0402_5%

SPI_CLK_USB USB_SO_SPI_SI

VCC NC SCLK SI

1

R03 modify

XT1 XT2

P6

R628 0_0402_5%

8 7 6 5

U2DN2

G14 OCI2B R307 1 USB30@2 10K_0402_5% H13 OCI1B R308 1 2 10K_0402_5% USB30@

PPON2 PPON1

U39

@ C827

U2AVDD10

B6

17 C725 R704 0.1U_0402_10V7K 10K_0402_5% USB30@ USB30@

D24

4

2

N14 M14

For USB2.0 ESD request

2 0_0402_5%

For ESD request

U3TXDP2

D

2 0_0402_5%

4U3RXDP2

1

1

1

B

USB3_XT1 USB3_XT2

R657 1 @

+3V_USB3.0L22 +3VA_USB3.0 EMI Request BLM18AG601SN1D_2P 1 2 USB30@ 1 C422 10U_0805_10V4Z USB30@ 2

U3TXDN2 U2DM2

GND

+3V_USB3.0 +3V_USB3.0

R683 1 @

R05 modify

GND GND GND

C14

USB30@ U3RXDN2 1 1 4

4U2DN2

4

8

As short as possible SPI_CLK_USB_R

3

3

WCM-2012-900T_0805

OCE2012120YZF_0805

C7050.1U_0402_10V7K USB30@ U3TX_C_DP21 2 U3TXDP2_L

Can be attach to EC, either.

SPISCK SPISCB SPISI SPISO

K13 K14 J13

EMI Request

SPEC Max:+3V---200mA;+1.05V---800mA Idle mode:0.489W: +3V---43mA;+1.05V---328mA D3 mode:0.066W: +3V---5.4mA;+1.05V---45mA

PCI Express/ExpressCard select signal 1:others 0:Express Card or Mini card PONRSTB

P5

3

3

C391 470P_0402_50V7K

14 USB30_CLKREQ#_L +3V_USB3.0

R803 33_0402_5% SPI_CLK_USB 1 2 USB30@

PETXP PETXN

2

USB30@ USB30@ USB30@ USB30@ USB30@ U3RXDP2_L

U2DN2_L

USB30@ U2DP2 1 1

C390 220U_6.3V_M

R606 1 USB30@2 0_0402_5% R601 1 USB30@2 0_0402_5%

17,35,38,39,40 PLT_RST_BUF# 15,35,38,39 PCH_PCIE_WAKE#

OD output

D2 D1 F2 F1

14 PCIE_PTX_C_DRX_P5 14 PCIE_PTX_C_DRX_N5

C

PECLKP PECLKN

2

2

2 0_0402_5%

L41 U3RXDN2_L

2 0_0402_5%

L43 2

2

14 PCIE_PRX_DTX_P5 14 PCIE_PRX_DTX_N5

B2 B1

U3AVDO33

14 CLK_PCIE_USB30_L 14 CLK_PCIE_USB30_L# USB30@ C699 1 2 0.1U_0402_10V7KPCIE_PRX_C_DTX_P5 C698 1 2 0.1U_0402_10V7KPCIE_PRX_C_DTX_N5 USB30@

VDD33 VDD33

GND RT9701-PB_SOT23-5 USB30@

VDD33 VDD33 VDD33

D10 F13 F14 VDD33 VDD33 VDD33

2

1 5

F3 G3 G4

U34 SYSON

39,40,44,51 SYSON

VIN VOUT VIN/CE VOUT

R680 1 @ U2DP2_L

2 0_0402_5%

R658 1 @

+3VA_USB3.0

+3V_USB3.0

U19 3 4

4U3TXDP2

4

3

+3VALW

+3V_USB3.0

For EMI request

1

+3VALW to +3V Transfer

3

R659 1 @

7K for customer request, can use other kind of capacitor, like Y5V.

R310 0_0805_5% 1 2

2

USB30@ U3TXDN2 1 1

OCE2012120YZF_0805 0.01U_0402_16V7K

1

C396

1 @

0.1U_0402_10V7K

2

C715

2

1

0.01U_0402_16V7K

GND

C716

2

1

0.01U_0402_16V7K

1

C369

2

USB30@ 1

2 0_0402_5%

L42 U3TXDN2_L 2

0.01U_0402_16V7K

Vout=0.8(1+10K/32.4K) 1.042 ~ 1.0469 ~ 1.0519V Spec: 0.9975 ~ 1.05 ~ 1.1025

2

@

R660 1 @

R02 modify

USB30@ USB30@ USB30@ USB30@

C370

APL5930KAI-TRG_SO8 USB30@

D

USB30@ 1

USB30@ USB30@

0.01U_0402_16V7K

1 R325 2 10K_0402_5% 1 USB30@ R326 32.4K_0402_1% 2 USB30@

2

1

C405 8P_0402_50V8D

FB

USB30@ 1

C379 0.01U_0402_16V7K

EN POK

USB30@

3 4

C406 0.1U_0402_10V7K

USB30@ USB30@

VOUT VOUT

C419 10U_0603_6.3V6M

SYSON 8 7 2 1 R327 5.1K_0402_1% USB30@

C386 8P_0402_50V8D

VCNTL VIN VIN

+1.05VR

USB30@

+3VA_USB3.0

C382 0.01U_0402_16V7K

6 5 9

+5VALW

+3VA_USB3.0

C397 0.1U_0402_10V7K

2

+1.5V

Close to U3.P13

C401

1

Close to U3.D7 +1.05V_USB3.0

U18

C697

+5VALW

C402 10U_0603_6.3V6M

2

C420 1U_0603_10V6K

1

+1.5V

1

EPAD

+1.5V to +1.05V Transfer +5VALW

2

9

5

2

Rev E Sheet

Wednesday, June 08, 2011 1

46

of

61

5

4

@ PJP1 ACES_50305-00441-001

3

VIN

PL1 SMB3025500YA_2P 1 2

1 2 3 4 GND GND

2

2

+3VALWP

@

PJ7

2

1

1

1

+3VALW

2

PC2 100P_0402_50V8J

1 PC3 100P_0402_50V8J

2

1

1 PC1 1000P_0402_50V7K

2

2

1

JUMP_43X118

PC4 1000P_0402_50V7K 2

+5VALWP

D

@

PJ9

2

1

@ 1

+5VALW

+VCCSAP

2

JUMP_43X118 @ 1

2

PJ10 1

+VCCSA

1

D

JUMP_43X118

PJ30

1

2

2

3

2

JUMP_43X39 @ PD9 PJSOT24CH_SOT23-3

@ +1.8VSP

2

1

VIN 2

1

PD2 LL4148_LL34-2 2 1

@ 1

1

2

2 41

1

51ON#

+1.8VS

1

2

PJ14 1

1

@

VS

+1.5VP

2

2

PR2 68_1206_5%

2

PJ15 1

@ +1.5V

1

1

+VSBP

JUMP_43X118

1

PJ16 2

2

+VSB

JUMP_43X39

1 @ PC6 0.1U_0603_25V7K

2

2

1

3

1

JUMP_43X118

2

1 PR3 100K_0402_5%

C

PC5 0.22U_0603_25V7K 2 1

N1

2

PR1 68_1206_5% PQ1 TP0610K-T1-E3_SOT23-3

PJ12

JUMP_43X118

PD1 LL4148_LL34-2

BATT+

2

+1.05VS_VCCPP

2

2

PR4 22K_0402_5%

2

PJ17 1

@ 1

2

PJ18 1

1

JUMP_43X118

@

@

2

PJ19 1

+1.05VS_VTT

1

2

+VGFX_COREP

JUMP_43X118 @ 2

2

JUMP_43X118

2

2

C

PJ20 1

1

+VGFX_CORE

JUMP_43X118

PJ26 1

1

JUMP_43X118 @ +1.5VSDGPUP

PreCHG

B

2

@

B

1 12

PD4 2

2

3

3

BAS40CW_SOT323-3

@ PQ3 PDTC115EU_SOT323-3

@PQ4 @ PQ4 PDTC115EU_SOT323-3 3

+5VALWP

B+

2 1

49

+1.5VSDGPU

1

@ PR13 @PR13 100K_0402_5% 1

ACOFF

1

1

@ PR12 1K_1206_5% 1 2

40,48

PJ25

2

@ PR11 1K_1206_5% 1 2

@ PR10 1

@

PR9 1

@ PR8 1K_1206_5% 1 2

3 100K_0402_5%

+3VLP

@ PQ2 TP0610K-T1-E3_SOT23-3

@ PD3 LL4148_LL34-2 2 1 100K_0402_5%

1 PR5 2 0_0603_5%

2

JUMP_43X118

2

@ PR7 1K_1206_5% 1 2

VIN +CHGRTC

2

A

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PWR DCIN / Pre-charge

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B SchematicsE

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

47

of

61

2 G PQ18 2N7002W-T/R7_SOT323-3

19

PHASE

18

6 7

ICM

9

CHLIM

BOOT

16

10

ACLIM

VDDP

15

11

VADJ

LGATE

14

12

GND

PGND

13

2

2

1

2

PR263 200K_0402_1%

PC182 10U_0805_25V6K

1 2

1

1 1

1 3

2

1 3

DH_CHG PR37 2.2_0603_5% BST_CHG 1 2

PC23 0.1U_0603_25V7K BST_CHGA 2 1 4

PD8 RB751V-40_SOD323-2 2

6251VDDP

1

26251VDD

1

2

DL_CHG

2

17

1

UGATE

PR41 4.7_0603_5%

PQ16 AO4466L_SO8

PC28 4.7U_0603_6.3V6M

4 PR34 0.02_1206_1% 3

1 2

BATT+

ISL6251AHAZ-T_QSOP24

40 CALIBRATE#

1 2 PR44 15.4K_0402_1%

3

PR45 31.6K_0402_1% 6251VDD

CC=0.6~4.48A

IREF=0.43V~3.24V

1

PR48 10K_0402_1% 1 2

PR47 10K_0402_1% 2

PR46 47K_0402_5%

ACIN

15,22,40,44,45

1

PACIN

1

2

PR49 14.3K_0402_1%

2 PQ19 PDTC115EU_SOT323-3

3

ACPRN

Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K R=514K//31.6K//(15.4K+3k)=11.372K r=514K//514K//31.6K=28.14K Vcell=0.175*Vadj+3.99v 4.2V=0.175*Vadj+3.99V =>Vadj=1.2V Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv A=Vref*(R/(R+514K))=0.052 Kv=9.451

4

Compal Secret Data

Security Classification Issued Date

WWW.AliSaler.Com A

TCR=50ppm / C PL2 10UH_PCMB104T-100MS_6A_20% CHG 1 2

S

Ki Vchlim=Iref*(PR374/(PR372+PR374)) =Iref*(100K/(80.6K+100K)) =Iref*0.5537 Ichanrge=(165mV/PR369)*(Vchlim/3.3V) =(165m/20m)*(1/3.3V)*Iref*0.5537 =1.3842*Iref Iref=0.7224*Ichanrge =>Ki=0.7224

4

2

4

2

VREF

PQ70 2N7002W-T/R7_SOT323-3

PQ15 AO4466L_SO8

3 2 1

8

S

0.1U_0603_25V7K PC16

CSIP

2

D

2 G

PC26 10U_1206_25V6M 2 1

VCOMP

1

CSOP

PACIN

PC25 10U_1206_25V6M 2 1

20

S

@ PC17 2200P_0402_50V7K 2 1

CSIN

PC18 0.047U_0402_16V7K 1 2 PR29 20_0402_5% 2 1 PR30 20_0402_5% PC21 0.1U_0603_25V7K 1 2 PR32 2_0402_5% LX_CHG

1

ICOMP

PR31

@ PQ12 2N7002W-T/R7_SOT323-3

CSON

PR35 4.7_1206_5%

PC19 6800P_0402_25V7K 1 2 5

PR28 20_0402_5% 1 2

D

2 G

PC27 680P_0402_50V7K

21

ACPRN 49

1

12.60V

PC181 10U_0805_25V6K 2 1

ACPRN

2

12600mV

PC11 2200P_0402_25V7K 2 1

1 2

PQ9 PDTC115EU_SOT323-3

3 2 1

CSOP

IREF=0.7224*Icharge Normal 3S LI-ON Cells

2 BAS40CW_SOT323-3

5 6 7 8

CSON

1

PC15 DCIN 2 1

1

CV mode

PC10 0.1U_0603_25V7K 2 1

1 PC14 1000P_0402_25V8J 2 1

PR22 10_1206_5% 2 1 23

1

2

CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A Charging Voltage (0x15)

ACSET ACPRN

CELLS

6251aclim

D

40,50 65W/90W#

BATT Type

3

5 6 7 8

3

12.1K_0402_1%

3

PQ17 PDTC115EU_SOT323-3

24

DCIN

EN

2

PR21 @ 100K_0402_5%

2 6251_EN 3

1 PR43 20K_0402_1%

2

1

VIN

PD10

0.1U_0603_25V7K

0.01U_0402_25V7K 10K_0402_1% 1 2 PR33 100_0402_1% 1 2 6251VREF PC22 .1U_0402_16V7K

3

ACOFF

2

ACOFF

VDD

VIN V1

PR15 10K_0402_1%

PR23 14.3K_0402_1%

PR40 6251VREF

PR16 47K_0402_1% 2

2

2

PR39 100K_0402_1%

PC24 0.01U_0402_25V7K 2 1

IREF

1

1

40

PR36 80.6K_0402_1% 2 1

ADP_I

1

ACSETIN

1

2

1 ACSETIN 2

4

1 2 1 PR42 2.55K_0402_1%

4

S

PC9 10U_1206_25V6M 2 1

1 PR26

1

2 3

PQ14B DMN66D0LDW-7_SOT363-6

40,50

3

RB751V-40_SOD323-2

22

PC20 1 2

PR38 47K_0402_5% PACIN 1 2

1

2

5 G

40,47

2

PU1

PR25 47K_0402_5% 1 2

3S/4S#

PR18 @ 191K_0402_1%

2

FSTCHG

B+

PD5

6251VDD

PQ13 PDTC115EU_SOT323-3

D

2

1

3

1

191K_0402_1%

S PQ14A DMN66D0LDW-7_SOT363-6

PreCHG PR262

1

1

1

6

PQ10 PDTC115EU_SOT323-3

40 1

2

VIN

PR24 0_0402_5% 2 1

8 7 6 5

CSIN

100K_0402_1%

1 V1

PQ8 PDTA144EU_SOT323-3

PL22 1.2UH_1231AS-H-1R2N=P3_2.9A_30% 1 2

CSIP

40

2

2 G

3

47K

6251VDD PR27 150K_0402_1%

D

2

1 2 3

CHG_B+

2

2

4

HCB4532KF-800T90_1812 2 @

1

47K

PR17 200K_0402_1%

B+

PR14 0.02_2512_1% 1

PC7 5600P_0402_25V7K 1 2

4 1

3

2

2

PR19 200K_0402_1%

PC12 0.1U_0603_25V7K 2 1

4 1

1

P3

PQ7 SI4459ADY-T1-GE3_SO8 1 8 2 7 3 6 5

1 2 3

1

ACOFF

CP = 85%*Iada ; CP = 4.07A

PC13 2.2U_0603_6.3V6K 2 1

P2

PQ6 AO4407A_SO8 8 7 6 5

PQ5 AO4407A_SO8

PC181 and PC182 reserve for EMI Isen solution

ADP_I = 19.9*Iadapter*Rsense

PL25

VIN

D

PC8 10U_1206_25V6M 2 1

Iada=0~4.74A(90W/19V=4.736A)

C

4

B

3

A

2011/02/08

Deciphered Date

2012/02/08

Title

Compal Electronics, Inc. PWR-CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B SchematicsE

Date:

B

C

Wednesday, June 08, 2011 D

Sheet

48

of

61

5

4

3

2

1

PC29 1U_0603_10V6K

2VREF_8205

3 2 1

PQ24B DMN66D0LDW-7_SOT363-6

PC46 1U_0603_10V6K 2 1

1 3 2 1

2

AO4712_SO8 PQ23

2VREF_8205

PC47 4.7U_0805_10V6K

2

1

VL

Typ: 175mA

PR60 4.7_1206_5%

2 1

4

18

17

16

RT8205EGQW_WQFN24_4X4

+5VALWP

1 +

PC43 PC45 680P_0402_50V7K

LG_5V

PL5 4.7UH_PCMC063T-4R7MN_5.5A_20% 1 2

5 6 7 8

19

NC

LGATE1 VREG5

LGATE2

VIN

LX_5V

13

5 6 7 8

PC37 2200P_0402_50V7K 2 1

PC38 0.1U_0603_25V7K 2 1

PC36 4.7U_0805_25V6-K 2 1

PC35 4.7U_0805_25V6-K 2 1

1

2 FB1

REF

3

4 TONSEL

UG_5V

20

GND

21

PHASE1

220U_6.3VM_R15

2

B

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ(+3VALWP)

1

+3.3VALWP Ipeak=5.78A ; 1.2Ipeak=6.94A; Imax=4.05A f=375KHz, L=4.7UH Rdson=15~18m ohm 1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.716A Vlimit=10*10^-6*110Kohm/10=0.11V Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A Iocp=7.06A~9.85AA (7.06A>6.94A -> ok) -DVT-

+5VALWP Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A f=300KHz, L=4.7UH,Rentrip=154k ohm Rdson=15~18m ohm 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A Vlimit=10*10^-6*154Kohm/10=0.15V Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A Iocp=8.44~11.57A (8.44>8.4 -> OK)

A

3

PC49 2.2U_0603_6.3V6K

2

1

2

PR66 100K_0402_1%

2

1

VS

UGATE1

PHASE2

2 1 PC48 0.1U_0603_25V7K

3

1

S

PQ27 PDTC115EU_SOT323-3

2

S

G

PQ25 PDTC115EU_SOT323-3

2 1 PR67 40.2K_0402_1%

1 EC_ON

5

Compal Secret Data

Security Classification 2011/02/08

Issued Date 3

40,41

1

ACPRN

A

3

48

D

UGATE2

RT8205_B+

C

PR64 100K_0402_1% 2 1

VL

2N7002W-T/R7_SOT323-3 PQ26 PR65 200K_0402_5% 2 1 2 G

2

D

4

G S

PR63 0_0402_5% 2 1

PR57 PC41 2.2_0603_5% 0.1U_0603_25V7K BST_5V 1 2 1 2

15

8 7 6 5

ENTRIP2

6

ENTRIP1

MAINPWON

22

B+

D

50

23

BOOT1

PR61 499K_0402_1% 1 2

B

PQ24A DMN66D0LDW-7_SOT363-6

PGOOD

VFB=2.0V

PQ21 AO4466L_SO8

4

BOOT2

4

+

2

12

50

VREG3

PR59 @ 0_0402_5% 2 1

1

PC42 220U_6.3V_M

MAINPWON

2

1

PQ22 AO4712_SO8

1 2 3

2

LG_3V

PR62 100K_0402_1%

1

PC44 680P_0402_50V7K 2 1

2

PC193 .1U_0402_16V7K

PC192 .1U_0402_16V7K

PC190 10P_0402_50V8J 2 1

PC191 10P_0402_50V8J 2 1

1

+3VALWP

PR58 4.7_1206_5% 2 1

4.7UH_PCMC063T-4R7MN_5.5A_20% PL4 1 2

R06 Modify

SPOK

24

EN

1 2 3

8 PR56 2 1 2 BST_3V 9 2.2_0603_5% PC40 UG_3V 10 0.1U_0603_25V7K LX_3V 11 1

PR55 154K_0402_1% 2

VO1

VO2

SKIPSEL

7

RT8205_B+

ENTRIP1

4

5

6

P PAD

2

25

ENTRIP2

PU2

1

FB2

PR54 110K_0402_1% 1 2

ENTRIP1

PR53 20K_0402_1% 1 2

1

PC39 4.7U_0805_10V6K

8 7 6 5

PC34 2200P_0402_50V7K 2 1

PC33 4.7U_0805_25V6-K 2 1

PQ20 AO4466L_SO8

1

PR52 20K_0402_1% 1 2

ENTRIP2

PR51 30K_0402_1% 1 2

Typ: 175mA +3VLP PC32 4.7U_0805_25V6-K 2 1

PC188 10P_0402_50V8J 2 1 PC189 10P_0402_50V8J 2 1

C

PC31 0.1U_0603_25V7K 2 1

PL3 HCB4532KF-800T90_1812 1 2

B+

PR50 13K_0402_1% 1 2

14

RT8205_B+

D

2

D

Deciphered Date

2012/02/08

Title

Compal Electronics, Inc. 3VALWP/5VALWP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

E JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Wednesday, June 08, 2011

Sheet 1

49

of

61

5

4

3

2

1

PJP2 SUYIN_200275GR008G13GZR D

10 9 8 7 6 5 4 3 2 1

2

EC_SMDA EC_SMCA TH PI

PR68 100_0402_1%

PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 72 degree C

2

GND GND 8 7 6 5 4 3 2 1

1

D

PR69 100_0402_1%

EC_SMB_DA1 40

VL

1

1

VMB BATT+

PC50 0.1U_0603_25V7K

PR72 21K_0402_1%

2

49 MAINPWON

2

VCC TMSNS1

8

2

GND RHYST1

7

2

3

OT1 TMSNS2

6

PR76 9.53K_0402_1%

OT2 RHYST2

5

1

1

4 BATT_TEMP 40

2

1 C

1

@ PR77 47K_0402_1% 1

G718TM1U_SOT23-8

1

1

1

PU3

@ PR74 100K_0402_1% PR75 1K_0402_1%

C

1

PR71 10K_0402_1%

VL

+3VALWP 2

PC52 0.01U_0402_25V7K

2

1 PR73 6.49K_0402_1% 2 1

1 PC51 1000P_0402_50V7K

2

2

1

2

EC_SMB_CK1 40 PR70 1K_0402_5%

2

PL6 SMB3025500YA_2P 1 2

PH2 @

PH1

2

100K_0402_1%_NCP15WF104F03RC 2

100K_0402_1%_NCP15WF104F03RC PQ28 TP0610K-T1-E3_SOT23-3

3

2

1

+VSBP

PC54 0.1U_0603_25V7K

2

65W@ PR240 3.92K_0402_1%

Change 5VALW to 3VALW on DVT

PR80 100K_0402_1%

B

1

ADP_I 40,48

PQ29 2N7002W-T/R7_SOT323-3

2

PR239 100K_0402_1%

D

2 G

3

1

VCC TMSNS1

8

2

GND RHYST1

7

1

3

OT1 TMSNS2

6

PR241 90W@ 16.2K_0402_1%

OT2 RHYST2

5

4

3

S

65W/90W# 40,48

2 G S

PU13

@ PQ66 2N7002W-T/R7_SOT323-3

2

1

1

D PQ65 2N7002W-T/R7_SOT323-3

2

90W@ PR240 9.09K_0402_1%

2

5,40 H_PROCHOT#

PR244 10K_0402_1% 2

@ PR250 0_0402_5% 1 2

@ PC170 0.1U_0603_25V7K

@ PR243 7.15K_0402_1%

1

2

+3VS

1

1

1

1

1

S

2 G

+3VALWP

PR245 0_0402_5%

1

2

D

3

SPOK

1

49

PC55 1U_0402_6.3V6K

1

B

PR81 1K_0402_5% 1 2

120W@ PR240 15.4K_0402_1%

2

1 2

1

2

VL

PC53 0.22U_0603_25V7K

PR79 22K_0402_1% 1 2

2 1 PR78 100K_0402_1%

B+

PR242 10K_0402_1%

G718TM1U_SOT23-8

2

65W@ PR241 10.5K_0402_1%

For 65W adapter==>action 70W , Recovery 54W For 90W adapter==>action 97W , Recovery 75W

A

A

120W@ PR241 17.4K_0402_1%

For 120W adapter==>action 135W , Recovery 100W Compal Secret Data

Security Classification Issued Date

WWW.AliSaler.Com 5

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. PWR-BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

50

of

61

A

B

C

D

PL7 HCB4532KF-800T90_1812 1 2

LGATE

9

DL_1.5V

8

RT8209MGQW_WQFN14_3P5X3P5 2

VFB=0.75V V=0.75*(1+10K/10K)=1.5V Fsw=298KHz

PC57 4.7U_0805_25V6-K 2 1

2

PC62 4.7U_0805_10V6K

AO4456_SO8

PC63 680P_0402_50V7K

PR90 1 1

Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm. Ipeak=19.53A, Imax=23.44A, Iocp=13.67A Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.63A =>1/2Delta I=2.315A choose Rcs=15K Iocpmax=((15K*11uA)/0.0045)+2.315A=35.65A Iocpmin=((15K*9uA)/(0.0056*1.3))+2.315A=23.06A Iocp=23.06A~35.65A

2 10K_0402_1%

PR91 10K_0402_1%

2

2

VGA@ PL9 HCB4532KF-800T90_1812 1 2

1 5 6 7 8 4

RT8209MGQW_WQFN14_3P5X3P5 VGA@

VGA@ PC71 4.7U_0805_10V6K

VGA@ PQ33 AO4456_SO8

NC

VGA@ PC65 4.7U_0805_25V6-K 2 1

VGA@ PC66 4.7U_0805_25V6-K 2 1

+1.5VSDGPUP 3

VGA@ PR97 4.7_1206_5%

1

VGA@ PC70 330U_6.3V_M

+

2 DL_1.5VDGPU

1

9

B+

2 VGA@ PC72 680P_0402_50V7K

2

10

LGATE

VGA@ PL10 1UH_FDUE1040D-1R0M-P3_21.3A_20% 1 2

3 2 1

CS VDDP

VGA@ PQ32 AO4466L_SO8

+5VALW

2

1

VGA@ VGA@ PR100 10K_0402_1% 1 2 1

VGA@ PC73 4.7U_0603_6.3V6K

LX_1.5VDGPU

1

PGOOD

12 11

2

6

DH_1.5VDGPU

1

FB

PHASE

VFB=0.75V

13

PR99 10K_0402_1%

VDD

5

14

15

1

4

UGATE

7

VGA@ PR98 100_0603_5% 1 2

2

+5VALW

VGA@ VGA@ PR96 PC68 2.2_0603_5% 0.1U_0603_25V7K 1 2BST_1.5VDGPU-1 1 2

BOOT

VOUT

PGND

TON

3

3

8

2

EN/DEM

PU5

GND

1 2

VGA@ PC69 1U_0402_6.3V6K

3 2 1

BST_1.5VDGPU

2 1

@ PR95 47K_0402_5%

45,54 VGA_ON

4

VGA@ PC175 0.1U_0603_25V7K 2 1

VGA@ PR92 267K_0402_1% 1 2

VGA@ PR94 100K_0402_1% 1 2

VGA@ PC174 2200P_0402_50V7K 2 1

5 6 7 8

1.5VDGPU_8209_B+

VGA@ PC185 0.1U_0603_25V7K 2 1

2

PC61 330U_6.3V_M

2

PC64 4.7U_0603_6.3V6K

+

4 1

10

1

14

15 NC

PGND

VDDP

1

PR87 4.7_1206_5%

PQ31

+5VALW

2

PGOOD

11

1

6

CS

+1.5VP

2

FB

LX_1.5V

VFB=0.75V

5 6 7 8

5

DH_1.5V

12

3 2 1

VDD

13

PHASE

1

PL8 1UH_FDUE1040D-1R0M-P3_21.3A_20% 1 2

1

4

UGATE

2

VOUT

B+

AO4406AL_SO8

PR85 PC59 2.2_0603_5% 0.1U_0603_25V7K 1 2BST_1.5V-1 1 2

PR89 15K_0402_1%

TON

3

BST_1.5V

BOOT

2

7

PR88 100_0603_5% 1 2

1

PU4

EN/DEM

@ PC60 .1U_0402_16V7K

GND

2

1

2

3 2 1

4

1

+5VALW

1

39,40,44,46 SYSON

@ PR86 47K_0402_5%

1

PR83 267K_0402_1% 1 2

PR84 0_0402_5% 1 2

PC56 4.7U_0805_25V6-K 2 1

PQ30

PC172 0.1U_0603_25V7K 2 1

PC173 2200P_0402_50V7K 2 1

5 6 7 8

1.5_8209_B+

VGA@ PR101 10K_0402_1%

4

2

VFB=0.75V V=0.75*(1+10K/10K)=1.5V Fsw=298KHz Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm. Ipeak=10.4A, Imax=12.48A, Iocp=7.28A Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.63A =>1/2Delta I=2.315A choose Rcs=10K Iocpmax=((10K*11uA)/0.0045)+2.315A=24.59A Iocpmin=((10K*9uA)/(0.0056*1.3))+2.315A=15.95A Iocp=15.95A~24.59A

4

Compal Secret Data

Security Classification Issued Date

2011/02/08

Deciphered Date

2012/02/08

Title

Compal Electronics, Inc. PWR-+1.5VP/+1.5VSDGPU

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

JE50-HR/SJV50-HR M/B SchematicsE

Date:

A

B

C

Wednesday, June 08, 2011 D

Sheet

51

of

61

5

4

3

2

1

1.8VSP Ipeak=3.35A ; 1.2Ipeak=4.02 ;Imax=2.345A Vout=0.6*(1+(20K/10K))=1.8V

1

2

SY8033BDBC_DFN10_3X3

PR105 10K_0402_1%

1 2

2

1

1

2

FB=0.6Volt

PC78 680P_0402_50V7K

PR106 1M_0402_5%

PC79 0.1U_0402_10V7K

S

1

D

2

1 2 G PQ67 2N7002W-T/R7_SOT323-3

3

2

PR104 100K_0402_5%

D

PC77 22U_0805_6.3VAM

1

1 PR103 20K_0402_1%

PC75 68P_0402_50V8J 2 1

FB_1.8V

2

6

1

FB

+1.8VSP

PC76 22U_0805_6.3VAM

11

2

3

2

2 1

38,40,44,53 SUSP#

LX

LX_1.8V

PR102 4.7_1206_5%

EN

2

NC

5

EN_1.8V

PG

SVIN

NC

PVIN

8

TP

9 PC74 22U_0805_6.3VAM

LX

1

PVIN

JUMP_43X118

D

38,44,53 SUSP

10

7

1

1

1

@

2

PL11 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% 1 2

4

PU6 PJ22 2

+5VALW

PL23 HCB3225KF-151T50_1210 1 2

PR107 267K_0402_1% 1 2

3 2 1

CS

11

VDDP

10

LGATE

9

PC187 0.1U_0603_25V7K 2 1 +

PR111 4.7_1206_5%

+5VALW 2

PQ35 AO4712_SO8

2 PR113 0_0402_5%

1 PC86 4.7U_0805_10V6K

PC85 470P_0603_50V8J

PR114 1 2 0_0402_5%

1

NC

SA_PGOOD 40

2

1

4

RT8209MGQW_WQFN14_3P5X3P5

PC84 330U_6.3V_M

2

1

LG_VCCSAP PR116 15K_0402_1%

0_0402_5% PR117 1

PGND

PGOOD

GND

FB

6

7 2

PC81 4.7U_0805_25V6-K 2 1

1

2

PC87 4.7U_0603_6.3V6K

2

1

1 2 PR115 10K_0402_5%

+3VS

8

PR112 100_0603_1% 1 2

+5VALW

5

+VCCSAP

1

PHASE

LX_VCCSAP

2

VDD

13 12

PL12 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% 1 2

5 6 7 8

VOUT

4

UGATE

UG_VCCSAP

2

2

TON

3

BOOT

2 @ PC83 0.1U_0402_16V7K

C

PQ34 AO4466L_SO8

PR109 PC82 2.2_0603_5% 0.1U_0603_25V7K 1 2 BST_VCCSAP-1 1 2

14

1 EN/DEM

1

@ PR110 47K_0402_5%

15

BST_VCCSAP

PU7 1

53 VCCPPWRGOOD

PC80 4.7U_0805_25V6-K 2 1

4

EN_VCCSAP PR108 0_0402_5% 1 2

B+

VSSSA_SENSE 9

3 2 1

C

PC176 0.1U_0603_25V7K 2 1

5 6 7 8

PC177 2200P_0402_50V7K 2 1

5603_VCCSAP_B+

PR118 2K_0402_1% 1 2

PR119 1

2

VCCSA_SENSE

VFB=0.75V

9

10_0402_5%

B

B

1

1

+3VS

PR120 15K_0402_1%

1 PR124 @ 100K_0402_5%

PQ37 PMBT2222A_SOT23-3 2

2 PR125

1 0_0402_5%

VCCSA_VID1

9

@ PR126 10K_0402_5%

VID[0] 0 0 1 1

VID[1] 0 1 1 1

VCCSA Vout 0.9 V 0.8 V 0.75V 0.65V

VFB=0.75V V=0.75*(1+2K/10K)=0.9V Fsw=298KHz Cout ESR=15m ohm Rdson(max)=18 mohm Rdson(typ)=15 mohm. Ipeak=6A, Imax=4.2A, Iocp=7.2A Delta I=((19-0.9)*(0.9/19))/(L*Fsw)=1.31A =>1/2Delta I=0.655A choose Rcs=15K Iocpmax=((15K*11uA)/0.015)+0.655A=11.48A Iocpmin=((15K*9uA)/(0.018*1.2))+0.655A=7.27A Iocp=7.27A~11.48A

2

3

2

@ PC88 4700P_0402_25V7K

1

1

PQ36 2N7002W-T/R7_SOT323-3

2

2

3

S

1

D

2 G

PR122 30K_0402_1%

2

1

1

2

PR121 10K_0402_5% PR123 10K_0402_5% 2 1

Require on 2011/ 2012 Required Yes/Yes Yes/Yes No/Yes No/Yes

A

A

Note:Use VCCSA_SEL to switch High & Low Level for VID[1] (ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.

Compal Secret Data

Security Classification Issued Date

WWW.AliSaler.Com 5

2011/02/08

Deciphered Date

2012/02/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

3

2

Compal Electronics, Inc. PWR +VCCSAP Document Number

Rev E

JE50-HR/SJV50-HR M/B Schematics Sheet

Wednesday, June 08, 2011 1

52

of

61

5

4

3

2

PU8

3 4

VCNTL

6

GND

NC

5

VREF

NC

7

VOUT

NC

8

TP

9

VIN

+3VALW

1

2

2

D

PC90 1U_0603_10V6K

2

PR127 1K_0402_1%

1

PC89 4.7U_0805_6.3V6K

2

1

1

+1.5V

1

D

+0.75VS 1

S

PR129 1K_0402_1%

PC93 10U_0603_6.3V6M

2

1 D

2

2 G PQ38 2N7002W-T/R7_SOT323-3

1

S

SUSP

3

PQ39 2N7002W-T/R7_SOT323-3

2

PC92 1U_0402_6.3V6K

D

2 G 3

1

38,44,52 SUSP

1

PR128 24.9K_0402_1% 1 2

PC91 .1U_0402_16V7K 2 1

G2992F1U_SO8

PL13 HCB4532KF-800T90_1812 1 2

4

LX_1.05VS_VCCP

11

VDDP

10

LGATE

9

2

B

1

4

+

2

PQ41 AO4456_SO8 PC102 4.7U_0805_10V6K

PC100 680P_0402_50V7K

PC99 330U_6.3V_M

2

PR134 0_0603_5%

1

RT8209MGQW_WQFN14_3P5X3P5

PR133 4.7_1206_5%

1 2

DL_1.05VS_VCCP

2

PC101 4.7U_0603_6.3V6K

3 2 1

+5VALW

1

PGOOD

PGND

VFB=0.75V

+1.05VS_VCCPP

1

1

12

CS

2

5 6 7 8

14 PHASE

PL14 1UH_FDUE1040D-1R0M-P3_21.3A_20%

3 2 1

FB

DH_1.05VS_VCCP

1

5

13

2

VDD

UGATE

PR136 15K_0402_1%

VOUT

4

PR132 PC98 2.2_0603_5% 0.1U_0603_25V7K BST_1.05VS_VCCP 1 2 1 2

BOOT

3

NC

EN/DEM

TON

6

15

1

1 2

2 PR135 100_0603_5% 1 2

2

1

+5VALW

PC97 4.7U_0603_6.3V6K

8

PQ68 2N7002W-T/R7_SOT323-3

PU9

GND

S

2 G

@ PR249 47K_0402_5%

7

1 SUSP

D

3

1

38,40,44,52 SUSP#

C

2

PR131 100K_0402_1% 1 2

PQ40 AO4406AL_SO8

B+

PC95 4.7U_0805_25V6-K 2 1

PR130 267K_0402_1% 1 2

PC94 4.7U_0805_25V6-K 2 1

C

PC178 0.1U_0603_25V7K 2 1

5 6 7 8

PC179 2200P_0402_50V7K 2 1

1.05VS_51117_B+

B

PR137 4.02K_0402_1% 1 2 PR140 10_0402_5% 2 1

1 52 PR138 10K_0402_1%

VCCPPWRGOOD

PR139

1

2

VCCIO_SENSE 8

+3VALW

2

2

10K_0402_1%

PR141 @ 10K_0402_1%

A

1

VFB=0.75V V=0.75*(1+4.02K/10K)=1.052V Fsw=298KHz Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm. Ipeak=12.866A, Imax=9A, Iocp=15.439A Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=3.33A =>1/2Delta I=1.665A choose Rcs=15K Iocpmax=((15K*11uA)/0.0045)+1.665A=37.62A Iocpmin=((15K*9uA)/(0.0056*1.3))+1.665A=23.02A Iocp=23.02A~37.62A

A

Compal Secret Data

Security Classification 2011/02/08

Issued Date

Deciphered Date

2012/02/08

Title

Compal Electronics, Inc. PWR +1.05VS_VCCPP/+0.75VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

E JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Wednesday, June 08, 2011

Sheet 1

53

of

61

5

VGA@ PL15 HCB3225KF-151T50_1210 1 2

2

3

EN

SW

8

SW_VCORE

4

VFB

V5IN

7

5

RF

DRVL

6

1

VGA@ PC109 680P_0402_50V7K GS@ PR153 2.37K_0402_1%

2

4

24

2

+3VSDGPU

VGA@ PR158 10K_0402_5%

2

1

VGA@ PR156 10K_0402_1%

2

GV@ PR157 8.66K_0402_1%

6

VGA@ PR159 10K_0402_5% 1 2

D

1

+3VSDGPU

2

2 1

S

1

1

DMN66D0LDW-7_SOT363-6 VGA@ PQ47A

GV@ PR160 10K_0402_5%

2

2

1

G

VGA@ PC114 4700P_0402_25V7K

VGA@ PR162 10K_0402_5% 1

2 VGA@ PR165 10K_0402_5% VGA@ PR166 10K_0402_5% 2 1

6

@ PR164 10K_0402_5%

D

G

VGA@ PQ48A

+3VSDGPU

2

2

1

1

0.860V(0.866V)

0.85V(0.851V)

@

G

PQ69A

2

X

1

0

0.975V(0.977V)

P0(Cold)

X

0

1

1.0V(1.004V)

X

0

0

----

1.0V(1.001V)

2 VGA@

G

PQ48B

DMN66D0LDW-7_SOT363-6

@ PR168 10K_0402_5% 1

GPU_VID0 22 VGA@ PR170 10K_0402_5%

S

2

P0(Hot)

GPU_VID2 22 @ PR258 10K_0402_5%

S

1

DMN66D0LDW-7_SOT363-6

VGA@ PR169 10K_0402_5% 5 2

1

X

D

1.025V(1.024V) ----

Issued Date

AP

Compal Secret Data

Security Classification 2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

WWW.AliSaler.Com

A

2

P8/P12 A

@ PR255 10K_0402_5% 2 1

3

D

4

NVIDIA/N12P-GV1

1

NVIDIA/N12P-GS

1

GPU_VID0

6

GPU_VID1

2

+3VSDGPU @ PR261 10K_0402_5%

GPU_VID1 22 @ PR167 10K_0402_5%

S

1

DMN66D0LDW-7_SOT363-6

1

2

4

S

+3VSDGPU

VGA@ PC115 4700P_0402_25V7K

1

5 1

G VGA@ PQ47B DMN66D0LDW-7_SOT363-6

B

2

D

1

VGA@ PR163 10K_0402_5% 1 2

3

Cout ESR=12m ohm Rdson(max)=3.2 mohm Rdson(typ)=2.6 mohm. Ipeak=41.02A, Imax=28.714A, Iocp=43A Delta I=((19-0.9)*(0.9/19))/(L*Fsw)=6.8A =>1/2Delta I=3.4A choose Rcs=75K Iocpmax=((75K*11uA)/0.0013)+3.4A=75.52A Iocpmin=((75K*9uA)/(0.0016*1.35))+3.4A=48.42A Iocp=48.42A~75.52A

GPU_VID2

@ PR161 10K_0402_5%

2

2

@ PR259 10K_0402_5% 1

2

@ PC183 4700P_0402_25V7K

1

S

4

DMN66D0LDW-7_SOT363-6 @ PQ69B

VFB=0.7V V=0.7*(1+Rtop/Rbottom) Fsw=350KHz

5

C

FB_GND

GCORE_SEN 24

GS@ PR157 12K_0402_1%

1

2

1 3

G

VGA@ PR151 0_0402_5% 1 2

2

GCORE_SEN

@ PR260 10K_0402_5% @ PR257 10K_0402_5% 1 2

D

Vtrip range ==> 0.2V ~ 3V

VGA@ PC113 2200P_0402_25V7K

GS@ PR160 15K_0402_1%

2

2

+3VSDGPU

VGA@ PC108 470U_V_2.5VM

+

2

VGA@ PR152 0_0402_5% 2 1

S

@ PR256 12.4K_0402_1%

B

1

+

GV@ PR153 2.15K_0402_1%

TPCA8057-H Rds=2.6m/3.2m ohm

VGA@ PQ46 2N7002W-T/R7_SOT323-3

VGA@ PC171 470U_V_2.5VM

1

3 2 1

VGA@ PC110 .1U_0402_16V7K

4

1

VGA@ PR150 10_0402_5%

2

Switch freq. (RF pin setting) 47K ==>450KHz 100K ==>390KHz 200K ==>350KHz (Currently setting) 470K ==>300KHz

VGA@ PR147 4.7_1206_5%

1

3

2 G

ESR=10mohm VGA@ PC106 1U_0603_6.3V6M

1

45 VGA_ON#

D

1

VFB=0.6V

1 1

2

C

+VGA_CORE

DL_VCORE

11

VGA@ PQ45 TPCA8028-H_SOP-ADVANCE8-5 2 1 2 1

TP

5

VGA@ PR148 200K_0402_1%

1

VGA@ PR149 100K_0402_1% 1 2

VGA@ PL16 0.36UH_MMD-12CE-R36M-M1L_34A_20% 1 2

+5VALW

TPS51218DSCR_SON10_3X3 VGA_ON

VGA@ PR144 2.2_0603_5% 1 2

VGA@ PQ43 TPCA8030-H_SOP-ADV8-5

DH_VCORE

3 2 1

BST_VCORE

9

3 2 1

10

DRVH

3 2 1

2

VBST

TRIP

4

VGA@ PQ44 TPCA8028-H_SOP-ADVANCE8-5

2

1 @ PR146 10K_0402_5%

PGOOD

2

VGA@ PC105 0.1U_0603_25V7K 1 2

5

+3VS

1

VGA@ PR143 2.2_0603_5% 1 2

D

2

VGA@ PR145 75K_0402_1% 1 2

VGA@

VGA@ PQ42 TPCA8030-H_SOP-ADV8-5

5 2

4 PU10

5

1

VGA@ PC107 10U_1206_25V6M 2 1

VGA@ PC104 10U_1206_25V6M 2 1

@ PR142 10K_0402_5%

18 VGA_PWROK

45,51 VGA_ON

1

+3VS VGA@ PC103 10U_1206_25V6M 2 1

D

3

B+_CORE

VGA@ PC186 0.1U_0603_25V7K 2 1

B+

4

4

3

2

+VGA_COREP Rev E

P5WE0

Wednesday, June 08, 2011

Sheet 1

54

of

61

4

3 2 1

PC117 220U_25V_M

GFX@ PC184 0.1U_0603_25V7K 2 1

GFX@ PC119 10U_1206_25V6M 2 1

GFX@ PC118 10U_1206_25V6M 2 1

TPCA8030-H_SOP-ADV8-5

5

TPCA8030-H_SOP-ADV8-5

1ISNG

1 2

@ PC137 470P_0402_50V7K

2

+5VS

2

100_0402_1% @ PR192 2

GFX@ PR193 604_0402_1%

1

1

@ PC136 0.01U_0402_16V7K

D

+

2

.1U_0402_16V7K GFX@ PC133 1 2

2

GFX@ PC132 .1U_0402_16V7K 1 2

DIS@ PR195 0_0402_5%

3

1

+CPU_CORE

2

QC@ PR205 10K_0402_1%

QC@ PR201 10K_0402_1% 1 2

1

QC@ PR207 1_0402_5% 1 2

QC@ PR204 3.65K_0402_1% VSUM+ 2 1

QC@ PR199 10K_0402_1% 2 1

C

ISEN3

QC@ PC140 QC@ PR202 680P_0402_50V7K 4.7_1206_5%

1 2

1 2

@ PQ55 TPCA8028-H_SOP-ADVANCE8-5

GFX@ PC123 330U_X_2VM_R6M

2

1

ISPG

PC139 10U_1206_25V6M 2 1

PC138 10U_1206_25V6M 2 1

TPCA8030-H_SOP-ADV8-5

1

GFX@ PR178 4.7_1206_5% 2 1 GFX@ PC130 680P_0402_50V7K

1 2 2

3 2 1

1

TPCA8028-H_SOP-ADVANCE8-5

5

GFX@ PQ51 TPCA8028-H_SOP-ADVANCE8-5

5 3 2 1 5 3 2 1

PC146 10U_1206_25V6M 2 1

2011/02/08

2012/02/08

Deciphered Date

PC96 4.7U_0805_25V6-K 2 1

B+

+CPU_CORE

PR238 10K_0402_1% 2 1 ISEN3

2

PR237 1_0402_5% 1 2

2

PR236 3.65K_0402_1% VSUM+ 2 1

PR235 10K_0402_1% 2 1 ISEN1

PR234 4.7_1206_5% Title

3

B

QC@ PR246 10K_0402_1%

PR220 10K_0402_1% 2 1 ISEN3

2

PR219 1_0402_5% 1 2

1

PR218 3.65K_0402_1% VSUM+ 2 1

PR217 10K_0402_1% 2 1 ISEN2

PC164 10U_1206_25V6M 2 1

PC163 10U_1206_25V6M 2 1

1 1 2

PC169 680P_0402_50V7K

3 2 1

4

1 2 PL17 HCB4532KF-800T90_1812

PL21 0.36UH_PCMC104T-R36MN1R17_30A_20% 4 1

2

1

PC168 0.22U_0603_10V7K 4

@ PQ64 TPCA8028-H_SOP-ADVANCE8-5

5

@ PQ62 TPCA8030-H_SOP-ADV8-5

4

+CPU_CORE

2

PC111 4.7U_0805_25V6-K 2 1

PR216 4.7_1206_5%

3

QC@ PR247 10K_0402_1%

PC145 10U_1206_25V6M 2 1

1 1 2 2

@ PQ58 TPCA8030-H_SOP-ADV8-5

PL20 0.36UH_PCMC104T-R36MN1R17_30A_20% 4 1

PC154 680P_0402_50V7K

3 2 1

4

@ PQ59 TPCA8028-H_SOP-ADVANCE8-5

5 5

3 2 1

4

Compal Electronics, Inc. PWR +CPU_CORE/+VGFX_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

E JE50-HR/SJV50-HR M/B Schematics

Date:

5

GFX@ 11K_0402_1% 1 PR187 2

QC@ PL19 0.36UH_PCMC104T-R36MN1R17_30A_20% 4

Compal Secret Data

Security Classification

*OCP setting value=37A

QC@ PQ56 TPCA8028-H_SOP-ADVANCE8-5

5 3 2 1

LGATE1

2.2_0603_5% PR233 2 1 2

A

Issued Date

GFX@ PR184 PH4 GFX@ 7.5K_0402_1% 10K_0402_5%_TSM0A103J4302RE 1 21 2

ISEN2

Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A Rdson=3.6~4.5m ohm DCR=1.1m ohm HW output cap: (1)22U_0805_6.3V *12 (2)470U_D2_2V *2(ESR=4.5m ohm)

GFX@ PR180 1_0402_5%

VSUM-

+VGFX_COREP

Icc-max=53A Rdson=3.6~4.5m ohm DCR=1.1m ohm HW output cap: (1)10U_0805_4V *10 (2)22U_0805_6.3V *15 (3)470U_D2_2V *4(ESR=4.5m ohm)

4

PHASE1

BOOT1

*OCP setting value=71.5A

5 3 2 1 5

3 2 1

@ PR231 100_0402_1%

2.2_0603_5% PR251 1

2

3 2 1

1

UGATE1

*Iccmax in Turbo Mode for SV (35W) is 53A +CPU_CORE

4

2.61K_0402_1%

PR223

1 2

PR227 2 1 11K_0402_1%

2

2 2

2

GFX@ PR179 10K_0402_1%

CPU_B+

VSUM.1U_0402_16V7K

@ PC166 330P_0402_50V7K

PC160 1

1 1

1

PH6 10KB_0603_5%_ERTJ1VR103J

2

2 1 10_0402_1%

DC@ PR229 2 1 1.47K_0402_1%

2

2.2_0603_5% PR214 2 1 2

LGATE2

PC167 2 1

1000P_0402_50V7K

BOOT2

0.22U_0603_25V7K

2 PC165

330P_0402_50V7K

PR232

1

PC162 2 1

1

2

+5VS

PHASE2

VSUM+

1 10_0402_1% 330P_0402_50V7K 2 1

(Ipeak=56A) (Vboot=0)

PC149 0.22U_0603_10V7K

QC@ PR229 1.37K_0402_1%

4

5

PC151 2 1

PC152 1

2

1 0.22U_0402_6.3V6K PC157 2 1 0.22U_0402_6.3V6K

4

DC@ PR212 1.69K_0402_1%

1_0603_5%

PC159 1

470P_0402_50V7K DC@ PR225 2 1 3.32K_0402_1%

PC153 2

1

0.068U_0402_16V7K

VSUM-

ISEN1

1

0.22U_0402_6.3V6K 2 1

1U_0603_10V6K

PC156 1

PR215

2

4

3 2 1

22P_0402_50V8J

2.2_0603_5% PR230 1

2

3 2 1

1 2

CPU_B+

3

+VGFX_COREP

CPU_B+

QC@ PR212 590_0402_1%

2

@ PQ54

3 2 1

VIN

4

PU12

24

23

22

21

20

19

18

17

PROG1

BOOT1

VDD

25

ISUMP

BOOT1

ISUMN

VW

RTN

UGATE1

12

VSEN

26

ISEN1

PHASE1

UG1 ISEN2

27

NTC

16

2

PR200 0_0402_5% LGATE1

11

FB

2

PQ57 TPCA8030-H_SOP-ADV8-5

28

1

PQ60 TPCA8028-H_SOP-ADVANCE8-5

VSSP1

DC@ PR198 0_0402_5%

PQ61 TPCA8030-H_SOP-ADV8-5

29

0.33U_0603_10V7K

2

3 2 1 5

30

LG1

4

2

3 2 1

PWM3

4

QC@ PQ53 TPCA8030-H_SOP-ADV8-5

1

QC@ PC129 1U_0603_10V6K

2

1

37 LGG

39 UGG

38

31

PH1

2

PR222 2 1 499_0402_1%

QC@ PC131 0.22U_0603_10V7K

2 1

LGATEG

PHASEG

1

BOOTG

41

40

PROG2

BOOTG

42

43 ISNG

NTCG

45

46

47

44 ISPG

RTNG

VSENG

PHG

VDDP

VR_HOT#

ISEN2

1 2

9

1

+

2

1

@ PQ52

+5VS

PR211

PC161

2

PGND

LGATE2

10

8 VSSSENSE

1

4

UGATE2

PR248 2K_0402_1% 8 VCCSENSE

PC180 680P_0402_50V7K

LGATE

5

IMON

32

ISL95831CRZ-T_TQFN48_6X6

PR228 QC@ PR225 3.83K_0402_1%

GND

4

CPU_B+

5

9

DC@ PC148

2

3

ISL6208ACRZ-T_QFN8_3X3

0_0603_5%

+CPU_CORE

7

2

PC147 1000P_0402_50V7K

PR213 8.06K_0402_1%

2

2

8

PHASE

GFX@ PL18 0.36UH_PCMC104T-R36MN1R17_30A_20%

1

ISEN1

PC158 150P_0402_50V8J

UGATE

PWM

5

PGOOD

33

LG2

1

PR224 412K_0402_1% 1 2 1

FCCM

2

B+

VSUM-

499K_0402_1%

6

1

VSSP2

PH5 470K_0402_5%_TSM0B474J4702RE PR2101 2 27.4K_0402_1%

1

1

5

VR_ON

8

PC155 33P_0402_50V8J

2

BOOT

PC142 2.2U_0603_10V6K 2 1

7

2

QC@ PC150

PR221 2

QC@ PR185 0_0402_5% 2 1

2 SCLK

B

@ 1

ISNG

ISPG

6

ISEN3

1

3.83K_0402_1%

48

SVID_SCLK

13

PC143 47P_0402_50V8J

470P_0402_50V7K 2 1

PR209

FBG

GND ALERT#

PC144 2 1 @

1

change from 43P to 47P for shortage problem 2010-03-15

PHASE2

COMP

1

PC141 0.047U_0603_16V7K

@ PR208 499_0402_1%

1

2

UGATE2

34

SDA

For shortage changed

2

1

35

PH2

5

0_0402_5%

VR_HOT#

+1.05VS_VTT

1 PR203

VR_ON

VCC

4

2 PL24 HCB4532KF-800T90_1812 GFX@

ISEN2

2

40

PU11 QC@

@ PQ50

1

ISEN1

40

2 1 PR206 19.1K_0402_1%

IMVP_IMON

UG2

PGOODG

3 4

15,40

VSSSENSE 40

IMONG

2

SVID_ALERT#

1.91K_0402_1%

VGATE

COMPG

49

SVID_SDA

C

BOOT2

ISEN3/ FB2

2

4

QC@ PR186 2.2_0603_5%

QC@ PR194 0_0402_5%

36

VWG

14

1

GFX_CORE_PWRGD

1

LGATEG

5

BOOT2

1

15

8 VR_SVID_CLK +3VS

NTCG

1

PR191 54.9_0402_1% PR196 GFX@ 1 1.91K_0402_1%

8 VR_SVID_ALRT#

40

PR189 @ 16.5K_0402_1%

PC122 2 1

2.2_0603_5% 0.22U_0603_10V7K GFX@ GFX@

330P_0402_50V7K PC127 VSS_AXG_SENSE 9 2 1 GFX@ 1000P_0402_50V7K GFX@ PR183 2 1 10_0402_1%

2

8 VR_SVID_DAT

PR197

+5VS

+3VS

2

2 1

2 1 130_0402_1% PR190

2

1

GFX@ PC134 0.047U_0603_16V7K

GFX@ PR188 18.2K_0402_1% 2 1

For shortage changed

PR175 BOOTG 2

VCC_AXG_SENSE 9

2 1 GFX@ PR182 2.55K_0402_1%

+1.05VS_VTT PC135 @ .1U_0402_16V7K

PHASEG

1

PC121 GFX@ 1 2

UGATEG

PC124 GFX@ 680P_0402_50V7K 2 1

+VGFX_COREP

GFX@ PR174 10_0402_1% 2 1

2

GFX@ PR173 27.4K_0402_1%

PC125 GFX@ 2 1

2 VSS_AXG_SENSE

2.2_0603_5% PR226 1

UGATEG 2

2

GFXVR_IMON

Parallel and tune length

GFX@ PQ49

4 1

GFX@ PR177 2 1 422_0402_1%

PC128 GFX@ 150P_0402_50V8J 2 1 2 1 PR181 GFX@ 475K_0402_1%

NTCG

GFX@ PR171 3.83K_0402_1%

330P_0402_50V7K

2

1

PC120 GFX@ 1000P_0402_50V7K

PR172 GFX@ 8.06K_0402_1% 2 1

1 PR176 @ 499K_0402_1%

1

GFX_B+

GFX@ PH3 470K_0402_5%_TSM0B474J4702RE 1 2 1

2

D

PC126 GFX@ 39P_0402_50V7K 2 1

2

VSUM- 2

3

@ PC116 470P_0402_50V7K 2 1

1

4

PQ63 TPCA8028-H_SOP-ADVANCE8-5

5

Alert# PU resister need close CPU, so the PU resister in HW schematic. but DAT and CLK need close PWM-IC, so the PU resister in POWER schematic.

3

2

Wednesday, June 08, 2011

Sheet 1

55

of

61

A

5

4

3

2

Version change list (P.I.R. List) Item

D

Fixed Issue

1

Add snubber R=4.7 ohm and C 680 pF

2

Change boost R from 0 to 2.2 ohm

Reason for change

Rev.

PG#

EMI solution

Modify List

1

Page 1 of 1 for PWR

Date

Phase

Add SD001470B80 for PR35,PR58,PR60,PR87,PR111, PR133,PR202,PR216,PR234 Add SE074681K80 for PC27,PC44,PC45,PC63,PC85, PC100,PC140,PC154,PC169

2010/10/20

DVT_P5WE0

0.2

---

EMI solution

0.2

---

Change R to SD013220B80 forPR37,PR56,PR57,PR85, PR109,PR132,PR186,PR214,PR233

2010/10/20

DVT_P5WE0

Change PL11 and PL12 from SH00000F800 to SH00000M700

Cost saving

0.2

52

Change PL11 and PL12 from SH00000F800 to SH00000M700

2010/10/20

DVT_P5WE0

Change PL18,PL19,PL20,PL21 from SH000005680 to SH00000HK00

Change DCR tolerance to 5%

0.2

55

Change PL18,PL19,PL20,PL21 from SH000005680 to SH00000HK00

2010/10/20

DVT_P5WE0

5

CPU CORE transient compensation

CPU CORE transient compensation

0.2

55

Add PR248, PC160, PC180

2010/10/20

DVT_P5WE0

6

Fixed adapter plug in will cause could not transitiion to AC mode when system was on battery mode

disable pre-charge circuit and don't use 連動線路

0.5

---

7

Fixed adapter plug in will cause could not transitiion to AC mode when system was on battery mode

disable pre-charge circuit and don't use 連動線路

0.5

---

8

Add 0.1UF on B+ input power

EMI solution

0.5

---

9

Adjust VGA CORE power sequesce

for NV request

0.5

10

Adjust 1.5VSDGPU power sequesce

for NV request

11

Adjust VID table

for NV request

3 4

D

C

B

C

Del PR7, PR8, PR9, PR10, PR11, PR12, PR13, PD3, PD4, PQ2, PQ3, PQ4, PR18, PR21, PQ12, PC17

Add PR262, PD10, PQ70, PR263, PC16 Change PQ7 to AO4459

PVT_P5WE0

2010/11/20

2010/11/20

PVT_P5WE0

Add PC184, PC185, PC186, PC187

2010/11/20

PVT_P5WE0

---

Change PR149 to 100K

2010/11/20

PVT_P5WE0

0.5

---

Change PR94 to 510K and add PC69

2010/11/20

PVT_P5WE0

0.5

---

Change PR153, PR157, PR160

2010/11/20

PVT_P5WE0

B

12

13

14 A

A

15

2011/02/08

Issued Date

WWW.AliSaler.Com 5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/02/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR (PWR) Rev

JE50-HR/SJV50-HR M/B SchematicsE

Date:

4

3

2

Wednesday, June 08, 2011

Sheet 1

56

of

61

5

4

VR_ON

3

(PU1000) ISL6266ACRZ-T

2

+CPU_CORE

1

+1.5VS_DMC

D

D

TQFN48 VGA_ON

Page 55

(PU998) APW7138NITRL SSOP16

ADAPTER SYSON

VS_ON

BATTERY

(SUSP#)

VCCPWRGOOD

SUSP

(U13) SI4800BDY-T1-GE3

VGA_ON#

+1.5VS

Page 44

(PU5) RT8209BGQW

+1.5V

SUSP

+1.05V_VCCP

Page 53

+1.5VSDGPU

Page 44

+0.75VS

Page 53

PJP25

(PU6) RT8209BGQW WQFN14

(PU8) APL5331KAC-TRL SO8

Page 51

(U40) AO4430L SO8

Page 54

WQFN14

B+

+VGA_CORE

L76

+1.05VS_PCH

+CLK_1.05VS

U38

+1.05VSDGPU

(PU3) RT8205EGQW

+VCCSA

C

C

WQFN24

CHARGER

Page 49

(PU3) RT8205EGQW WQFN24

Page 49

+5VALW

SUSP

SYSON#

(U49) SI4800BDY SO8

(U46) TPS2062ADR

Page 44

+3VALW

SUSP

PCH_PWR_EN#

(PU6) SY8033BDBC DFN10

Page 51

SUSP

(U14) SI4800BDY SO8

R599

(RE1)

Page 44

SUSP

(U68) SI4800BDY

(UB1) RT9701-PB

SO8

SOT23-5

Page 44

Page 45

B

B

+5VS

+USB_VCCB

+1.8VS

+3VALW_PCH

+3V_LAN (U39) BCM57780

+CRT_VCC

+3VALW_EC

+3V

ENVDD

ENVDD

(Q51) AO3413L SO23-3

+HDMI_5V_OUT

+3VS

+3VS_CK505 Page 37

VGA_ON

(Q30) AO3413L SO23-3

+1.2V_LAN

(Q34) AO3413L Page 30

SO23-3

Page 24

+DVDD_AUDIO +BT_VCC

+LCDVDD

+3VSDGPU

+5VS_HDD1 +3V_WLAN +5VS_ODD +3V_DMC A

A

+5VAMP

+VDDA

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. Power Rail

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev E JE50-HR/SJV50-HR M/B Schematics Sheet

Wednesday, June 08, 2011 1

57

of

61

5

4

3

2

1

D

D

2

PU3

B5

+3VALW

A5 B7

V

B4

V

4

EC

PBTN_OUT#

EC_ON

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_A# PM_SLP_SUS#

C

B6

V

14

15

CPU C

6

+1.5V PU5

V

V

SUSP#,SUSP

V

V

B

U68 +3VS

+1.8VSDGPU U37

U13 +1.5VS PU8 +0.75V

V

PU9 +1.05VS_VCCP

PU7 +VCCSA

V

+1.5VSDGPU U40

V

VCCPPWRGOOD

U49 +5VS

+3VSDGPU Q6

11 VGATE

V

8

V

8a (DIS) VGA_ON

VGA B

+1.05VSDGPU U38

V

SYSON#

+VGA_CORE PU998

V

DGPU_PWR_EN

7

V

SYSON

V

V

V

ON/OFF

H_CPUPWRGD PLT_RST#

V

A4

PCH

5

V V

B7

PM_DRAM_PWRGD

V

A5

V

51ON#

PCH_RSMRST#

V V

B3

SYS_PWROK 13

PQ2

V

B+

V

B2

+3VALW_PCH +5VALW_PCH

3

2

V

B1

2

V

BATT

U14,+3VALW_PCH QH4,+5VALW_PCH

V

B+

V

A3

V

A2

PU2

VV

VIN

V V

BATT MODE

A1

V

AC MODE

V

PCH_PWR_EN#

VGA_PWROK

8b (DIS)

U47 CK505

V

9

V

VR_ON

PU1000 +CPU_CORE

10

A

A

Compal Secret Data

Security Classification Issued Date

WWW.AliSaler.Com 5

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. Power sequence

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

58

of

61

5

4

3

2

Version Change List ( P. I. R. List ) Item Page# 1

P.18

Title PCH_GPIO71

Date 09/01

Request Owner

Page 1

Issue Description

SW

1

Solution Description

Rev.

For identofy VRAM 900 or 800 MHz

0.2

D

D

2

P.31

DPST buffer

09/03

HW

Change U1 from NOT gate to Buffer

0.2

3

P.39

EC_MUTE# pull high

09/03

HW

Change EC_MUTE# Pull high from +3VALW to +3VS

0.2

4

P.40

TP Conn. Reverse

09/03

HW

TP Mudule change,so reverse TP pin

0.2

5

P.13

09/03

HW

Already pull high R655~

0.2

6

P.45

09/03

HW

7

P.35

8

P.5

R624 pop @ Change Cap from 0.1u to 0.01u Change 0 Ohm to 47 Ohm

09/04 09/17

C696,C368,C717,C718,C695,C366,C697, C401,C370,C369,C715 change to 0.01U Follow Vendor Suggest .. R199,R207,R211,R215,R168,R171,R179, R182,R195,R216,R192 change to 47 Ohm Follow Vendor Suggest .. CPU XDP socket take off

Broadcom HW

C

0.2

0.2 0.2 C

TP pin reverse

9

P.40

09/17

HW

10

P.13

09/17

HW

R624 change to 4.7K

0.2

11

P.45

09/17

HW

OCI2B(R313) place @ for BOM

0.2

12

P.33

09/17

HW

HDMI output from PCH (by UMA)

0.2

13 14

P.35 P.17,35 ,37,38, 39,45

09/17

HW

09/17

HW

0.2

switch the LAN MIDI0 and MIDI2 pin

0.2

Change IO port PLT_RST# to PLT_RST_BUF#

0.2

OPTIMUS_EN# pull high, pull low resistor value both change to 10K

0.2

15

P.18

09/17

HW

16

P.24

09/20

HW

modify the VRAM strap pin ROM_SI pull low resistor for implement VRAM 900MHz

0.3

17

P.33

09/23

HW

Add R784 and R785 for DDC pull high...

0.3

18

P.44

09/23

HW

Add C818 and C819 for coupling noise from other spare trace...

0.3

19

P.45

09/23

HW

Add R786,R787,R788 and R789 pull down from vendor's suggestion..

0.3

20

P.37

09/23

HW

Add C820,R790 and Q58 for 3G/B and change source voltage from +3VS to +3VALW..

09/23

HW

09/24

HW

B

B

21

22

P.45

P.46

0.3

Add C821,C822,C823,C824 for +1.5V... and move the PJ26 & PJ27 between 1.5V to 1.5VSDGPUH

0.3

Change JUSB5 to USB2.0 Conn. Add D34 as ESD Diode for USB3.0

0.3

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

A

Compal Electronics, Inc. EE P.I.R (1)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

59

of

61

5

4

3

2

Version Change List ( P. I. R. List ) Item Page# 23

Title

P.41

Date 09/24

Request Owner

C

Page 2

Issue Description

HW

D

1

Solution Description

Rev.

Add R791 pull down 22k Ohm to ground Vendor's request... Add D31 to connect to ACIN Vendor's request... Add JP1,JP2 and JP3 for 家電下鄉 ESD protection

0.3

0.3 D

24

P.22

09/24

HW

25

P.36

09/29

HW

26

P.36

09/29

ME

Update the JREAD1 symbol

0.3

27

P.13

09/29

HW

Add R792 follow DG1.5

0.3

28

P.33

09/29

HW

Change HDMI termination R to 680 Ohm

0.3

29

P.44

09/29

30

P.17,38 ,45

09/30

HW

31

P.5

10/04

HW

32

P.17,18

10/04

HW

33

P.17,45

10/04

HW

M/B USB port from port 2 change to port1

0.3

34

P.26

10/04

HW

C1 and C604 chaneg to 470uF

0.3 0.3

HW

0.3

0.3

Add C825 fro +1.05VSDGPU Change the M/B to USB port to port 1 Sub/B to port 0 and port 2 Add test point for TCK,TMS, TRST#,TDO,TDI WWAN_OFF# from GPIO51 to GPIO37 WL_OFF# from GPIO55 to GPIO49

0.3 C

0.3 0.3

35

P.36

10/04

HW

Add C827 as DGND and RJ45_GND bridge

36

P.36

10/04

HW

Change R490,R491,R492 and R493 to 0603 package

37

P.35

10/04

HW

Chaneg R214 to 0603 package

0.3

38

P.35

10/04

HW

Chaneg R192,R195,R199,R207,R211 ,R215,R168,R171,R179,R182 to 0 Ohm

0.3

39

P.40

10/04

HW

follow broadcom suggestion,add R496

0.3

40

P.40

10/04

HW

Add keyboard cap for EMI

0.3

Add C826 for +1.5VSDGPU

0.3

0.3

B

B

41

P.44

10/04

HW

42

P.37

10/05

HW

43

P.13

10/12

HW

44

P.14

10/12

45

P.24

46

P.25

47 48

Add RTS5138 circuit Add D35 ,R799 and C838 for changing the RTC to samll size... and can be charged!!

0.4

HW

Add CLK_SD_48M for Card Reader 5138

0.4

10/12

HW

Pop R129 follow NV suggestion

0.4

10/12

HW

Pop R82 and De-pop R92 follow NV suggestion

0.4

P.25

10/12

HW

Add R800 and R801 10K Ohm pull down follow NV suggestion

0.4

P.24

10/12

HW

Change R775,R777,R778 and R779 to GV@

0.4

0.4

A

A

Compal Secret Data

Security Classification Issued Date

WWW.AliSaler.Com 5

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. EE P.I.R (2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

4

3

2

Sheet

Wednesday, June 08, 2011 1

60

of

61

5

4

3

2

Version Change List ( P. I. R. List ) Item Page# 49

Title

9

Date 11/12

Request Owner

50

20

11/12

HW

51

36

11/15

HW

LANGND add C808 0.1n_0402

52

19

11/15

HW

+VCCADAC add C832 10p_0402

53

40

11/15

HW

54

32

11/25

HW

55

36

56

13 & 34

0208

HW

Solution Description

Rev.

+1,8VS add C830,C831 10U_0603 +VCCSA add C828,C829 10U_0603

HW

HW

Page 3

Issue Description

D

11/25

1

D

+1.05VS_PCH add R808 0_0603

EC Board ID change to 56K add EC debug port EMI cost down request D17,D18 @ EMI cost down request D36 @ Change Odd sata port from port 2 to port 1 cause by intel sata II port issue

Rev 2.0

C

C

B

B

A

A

Compal Secret Data

Security Classification Issued Date

2011/02/08

2012/02/08

Deciphered Date

Title

Compal Electronics, Inc. EE P.I.R (3)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev E

JE50-HR/SJV50-HR M/B Schematics

Date:

5

4

3

2

Sheet

Wednesday, June 08, 2011 1

61

of

61