Acer Aspire 5310 5710
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A
B
C
D
E
1
1
-c c
Compal Confidential 2
2
-c o
JDW50/JDY70 Schematics Document
Intel Merom Processor with Crestline(PM945/GM945) + DDRII + ICH7M (With ATI MXM/B)
2007-4-12
3
VF
3
REV: 0.3
4
4
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Cover Page Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
1
of
44
A
B
C
Compal Confidential page 33
uPGA-478 Package (Socket M) page
1
DVI-D Conn.
LCD Conn.
CRT & TV-out
page 16
page 16
page 4
4,5 1
H_D#(0..63)
533/667MHz
Intel 945/PM/GM/943GML
LVDS SDVO
Memory BUS(DDRII) Dual Channel
PCI-Express
-c c
DMI
page 15
Intel ICH7-M
USB port 1
WLAN
Boardcom page 26
page 24
USB port 7
3.3V 33 MHz
Bluetooth Conn page
CMOS Camera
27
USB port 5
page 16
USB port 3 2
USB
3.3V ATA-100
BGA-652
HD Audio
IDE
S-ATA
page 20,21,22,23
-c o
page 27
3.3V 48MHz
3.3V 24.576MHz/48Mhz
PCI BUS LAN(GbE)
USB conn x2
USB port 0, 2
PCI-Express
MINI Card x1
C-Link
page 26
IDSEL:AD20 (PIRQA#, GNT#2, REQ#2)
page 12,13
BANK 0, 1, 2, 3
page 6,7,8,9,10,11
MXM II VGA/B
New Card Socket
200pin DDRII-SO-DIMM X2
1.8V DDRII 533/667
uFCBGA-1466
2
page 14
page 17
LVDS
DVI
Clock Generator
ADM1032
FSB
H_A#(3..35)
E
Thermal Sensor
Intel Merom Processor
Fan Control
Model Name : JDW50/70 File Name : LA-3771P
D
Card Reader
CDROM Conn. page 22
port 0, 1
MDC 1.5 Conn page 30
HDA Codec ALC268 page 31
ENE MR510
page 23
RJ45 page 25
4 in 1 socket
LS3553P
Power On/Off CKT. page 30
DC/DC Interface CKT.
LED/B Conn.
page 29
page 32
page 29
EC I/O Buffer
LS3551P
3
Phone Jack x3
Int.KBD
Touch Pad
LS3557P
page 29
USB Conn.
page 32
page 28
page 29
page 30
Audio AMP
ENE KB926
VF
BTN/B Conn.
RTC CKT.
22
LPC BUS
page 23
3
SATA HDD Conn. page
BIOS
page 29
page 29
USB port 4, 6 page 34
Power Circuit DC/DC 4
page 35
page 26
AUDIO/B Conn. w/Woofer(JDY70)
LS3558P 4
page 32
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Block Diagrams Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
2
of
44
A
B
C
D
SIGNAL
STATE
Voltage Rails
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
Description
S1
S3
S5
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
VIN
Adapter power supply (19V)
N/A
N/A
N/A
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
+0.9VS
0.9V switched power rail for DDR terminator
ON
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
+1.05VS
1.05V switched power rail
ON
OFF
OFF
+1.25VS
1.25V switched power rail
ON
OFF
OFF
+1.5VS
1.5V switched power rail
ON
OFF
OFF
+1.8V
1.8V power rail for DDR
ON
ON
OFF
+1.8VS
1.8V switched power rail
ON
OFF
OFF
Vcc Ra/Rc/Re
+2.5VS
2.5V switched power rail
ON
OFF
OFF
Board ID
+3VALW
3.3V always on power rail
ON
ON
ON*
+3V
3.3V power rail for SB
ON
ON
X
+3V_LAN
3.3V power rail for LAN
ON
ON
X
+3VS
3.3V switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
0 1 2 3 4 5 6 7
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC
V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V
V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V
BOARD ID Table Board ID 0 1 2 3 4 5 6 7
IDSEL# AD16
Address
Smart Battery
0001 011X b
EEPROM(24C16/02)
1010 000X b
GMT G781-1
1001 101X b
Interrupts PIRQE
0
EC SM Bus1 address Device
REQ#/GNT#
Device
Device
Address
Clock Generator (ICS9LPRS365)
1101 001Xb
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
BTO Item Discrete UMA DVI SATA*1 SATA*2 Dbg
BOM Structure PM@ GM@ DVI@ SATA*1@ SATA*2@ Dbg@
EC SM Bus2 address
3
Address
ADI ADM1032
ICH7M SM Bus address
2
1001 100X b
VF
Device
V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V
BTO Option Table
PCB Revision 0.1
-c o
External PCI Devices Card Reader
1
Board ID / SKU ID Table for AD channel
2
3
Clock
Power Plane
-c c
1
Full ON
E
4
4
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Notes List Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
3
of
44
5
4
3
2
1
JP22A
6 6
J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31#
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
K3 H2 K2 J3 L5
REQ0# REQ1# REQ2# REQ3# REQ4#
L2 V4
ADSTB0# ADSTB1#
H_ADSTB#0 H_ADSTB#1
YONAH
ADDR GROUP
DATA GROUP
C
6 6 6 6
H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRDY# H_HIT# H_HITM#
H_IERR#
H_LOCK# H_RESET#
H_RESET# H_RS#0 H_RS#1 H_RS#2
6
H_TRDY#
B
XDP_DBRESET#
20 XDP_DBRESET# 6 H_DBSY# 19 H_DPSLP# 19,42 H_DPRSTP# 6 H_DPW R#
XDP_BPM#5 H_PROCHOT# H_PW RGOOD H_CPUSLP# XDP_TCK XDP_TDI XDP_TDO TEST1 TEST2 XDP_TMS XDP_TRST#
19 H_PW RGOOD 6 H_CPUSLP#
THERMDA THERMDC 6,19 H_THERMTRIP# A
BCLK0 BCLK1
H1 E2 G5 F1 H5 F21 G6 E4 D20 H4 B1
ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT# HITM# IERR# LOCK# RESET#
F3 F4 G3 G2
HOST CLK
CONTROL
RS0# RS1# RS2# TRDY#
AD4 AD3 AD1 AC4
BPM0# BPM1# BPM2# BPM3#
C20 E1 B5 E5 D24 AC2 AC1 D21
DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT#
D6 D7 AC5 AA6 AB3 C26 D25 AB5 AB6
PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST#
DINV0# DINV1# DINV2# DINV3# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3#
MISC
A20M# FERR# IGNNE# INIT# LINT0 LINT1
THERMAL
A24 A25 C7
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
H_D#[0..63]
H_A#[3..31] H_REQ#[0..4] H_RS#[0..2]
H_D#[0..63]
H_A#[3..31]
6
6
H_REQ#[0..4] H_RS#[0..2]
6
6
D
XDP_TDI
J26 M26 V23 AC20
H23 M24 W24 AD23 G22 N25 Y25 AE24
A6 A5 C4 B3 C6 B4
LEGACY CPU
THERMDA DIODE THERMDC THERMTRIP#
STPCLK# SMI#
D5 A3
R59
XDP_TDO
XDP_TMS
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
6 6 6 6
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI
+1.05VS
2
1
56_0402_5%
R525 2
1
56_0402_5%
R63
H_PROCHOT#
-c o
6 6 6 6 6 6
A22 A21
E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26
VF
14 CLK_CPU_BCLK 14 CLK_CPU_BCLK#
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
-c c
D
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
R114
C
2
1
56_0402_5%
2
1
75_0402_5%
XDP_BPM#5
R46
2
1
56_0402_5%
H_IERR#
R113 2
1
56_0402_5%
XDP_TRST#
R57
2
1
56_0402_5%
XDP_TCK
R37
2
1
56_0402_5%
TEST1
R526
2
1 @ 1K_0402_5%
TEST2
R527
2
1
51_0402_5% B
6 6 6 6 6 6 6 6
+3VS C485 0.1U_0402_16V4Z 1 2
19 19 19 19 19 19
U21
1 C484 2200P_0402_50V7K 2
1
VDD
SCLK
8
EC_SMB_CK2 28
THERMDA
2
D+
SDATA
7
EC_SMB_DA2 28
THERMDC
3
D-
ALERT#
6
4
THERM#
GND
5
H_STPCLK# 19 H_SMI# 19
ADM1032ARMZ_MSOP8 A
FOX_PZ47903-2741-42_YONAH
Layout Note: THERMDA & THERMDC Trace / Space = 10 / 10 mil
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Merom (1/2) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
4
of
44
5
4
3
2
1
+CPU_CORE
VCCSENSE VSSSENSE
R20
2 1 R21 100_0402_1%
VCCSENSE AF7 VSSSENSE AE7
+1.5VS D
C148 10U_0805_10V4Z
1
1
2
2
+1.05VS
C153
0.01U_0402_16V7K
Layout Note: Place C626 near Pin B26
+1.05VS
42
PSI#
2
42 42 42 42 42 42 42
B26
VCCA
K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
AE6
PSI#
AD6 AF5 AE5 AF4 AE3 AF2 AE2
VID0 VID1 VID2 VID3 VID4 VID5 VID6
1
R366 1K_0402_1%
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
VCCSENSE VSSSENSE
Trace Close CPU < 0.5' 14 14 14
2
C
1
R369 2K_0402_1%
27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1%
GTL_REF0
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
1 R376 1 R375 1 R54 1 R56
2 2 2 2
+CPU_CORE
B
COMP0 COMP1 COMP2 COMP3
AD26
GTLREF
B22 B23 C21
BSEL0 BSEL1 BSEL2
R26 U26 U1 V1
COMP0 COMP1 COMP2 COMP3
E7 AB20 AA20 AF20 AE20 AB18 AB17 AA18 AA17 AD18 AD17 AC18 AC17 AF18 AF17
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 AC16 AF16 AE16 AB13 AA14 AD13 AC14 AF13 AE14 AB11 AA11 AD11 AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 F5 E6 H6 J5 M5 L6 P6 R5 V5 U6 Y6 A4 D4 E3 H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1
1
1
+ C669
2
1
+ C670
330U_D2E_2.5VM_R9
2
+ C671
@
330U_D2E_2.5VM_R9
2
330U_D2E_2.5VM_R9
South Side Secondary +CPU_CORE
3 x 330uF(9mOhm/3) 1
1
+ C672
2
330U_D2E_2.5VM_R9
1
+ C673 @ 330U_D2E_2.5VM_R9 2
+ C674
2
330U_D2E_2.5VM_R9
North Side Secondary +CPU_CORE
1
10U_0805_6.3V6M 1 C676
C675
2 10U_0805_6.3V6M
1
+CPU_CORE
10U_0805_6.3V6M 1 1 C685 C682
2 10U_0805_6.3V6M
10U_0805_6.3V6M 1 C678
1
C677
10U_0805_6.3V6M 1 C680
10U_0805_6.3V6M 1 1 C686 C683
1
C679
2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on South side,Secondary Layer)
2
10U_0805_6.3V6M 1 C649
C681
2 10U_0805_6.3V6M
2
10U_0805_6.3V6M 1 1 C684 C687
2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on South side,Secondary Layer)
2
+CPU_CORE
1
10U_0805_6.3V6M 1 C689
1
C688
2 10U_0805_6.3V6M
10U_0805_6.3V6M 1 C691
1
C690
10U_0805_6.3V6M 1 C693
C692
2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on North side,Secondary Layer)
2
+CPU_CORE
1
10U_0805_6.3V6M 1 C695
1
C694
2 10U_0805_6.3V6M
2
VF
D2 F6 D3 C1 AF1 D22 C23 C24 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 T22 B25
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
YONAH
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE18 AE17 AB15 AA15 AD15 AC15 AF15 AE15 AB14 AA13 AD14 AC13 AF14 AE13 AB12 AA12 AD12 AC12 AF12 AE12 AB10 AB9 AA10 AA9 AD10 AD9 AC10 AC9 AF10 AF9 AE10 AE9 AB7 AA7 AD7 AC7 B20 A20 F20 E20 B18 B17 A18 A17 D18 D17 C18 C17 F18 F17 E18 E17 B15 A15 D15 C15 F15 E15 B14 A13 D14 C13 F14 E13 B12 A12 D12 C12 F12 E12 B10 B9 A10 A9 D10 D9 C10 C9 F10 F9 E10 E9 B7 A7 F7
-c c
20mils
42 42
JP22C
3 x 330uF(9mOhm/3)
-c o
+CPU_CORE
+CPU_CORE JP22B
POWER, GROUNG, RESERVED SIGNALS AND NC
100_0402_1% 2 1
10U_0805_6.3V6M 1 C697
1
C696
10U_0805_6.3V6M 1 C699
1
C698
2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on North side,Secondary Layer)
10U_0805_6.3V6M 1 C668
C700
2 10U_0805_6.3V6M
+CPU-CORE Decoupling SPCAP,Polymer
C,uF
ESR, mohm
6X330uF
9m ohm/6
1.8nH/6
MLCC 0805 X5R
32X22uF
3m ohm/32
0.6nH/32
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
ESL,nH
+1.05VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C701
+
1
C702
1
C703
1
C704
1
C705
1
C706
1
C707
1
FOX_PZ47903-2741-42_YONAH
220U_D2_2VMR15
2
2
2
2
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
2
C708 @
2
0.1U_0402_16V4Z
1
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
YONAH
POWER, GROUND
K1 J2 M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 A19 D19 C19 F19 E19 B16 A16 D16 C16 F16 E16 B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 G23 K23 L24 P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
D
C
B
FOX_PZ47903-2741-42_YONAH C709 @
2 0.1U_0402_16V4Z
A
A
TRACE CLOSELY CPU < 0.5'
Compal Electronics, Inc.
Compal Secret Data
Security Classification
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Space 25mils (55Ohms)
2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Merom (2/2) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
5
of
44
H_A#[3..31]
D8 G8 B8 F8 A8
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
HADSTB#0 HADSTB#1
B9 C13
H_ADSTB#0 H_ADSTB#1
HCLKN HCLKP
AG1 AG2
CLK_MCH_BCLK# CLK_MCH_BCLK
HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3
K4 T7 Y5 AC4 K3 T6 AA5 AC5
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
J7 W8 U3 AB10
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_ADSTB#0 4 H_ADSTB#1 4 CLK_MCH_BCLK# 14 CLK_MCH_BCLK 14 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
4 4 4 4 4 4 4 4
DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3
20 20 20 20
DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3
20 20 20 20
DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
AE35 AF39 AG35 AH39
DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3
DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3
AC35 AE39 AF35 AG39
DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3
DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3
AE37 AF41 AG37 AH41
DMITXN0 DMITXN1 DMITXN2 DMITXN3
DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
AC37 AE41 AF37 AG41
DMITXP0 DMITXP1 DMITXP2 DMITXP3
12 12 13 13
AY35 AR1 AW7 AW40
DDRA_CLK0 DDRA_CLK1 DDRB_CLK0 DDRB_CLK1
DDRA_CLK0# DDRA_CLK1# DDRB_CLK0# DDRB_CLK1#
AW35 AT1 AY7 AY40
SM_CK0# SM_CK1# SM_CK2# SM_CK3#
12 12 13 13
DDRA_CKE0 DDRA_CKE1 DDRB_CKE0 DDRB_CKE1
AU20 AT20 BA29 AY29
SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3
12 12 13 13
DDRA_SCS#0 DDRA_SCS#1 DDRB_SCS#0 DDRB_SCS#1
AW13 AW12 AY21 AW21
SM_CS0# SM_CS1# SM_CS2# SM_CS3#
T37 T38
12 12 +1.8V13 13
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
PAD PAD
4 4 4 4
DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1
R426 180.6_0402_1% 2 R425 1 2 80.6_0402_1%
HVREF0 HVREF1 HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING
B7 E8 E7 J9 H8 C3 D4 D3 B3 C7 C6 F6 A7 E3
HRS0# HRS1# HRS2#
B4 E6 D6
H_ADS# H_TRDY# H_DPW R# H_DRDY# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# H_CPUSLP#
H_RESET# 4 H_ADS# 4 20 PM_BMBUSY# H_TRDY# 4 PM_EXTTS#0 H_DPW R# 4 12,13 PM_EXTTS#0 PM_EXTTS#1 H_DRDY# 4 R5301 0_0402_5% 2 4,19 H_THERMTRIP# H_DEFER# 4 GMCH_PW ROK H_HITM# 4 MCH_RSTIN# H_HIT# 4 H_LOCK# 4 18 MCH_ICH_SYNC# H_BR0# 4 H_BNR# 4 H_BPRI# 4 H_DBSY# 4 H_CPUSLP# 4 H_RS#[0..2]
H_RS#0 H_RS#1 H_RS#2
AL20 AF10
SM_OCDCOMP0 SM_OCDCOMP1
BA13 BA12 AY20 AU21
SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3
SMRCOMP SMRCOMP#
SM_VREF
HCPURST# HADS# HTRDY# HDPWR# HDRDY# HDEFER# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP#
SM_CK0 SM_CK1 SM_CK2 SM_CK3
12 12 13 13
AV9 AT9
SM_VREF0 SM_VREF1
G28 F25 H26 G6 AH33 AH34
PM_BMBUSY# PM_EXTTS0# PM_EXTTS1# PM_THERMTRIP# PWROK RSTIN#
18,20,22,24,28 PLT_RST#
R326
ICH_SYNC#
CALISTOGA_FCBGA1466~D PM@
4
MCH_RSTIN# 100_0402_5%
Layout Note: H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 10/20. 5
2
0.1U_0402_16V4Z C712
100_0402_1%
1
R539
2
0.1U_0402_16V4Z C711
2
C40 D41
CLK_REQ#
H32
MCH_CLKREQ#
CLK_DREF_96M# 14 CLK_DREF_96M 14 CLK_DREF_SSC# 14 CLK_DREF_SSC 14 MCH_CLKREQ# 14 C
NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18
A3 A39 A4 A40 AW1 AW41 AY1 BA1 BA2 BA3 BA39 BA40 BA41 C1 AY41 B2 B41 C41 D1
RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13
T32 R32 F3 F7 AG11 AF11 H7 J19 A41 A34 D28 D27 A35
VGATE 1 R333 SYS_PW ROK 1 R332
2 SM_VREF
1 C894 @ 0.1U_0402_16V4Z 2
20,30 SYS_PW ROK
C354
1
0.1U_0402_16V4Z 2
R335 100_0402_1% 20,42 PM_DPRSLPVR
1 R536
B
GMCH_PW ROK 2 @ 0_0402_5% 2 0_0402_5%
2007/1/15
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3
PM_EXTTS#0 R183 PM_EXTTS#1 2 0_0402_5% R196
+3VS
10K_0402_5% @
A
10K_0402_5%
Compal Electronics, Inc.
Compal Secret Data
Security Classification Issued Date
4
D_REF_SSCLKN D_REF_SSCLKP
CLK_DREF_SSC# CLK_DREF_SSC
CLK_MCH_3GPLL 14 CLK_MCH_3GPLL# 14
1
20/20mil
H_SW NG1
1
CLK_DREF_96M# CLK_DREF_96M
D
2
1
221_0603_1%
R535
2
1
R534
2 2 R538
1
0.1U_0402_16V4Z C710
200_0603_1%
2
100_0402_1%
2
100_0402_1%
R533
1 1 R537
1
1
A27 A26
D_REF_CLKN D_REF_CLKP
MCH_CLKSEL0 14 MCH_CLKSEL1 14 MCH_CLKSEL2 14 T17 T22 CFG5 10 T20 CFG7 10 T19 CFG9 10 T18 CFG11 10 CFG12 10 CFG13 10 T15 T21 CFG16 10 T16 CFG18 10 CFG19 10 CFG20 10
reserve VGATE for GMCH_PWROK
R334 100_0402_1%
H_VREF
A
2
H_SW NG0
CLK_MCH_3GPLL CLK_MCH_3GPLL#
14,20,42 VGATE
+1.05VS
221_0603_1%
+1.05VS
AG33 AF33
G_CLKP G_CLKN
+1.8V
CALISTOGA_FCBGA1466~D PM@ +1.05VS
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 CFG3 PAD CFG4 PAD CFG5 CFG6 PAD CFG7 CFG8 PAD CFG9 CFG10 PAD CFG11 CFG12 CFG13 CFG14 PAD CFG15 PAD CFG16 CFG17 PAD CFG18 CFG19 CFG20
SM_RCOMPN SM_RCOMPP
AK1 AK41
K28
K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
CFG
20 20 20 20
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3
CLK
4
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3
NC
H_REQ#[0..4]
20 20 20 20
RESERVED
HDINV#0 HDINV#1 HDINV#2 HDINV#3
Description at page10
U41B
-c o
HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4
4
1
R532 24.9_0402_1% 2 1
R531 24.9_0402_1% 2 1
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
VF
J13 H_VREF K13 H_XRCOMP E1 H_XSCOMP E2 H_YRCOMP Y1 H_YSCOMP U1 H_SW NG0 E4 H_SW NG1 W1
B
H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#
PM
R529 54.9_0402_1% 1 2
+1.05VS
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
1
DDR MUXING
C
F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8
2
DMI
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
D
R528 54.9_0402_1% 1 2
3
U41A
H_D#[0..63]
HOST
4
4
-c c
5
2
Title
Calistoga (1/6) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
6
of
44
5
4
3
2
1
13 DDRB_SDQ[0..63] 12 DDRA_SDQ[0..63] 12 DDRA_SMA[0..13]
DDRB_SDQ[0..63]
DDRA_SDQ[0..63] 13 DDRB_SMA[0..13]
DDRB_SMA[0..13]
DDRA_SMA[0..13]
D
D
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
C
12 12 12 12 12 12 12 12
DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7
DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7
AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7
12 12 12 12 12 12 12 12
DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7#
DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7#
AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5
SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#
DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13
AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13
B
12 DDRA_SCAS# 12 DDRA_SRAS# 12 DDRA_SW E# T28 T30
SA_RCVENIN# SA_RCVENOUT#
AY13 AW14 AY14 AK23 AK24
SA_CAS# SA_RAS# SA_WE# SA_RCVENIN# SA_RCVENOUT#
PAD PAD
AT24 AV23 AY28
SB_BS0 SB_BS1 SB_BS2
DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7
AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7
AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7
DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7#
AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5
SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#
DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13
AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13
SB_RCVENIN# SB_RCVENOUT#
AR24 AU23 AR27 AK16 AK18
SB_CAS# SB_RAS# SB_WE# SB_RCVENIN# SB_RCVENOUT#
13 DDRB_SBS0# 13 DDRB_SBS1# 13 DDRB_SBS2# 13 DDRB_SDM[0..7]
-c c
AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4
DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63
13 13 13 13 13 13 13 13
DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7
-c o
DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7
AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8
13 13 13 13 13 13 13 13
VF
12 DDRA_SDM[0..7]
U41E
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
DDR SYS MEMORY A
SA_BS0 SA_BS1 SA_BS2
DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7#
13 DDRB_SCAS# 13 DDRB_SRAS# 13 DDRB_SW E# T29 T31
PAD PAD
CALISTOGA_FCBGA1466~D PM@
DDR SYS MEMORY B
U41D
AU12 AV14 BA20
12 DDRA_SBS0# 12 DDRA_SBS1# 12 DDRA_SBS2#
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3
DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63
C
B
CALISTOGA_FCBGA1466~D PM@
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Calistoga (2/6) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
7
of
44
5
4
3
2
1
U41C
16 GMCH_TXOUT016 GMCH_TXOUT116 GMCH_TXOUT2-
D
16 GMCH_TZOUT016 GMCH_TZOUT116 GMCH_TZOUT216 16 16 16 15,28
C
R541 GM@ 0_0402_5% 1 2 LBKLT_EN
ENBKL
LA_DATA0 LA_DATA1 LA_DATA2
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-
C37 B35 A37
LA_DATA#0 LA_DATA#1 LA_DATA#2
GMCH_TZOUT0+ GMCH_TZOUT1+ GMCH_TZOUT2+
F30 D29 F28
LB_DATA0 LB_DATA1 LB_DATA2
GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-
G30 D30 F29
LB_DATA#0 LB_DATA#1 LB_DATA#2
GMCH_TXCLK+ GMCH_TXCLKGMCH_TZCLK+ GMCH_TZCLK-
A32 A33 E26 E27
LA_CLK LA_CLK# LB_CLK LB_CLK#
D32 J30 H30 H29 G26 G25 F32 B38 C35 C33 C32
LBKLT_CTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL
A16 C18 A19
TVDAC_A TVDAC_B TVDAC_C
J20
TV_IREF
B16 B18 B19
TV_IRTNA TV_IRTNB TV_IRTNC
R7372 1@ 0_0402_5% LBKLT_EN LCTLA_CLK LCTLB_DATA GMCH_LCD_CLK 16 GMCH_LCD_CLK GMCH_LCD_DATA 16 GMCH_LCD_DATA GMCH_ENVDD 16 GMCH_ENVDD LIBG DPST_PW M
GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA
2 TV_IREF 4.99K_0402_1%
17 GMCH_CRT_VSYNC 17 GMCH_CRT_HSYNC 17 GMCH_CRT_B 17 GMCH_CRT_G 17 GMCH_CRT_R
GMCH_CRT_CLK GMCH_CRT_DATA
2 R543 2 R544 2 R545
1 1 1
150_0402_1% 150_0402_1% 150_0402_1%
2 CRT_IREF 255_0402_1%
1 R546
B
J29 K30
TV_DCONSEL1 TV_DCONSEL0
C26 C25
DDCCLK DDCDATA
H23 G23 E23 D23 C22 B22 A21 B21
VSYNC HSYNC BLUE BLUE# GREEN GREEN# RED RED#
J22
CRT_IREF
CRT
17 GMCH_CRT_CLK 17 GMCH_CRT_DATA
A
VF
10mils +3VS
R547 1
2 10K_0402_5%
GMCH_LCD_CLK
R548 1
2 10K_0402_5%
GMCH_LCD_DATA
R549 1
2 10K_0402_5%
LCTLB_DATA
R550 1
2 10K_0402_5%
LCTLA_CLK
R551 1
2 4.7K_0402_5%
GMCH_CRT_CLK
R552 1
2 4.7K_0402_5%
GMCH_CRT_DATA
R553 1
2 100K_0402_5%
LBKLT_EN
R554 1
2 1.5K_0402_1%
LIBG
R555 1
2 150_0402_1%
GMCH_TV_COMPS
R556 1
2 150_0402_1%
GMCH_TV_LUMA
R557 1
2 150_0402_1%
GMCH_TV_CRMA
D40 D38
PEG_COMP
10mils
1 R540
EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15
F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15
EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15
D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38
PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15
EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15
F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40
PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15
EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15
D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40
PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15
-c o
1 R542
TV
17 GMCH_TV_COMPS 17 GMCH_TV_LUMA 17 GMCH_TV_CRMA
16
GMCH_TXCLK+ GMCH_TXCLKGMCH_TZCLK+ GMCH_TZCLK-
B37 B34 A36
LVDS
16 GMCH_TZOUT0+ 16 GMCH_TZOUT1+ 16 GMCH_TZOUT2+
GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+
EXP_COMPI EXP_COMPO
2
24.9_0402_1%
+1.5VS_PCIE
PCIE_MTX_C_GRX_N[0..15]
C188 1 C201 1 C217 1 C240 1 C252 1 C270 1 C285 1 C304 1 C180 1
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
C179 2 PM@ 0.1U_0402_16V7K C195 PM@ 0.1U_0402_16V7K 2 C212 2 PM@ 0.1U_0402_16V7K C229 2 PM@ 0.1U_0402_16V7K C246 2 PM@ 0.1U_0402_16V7K C261 2 PM@ 0.1U_0402_16V7K C277 2 PM@ 0.1U_0402_16V7K C296 2 PM@ 0.1U_0402_16V7K
1
C176 0.1U_0402_16V7K C189 0.1U_0402_16V7K C204 0.1U_0402_16V7K C219 0.1U_0402_16V7K C241 0.1U_0402_16V7K C253 0.1U_0402_16V7K C272 0.1U_0402_16V7K C288 0.1U_0402_16V7K
1
2 PM@
C198 1
2 PM@
C214 1
2 PM@
C232 1
2 PM@
C248 1
2 PM@
C263 1
2 PM@
C283 1
2 PM@
C297 1
2 PM@
1 1 1 1 1 1 1
1 1 1 1 1 1 1
15
PCIE_MTX_C_GRX_P[0..15] 15 15
D
PCIE_GTX_C_MRX_P[0..15] 15
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10 2 PCIE_MTX_C_GRX_N11 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14 2 PCIE_MTX_C_GRX_N15
C
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15
B
CALISTOGA_FCBGA1466~D PM@
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
-c c
16 GMCH_TXOUT0+ 16 GMCH_TXOUT1+ 16 GMCH_TXOUT2+
SDVOCTRL_DATA SDVOCTRL_CLK
PCI-EXPRESS GRAPHICS
H27 H28
4
3
2
Title
Calistoga (3/6) Size Document Number Custom
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Monday, April 16, 2007
Sheet 1
8
of
44
5
4
3
2
1
+2.5VS
2
+1.5VS A
1
2
AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12
2
close pin G41
1
2
2
220U_D2_4VM
CRTDAC: Route caps within 250mil of Alviso. Route FB within 3" of Calistoga
AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14
VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40
330U_D2E_2.5VM
+3VS_TVDACB
+3VS_TVDACC
1
1
2
2
1
2
2
+3VS L60 MBK1608301YZF_0603 2 1
1
2
1 + C727 2
220U_D2_4VM
C
+3VS L61 MBK1608301YZF_0603 2 1
1
2
close pin A38
(20mA)
+3VS_TVBG
+3VS R559 0_0603_5% 2 1
+1.5VS_TVDAC
+3VS
(40mA)
1
1
1
2
2
2
1
2
PCI-E/MEM/PSB PLL decoupling +1.5VS_3GPLL
1
2
+1.5VS
1
2
R561 0_0603_5% 2 1
1
@
2
+1.5VS_MPLL
R562 0_0603_5% 2 1
45mA Max. 1
2
+1.5VS
+1.5VS_TVDAC
1
2
1
R560 0_0603_5% 2 1
1
2
2
1
2
2
1
2
R563 0_0603_5% 2 1
45mA Max. 1
B
@
+1.5VS_HPLL +1.5VS
+1.5VS
C747 0.1U_0402_16V4Z
VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31
+3VS_TVDACA
D21 (24mA) H19
A23 B23 B25
2
+3VS_TVDACA
C746 0.022U_0402_16V7K
VCCHV0 VCCHV1 VCCHV2
C718 2
1
C745 0.1U_0402_16V4Z
VCCD_TVDAC VCCDQ_TVDAC
1
+3VS_TVDACC
AH1 (150mA) +1.5VS AH2
A28 B28 C28
+3VS L59 MBK1608301YZF_0603 2 1
C744 0.1U_0402_16V4Z
VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2
1
+ C729
C743 10U_0805_10V4Z
VCCD_HMPLL0 VCCD_HMPLL1
E19 F19 C20 D20 E20 F20
+
2
C730 0.1U_0402_16V4Z
1
+2.5VS
+3VS_TVDACB
C742 0.1U_0402_16V4Z
VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1
C717 0.1U_0402_16V4Z
C715 0.1U_0402_16V4Z
C721 10U_0805_10V4Z
C722 0.1U_0402_16V4Z
2
L58 MBK1608301YZF_0603 2 1
+2.5VS
+3VS_TVBG (120mA)
1
C726 0.022U_0402_16V7K
+1.5VS_MPLL
330U_D2E_2.5VM
C725 0.1U_0402_16V4Z
AF2 (45mA) H20 G20
2
C724 0.022U_0402_16V7K
+2.5VS
2
C735 0.022U_0402_16V7K
A38 (10mA) B39
C716
-c c
VCCA_LVDS VSSA_LVDS
2
1
C734 0.1U_0402_16V4Z
+1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_HPLL
+
+1.5VS
+2.5VS 2
C728 0.1U_0402_16V4Z
1 B26 (50mA) C39 (50mA) AF1 (45mA)
VCCA_MPLL
C720 10U_0805_10V4Z
+2.5VS_CRTDAC
1
L57 MBK1608301YZF_0603 2 1
1
C755 10U_0805_10V4Z
1
E21 (70mA) F21 G21
2
1
+1.5VS
1
C754 0.1U_0402_16V4Z
MCH_D2 C750 0.22U_0603_16V7K
2
2
+1.5VS_3GPLL +2.5VS (2mA)
VCCA_DPLLA VCCA_DPLLB VCCA_HPLL
VCCA_TVBG VSSA_TVBG
2
1
C753 10U_0805_10V4Z
1
1
C751 0.47U_0603_16V4Z MCH_AB1
C748 0.22U_0603_16V7K
B
C719 220U_D2_2VMR15
+
C752 0.1U_0402_16V4Z
C737 0.47U_0603_16V4Z
MCH_A6
1
+1.5VS
C741 0.1U_0402_16V4Z
2
P O W E R
(1500mA)
C733 0.01U_0402_16V7K
1
VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC2
R558 0_0805_5% 2 1
C739 0.022U_0402_16V7K
2
VCCA_3GPLL VCCA_3GBG VSSA_3GBG
AC33 G41 H41
+1.5VS_PCIE
W=60 mils
-c o
1
C732 2.2U_0805_10V6K
C731 4.7U_0805_10V4Z
C
AB41 AJ41 L41 N41 R41 V41 Y41
C723 0.022U_0402_16V7K
2
VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6
+2.5VS
+1.5VS_DPLLB
L56 MBK1608301YZF_0603 2 1
1 2 C714 0.1U_0402_16V4Z
(60mA) B30 C30 A30
C738 10U_0805_10V4Z
220U_D2_2VMR15
+
VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2
H22
C749 0.1U_0402_16V4Z
C713
VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35 VTT36 VTT37 VTT38 VTT39 VTT40 VTT41 VTT42 VTT43 VTT44 VTT45 VTT46 VTT47 VTT48 VTT49 VTT50 VTT51 VTT52 VTT53 VTT54 VTT55 VTT56 VTT57 VTT58 VTT59 VTT60 VTT61 VTT62 VTT63 VTT64 VTT65 VTT66 VTT67 VTT68 VTT69 VTT70 VTT71 VTT72 VTT73 VTT74 VTT75 VTT76
VF
1
VCC_SYNC AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1
C740 0.1U_0402_16V4Z
+1.05VS
(800mA)
D
+1.5VS_DPLLA
U41H
C736 0.1U_0402_16V4Z
D
+1.5VS
1
2
A
CALISTOGA_FCBGA1466~D PM@
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/10/4
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Calistoga (4/6) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
9
of
44
5
4
3
2
1
Strap Pin Table CFG[3:17] have internal pull up
+ 2
1 C770 + @ 220U_D2_2VMR15 2
B
+1.05VS
M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16
VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12
AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17 +1.8V
VCC100 VCC101 VCC102 VCC103 VCC104 VCC105 VCC106 VCC107 VCC108 VCC109 VCC110 CALISTOGA_FCBGA1466~D PM@
VCC_SM100 VCC_SM101 VCC_SM102 VCC_SM103 VCC_SM104 VCC_SM105 VCC_SM106 VCC_SM107
AR6 AP6 AN6 AL6 AK6 AJ6 AV1 MCH_AV1 AJ1 MCH_AJ1
1
2
1
2
Place near pin AV1 & AJ1
1
2
1
2
CFG5 CFG7
0 = Reserved 1 = Mobile Yonah CPU *(Default)
CFG9
0 = Lane Reversal Enable 1 = Normal Operation *(Default)
CFG11
1
2
C764 0.1U_0402_16V4Z
2
C763 0.1U_0402_16V4Z
2
C762 0.1U_0402_16V4Z
2
1
1 = Calistoga 00 01 10 11
CFG[13:12]
1
D
0 = Reserved
Place near pin AT41 & AM41
1
= 667MT/s FSB = 533MT/s FSB
0 = DMI x 2 1 = DMI x 4 *(Default)
PSB 4X CLK Enable
C761 0.1U_0402_16V4Z
P O W E R
011 001
CFG[2:0] C759 0.47U_0603_16V4Z
C758 0.47U_0603_16V4Z
MCH_AT41 MCH_AM41
= = = =
*
Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation *(Default)
CFG16
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled *(Default)
CFG18
0 = 1.05V 1 = 1.5V
CFG19
0 = Normal Operation * (Default) 1 = DMI Lane Reversal Enable
*(Default)
0 = No SDVO Device Present * (Default)
SDVO_CTRLDATA
1 = SDVO Device Present
CFG20
(PCIE/SDVO select)
0 = Only PCIE or SDVO is operational. *(Default) 1 = PCIE/SDVO are operating simu.
C
1
2
Place near pin BA23
1
2
C772 10U_0805_10V4Z
220U_D2_2VMR15
CFG[19:18] have internal pull down
-c c
1 C768
AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6
C769 0.47U_0603_16V4Z
C757 0.22U_0603_16V7K
C
VCC_SM0 VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4 VCC_SM5 VCC_SM6 VCC_SM7 VCC_SM8 VCC_SM9 VCC_SM10 VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15 VCC_SM16 VCC_SM17 VCC_SM18 VCC_SM19 VCC_SM20 VCC_SM21 VCC_SM22 VCC_SM23 VCC_SM24 VCC_SM25 VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36 VCC_SM37 VCC_SM38 VCC_SM39 VCC_SM40 VCC_SM41 VCC_SM42 VCC_SM43 VCC_SM44 VCC_SM45 VCC_SM46 VCC_SM47 VCC_SM48 VCC_SM49 VCC_SM50 VCC_SM51 VCC_SM52 VCC_SM53 VCC_SM54 VCC_SM55 VCC_SM56 VCC_SM57 VCC_SM58 VCC_SM59 VCC_SM60 VCC_SM61 VCC_SM62 VCC_SM63 VCC_SM64 VCC_SM65 VCC_SM66 VCC_SM67 VCC_SM68 VCC_SM69 VCC_SM70 VCC_SM71 VCC_SM72 VCC_SM73 VCC_SM74 VCC_SM75 VCC_SM76 VCC_SM77 VCC_SM78 VCC_SM79 VCC_SM80 VCC_SM81 VCC_SM82 VCC_SM83 VCC_SM84 VCC_SM85 VCC_SM86 VCC_SM87 VCC_SM88 VCC_SM89 VCC_SM90 VCC_SM91 VCC_SM92 VCC_SM93 VCC_SM94 VCC_SM95 VCC_SM96 VCC_SM97 VCC_SM98 VCC_SM99
C771 10U_0805_10V4Z
2
VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99
C774 0.47U_0603_16V4Z
2
1
U41G AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19
-c o
1
2
AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15
+1.8V
VF
2
2
1
VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57
C776 0.47U_0603_16V4Z
1
1
C767 1U_0603_10V4Z
2
C760 0.22U_0603_16V7K
1
C766 10U_0805_10V4Z
C765 10U_0805_10V4Z
C756 0.22U_0603_16V7K
D
VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72
P O W E R
(3500mA)
U41F AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18
+1.05VS
+1.5VS
C775 0.47U_0603_16V4Z
+1.05VS
1 1
2
+ C773 2
330U_D2E_2.5VM_R9
6
CFG5
6
CFG7
6
CFG9
6
CFG11
6
CFG12
6
CFG13
6
CFG16
6
CFG18
6
CFG19
6
CFG20
R564
1
2 @
2.2K_0402_5%
R565
1
2 @
2.2K_0402_5%
R566
1
2 @
2.2K_0402_5%
R567
1
2 @
2.2K_0402_5%
R568
1
2 @
2.2K_0402_5%
R569
1
2 @
2.2K_0402_5%
R570
1
2 @
2.2K_0402_5%
R571
1
2 @ 1K_0402_5%
R572
1
2 @ 1K_0402_5%
R573
1
2 @ 1K_0402_5%
+3VS
1
B
2
Place near pin BA15
CALISTOGA_FCBGA1466~D PM@
A
A
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/10/4
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Calistoga (5/6) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
10
of
44
5
4
3
2
U41I
C
P O W E R
AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21
AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11 J11 D11 B11 AV10 AP10 AL10 AJ10
VF
B
U41J VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199
VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS265 VSS264 VSS263 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279
VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS292 VSS291 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 VSS353 VSS354 VSS355 VSS356 VSS357 VSS358 VSS359 VSS360
AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1
D
-c c
D
VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99
P O W E R
-c o
AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34 AK34 AG34 AF34
1
C
B
CALISTOGA_FCBGA1466~D PM@
CALISTOGA_FCBGA1466~D PM@
A
A
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/10/4
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Calistoga (6/6) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
11
of
44
5
4
+1.8V
3
2
+1.8V
+1.8V
DDRA_SDQ8 DDRA_SDQ14 DDRA_SDQS1# DDRA_SDQS1
7 DDRA_SDQS1# 7 DDRA_SDQS1
DDRA_SDQ9 DDRA_SDQ15
DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQS2# DDRA_SDQS2
7 DDRA_SDQS2# 7 DDRA_SDQS2
DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ29 DDRA_SDQ24 DDRA_SDM3 DDRA_SDQ26 DDRA_SDQ27 C
6 7
DDRA_CKE0
DDRA_CKE0
DDRA_SBS2#
DDRA_SBS2#
DDRA_SMA12 DDRA_SMA9 DDRA_SMA8 DDRA_SMA5 DDRA_SMA3 DDRA_SMA1
7 7
DDRA_SBS0# DDRA_SWE#
7 6
DDRA_SCAS# DDRA_SCS#1
6
DDRA_SMA10 DDRA_SBS0# DDRA_SWE# DDRA_SCAS# DDRA_SCS#1 DDRA_ODT1
DDRA_ODT1
DDRA_SDQ37 DDRA_SDQ36 DDRA_SDQS4# DDRA_SDQS4
7 DDRA_SDQS4# 7 DDRA_SDQS4
DDRA_SDQ35 DDRA_SDQ32 DDRA_SDQ40 DDRA_SDQ44 B
DDRA_SDM5 DDRA_SDQ41 DDRA_SDQ46 DDRA_SDQ49 DDRA_SDQ48
DDRA_SDQS6# DDRA_SDQS6
7 DDRA_SDQS6# 7 DDRA_SDQS6
DDRA_SDQ54 DDRA_SDQ50 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDM7 DDRA_SDQ59 DDRA_SDQ58 D_CK_SDATA D_CK_SCLK
13,14 D_CK_SDATA 13,14 D_CK_SCLK
+3VS
A
1
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204
DDRA_SDQ6 DDRA_SDQ0
R345
+DIMM_VREF
1K_0402_1% 2
DDRA_SDM0
1
DDRA_SDQ5 DDRA_SDQ7
R344 DDRA_SDQ13 DDRA_SDQ12
1K_0402_1%
DDRA_SDM1
+DIMM_VREF 1 C376
2
20mils 1
2.2U_0805_10V6K
2
C410 D
0.1U_0402_16V4Z
DDRA_CLK0 6 DDRA_CLK0# 6 DDRA_SDQ11 DDRA_SDQ10 DDRA_SMA[0..13]
7 DDRA_SMA[0..13]
DDRA_SDQ[0..63]
7 DDRA_SDQ[0..63] DDRA_SDQ20 DDRA_SDQ21 DDRA_SDM2
R1191 0_0402_5% 2
C611
DDRA_SDQS3# 7 DDRA_SDQS3 7
DDRA_ODT0 DDRA_SMA13
DDRA_SDQ39 DDRA_SDQ38 DDRA_SDM4 DDRA_SDQ34 DDRA_SDQ33 DDRA_SDQ45 DDRA_SDQ43 DDRA_SDQS5# DDRA_SDQS5 DDRA_SDQ47 DDRA_SDQ42
1
C608
1
C606
1
C389
1
C400
1
C388
1
+0.9VS
DDRA_CKE0 1 DDRA_SBS2# 2 RP19
DDRA_CKE1 6
DDRA_SMA11 DDRA_SMA7 DDRA_SMA6
DDRA_SBS1# DDRA_SRAS# DDRA_SCS#0
C605
+1.8V
DDRA_SDQ31 DDRA_SDQ30
DDRA_SMA4 DDRA_SMA2 DDRA_SMA0
1
2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2 2 2 2 2 2 2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z
DDRA_SDQ28 DDRA_SDQ25
DDRA_CKE1
+1.8V
PM_EXTTS#0 6,13
DDRA_SDQ23 DDRA_SDQ22
DDRA_SDQS3# DDRA_SDQS3
DDRA_SDM[0..7]
7 DDRA_SDM[0..7]
4 3 56_0404_4P2R_5%
DDRA_SMA12 1 DDRA_SMA9 2 RP20
4 3 56_0404_4P2R_5%
DDRA_SMA5 DDRA_SMA8
4 3 56_0404_4P2R_5%
1 2 RP21
DDRA_SMA1 DDRA_SMA3
DDRA_SBS1# 7 DDRA_SRAS# 7 DDRA_SCS#0 6 DDRA_ODT0 6
DDRA_SDQS5# 7 DDRA_SDQS5 7
DDRA_SDQ52 DDRA_SDQ53
DDRA_CLK1 6 DDRA_CLK1# 6
1 2 RP22
4 3 56_0404_4P2R_5%
DDRA_SMA10 1 DDRA_SBS0# 2 RP23
4 3 56_0404_4P2R_5%
DDRA_SWE# 1 DDRA_SCS#1 2 RP24
4 3 56_0404_4P2R_5%
DDRA_SCAS# 1 DDRA_ODT1 2 RP25
4 3 56_0404_4P2R_5%
DDRA_SMA11 1 DDRA_CKE1 2 RP26
4 3 56_0404_4P2R_5%
C411
1
C414
1
C417
1
C413
C
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+0.9VS
C427
1
C404
1
C407
1
C425
1
1 C403 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+0.9VS
C422
1
1 C405
C409
1
C408
1
C406
1 B
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA6 DDRA_SMA7
1 2 RP27
4 3 56_0404_4P2R_5%
DDRA_SMA2 DDRA_SMA4
1 2 RP28
4 3 56_0404_4P2R_5%
DDRA_SBS1# 1 DDRA_SMA0 2 RP29
4 3 56_0404_4P2R_5%
C424
DDRA_SCS#0 1 DDRA_SRAS# 2 RP30
4 3 56_0404_4P2R_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z
DDRA_SMA13 1 DDRA_ODT0 2 RP31
4 3 56_0404_4P2R_5%
+0.9VS
1
C423
1
C426
1
DDRA_SDM6
DDRA_SDQ51 DDRA_SDQ55 DDRA_SDQ57 DDRA_SDQ56
DDRA_SDQS7# DDRA_SDQS7
DDRA_SDQS7# 7 DDRA_SDQS7 7
DDRA_SDQ62 DDRA_SDQ63
R3531 R3541
2 10K_0402_5% 2 10K_0402_5%
FOX_AS0A426-M2RN-7F CONN@
+3VS
C607
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
2
D
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
-c c
DDRA_SDQ2 DDRA_SDQ3
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
-c o
DDRA_SDQS0# DDRA_SDQS0
7 DDRA_SDQS0# 7 DDRA_SDQS0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
VF
DDRA_SDQ4 DDRA_SDQ1
1
JP28 +DIMM_VREF
1
C402
1
A
DIMM0 REV H:5.2mm (BOT)
0.1U_0402_16V4Z 2 2 2.2U_0805_10V6K
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
DDRII-SODIMM0 Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Sheet
Monday, April 16, 2007 1
12
of
44
A
B
C
D
+DIMM_VREF +1.8V
1
DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQS1# DDRB_SDQS1
7 DDRB_SDQS1# 7 DDRB_SDQS1
DDRB_SDQ10 DDRB_SDQ11
DDRB_SDQ17 DDRB_SDQ20 DDRB_SDQS2# DDRB_SDQS2
7 DDRB_SDQS2# 7 DDRB_SDQS2
DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ28 DDRB_SDQ25 DDRB_SDM3 2
DDRB_SDQ30 DDRB_SDQ31 6
DDRB_CKE0
7
DDRB_SBS2#
DDRB_CKE0 DDRB_SBS2# DDRB_SMA12 DDRB_SMA9 DDRB_SMA8 DDRB_SMA5 DDRB_SMA3 DDRB_SMA1
7 7
DDRB_SBS0# DDRB_SWE#
7 6
DDRB_SCAS# DDRB_SCS#1
6
DDRB_SMA10 DDRB_SBS0# DDRB_SWE# DDRB_SCAS# DDRB_SCS#1 DDRB_ODT1
DDRB_ODT1
DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQS4# DDRB_SDQS4
7 DDRB_SDQS4# 7 DDRB_SDQS4
DDRB_SDQ34 DDRB_SDQ35
3
DDRB_SDQ40 DDRB_SDQ41 DDRB_SDM5 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ48 DDRB_SDQ49
DDRB_SDQS6# DDRB_SDQS6
7 DDRB_SDQS6# 7 DDRB_SDQS6
DDRB_SDQ51 DDRB_SDQ50 DDRB_SDQ56 DDRB_SDQ61 DDRB_SDM7 DDRB_SDQ59 DDRB_SDQ58 D_CK_SDATA D_CK_SCLK
12,14 D_CK_SDATA 12,14 D_CK_SCLK
+3VS
4
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND
DDRB_SDQ5 DDRB_SDQ4
1
C386
1
1
C519 +
2.2U_0805_10V6K 2 2 0.1U_0402_16V4Z
C556+ 2
DDRB_SDM0
2
330U_D2E_2.5VM_R9
1
C420
C429
1
C385
1
C374
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
150U_D2_6.3VM @ 1
DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ12 DDRB_SDQ13
For EMI
DDRB_SDM1 +1.8V
+1.8V
+1.8V
+1.8V
DDRB_CLK1 6 DDRB_CLK1# 6 DDRB_SDQ14 DDRB_SDQ15
7 DDRB_SMA[0..13] 7 DDRB_SDQ[0..63] 7 DDRB_SDM[0..7]
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202
DDRB_SDQ21 DDRB_SDQ16 0_0402_5% R356 1 2 DDRB_SDM2
PM_EXTTS#0 6,12
DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ26 DDRB_SDQ24 DDRB_SDQS3# DDRB_SDQS3
C615
1
C617
DDRB_SDM[0..7]
+1.05VS
DDRB_CKE1 6
DDRB_SMA4 DDRB_SMA2 DDRB_SMA0
DDRB_ODT0 DDRB_SMA13
C616
1
C618
1
C619
1
C620
1
C622
1
C621
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+5VALW
+1.5VS
+0.9VS
DDRB_SMA11 DDRB_SMA7 DDRB_SMA6
DDRB_SBS1# DDRB_SRAS# DDRB_SCS#0
1
DDRB_SDQ[0..63]
+1.8V
DDRB_SDQS3# 7 DDRB_SDQS3 7
DDRB_SDQ29 DDRB_SDQ27 DDRB_CKE1
DDRB_SMA[0..13]
-c c
DDRB_SDQS0# DDRB_SDQS0
7 DDRB_SDQS0# 7 DDRB_SDQS0
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
C373 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
DDRB_CKE0 DDRB_SBS2#
1 2 RP32
4 3 56_0404_4P2R_5%
DDRB_SMA12 DDRB_SMA9
1 2 RP33
4 3 56_0404_4P2R_5%
DDRB_SMA8 DDRB_SMA5
1 2 RP34
4 3 56_0404_4P2R_5%
DDRB_SMA3 DDRB_SMA1
1 2 RP35
4 3 56_0404_4P2R_5%
DDRB_SMA10 DDRB_SBS0#
1 2 RP36
4 3 56_0404_4P2R_5%
DDRB_SWE# DDRB_SCAS#
1 2 RP37
4 3 56_0404_4P2R_5%
DDRB_SCS#1 DDRB_ODT1
1 2 RP38
4 3 56_0404_4P2R_5%
DDRB_SMA11 DDRB_CKE1
1 2 RP39
4 3 56_0404_4P2R_5%
DDRB_SMA6 DDRB_SMA7
1 2 RP40
4 3 56_0404_4P2R_5%
DDRB_SMA2 DDRB_SMA4
1 2 RP41
4 3 56_0404_4P2R_5%
DDRB_SBS1# DDRB_SMA0
1 2 RP42
4 3 56_0404_4P2R_5%
-c o
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
DDRB_SBS1# 7 DDRB_SRAS# 7 DDRB_SCS#0 6 DDRB_ODT0 6
DDRB_SDQ36 DDRB_SDQ37
1
C372
C369
1
C370
2
1
C371
1
C421
1
C419
1
C428
1
2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2 2 2 2 2 2 2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z
+1.8V
1
C384
C398
1
C375
1
C399
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+0.9VS
DDRB_SDM4
DDRB_SDQ39 DDRB_SDQ38 DDRB_SDQ44 DDRB_SDQ45
VF
DDRB_SDQ0 DDRB_SDQ1
+1.8V
+1.8V JP29
+DIMM_VREF
E
DDRB_SDQS5# DDRB_SDQS5
DDRB_SDQS5# 7 DDRB_SDQS5 7
DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ52 DDRB_SDQ53
DDRB_CLK0 6 DDRB_CLK0# 6
DDRB_SDM6
DDRB_SDQ54 DDRB_SDQ55
DDRB_SCS#0 DDRB_SRAS#
1 2 RP43
4 3 56_0404_4P2R_5%
DDRB_SMA13 DDRB_ODT0
1 2 RP44
4 3 56_0404_4P2R_5%
DDRB_SDQ60 DDRB_SDQ57
DDRB_SDQS7# DDRB_SDQS7
2 2 10K_0402_5% 10K_0402_5%
C391
1
C392
1
C378
1
C393
1 3
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+0.9VS
1
C397
C396
1
C383
1
C379
1
C394
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+0.9VS
C381
DDRB_SDQS7# 7 DDRB_SDQS7 7
1
C395
1
C380
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z
DDRB_SDQ62 DDRB_SDQ63 1 R3481 R349
1
C382
+3VS
4
FOX_AS0A426-MARG-7F CONN@
DIMM1 REV H:9.2mm (BOT)
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
DDRII-SODIMM1 Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
13
of
44
FSLC
B
FSLB
FSLA
CLKSEL2 CLKSEL1 CLKSEL0
C
CPU MHz
SRC MHz
PCI MHz
1
2
0
0
1
133
100
33.3
0
1
1
166
100
33.3
D
+CLK_VDD48
+CLK_VDDREF 1
C777 10U_0805_10V4Z
2
1
C778 0.047U_0402_16V7K
2
0 **SEL_PCI5/REF1
CLKREQ3#
33.3MHz PCICLK5
**SEL_PCI6/PCICLK1
CLKREQ5#
33.3MHz PCICLK6
**SEL_24M/PCICLK2
TESTMODE
24MHz Output
**SEL_48M/PCICLK3
CLKREQ7#
48MHz_1 Output
ITP_EN/PCICLK_F0
SRC pair
+CLK_VDD2
C790 33P_0402_50V8J 1 2
1 R578 1 R580
1
**SEL_24M/PCICLK2=0=TESTMODE **SEL_PCI6/PCICLK1=0=CLKREQ5#
+3VS
CLK_XTALIN
1 R586
CLK_PCI0 2 10K_0402_5%
CLK_48M_SD R693 1 CLK_ICH_48M R694 1
23 CLK_48M_SD 20 CLK_ICH_48M
2 CLK_PCI4 10K_0402_5%
28 CLK_PCI_LPC 20 CLK_ICH_14M
2 33_0402_5%
R688 1 Dbg@
26 CLK_PCI_Dbg
23 CLK_PCI_card
2 12_0402_5% 2 12_0402_5%
R687 1 Dbg@
26 CLK_14M_Dbg 1 R592
20
VDDSRC VDDSRC VDDSRC VDDSRC
VDDA GNDA PCI_SRC_STOP#
VDDPCI VDDPCI
2 33_0402_5%
19
X1 X2
CLK_MCH_BCLK
CLK_CPU1# R579 1
2 0_0402_5%
CLK_MCH_BCLK#
CPUCLKT0LP
14
CLK_CPU0
2 0_0402_5%
CLK_CPU_BCLK
R594 1
2 33_0402_5%
CLK_PCI2
32
SEL_24M/PCICLK2
CLK_PCI_LPC
R596 1
2 33_0402_5%
CLK_PCI1
27
SEL_PCI6/PCICLK1
2 0_0402_5%
CLK_DOT
CLK_REF
43
CLK_DREF_96M#
R601 1 GM@
2 0_0402_5%
CLK_DOT#
44
22
CLK_PCI_ICH
18 CLK_PCI_ICH
R605 1
2 33_0402_5%
CLK_PCI0
42 CLK_ENABLE#
CLK_ENABLE#_R
37
R743 2 0_0402_5% @
R612 1
+3VS
2 0_0402_5%
CLKIREF
9
15mil
CLK_ENABLE#_R 2 10K_0402_5%
1 R617
D_CK_SCLK
12,13 D_CK_SCLK
D_CK_SDATA
12,13 D_CK_SDATA
SRCCLKT9LP
CLK_SRC9
R588 1
2 0_0402_5%
CLK_PCIE_CARD
SRCCLKC9LP
2
CLK_SRC9# R590 1
2 0_0402_5%
CLK_PCIE_CARD#
CLKREQ9#
72
SRCCLKT8LP
70
SRCCLKC8LP
69
CLKREQ8#
71
SRCCLKT7LP
DOTT_96MHz/27MHz_NonspreadCLKREQ7#/48Mhz_1 DOTC_96MHz/27MHz_spread
SRCCLKT6LP
SRCCLKC6LP
ITP_EN/PCICLK_F0 VTT_PWRGD#/PD
SRCCLKT5LP
SRCCLKC5LP
GND
CLKREQ5#/PCICLK6
16
17
1
3
D
S
2 G
R638 4.7K_0402_5% 1 2 +3VS
Q50
D_CK_SCLK
2N7002_SOT23
1 2 R655 @ 1K_0402_5%
3
Q49 2N7002_SOT23
2
R642 @ 56_0402_5% R646 1K_0402_5% 1 2 1 2 R651 0_0402_5%
MCH_CLKSEL0 6 CPU_BSEL0 5
CLKSEL1 1 2 R650 @ 0_0402_5%
1 2 R652 0_0402_5%
CLK_PCIE_SATA#
CLK_PCIE_SATA 19
R607 1 R609 1
2 10K_0402_5% CLK_PCIE_ICH 2 0_0402_5%
60
CLK_SRC5
61
CLK_SRC5# R611 1
29
R614 1
2 10K_0402_5%
SATA_CLKREQ# 20 +3VS CLK_PCIE_ICH 20
CLK_PCIE_ICH#
2 0_0402_5%
CLK_PCIE_ICH# 20 +3VS
CLK_PCIE_LAN CLK_PCIE_LAN#
CLKREQ4#
57
R621 1
2 @ 10K_0402_5%
CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24 +3VS
2 0_0402_5%
CLK_PCIE_VGA
2 0_0402_5%
CLK_PCIE_VGA#
CLKREQ3#/PCICLK5
28
CLK_PCI5
R627 1
2 @ 10K_0402_5%
SRCCLKT2LP
52
CLK_SRC2
R630 1
2 0_0402_5%
CLK_MCH_3GPLL
GNDPCI
SRCCLKC2LP
53
CLK_SRC2# R632 1
2 0_0402_5%
CLK_MCH_3GPLL#
GNDPCI
CLKREQ2#
26
GNDREF
31 35
R634 1 R636 1
GND48
SRCCLKT1LP
50
CLK_SRC1
68
GNDSRC
SRCCLKC1LP
51
CLK_SRC1# R637 1
CLKREQ1#
46
LCD100/96/SRC0_TLP
47
CLK_SRC0
LCD100/96/SRC0_CLP
48
CLK_SRC0# R641 1 GM@
1 2 R653 @ 0_0402_5%
CPU_BSEL1 5
CLK_PCIE_VGA# 15 +3VS
2 0_0402_5%
R639 1 R640 1 GM@
CLK_PCIE_MINI1#
2 10K_0402_5% +3VS CLK_DREF_SSC 2 0_0402_5% 2 0_0402_5%
CLK_DREF_SSC#
R649 1K_0402_5% 1 2 1 2 R654 0_0402_5%
B
C
D
CLK_MCH_3GPLL 6 CLK_MCH_3GPLL# 6 MCH_CLKREQ# 6 CLK_PCIE_MINI1 26
3
CLK_PCIE_MINI1# 26 MINI1_CLKREQ# 26 CLK_DREF_SSC 6 CLK_DREF_SSC# 6
4
MCH_CLKSEL2 6 CPU_BSEL2 5
Compal Electronics, Inc.
Compal Secret Data 2007/1/15
2007/10/4
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1%
R644 @ 1K_0402_5%
Security Classification Issued Date
1 R600 1 R603 CLK_PCIE_MINI1 1 R606 CLK_PCIE_MINI1# 1 R608 CLK_PCIE_SATA 1 R610 CLK_PCIE_SATA# 1 R613 CLK_DREF_SSC 1 R615 CLK_DREF_SSC# 1 R618 CLK_DREF_96M 1 R620 CLK_DREF_96M# 1 R622 CLK_PCIE_CARD 1 R624 CLK_PCIE_CARD# 1 R626 CLK_MCH_3GPLL 1 R628 CLK_MCH_3GPLL# 1 R631 CLK_PCIE_LAN 1 R633 CLK_PCIE_LAN# 1 R635
+1.05VS
R648 8.2K_0402_5% CLKSEL2 1 2
MCH_CLKSEL1 6
CLK_PCIE_VGA 15
2 10K_0402_5% +3VS CLK_PCIE_MINI1 2 0_0402_5%
42
THRM_PAD THRM_PAD THRM_PAD THRM_PAD
2 @ 49.9_0402_1% 2 @ 49.9_0402_1%
CLK_PCIE_ICH#
CLK_PCIE_SATA# 19
62
2 0_0402_5%
R643 @ 1K_0402_5% R647 1K_0402_5% 1 2
CLK_PCIE_SATA
2 0_0402_5%
2 0_0402_5%
ICS9LPR325AKLFT_MLF72
+1.05VS
2 0_0402_5%
R623 1 PM@
GNDCPU
73 74 75 76
1
R645 8.2K_0402_5% CLKSEL0 1 2
1
2
+1.05VS
1
R602 1
CLK_SRC6# R604 1
R616 1
2
CLK_ENABLE#_R
+3VS
CLK_SRC6
CLK_SRC3# R625 1 PM@
21
1 R595 1 R597
CLK_PCIE_ICH
63
64
CLK_SRC3
15
CLK_PCIE_VGA
2
67
CLK_SRC4# R619 1
SRCCLKC3LP
2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1%
CLK_PCIE_VGA#
38
55
GNDSRC
CLK_PCIE_CARD# 27
1 R585 CLK_MCH_BCLK# 1 R587 CLK_CPU_BCLK 1 R589 CLK_CPU_BCLK# 1 R591
66
CLK_SRC4
1
2 G
2N7002_SOT23
20,24,26,27 ICH_SMBCLK
6,20,42
CLK_PCIE_CARD 27
56
4
CLK_MCH_BCLK
+3VS
58
SMBDAT
CLK_CPU_BCLK# 4
EXP_CLKREQ# 27
2 10K_0402_5%
59
SRCCLKT4LP
VF VGATE
D_CK_SDATA
S
3
D
1
S
20,24,26,27 ICH_SMBDATA
D
2 G
+3VS R629 4.7K_0402_5% Q48 1 2 +3VS
R593 1
SRCCLKC4LP
SMBCLK
SRCCLKT3LP
3
4
39
CLK_CPU_BCLK 4
3
CLKREQ6#
CLK_ENABLE# 1
2
CLK_MCH_BCLK# 6
CLK_CPU_BCLK#
5
SEL_PCI5/REF1
R581 1
-c o
6 CLK_DREF_96M#
C789 10U_0805_10V4Z
CLK_MCH_BCLK 6
2 0_0402_5%
SRCCLKC7LP
6 CLK_DREF_96M
2
1
+3VS
1
PM_STP_CPU# 20
CLK_CPU0# R582 1
13 6
PCICLK4/FCTSEL1
CLK_PCI_card
2 33_0402_5%
C788
0.047U_0402_16V7K 2
1
PM_STP_PCI# 20
10
CPUCLKT2_ITP/SRCCLKT10LP
REF0/FSLC/TEST_SEL
SEL_48M/PCICLK3
R599 1 GM@
PM_STP_PCI#
1
VDD48
33
R598 1
C787
CPUCLKC1LP
FSLB/TEST_MODE/24Mhz
CLK_DREF_96M
25
R576 0_0805_5% 1 2
40mil
0.047U_0402_16V7K
2 0_0402_5%
USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
CLK_ICH_14M
2
C786 0.047U_0402_16V7K
R577 1
45
34
C784 0.047U_0402_16V7K
+CLK_VDD1
CLK_CPU1
VDDREF
2
+CLK_VDD2 1 2 R575 2.2_0603_5%
CPUCLKT1LP
41
CLK_PCI4
1 C783 0.047U_0402_16V7K
PM_STP_CPU#
CLKSEL1
23
2
24
CLKSEL0
CLKSEL2
2
8
1 C782 0.047U_0402_16V7K
+CLK_VCCA 1
C785 10U_0805_10V4Z
7
2
11
CPU_STOP#
VDDCPU
CPUCLKC0LP
CLK_XTALOUT
1 C781 0.047U_0402_16V7K
20mil
14.31818MHz_20P_1BX14318BE1A
2
1 R583
CLK_REF 2 10K_0402_5%
ITP_EN/PCICLK_F0=0=SRC pair
2
2 +CLK_VDDREF 18 1_0603_5% 15mil 2 +CLK_VDD48 40 2.2_0603_5% 15mil
Y1 C791 33P_0402_50V8J 1 2
**SEL_PCI5=1=PCICLK5
2
1
12
+CLK_VDD1
1 C780 10U_0805_10V4Z
U1
30 36
CPU_ITP pair
2
H
Clock Generator
+CLK_VDD1
1
1 49 54 65
G
40mil
0.047U_0402_16V7K
+CLK_VDD1
1
F
R574 0_0805_5% 1 2
+3VS
C779
Table : ICS9LPR325 1
E
-c c
A
E
F
Title
Clock Generator Size B
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Monday, April 16, 2007 G
Sheet
14 H
of
44
5
4
2
PCIE_MTX_C_GRX_P[0..15]
8 PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
8 PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
D
PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P6
B
PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P2
CLK_PCIE_VGA# CLK_PCIE_VGA
18 PLTRST_VGA#
D_EC_SMB_DA1 D_EC_SMB_CK1
26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108
17 VGA_CRT_HSYNC 17 VGA_CRT_VSYNC 17 VGA_DDC_CLK 17 VGA_DDC_DATA
PCIE_MTX_C_GRX_N15 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12
VGA_CRT_HSYNC VGA_CRT_VSYNC VGA_DDC_CLK VGA_DDC_DATA
PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P6
16 DVI_DET 16 VGA_DVI_TXC16 VGA_DVI_TXC+
DVI_DET VGA_DVI_TXCVGA_DVI_TXC+
PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P4
16 VGA_DVI_TXD216 VGA_DVI_TXD2+
VGA_DVI_TXD2VGA_DVI_TXD2+
PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P3
16 VGA_DVI_TXD116 VGA_DVI_TXD1+
VGA_DVI_TXD1VGA_DVI_TXD1+
PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P2
16 VGA_DVI_TXD016 VGA_DVI_TXD0+
VGA_DVI_TXD0VGA_DVI_TXD0+
PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P5
ACES_88990-2D08 CONN@
L44 2 1 KC FBM-L11-201209-221LMAT_0805 PM@ L43 2 1 KC FBM-L11-201209-221LMAT_0805 PM@ 1 C527
A
1 C526 PM@ 680P_0603_50V7K 68P_0402_50V8J 2 2
2
PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P0 VGA_TV_CRMA
+2.5VS
C471
C520
0.1U_0402_16V4Z PM@ 2
1 0.1U_0603_25V7K
VGA_TV_COMPS 17
VGA_CRT_R
VGA_CRT_R 17
VGA_CRT_G
VGA_CRT_G 17
VGA_CRT_B
VGA_CRT_B 17
VGA_TZCLKVGA_TZCLK+
VGA_TZCLK- 16 VGA_TZCLK+ 16
VGA_TZOUT2VGA_TZOUT2+
VGA_TZOUT2- 16 VGA_TZOUT2+ 16
VGA_TZOUT1VGA_TZOUT1+
VGA_TZOUT1- 16 VGA_TZOUT1+ 16
VGA_TZOUT0VGA_TZOUT0+
VGA_TZOUT0- 16 VGA_TZOUT0+ 16
VGA_TXCLKVGA_TXCLK+
VGA_TXCLK- 16 VGA_TXCLK+ 16
VGA_TXOUT2VGA_TXOUT2+
VGA_TXOUT2- 16 VGA_TXOUT2+ 16
VGA_TXOUT1VGA_TXOUT1+
VGA_TXOUT1- 16 VGA_TXOUT1+ 16
VGA_TXOUT0VGA_TXOUT0+
VGA_TXOUT0- 16 VGA_TXOUT0+ 16
I2CC_SDA I2CC_SCL ENVDD
I2CC_SDA 16 I2CC_SCL 16 ENVDD 16
ENBKL VGA_DVI_SDATA VGA_DVI_SCLK
C
B
ENBKL 8,28 VGA_DVI_SDATA 16 VGA_DVI_SCLK 16
+2.5VS +3VS
+5VS
1
VGA_TV_LUMA 17
VGA_TV_COMPS
+3VS
28,29,38 EC_SMB_DA1
160mil(4A)
VGA_TV_CRMA 17
VGA_TV_LUMA
ACES_88990-2D08 CONN@
B+
C525
PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P1
1
D_EC_SMB_DA1
3
Q46 PM@ 2N7002_SOT23
1
2 G
+MXM_B+
160mil(4A)
110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232
2 0.1U_0402_16V4Z PM@
28,29,38 EC_SMB_CK1
1
3 S
PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P10
VGA_ON 30 +5VS
14 CLK_PCIE_VGA# 14 CLK_PCIE_VGA
PEX_RX1# GND PEX_RX1 PEX_TX1# GND PEX_TX1 PEX_RX0# GND PEX_RX0 PEX_TX0# GND PEX_TX0 PEX_REFCLK# PRSNT1# PEX_REFCLK TV_C/HDTV_Pr CLK_REQ# GND PEX_RST# TV_Y/HDTV_Y RSVD GND RSVD TV_CVBS/HDTV_Pb SMB_DAT GND SMB_CLK VGA_RED THERM# GND VGA_HSYNC VGA_GRN VGA_VSYNC GND DDCA_CLK VGA_BLU DDCA_DAT GND IGP_UCLK# LVDS_UCLK# IGP_UCLK LVDS_UCLK GND GND RSVD LVDS_UTX3# RSVD LVDS_UTX3 RSVD GND IGP_UTX2# LVDS_UTX2# IGP_UTX2 LVDS_UTX2 GND GND IGP_UTX1# LVDS_UTX1# IGP_UTX1 LVDS_UTX1 GND GND IGP_UTX0# LVDS_UTX0# IGP_UTX0 LVDS_UTX0 GND GND IGP_LCLK#/DVI_B_CLK# LVDS_LCLK# IGP_LCLK/DVI_B_CLK LVDS_LCLK DVI_B_HPD/GND GND RSVD LVDS_LTX3# RSVD LVDS_LTX3 GND GND IGP_LTX2#/DVI_B_TX2# LVDS_LTX2# IGP_LTX2/DVI_B_TX2 LVDS_LTX2 GND GND IGP_LTX1#/DVI_B_TX1# LVDS_LTX1# IGP_LTX1/DVI_B_TX1 LVDS_LTX1 GND GND IGP_LTX0#/DVI_B_TX0# LVDS_LTX0# IGP_LTX0/DVI_B_TX0 LVDS_LTX0 DVI_A_HPD GND DVI_A_CLK# DDCC_DAT DVI_A_CLK DDCC_CLK GND LVDS_PPEN DVI_A_TX2# LVDS_BL_BRGHT DVI_A_TX2 LVDS_BLEN GND DDCB_DAT DVI_A_TX1# DDCB_CLK DVI_A_TX1 2V5RUN GND GND DVI_A_TX0# 3V3RUN DVI_A_TX0 3V3RUN GND 3V3RUN GND GND
D
PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P11
109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P0
2 G
PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P12
PRSNT2# PEX_TX15# PEX_TX15 GND PEX_TX14# PEX_TX14 GND PEX_TX13# PEX_TX13 GND PEX_TX12# PEX_TX12 GND PEX_TX11# PEX_TX11 GND PEX_TX10# PEX_TX10 GND PEX_TX9# PEX_TX9 GND PEX_TX8# PEX_TX8 GND PEX_TX7# PEX_TX7 GND PEX_TX6# PEX_TX6 GND PEX_TX5# PEX_TX5 GND PEX_TX4# PEX_TX4 GND PEX_TX3# PEX_TX3 GND PEX_TX2# PEX_TX2
PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P1
+1.8VS
140mil(3.5A)
S
PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P13
PEX_RX15# PEX_RX15 GND PEX_RX14# PEX_RX14 GND PEX_RX13# PEX_RX13 GND PEX_RX12# PEX_RX12 GND PEX_RX11# PEX_RX11 GND PEX_RX10# PEX_RX10 GND PEX_RX9# PEX_RX9 GND PEX_RX8# PEX_RX8 GND PEX_RX7# PEX_RX7 GND PEX_RX6# PEX_RX6 GND PEX_RX5# PEX_RX5 GND PEX_RX4# PEX_RX4 GND PEX_RX3# PEX_RX3 GND PEX_RX2# PEX_RX2 GND
2 4 6 8 10 12 14 16 18 20 22 24
-c c
PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P14
25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107
1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN RUNPWROK 5VRUN GND GND GND
-c o
PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P15
PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC GND GND GND GND
VF
1 3 5 7 9 11 13 15 17 19 21 23
+MXM_B+
JP19B
D
8 PCIE_GTX_C_MRX_P[0..15]
JP19A
C
1
PCIE_MTX_C_GRX_N[0..15]
8 PCIE_MTX_C_GRX_N[0..15]
D
3
PM@
D_EC_SMB_CK1 A
Q47 2N7002_SOT23
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
MXM Connector Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
15
of
44
5
4
3
2
TXOUT0TXOUT0+
LCD POWER CIRCUIT +LCDVDD
3
2
1 2
2
1
3
R13
TZOUT2TZOUT2+
+LCDVDD
1
S
1
C17
4.7U_0805_10V4Z 2
R12 100K_0402_5%
TZCLKTZCLK+
W=60mils
0.047U_0402_16V7K 2
Q3 2N7002_SOT23
2 G 1
ENVDD
1
3
15
GM@ 2 0_0402_5% PM@ 2 0_0402_5%
D
4.7U_0805_10V4Z
Q1 AO3413_SOT23-3
2
1
1 1K_0402_5% 1 C16
S
1
G
2 R9
TZOUT0TZOUT0+ TZOUT1TZOUT1+
D
2 G
1 2 RP10 1 2 RP12 1 2 RP14 1 2 RP16 1 2 RP18
C19
S
D Q2 2N7002_SOT23
R14
RP8 1
R10 100K_0402_5%
1 2
TXCLKTXCLK+
1
1 R11 300_0603_5%
8 GMCH_ENVDD
TXOUT2TXOUT2+
W=60mils
D
1 2 RP6
+3VS
+3V
1 2 RP4
TXOUT1TXOUT1+
2
4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@
1
VGA_TXOUT0VGA_TXOUT0+ 0_0404_4P2R_5% VGA_TXOUT1VGA_TXOUT1+ 0_0404_4P2R_5% VGA_TXOUT2VGA_TXOUT2+ 0_0404_4P2R_5% VGA_TXCLKVGA_TXCLK+ 0_0404_4P2R_5% VGA_TZOUT0VGA_TZOUT0+ 0_0404_4P2R_5% VGA_TZOUT1VGA_TZOUT1+ 0_0404_4P2R_5% VGA_TZOUT2VGA_TZOUT2+ 0_0404_4P2R_5% VGA_TZCLKVGA_TZCLK+ 0_0404_4P2R_5%
VGA_TXOUT0- 15 VGA_TXOUT0+ 15 VGA_TXOUT1- 15 VGA_TXOUT1+ 15 VGA_TXOUT2- 15 VGA_TXOUT2+ 15 VGA_TXCLK- 15 VGA_TXCLK+ 15 VGA_TZOUT0- 15 VGA_TZOUT0+ 15
D
VGA_TZOUT1- 15 VGA_TZOUT1+ 15 VGA_TZOUT2- 15 VGA_TZOUT2+ 15 VGA_TZCLK- 15 VGA_TZCLK+ 15
C10 I2CC_SCL I2CC_SDA
0.1U_0402_16V4Z
1 2
GMCH_LCD_CLK 4 GMCH_LCD_DATA 3 GM@ 0_0404_4P2R_5%
GMCH_LCD_CLK 8 GMCH_LCD_DATA 8
-c c
2
RP2
TXOUT0TXOUT0+
+3VS
2 1
RP3
1
TXOUT1TXOUT1+
DAC_BRIG
R8
1
4.7K_0402_5%
INVTPWM
DISPOFF#
DISPOFF#
1
2
1
2
C15
220P_0402_50V7K
C11
2 1
RP7
TXCLKTXCLK+
220P_0402_50V7K
2 1
RP9
C
TZOUT0TZOUT0+ TZOUT1TZOUT1+
LCD/PANEL BD. Conn.
TZOUT2TZOUT2+
JP1
5 P
1
Y
A
2
R501 1
15 VGA_DVI_TXD015 VGA_DVI_TXD0+
1 2 RP45
15 VGA_DVI_TXD115 VGA_DVI_TXD1+
2 1
+3VS
1
RP1
2 1 RP46
1
10K_0402_5% @
@
2 180_0402_1% DVI_TXD1@ DVI_TXD1+ DVI_TXD2DVI_TXD2+ 180_0402_1% @
1 2 RP47
4 3 0_0404_4P2R_5% DVI@
2 180_0402_1% @ DVI_TXC+ DVI_TXC-
Optional for ATI M66M/M7x
For GMCH DPST
1 2
4 5
23 24
25 26 27 28 31 32 8
1
1.1A_6VDC_FUSE C23 DVI@ 0.1U_0402_16V4Z DVI@
TMDS_DATA0TMDS_DATA0+
+5V
14
R17 4.7K_0402_5% DVI@
TMDS_DATA1TMDS_DATA1+ DDC_CLOCK
TMDS_DATA3TMDS_DATA3+
DDC_DATA
R18 4.7K_0402_5% DVI@
B
3
Q35 2N7002_SOT23 DVI@ 1
6 7
VGA_DVI_SCLK 15
3
VGA_DVI_SDATA 15
Q36 2N7002_SOT23 DVI@
TMDS_DATA4TMDS_DATA4+ R360
TMDS_DATA5TMDS_DATA5+
Hot Plug Detect
16
TMDS_Clock+ TMDS_Clock-
Shield Shield Shield Shield Shield Shield
+5VS
+3VS
1
TMDS_DATA2TMDS_DATA2+
2
RB411DT146_SOT23-3 DVI@
TMDS_DATA2/4 shield TMDS_DATA1/3 shield TMDS_DATA0/5 shield TMDS_Clock shield
Analog VSYNC
GND
3 11 19 22
1
2 20K_0402_5% DVI@ R361
DVI_DET
DVI_DET
15
100K_0402_5% DVI@
D20 SKS10-04AT_TSMA @
15
SUYIN_070939FR024S531PL CONN@
A
+INVPWR_B+
9 10
D7 2
+DVI_VCC
JP15 17 18
12 13
2
2
DVI-D Connector
2 180_0402_1% DVI_TXD0@ DVI_TXD0+
3
Q56 2N7002_SOT23
F2 1 1
20 21 R504 1
2 G
2
INVTPWM
D
+3VS
4 3 0_0404_4P2R_5% DVI@ R502 1 3 4 0_0404_4P2R_5% DVI@ 3 4 0_0404_4P2R_5% DVI@ 1 R503
W=40mils +DVI_VCC
2 G
TXCLKTXCLK+
S
R746
GMCH_TZCLK- 8 GMCH_TZCLK+ 8
0_0404_4P2R_5%
S
TXOUT2+ TXOUT2-
15 VGA_DVI_TXC+ 15 VGA_DVI_TXC-
3
NC7SZ14P5X_NL_SC70-5 @
GMCH_TZCLKGMCH_TZCLK+
2 G
TXOUT1TXOUT1+
DPST_PWM 8
G
4
NC
U48 INVTPWM
GMCH_TZOUT2- 8 GMCH_TZOUT2+ 8
0_0404_4P2R_5%
W=60mils TXOUT0TXOUT0+
15 VGA_DVI_TXD215 VGA_DVI_TXD2+
+3VS
GMCH_TZOUT2GMCH_TZOUT2+
+LCDVDD
ACES_88242-4001 CONN@
B
GMCH_TZOUT1- 8 GMCH_TZOUT1+ 8
0_0404_4P2R_5%
S
USB20_N3_R USB20_P3_R
2 2
GMCH_TZOUT1GMCH_TZOUT1+
D
0_0603_5% R3 1 R4 1 0_0603_5%
USB20_N3 USB20_P3
INVT_PWM 28
VF
20 20
2 0_0402_5%
C
GMCH_TZOUT0- 8 GMCH_TZOUT0+ 8
0_0404_4P2R_5%
D
TZCLKTZCLK+
1
GMCH_TZOUT0GMCH_TZOUT0+
1
TZOUT2+ TZOUT2-
R7
GMCH_TXCLK- 8 GMCH_TXCLK+ 8
0_0404_4P2R_5%
2
TZOUT1+ TZOUT1-
DAC_BRIG 28
INVTPWM DISPOFF#
GMCH_TXCLKGMCH_TXCLK+
1
TZOUT0TZOUT0+
GND 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
GMCH_TXOUT2- 8 GMCH_TXOUT2+ 8
0_0404_4P2R_5%
2
I2CC_SCL I2CC_SDA
15 I2CC_SCL 15 I2CC_SDA
GND 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
TZCLKTZCLK+
GMCH_TXOUT2GMCH_TXOUT2+
1
+3VS
DAC_BRIG
GMCH_TXOUT1- 8 GMCH_TXOUT1+ 8
0_0404_4P2R_5%
2
+INVPWR_B+
41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
-c o
42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
2 1 RP11 2 1 RP13 2 1 RP15 2 1 RP17
GMCH_TXOUT0- 8 GMCH_TXOUT0+ 8
GMCH_TXOUT1GMCH_TXOUT1+
1
D4 2 RB751V_SOD323
1
2
BKOFF#
BKOFF#
TXOUT2TXOUT2+
220P_0402_50V7K
GMCH_TXOUT0GMCH_TXOUT0+
0_0404_4P2R_5%
2
28
RP5
2
C9
2 1
3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@
+LCDVDD
A
+3VS L31 2 1 KC FBM-L11-201209-221LMAT_0805
W=40mils
L29 2 1 KC FBM-L11-201209-221LMAT_0805 C432
1
1
B+ 1
2
C433
1
C18 0.1U_0402_16V4Z
2
680P_0603_50V7K 68P_0402_50V8J 2 2
5
C14 10U_0805_10V4Z
1
2
C8 0.1U_0402_16V4Z
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
2
Title
LVDS & DVI Connector Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
16
of
44
B
C
D
CRT Connector
E
W=40mils +5VS
+R_CRT_VCC D19
1
1
D3 D2 D1 @ @ @ DAN217_SC59 DAN217_SC59 DAN217_SC59 1
A
2
1
1
W=40mils
2 1.1A_6VDC_FUSE 1
C430 0.1U_0402_16V4Z 2
3
2
1 R685 0_0603_5% 1 R686 0_0603_5%
3
2
2
2
@
2
@
+3VS
3
RB411DT146_SOT23-3 +2.5VS
+CRT_VCC
F1
1
1
CRT_R
2 FCM2012C-800_0805
CRT_R_2
1
2 FCM2012C-800_0805
CRT_G_2
1
2 FCM2012C-800_0805
CRT_B_2
1 L5
CRT_G L3 L1 1
R1 C12 2
1
1
C2
150_0402_1%
2 2 10P_0402_50V8J 10P_0402_50V8J
change to 47pf for ATI M66/M7x +CRT_VCC
5
2 R359
P
2
RP51
G
Y
1 L32
CRT_HSYNC_2 2 FCM1608C-121T_0603
1 L30
CRT_VSYNC_2 2 FCM1608C-121T_0603
1 10K_0402_5%
C435 10P_0402_50V8J
1
1
2
2
C436
1
CRT_DET 20 DSUB_12
R763 100K_0402_5%
1
C434
10P_0402_50V8J
16 17
SUYIN_070549FR015S208CR CONN@
2 100P_0402_50V8J
C437 2 68P_0402_50V8J 1
2
SN74AHCT1G125DCKR_SC70-5
DSUB_15
+CRT_VCC
2
C431 68P_0402_50V8J
+CRT_VCC
1 C438
2 0.1U_0402_16V4Z
5
1
4 3
A
C3 10P_0402_50V8J
CRT_HSYNC_1
4
P
4 3 RP50
2
2
CRT_VSYNC
2
A
+CRT_VCC
U19
Y
CRT_VSYNC_1
4
Place closed to chipset
G
8 GMCH_TV_LUMA 8 GMCH_TV_CRMA
4 3 RP49
CRT_HSYNC
U18
OE#
8 GMCH_CRT_R 8 GMCH_TV_COMPS
RP48
CRT_VSYNC CRT_HSYNC 33_0404_4P2R_5% CRT_B CRT_G 0_0404_4P2R_5% CRT_R TV_COMPS 0_0404_4P2R_5% TV_LUMA TV_CRMA 0_0404_4P2R_5%
1
-c o
8 GMCH_CRT_B 8 GMCH_CRT_G
1 2 GM@ 1 2 GM@ 1 2 GM@ 1 2 GM@
3
8 GMCH_CRT_VSYNC 8 GMCH_CRT_HSYNC
4 3
1
2 0.1U_0402_16V4Z
OE#
1 C439
1
C7 C5 10P_0402_50V8J 10P_0402_50V8J 2 2
-c c
150_0402_1%
1 C6
2 10P_0402_50V8J
2
2
150_0402_1%
2
R2
1
R6
1
1
1
CRT_B
JP14 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
VF
1
1
pull-up 2.2k on GPU side 1
VGA_DDC_DATA 15
1
3
D
S
1
GMCH_CRT_DATA 8
2 G
D
Q20 2N7002_SOT23 DSUB_15
R398 GM@ 0_0402_5% 2 1
3 S
4.7K_0402_5% 1
DSUB_12
2 R391 PM@ 0_0402_5%
2 G
2
R384 2
3
TV-OUT Conn.
Place closed to chipset
3
+3VS
Q21 2N7002_SOT23
2 1 R399 GM@ 0_0402_5%
GMCH_CRT_CLK 8 3
1
2 R392 PM@ 0_0402_5%
VGA_DDC_CLK 15
pull-up 2.2k on GPU side
3
RP55
R381 4.7K_0402_5%
D14 D24 D25 @ @ @ DAN217_SC59 DAN217_SC59 DAN217_SC59
2
1 2
1
1 2 RP54
3
RP53
2
15 VGA_TV_LUMA 15 VGA_TV_CRMA
1 2
CRT_VSYNC CRT_HSYNC 0_0404_4P2R_5% CRT_B CRT_G 0_0404_4P2R_5% CRT_R TV_COMPS 0_0404_4P2R_5% TV_LUMA TV_CRMA 0_0404_4P2R_5%
1
15 VGA_CRT_R 15 VGA_TV_COMPS
RP52
4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@
3
15 VGA_CRT_B 15 VGA_CRT_G
1 2
2
15 VGA_CRT_VSYNC 15 VGA_CRT_HSYNC
SN74AHCT1G125DCKR_SC70-5
+3VS
TV_LUMA
1
2 FCM1608C-121T_0603
1
2 FCM1608C-121T_0603
1
2 FCM1608C-121T_0603
L42
TV_CRMA
L40
TV_COMPS
R413
1
R205
1
1
L18
R416
C211
150_0402_1% 2
2
2
150_0402_1%
150_0402_1%
4
1
C510
1
C514
1
GM@ 2 2 6P_0402_50V8K GM@ GM@ 6P_0402_50V8K 6P_0402_50V8K 2
1
C216 GM@ 6P_0402_50V8K 2
JP24 TV_CRMA_1 TV_COMPS_1 TV_LUMA_1
C508
1
1
3 6 7 5 2 4 1 8 9
C515 GM@ GM@ 6P_0402_50V8K 2 2 6P_0402_50V8K
SUYIN_030107FR007SX08FU CONN@
4
change to 47pf for ATI M66/M7x P/N: SE071470J80 ( S CER CAP 47P 50V J NPO 0402 )
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
CRT & TV-OUT Connector Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
17
of
44
5
4
3
2
1
+3VS U42B
R144 1
2 8.2K_0402_5%
PCI_STOP#
R139 1
2 8.2K_0402_5%
PCI_TRDY#
R145 1
2 8.2K_0402_5%
PCI_FRAME#
R137 1
2 8.2K_0402_5%
PCI_PLOCK#
R122 1
2 8.2K_0402_5%
PCI_IRDY#
R124 1
2 8.2K_0402_5%
PCI_SERR#
R138 1
2 8.2K_0402_5%
PCI_PERR#
+3VS
PCI_PIRQA#
2 8.2K_0402_5%
PCI_PIRQB#
R136 1
2 8.2K_0402_5%
PCI_PIRQC#
R140 1
2 8.2K_0402_5%
PCI_PIRQD#
R108 1
2 8.2K_0402_5%
PCI_PIRQE#
R111 1
2 8.2K_0402_5%
PCI_PIRQF#
R112 1
2 8.2K_0402_5%
PCI_PIRQG#
R134 1
2 8.2K_0402_5%
PCI_PIRQH#
R135 1
2 8.2K_0402_5%
PCI_REQ#0
R125 1
2 8.2K_0402_5%
PCI_REQ#1
R146 1
2 8.2K_0402_5%
PCI_REQ#2
R142 1
2 8.2K_0402_5%
PCI_REQ#3
R666 1
2 8.2K_0402_5%
PCI_REQ#4
R667 1
2 8.2K_0402_5%
PCI_REQ#5
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
A3 B4 C5 B5 AE5 AD5 AG4 AH4 AD9
D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8
PCI_REQ#0 PCI_GNT#0 PCI_REQ#1
C/BE0# C/BE1# C/BE2# C/BE3#
B15 C12 D12 C15
PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
A7 E10 B18 A12 C9 E11 B10 F15 F14 F16
PCI_IRDY# PCI_PAR PCI_RST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
PLTRST# PCICLK PME#
C26 A9 B19
PLT_RST# CLK_PCI_ICH PCI_PME#
G8 F7 F8 G7
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PCI
Interrupt
PIRQA# PIRQB# PIRQC# PIRQD#
I/F
GPIO2 / PIRQE# GPIO3 / PIRQF# GPIO4 / PIRQG# GPIO5 / PIRQH#
MISC
RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]
RSVD[6] RSVD[7] RSVD[8] RSVD[9] MCH_SYNC#
PCI_REQ#0 23 PCI_GNT#0 23
PCI_REQ#2
D
PCI_REQ#3 PCI_REQ#4 PCI_GNT#4 PCI_REQ#5 PCI_GNT#5 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3
23 23 23 23
PCI_IRDY# 23 PCI_PAR 23 PCI_RST# 23,26,27 PCI_DEVSEL# 23 PCI_PERR# 23 PCI_SERR# 23 PCI_STOP# 23 PCI_TRDY# 23 PCI_FRAME# 23
Place closely pin B10 CLK_PCI_ICH
PLT_RST# 6,20,22,24,28 CLK_PCI_ICH 14 PCI_PME#
PCI_PIRQE#
AE9 AG8 AH8 F21 AH20
R123 10_0402_5% @
23
MCH_ICH_SYNC#
C126 10P_0402_50V8J @
C
1
2
6
ICH7_BGA652~D
1
0
PCI
1
1
LPC*
1
Y A
4
NC7SZ08P5X_NL_SC70-5
R316 100K_0402_5%
+3VS
U9 2 B
1
Y A
NC7SZ08P5X_NL_SC70-5
PLT_RST_BUF# 26
1
SPI
4
2 R321
1 100_0402_5% PM@
1
1
3
0
U8 2 B
2
PLT_RST#
Boot BIOS Loaction
5
+3VS
Boot BIOS Strap
PCI_GNT#5 PCI_GNT#4
B
P
2 1K_0402_5% PCI_GNT#4 @
G
1
5
2 1K_0402_5% PCI_GNT#5 @
P
1
R126
G
R121
VF
B
2 8.2K_0402_5%
R120 1
REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ4# / GPIO22 GNT4# / GPIO48 GPIO1 / REQ5# GPIO17 / GNT5#
-c o
C
R109 1
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
2
PCI_DEVSEL#
1
2 8.2K_0402_5%
E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6
3
D
R143 1
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
-c c
23 PCI_AD[0..31]
PLTRST_VGA# 15
R317 100K_0402_5% PM@
2
PM@
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
ICH7M(1/4)-PCI Size
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Date:
Monday, April 16, 2007
Sheet 1
18
of
44
5
4
3
2
1
+RTCVCC
NC
OUT
4
2
NC
IN
1
D
+RTCVCC
R281 332K_0402_1%
ICH_RTCX2
AB1 AB2
ICH_RTCRST#
AA3 ICH_INTVRMEN SM_INTRUDER#
2
W1 Y1 Y2 W3
C292 1U_0603_10V4Z 1 2
High = Internal VR Enable
INTVRMEN INTRUDER#
+3VS
EE_CS EE_SHCLK EE_DOUT EE_DIN
V3
LAN_CLK
U3
LAN_RSTSYNC
U5 V4 T5
LAN_RXD0 LAN_RXD1 LAN_RXD2
1
U7 V6 V7
R298
2
30 HDA_RST_MDC#
U1 R6
31 HDA_SDIN0 30 HDA_SDIN1
30 HDA_SDOUT_MDC
1 R279
31 HDA_SYNC_AUDIO
1 R273
HDA_SYNC_ICH 2 39_0402_5%
31 HDA_RST_AUDIO#
1 R300
HDA_RST_ICH# 2 39_0402_5%
31 HDA_SDOUT_AUDIO
1 R299
HDA_SDOUT_ICH 2 39_0402_5%
R5
ACZ_RST#
T2 T3 T1
ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2
T4
SATALED#
22 SATA_DTX_C_IRX_N0 22 SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 SATA_ITX_DRX_N0 SATA_ITX_DRX_P0
AF3 AE3 AG2 AH2
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
22 SATA_DTX_C_IRX_N1 22 SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_ITX_DRX_N1 SATA_ITX_DRX_P1
AF7 AE7 AG6 AH6
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
CLK_PCIE_SATA# CLK_PCIE_SATA
AF1 AE1
SATA_CLKN SATA_CLKP
SATA_LED#
14 CLK_PCIE_SATA# 14 CLK_PCIE_SATA
1
2 24.9_0402_1%
AH10 SATARBIAS AG10
8.2K_0402_5%
SATA_ITX_DRX_N0
1 R203
2
1 R199
2
VF
4.7K_0402_5%
IDE_IRQ
1 C290 1 C291
SATA_ITX_C_DRX_N0 2 3900P_0402_50V7K SATA_ITX_C_DRX_P0 2 3900P_0402_50V7K
SATA_ITX_DRX_N1 1 SATAX2@ C281 SATA_ITX_DRX_P1 1 SATAX2@ C280
SATA_ITX_C_DRX_N1 2 3900P_0402_50V7K SATA_ITX_C_DRX_P1 2 3900P_0402_50V7K
SATA_ITX_DRX_P0
A
22 IDE_DIORDY 22 IDE_IRQ 22 IDE_DDACK# 22 IDE_DIOW # 22 IDE_DIOR#
IDE_DIORDY
AE22 AH28
CPUSLP#
AG27
TP1 / DPRSTP# TP2 / DPSLP#
AF24 AH25
DPRSTP# R260 1 DPSLP# R261 1
IDE_DIORDY IDE_IRQ IDE_DDACK# IDE_DIOW # IDE_DIOR#
D
26,28 26,28 26,28 26,28
H_FERR#
EC_GA20 H_A20M#
AG26
AG24
H_PW RGOOD
IGNNE# INIT3_3V# INIT# INTR
AG22 AG21 AF22 AF25
H_IGNNE#
RCIN#
AG23
EC_KBRST#
AF23 AH24
H_SMI# H_NMI
STPCLK#
AH22
H_STPCLK#
THERMTRIP#
AF26
THRMTRIP_ICH#
SMI# NMI
IDE
AG16 AH16 AF16 AH15 AF15
IORDY IDEIRQ DDACK# DIOW# DIOR#
R250
1
56_0402_5%
LPC_FRAME# 26,28
2
1 R271 10K_0402_5%
H_INIT# H_INTR
DA0 DA1 DA2
AH17 AE17 AF17
IDE_DA0 IDE_DA1 IDE_DA2
DCS1# DCS3#
AE16 AD16
IDE_DCS1# IDE_DCS3#
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15
IDE_DD0 IDE_DD1 IDE_DD2 IDE_DD3 IDE_DD4 IDE_DD5 IDE_DD6 IDE_DD7 IDE_DD8 IDE_DD9 IDE_DD10 IDE_DD11 IDE_DD12 IDE_DD13 IDE_DD14 IDE_DD15
DDREQ
AE15
IDE_DDREQ
+3VS
EC_GA20 28 H_A20M# 4
0_0402_5% H_DPRSTP# 0_0402_5% H_DPSLP#
2 2
H_DPRSTP# 4,42 H_DPSLP# 4
H_FERR# 4
H_PW RGOOD 4 H_IGNNE# H_INIT# H_INTR
H_SMI# H_NMI
4
4 4
R272
1 10K_0402_5%
2
+3VS
C
EC_KBRST# 28
4 4
H_STPCLK# 4
R258 1
2 24.9_0402_1%
IDE_DA[0..2]
22
H_THERMTRIP#
2 R257
H_THERMTRIP# 4,6
1 56_0402_5%
+1.05VS
IDE_DCS1# 22 IDE_DCS3# 22 IDE_DD[0..15]
22
MAINPW ON 35,36,38 B
R189 @ 330_0402_5% 1 2
+1.05VS
C
Q10
2 B E
IDE_DDREQ
22
2SC2411K_SOT23 @
H_THERMTRIP#
ICH7_BGA652~D
SATAX1@ SATA_DTX_C_IRX_N1 1 2 R656 1K_0402_5% SATA_DTX_C_IRX_P1 1 SATAX1@ 2 1K_0402_5% R657
SATA_ITX_C_DRX_N0 22 SATA_ITX_C_DRX_P0 22
SATA_ITX_C_DRX_N1 22 SATA_ITX_C_DRX_P1 22
SATA_RXn/p need tie to ground when SATA port no used
close ICH8
2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
5
2
LPC_DRQ#1 26
FERR#
SATARBIASN SATARBIASP
10mils width less than 500mils
+3VS
A20GATE A20M#
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LPC_FRAME#
GPIO49 / CPUPWRGD
ACZ_SDOUT
AF18
R242
B
AB3
SATA
31 HDA_BITCLK_AUDIO
LFRAME#
H_FERR#
ACZ_BCLK ACZ_SYNC
SATA_LED#
28
2 HDA_BITCLK_ICH 39_0402_5%
HDA_SDOUT_ICH 2 39_0402_5%
AC3 AA5
-c o
1 R310
LDRQ0# LDRQ1# / GPIO23
AC-97/AZALIA
HDA_BITCLK_ICH 2 39_0402_5% HDA_SYNC_ICH 2 39_0402_5% HDA_RST_ICH# 2 39_0402_5%
1 R293 1 R292 1 R301
30 HDA_BITCLK_MDC 30 HDA_SYNC_MDC SATA_LED#
AA6 AB5 AC4 Y6
LAN_TXD0 LAN_TXD1 LAN_TXD2
10K_0402_5% C
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LAD0 LAD1 LAD2 LAD3
LAN
ICH_INTVRMEN
RTCRST#
W4 Y5
R754 1 2 @ 10K_0603_5%
close to RAM door
RTXC1 RTCX2
3
1
+RTCVCC
1 2 R264 20K_0402_5%
+1.05VS U42A
RTC
C286 18P_0402_50V8J 2 1
1
SM_INTRUDER#
3
-c c
32.768KHZ_12.5P_MC-306
LPC
1M_0402_5%
2
ICH_RTCX1
X1
R263 10M_0402_5% 2 1
R265
CPU
1
C287 18P_0402_50V8J 2 1
2
Title
ICH7M(2/4)-LAN,IDELPC,RTC Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
19
of
44
5
4
3
2
1
+3V
SERIRQ
8.2K_0402_5% R270 1 2
PM_CLKRUN#
10K_0402_5% R658 1 2
ICH_VGATE
8.2K_0402_5% R309 1 2 @
EC_THERM#
R157 2.2K_0402_5%
28 PM_CLKRUN# 22 IDE_HRESET#
150_0402_1% R311 1 2
XDP_DBRESET#
1K_0402_5% R302 1 2
ICH_PCIE_WAKE#
10K_0402_5% R290 1 2
SPI_CS#1
ICH_PCIE_WAKE# SERIRQ EC_THERM#
F20 AH21 AF20
WAKE# SERIRQ THRM#
1 ICH_VGATE AD22 0_0402_5%
28
AC21 AC18 E21
EC_SMI#
EC_SMI#
PWRBTN#
C23
PBTN_OUT#
LAN_RST#
C19
RSMRST#
VRMPWRGD
GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35 / SATAREQ# GPIO38 GPIO39
GPIO
GPIO6 GPIO7 GPIO8
SPI_MOSI ICH7_BGA652~D SPI_MISO
SMBALERT#
1 2
PM_DPRSLPVR 6,42
PBTN_OUT# 28 PLT_RST# 6,18,22,24,28
No used Integrated LAN, connecting to PLT_RST#
SB_RSMRST#
Y4
EC_SCI#
E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20
EC_SCI#
100K_0402_5% +3VS 2 1 R278
28
2
EC_LID_OUT# 28
1 D15
ACIN
28,38
@ R453 2 1 0_0402_5% Q14 MMBT3906_NL_SOT23-3 SB_RSMRST#
RB751V_SOD323
SATA_CLKREQ# 14
R259 10K_0402_5%
1 R325
For Express Card
PROJECT_ID1
27 27 27 27
PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P1 PCIE_ITX_C_PRX_N1 PCIE_ITX_C_PRX_P1
+3V
26 26 26 26
PCIE_PTX_C_IRX_N4 PCIE_PTX_C_IRX_P4 PCIE_ITX_C_PRX_N4 PCIE_ITX_C_PRX_P4
1 R294 1 R320 1 R296 1 R668
1 R512 1 R513
2 USB_OC#4 10K_0402_5% 2 USB_OC#6 10K_0402_5%
2 1
1 1
C162 2 C158 2
1 1
PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PCIE_ITX_PRX_N3 PCIE_ITX_PRX_P3
K26 K25 J28 J27
PCIE_PTX_C_IRX_N4 PCIE_PTX_C_IRX_P4 PCIE_ITX_PRX_N4 PCIE_ITX_PRX_P4
M26 M25 L28 L27
0.1U_0402_16V7K 0.1U_0402_16V7K
0.1U_0402_16V7K 0.1U_0402_16V7K
2 USB_OC#1 10K_0402_5% 2 USB_OC#3 10K_0402_5% 2 USB_OC#5 10K_0402_5% 2 USB_OC#7 10K_0402_5%
R670 100K_0402_5%
D33
C166 2 C168 2
27
USB_OC#0
27
USB_OC#2
P26 P25 N28 N27 T25 T24 R28 R27
SPI_CS#1
R2 P6 P1
SPI_MOSI SPI_MISO
P5 P2
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7
D3 C4 D5 D4 E5 C3 A2 B3
CRT_DET#
PERn2 PERp2 PETn2 PETp2 PERn3 PERp3 PETn3 PETp3 PERn4 PERp4 PETn4 PETp4 PERn5 PERp5 PETn5 PETp5 PERn6 PERp6 PETn6 PETp6
SPI_CLK SPI_CS# SPI_ARB
SPI
+3VS
PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PCIE_ITX_C_PRX_N3 PCIE_ITX_C_PRX_P3
VF
For Wireless LAN
24 24 24 24
PERn1 PERp1 PETn1 PETp1
PCI-EXPRESS
For PCIE LAN
2
1 1
F26 F25 E28 E27
H26 H25 G28 G27
SUS_CLK
1
C175 2 C174 2
PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P1 PCIE_ITX_PRX_N1 0.1U_0402_16V7K PCIE_ITX_PRX_P1 0.1U_0402_16V7K
SPI_MOSI SPI_MISO OC0# OC1# OC2# OC3# OC4# OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31
USB
EC_RSMRST# 28
2 4.7K_0402_5%
+3V
D17A 6 2 BAV99DW-7_SOT363 D17B 4 3
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP
DMI_CLKN DMI_CLKP DMI_ZCOMP DMI_IRCOMP USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBRBIAS# USBRBIAS
V26 V25 U28 U27
DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_ITX_MRX_N0 DMI_ITX_MRX_P0
Y26 Y25 W28 W27
DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_ITX_MRX_N1 DMI_ITX_MRX_P1
AB26 AB25 AA28 AA27
DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_ITX_MRX_N2 DMI_ITX_MRX_P2
AD25 AD24 AC28 AC27
DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_ITX_MRX_N3 DMI_ITX_MRX_P3
AE28 AE27
5 DMI_MTX_IRX_N0 6 DMI_MTX_IRX_P0 6 DMI_ITX_MRX_N0 6 DMI_ITX_MRX_P0 6
DMI_IRCOMP
F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7
D2 D1
USBRBIAS
R329 2.2K_0402_5%
DMI_MTX_IRX_N2 6 DMI_MTX_IRX_P2 6 DMI_ITX_MRX_N2 6 DMI_ITX_MRX_P2 6 DMI_MTX_IRX_N3 6 DMI_MTX_IRX_P3 6 DMI_ITX_MRX_N3 6 DMI_ITX_MRX_P3 6
CLK_PCIE_ICH# CLK_PCIE_ICH
C25 D25
BAV99DW-7_SOT363
DMI_MTX_IRX_N1 6 DMI_MTX_IRX_P1 6 DMI_ITX_MRX_N1 6 DMI_ITX_MRX_P1 6
B
CLK_PCIE_ICH# 14 CLK_PCIE_ICH 14 R213 24.9_0402_1% 1 2 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7
Within 500 mils +1.5VS 27 27 27 27 27 27 16 16 26 26 27 27 26 26 26 26
USB Conn. New Card USB Conn. CMOS Camera USB/B Bluetooth USB/B Mini Card(WLAN)
1 2 R160 22.6_0402_1%
ICH7_BGA652~D
Within 500 mils
A
1SS355_SOD323-2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
C
1
U42D
PROJECT_ID0
B
CRT_DET
GPIO33 / AZ_DOCK_EN# GPIO34 / AZ_DOCK_RST#
CRT_DET#
100K_0402_5% PM_DPRSLPVR R285 1 2
@ 10K_0402_5% R663 1 2
GPIO32 / CLKRUN#
AC19 U2
PM_BATLOW#
@ 10K_0402_5% R269 1 2 10K_0402_5% R268 1 2
GPIO27 GPIO28
C21
TP0 / BATLOW#
SYS_PWROK 6,30 2 210K_0402_5% 100_0402_5%
2
10K_0402_5% R277 1 2
B21 E23
IDE_HRESET#
2 R267
VGATE
GPIO26
1 DPRSLPVRR2621 R286 PM_BATLOW#
AC22
D
PM_SLP_S3# 28 PM_SLP_S4# 28 PM_SLP_S5# 28
AA4 SYS_PWROK
DIRECT MEDIA INTERFACE
10K_0402_5% R660 1 2 10K_0402_5% R661 1 2 10K_0402_5% R662 1 2
6,14,42
A21
PWROK GPIO16 / DPRSLPVR
-c o
8.2K_0402_5% R287 2 1
24,26,27 ICH_PCIE_WAKE# 26,28 SERIRQ 28 EC_THERM#
GPIO18 / STPPCI# GPIO20 / STPCPU#
AG18
LINKALERT#
PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#
C298 10P_0402_50V8J @
1
PROJECT_ID0 PROJECT_ID1 PM_CLKRUN#
SUS_CLK
2
E
ICH_SMLINK1
CP_PE#
C20 B24 D23 F22
1
C165 10P_0402_50V8J @
CLK_ICH_14M 14 CLK_ICH_48M 14
C
10K_0402_5% R303 1 2
27
CP_PE#
SUSCLK SLP_S3# SLP_S4# SLP_S5#
R283 10_0402_5% @
B
ICH_SMLINK0
AC20 AF21
1
CLK_ICH_14M CLK_ICH_48M
AC1 B2
2
GPIO11 / SMBALERT#
GPIO
10K_0402_5% R312 1 2
PM_STP_PCI# PM_STP_CPU#
14 PM_STP_PCI# 14 PM_STP_CPU#
EC_SWI#
B23
GPIO0 / BM_BUSY#
R168 10_0402_5% @
2 1 R65910K_0402_5%
1
AB18
SYS
PM_BMBUSY#
SPKR SUS_STAT# SYS_RST#
CLK14 CLK48
AF19 AH18 AH19 AE19
1
SUS_STAT#
A19 A27 A22
PM_BMBUSY#
+3V
10K_0402_5% R276 1 2
CLK_ICH_14M
2
RI#
SATA GPIO
A28
GPIO21 / SATA0GP GPIO19 / SATA1GP GPIO36 / SATA2GP GPIO37 / SATA3GP
@ R284 2 1 10K_0402_5%
2
PAD T6 XDP_DBRESET#
EC_SWI#
SMBALERT# 10K_0402_5% R313 1 2
Place closely pin AC1
CLK_ICH_48M
-c c
SB_SPKR
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1
Clocks
31
EC_SWI# SB_SPKR
C22 B22 A26 B25 A25
POWER MGT
2
2 28
6
17
+3VS
ICH_SMBCLK ICH_SMBDATA LINKALERT# ICH_SMLINK0 ICH_SMLINK1
14,24,26,27 ICH_SMBCLK 14,24,26,27 ICH_SMBDATA
4 XDP_DBRESET#
A
R155 2.2K_0402_5% U42C
High: CRT Plugged
C
Place closely pin B2
1
10K_0402_5% R308 1 2
SMB
D
1
+3VS
2
Title
ICH7M(3/4)-USB,GPIO,PCIE Size Document Number Custom
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Monday, April 16, 2007
Sheet 1
20
of
44
5
4
3
2
1
+1.05VS +5VALW
0.1U_0402_16V4Z
1
1
RB751V_SOD323
C150
+ICH_V5REF
2
0.1U_0402_16V4Z 1
2
R158
D10 RB751V_SOD323
2
1
+ICH_V5REF_SUS C159 0.1U_0402_16V4Z
+3VS
C807
0.1U_0402_16V4Z
Place closely pin AG28 within 100mlis. R664 +1.5VS_DMIPLLR 0.5_0603_1% 1 2 1
+1.5VS_DMIPLL
0_0603_5%
+3V C821 0.1U_0402_16V4Z
1
+1.5VS_DMIPLL 1
+1.5VS
2
C816
0.1U_0402_16V4Z
1
2
+3VS
AG28 AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5
1
2
AD2
AH11
AB10 AB9 AC10 AD10 AE10 AF10 AF9 AG9 AH9
+1.5VS
C820
1U_0603_10V4Z
1
2
Place closely pin AG9.
E3
C1
+1.5VS
2
2
Place closely pin AG5.
0.1U_0402_16V4Z
2
2
C818
1
0.1U_0402_16V4Z
C817
+1.5VS
1
C822
0.1U_0402_16V4Z
1
T35 T36
PAD PAD
ICH_AA2 ICH_Y7
AA2 Y7
2
V5 V1 W2 W7
+3V
A
V_CPU_IO[1] V_CPU_IO[2] V_CPU_IO[3]
AE23 AE26 AH26
Vcc3_3[3] Vcc3_3[4] Vcc3_3[5] Vcc3_3[6] Vcc3_3[7] Vcc3_3[8] Vcc3_3[9] Vcc3_3[10] Vcc3_3[11]
AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19
Vcc3_3[12] Vcc3_3[13] Vcc3_3[14] Vcc3_3[15] Vcc3_3[16] Vcc3_3[17] Vcc3_3[18] Vcc3_3[19] Vcc3_3[20] Vcc3_3[21]
A5 B13 B16 B7 C10 D15 F9 G11 G12 G16
VccRTC
VccSus3_3[1] VccSus3_3[2] VccSus3_3[3] VccSus3_3[4] VccSus3_3[5] VccSus3_3[6]
Vcc3_3[1]
VccSus3_3[7] VccSus3_3[8] VccSus3_3[9] VccSus3_3[10] VccSus3_3[11] VccSus3_3[12] VccSus3_3[13] VccSus3_3[14] VccSus3_3[15] VccSus3_3[16] VccSus3_3[17] VccSus3_3[18]
VccDMIPLL
Vcc1_5_A[1] Vcc1_5_A[2] Vcc1_5_A[3] Vcc1_5_A[4] Vcc1_5_A[5] Vcc1_5_A[6] Vcc1_5_A[7] Vcc1_5_A[8] Vcc1_5_A[9]
VF
B
C815 0.01U_0402_16V7K
2
1
B27
R665 C814 10U_0805_10V4Z
+1.5VS
U6 R7
C794
2
1
+ C795
2
2
1
2
220U_D2_2VMR15
1U_0603_10V4Z
+3VS 1
+1.05VS
+3V
C800 1 2
1
2
1
2
1
2
0.1U_0402_16V4Z
C803 4.7U_0805_10V4Z
Vcc1_5_A[19] Vcc1_5_A[20]
VccSATAPLL Vcc3_3[2]
Vcc1_5_A[21] Vcc1_5_A[22] Vcc1_5_A[23]
Vcc1_5_A[10] Vcc1_5_A[11] Vcc1_5_A[12] Vcc1_5_A[13] Vcc1_5_A[14] Vcc1_5_A[15] Vcc1_5_A[16] Vcc1_5_A[17] Vcc1_5_A[18]
Vcc1_5_A[24] Vcc1_5_A[25] VccSus1_05[1] VccSus1_05[2] VccSus1_05[3]
VccSus3_3[19]
Vcc1_5_A[26] Vcc1_5_A[27] Vcc1_5_A[28] Vcc1_5_A[29] Vcc1_5_A[30]
VccUSBPLL
VccSus1_05/VccLAN1_05[1] VccSus1_05/VccLAN1_05[2]
1
2
+3VS
2005/09/12 +RTCVCC
P7
1
A24 C24 D19 D22 G19
2
K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7
1
2
1
C808 0.1U_0402_16V4Z
2
1
C812 0.1U_0402_16V4Z
AB17 AC17
2
+3V C809 0.1U_0402_16V4Z
1
1
2
2
+3V C813 0.1U_0402_16V4Z
+1.5VS
T7 F17 G17 AB8 AC8
1
2
K7
C819 0.1U_0402_16V4Z ICH_K7 PAD
C28 G20
ICH_C28 ICH_G20
A1 H6 H7 J6 J7
PAD PAD
T32 T33 T34
+1.5VS 1
2
C823 0.1U_0402_16V4Z
A4 A23 B1 B8 B11 B14 B17 B20 B26 B28 C2 C6 C27 D10 D13 D18 D21 D24 E1 E2 E4 E8 E15 F3 F4 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G18 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J1 J2 J5 J24 J25 J26 K24 K27 K28 L13 L15 L24 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M17 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N14 N15 N16 N17 N18 N24 N25 N26 P3 P4 P12 P13 P14 P15 P16 P17 P24 P27
VccSus3_3/VccLAN3_3[1] VccSus3_3/VccLAN3_3[2] VccSus3_3/VccLAN3_3[3] VccSus3_3/VccLAN3_3[4]
VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97]
VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194]
P28 R1 R11 R12 R13 R14 R15 R16 R17 R18 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U14 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V27 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA24 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB27 AB28 AC2 AC5 AC9 AC11 AD1 AD3 AD4 AD7 AD8 AD11 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27
D
C
B
ICH7_BGA652~D A
ICH7_BGA652~D C824 0.1U_0402_16V4Z
Compal Electronics, Inc.
Compal Secret Data 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
0.1U_0402_16V4Z
C801 0.1U_0402_16V4Z 1 2
C802
W5
Security Classification
5
2
C799
0.1U_0402_16V4Z 1 2
+3VS
-c o
1
10_0402_5% 10_0402_5% @ 1
C
+3V
1
R165
2
+5V
2
+5VALW
Vcc3_3 / VccHDA VccSus3_3/VccSusHDA
1
C811 1U_0402_6.3V4Z
2
Vcc1_5_B[1] Vcc1_5_B[2] Vcc1_5_B[3] Vcc1_5_B[4] Vcc1_5_B[5] Vcc1_5_B[6] Vcc1_5_B[7] Vcc1_5_B[8] Vcc1_5_B[9] Vcc1_5_B[10] Vcc1_5_B[11] Vcc1_5_B[12] Vcc1_5_B[13] Vcc1_5_B[14] Vcc1_5_B[15] Vcc1_5_B[16] Vcc1_5_B[17] Vcc1_5_B[18] Vcc1_5_B[19] Vcc1_5_B[20] Vcc1_5_B[21] Vcc1_5_B[22] Vcc1_5_B[23] Vcc1_5_B[24] Vcc1_5_B[25] Vcc1_5_B[26] Vcc1_5_B[27] Vcc1_5_B[28] Vcc1_5_B[29] Vcc1_5_B[30] Vcc1_5_B[31] Vcc1_5_B[32] Vcc1_5_B[33] Vcc1_5_B[34] Vcc1_5_B[35] Vcc1_5_B[36] Vcc1_5_B[37] Vcc1_5_B[38] Vcc1_5_B[39] Vcc1_5_B[40] Vcc1_5_B[41] Vcc1_5_B[42] Vcc1_5_B[43] Vcc1_5_B[44] Vcc1_5_B[45] Vcc1_5_B[46] Vcc1_5_B[47] Vcc1_5_B[48] Vcc1_5_B[49] Vcc1_5_B[50] Vcc1_5_B[51] Vcc1_5_B[52] Vcc1_5_B[53]
1 C792
C810 0.1U_0402_16V4Z
1
Place closely pin D28,T28,AD28.
2
2 1
C798
2
0.1U_0402_16V4Z
D8
100_0402_5%
C797
2
1
V5REF_Sus
0.1U_0402_16V4Z
C806 0.1U_0402_16V4Z
C796
2
1
V5REF[2]
L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
C805 0.1U_0402_16V4Z
G +
C793 220U_D2_2VMR15
+3VS
R149
AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28 D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 R25 R26 T22 T23 T26 T27 T28 U22 U23 V22 V23 W22 W23 Y22 Y23
1
+5V
+5VS
F6
0.1U_0402_16V4Z
0.1U_0603_25V7K 2
D
+ICH_V5REF_SUS
D
C630
+1.5VS
Q44 AO3413_SOT23-3
Vcc1_05[1] Vcc1_05[2] Vcc1_05[3] Vcc1_05[4] Vcc1_05[5] Vcc1_05[6] Vcc1_05[7] Vcc1_05[8] Vcc1_05[9] Vcc1_05[10] Vcc1_05[11] Vcc1_05[12] Vcc1_05[13] Vcc1_05[14] Vcc1_05[15] Vcc1_05[16] Vcc1_05[17] Vcc1_05[18] Vcc1_05[19] Vcc1_05[20]
C804 0.1U_0402_16V4Z
AD17
2 1
V5REF[1]
-c c
G10
S
3
+ICH_V5REF
34 SBPWR_EN#
U42E
U42F
3
2
Title
ICH7M(4/4)-POWER&GND Size Document Number Custom
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Sheet
Monday, April 16, 2007 1
21
of
44
A
B
D
E
F
G
H
Placea caps. near ODD CONN.
C183
10U_0805_10V4Z
1
1
2
2
1
C184
1
C194
+3VS
2
2
C192
1000P_0402_50V7K
10U_0805_10V4Z
1U_0402_6.3V4Z
IDE_DD[0..15]
19 IDE_DD[0..15]
1
C239 2 0.1U_0402_16V4Z
1
IDE_DA[0..2]
19 IDE_DA[0..2]
U7 20 IDE_HRESET# 6,18,20,24,28 PLT_RST#
IDE_HRESET#
2
PLT_RST#
1
1
5
C197
P
1
B
Y A
NC7SZ08P5X_NL_SC70-5
4
IDE_RST#
G
0.1U_0402_16V4Z
3
+5VS
2
C
IDE_RST# IDE_DD7 IDE_DD6 IDE_DD5 IDE_DD4 IDE_DD3 IDE_DD2 IDE_DD1 IDE_DD0 19 IDE_DIOW# 19 IDE_DIORDY 19 IDE_IRQ 19 28 2
IDE_DCS1# IDE_LED# +5VS
1 R169
IDE_DIOW# IDE_DIORDY IDE_IRQ IDE_DA1 IDE_DA0 IDE_DCS1# IDE_LED#
2 475_0402_1%
IDE_CSEL
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
IDE_DD8 IDE_DD9 IDE_DD10 IDE_DD11 IDE_DD12 IDE_DD13 IDE_DD14 IDE_DD15 IDE_DDREQ IDE_DIOR#
IDE_DDREQ 19 IDE_DIOR# 19
IDE_DDACK# IDE_PDIAG# IDE_DA2 IDE_DCS3#
IDE_DDACK# 19 1
2 R200 100K_0402_5% IDE_DCS3# 19 +5VS
+5VS
0.1U_0402_16V4Z
2 R185
1
1
C196
C182
1
2
IDE_LED# 100K_0402_5%
2
1000P_0402_50V7K
3
SATA_DTX_C_IRX_N0
1 C566
VF
19 SATA_DTX_C_IRX_N0
+3VS
C193
-c o
1
+5VS
2
+5VS
OCTEK_CDR-50JD1 CONN@
IDE_CSEL Grounding for Master (When use SATA HDD) Open or High for Slaver (Normal)
-c c
JP25
1
2
2
1U_0402_6.3V4Z
SATA_DTX_C_IRX_P0
1 C562
SATA_DTX_IRX_P0 2 3900P_0402_50V7K
19 SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_P1 1 SATAX2@ C541
SATA_DTX_IRX_P1 2 3900P_0402_50V7K
19 SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_N1 1 SATAX2@ C539
SATA_DTX_IRX_N1 2 3900P_0402_50V7K
0.1U_0402_16V4Z
SATA HDD Conn.(SAS Connector) JP27 19 SATA_ITX_C_DRX_P0 19 SATA_ITX_C_DRX_N0
1 2 3 4 5 6 7
SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 SATA_DTX_IRX_N0 SATA_DTX_IRX_P0
SATA_DTX_IRX_N0 2 3900P_0402_50V7K
19 SATA_DTX_C_IRX_P0
C245
19 SATA_ITX_C_DRX_P1 19 SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1 SATA_DTX_IRX_N1 SATA_DTX_IRX_P1
+3VS
+5VS
4
GND HTX0+ HTX0GND HRX0HRX0+ GND
First HDD for 15.4"
23 24 25 26 27 28 29
GND HTX1+ HTX1GND HRX1HRX1+ GND
2nd HDD for 17"
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND RESERVED GND VCC12 VCC12 VCC12
30 31
GND1 GND2
3
4
OCTEK_SAS-22CA1G CONN@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
E
F
Title
HDD & ODD Connector Size B
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Monday, April 16, 2007 G
Sheet
22 H
of
44
A
B
C
D
E
PS: only below need to pull high others have internal Pull high +3VS
pin 118 pin 7 pin 111 pin 21
40mil 0.1U_0402_16V4Z U46
2
@ 15P_0402_50V8J
PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 18 PCI_GNT#0 18 PCI_REQ#0 18 PCI_PAR 18 PCI_SERR# 18 PCI_PERR# 18 PCI_STOP# 18 PCI_DEVSEL# 18 PCI_TRDY# 18 PCI_IRDY# 18 PCI_FRAME# 18,26,27 PCI_RST# 14 CLK_PCI_Card
+3VS 27,28,30,34,40 SUSP# +3VS +3VS
28
5IN1_LED#
18
PCI_PIRQE#
0_0402_5% 2 @ R728 1 1 2 R73143K_0402_5% R732 1 2 10K_0402_5% SDOC# 5IN1_LED# R729 1 10K_0402_5% 2 R730 1 10K_0402_5% 2
MFUN0
MFUN1 w/o eerom pull low MFUN2
C/BE0# C/BE1# C/BE2# C/BE3#
17 16 59 58 57 56 55 54 53 49 37 38
PCIGNT# PCIREQ# PAR SERR# PERR# STOP# DEVSEL# TRDY# IRDY# FRAME# PCIRST# PCICLK
28
IDSEL
108 93
GRST#
104
MFUN3
110 107 106 105 103 102 100 94
2 13 14 15 30 31 32 44 45 50
@
2 0_0402_5%
2
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS
MSDATA0/SMDATA2 MSDATA1/SMDATA6 MSDATA2/SMDATA5 MSDATA3/SMDATA3
115 114 116 117
xDDATA2/MSDATA0 xDDATA6/MSDATAT1 xDDATA5/MSDADTA2 xDDATA3/MSDADTA3
MSCLK/SMRE#
118
MMDAT4 MMDAT5/SMWP# MMDAT6/SMBAY# MMDAT7/SMCE#
99 112 111 98
R708 2xDSMRE#/MSCLK 1 22_0402_1% XMDAT4B XMDAT5B/XDW PO# XMDAT6B_XDBSY# XMDAT7B_XDCe#
SDCLKI
SUSPEND# RIOUT#_PME#
5 4 9 8 6 7
1 121 122 89
GND_SD1 GND_SD2 NC23 GND7 GND6 GND5 GND4 GND3 GND2 GND1
3 109 12 119 97 92 80 61 43 21
MFUNC7 MFUNC6 MFUNC5 MFUNC4 MFUNC3 MFUNC2 MFUNC1 MFUNC0
NC22 NC21 NC20 NC19 NC18 NC17 NC16 NC15 NC14 NC13 NC12 NC11
128 124 123 79 78 77 76 75 64 63 62 51
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10
MFUN5
0.1U_0402_16V4Z
+3V_MCVCC 1 C882 0.1U_0402_16V4Z
1 C873 2
MS_INS#
2
1 R700 43K_0402_5% 2
xDDATA1/MSBS
1 R703 43K_0402_5% 2
xDDATA2/MSDATA0 xDDATA6/MSDATAT1 xDDATA5/MSDADTA2 xDDATA3/MSDADTA3
1 1 1 1
xDDATA4/SDDAT3 xDCLE/SDDAT2 xDDATA0/SDDAT1 xDDATA7/SDDAT0 xDALE/SDCMD R721 2xDSMW E#/SDCLK 1 22_0402_1%
41
SDPWREN33# SDWP/SMWPD# SDCD# SMCD#
1
xD PU and PD. Close to Socket
MS_INS# MSSMXD_PW REN# xDDATA1/MSBS
SDDAT3/SMDATA4 SDDAT2/SMCLE SDDAT1/SMDATA0 SDDAT0/SMDATA7 SDCMD/SMALE SDCLK/SMWE#
0.1U_0402_16V4Z
SD_PW REN#
PCI_RST#
xDSMRE#/MSCLK
R704 R705 R706 R707
+3VS
MS signal
43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2
1 R709 43K_0402_5% 2
XMDAT4B xDSMW E#/SDCLK XMDAT6B_XDBSY# XMDAT7B_XDCe# xDDATA4/SDDAT3 xDCLE/SDDAT2 xDDATA0/SDDAT1 xDDATA7/SDDAT0 xDALE/SDCMD
1 1 1 1
R710 R711 R712 R713
SD_PW REN# SMW PD#/SDW P SDCD# xDSMCD#
1 R723 43K_0402_5% 2 1 R724 43K_0402_5% 2 R725 1 2 8.2K_0402_5%
8 7 6 5
40mil
GND OUT IN OUT IN OUT MC_PW REN# EN# FLG 1 C890 TPS2061DRG4_SO8 @ R716 0.1U_0402_16V4Z SDOC# 300_0603_5% 2
43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2
MSSMXD_PW REN# R699 20_0402_5% MC_PW REN#2 1 G SD_PW REN# 1 2 R701 0_0402_5%
SD signal
C885
1 C886 1 C887 1
R714 150K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z @ 2 2 2 0.1U_0402_16V4Z
D
S
Q55 2N7002_SOT23
+3VS
4 IN 1 Socket Push Type(New) 3
JP30
xD PU and PD. Close to Socket
33
XD-VCC
xDDATA0/SDDAT1 xDDATA1/MSBS xDDATA2/MSDATA0 xDDATA3/MSDADTA3 xDDATA4/SDDAT3 xDDATA5/MSDADTA2 xDDATA6/MSDATAT1 xDDATA7/SDDAT0
8 9 26 27 28 30 31 32
XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7
xDSMW E#/SDCLK XMDAT5B/XDW PO# xDALE/SDCMD xDSMCD# XMDAT6B_XDBSY# xDSMRE#/MSCLK XMDAT7B_XDCe# xDCLE/SDDAT2
6 7 5 34 1 2 3 4
XD-WE XD-WP XD-ALE XD-CD XD-R/B XD-RE XD-CE XD-CLE
13 22
4IN1 GND 4IN1 GND
+3V_MCVCC
Reserve for SD,MS CLK. Close to Socket
MR510QFA1_LQFP128_14X14
+3V_MCVCC U47
1 2 3 4
R702
xd signal 1 1 1 1 1
Memory Card Power Switch
+3V_MCVCC
43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2
R715 R717 R718 R719 R720
2
+3VS
CLK_48M_SD 14
MFUN4 w/o eerom pull low 4
1 C881
1 R722 43K_0402_5% 2
90 95 96
MSINS# MSPWREN#/SMPWREN# MSBS/SMDATA1
1 C880
4.7U_0805_10V4Z
VF
3
R726 100_0402_5% PCI_AD16 1 2 10K_0402_5% 2 R727 1
74 60 48 27
127 R696 1 126
1 C879
1
@ 15P_0402_50V8J
PMPWR_ENI# PMPWR_OUT
2
1 C878
2
2
C884
125 120 101 81 69 52 42 29 11 113 10
1 C877
1
2
1
C883
PMPWR_VCC VCC8 VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 NC24 VCC_SD2 VCC_SD1
1 C876
SMRE# SMWE# BSY# CE#
1 2
1
2
R698 @ 10_0402_5%
2
R695 @ 10_0402_5%
MR510
1 C875
XD XD XD XD
3
1
CLK_48M_SD
1
CLK_PCI_card
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
0.1U_0402_16V4Z
-c c
PCI_CBE#[0..3]
18 PCI_CBE#[0..3]
18 19 20 22 23 24 25 26 33 34 35 36 39 40 46 47 65 66 67 68 70 71 72 73 82 83 84 85 86 87 88 91
C874
-c o
PCI_AD[0..31]
18 PCI_AD[0..31]
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
1
0.1U_0402_16V4Z
8.2K_0402_5% 1 2
1
0.1U_0402_16V4Z
xDSMW E#/SDCLK 1 C888
2 10P_0402_50V8K
xDSMRE#/MSCLK 1 C889
2 10P_0402_50V8K
37 38
4 IN 1 CONN
SD-VCC MS-VCC
23 14
SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-CMD SD-CD-SW
24 25 29 10 11 12 36
xDSMW E#/SDCLK xDDATA7/SDDAT0 xDDATA0/SDDAT1 xDCLE/SDDAT2 xDDATA4/SDDAT3 xDALE/SDCMD SDCD#
SD-WP-SW
35
SMW PD#/SDW P
MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-INS MS-BS
15 19 20 18 16 17 21
xDSMRE#/MSCLK xDDATA2/MSDATA0 xDDATA6/MSDATAT1 xDDATA5/MSDADTA2 xDDATA3/MSDADTA3 MS_INS# xDDATA1/MSBS
+3V_MCVCC
4IN1 GND 4IN1 GND
4
TAITW _R015-312-LM CONN@
MFUN6 MFUN7
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
R5C833 5IN1 & IEEE1394 Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
23
of
44
4
+3VALW
+3V_LAN
4.7U_0805_10V4Z 2
+VSB
@
1 2 3 4
1
2 13VLAN_GATE R508 200K_0402_5%
1
1
D
2 G
SYSON#
1
C29
1
C58
1
C89
C111
2
1
C28
Q18 MMJT9435T1G_SOT223
C634 @ 0.1U_0603_25V7K
C447
R23
1
2 1_1206_1%
R24
1
2 1_1206_1%
C30
0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z
LAN_REGCTL25 1
4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
D
26,27,34
+3V_LAN 1
AO4468_SO8 @
2
+2.5V_LAN
1
1
1
C52
1
C449
Q6 MMJT9435T1G_SOT223
C110
C31
10U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
3
Q40 S @ 2N7002_SOT23
1
LAN BCM5787M C26
0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z
LAN_REGCTL12 1
20mil
1
60mil +3V_LAN_R 1 C25
3
S S S G
3
1
D D D D
2 4
8 7 6 5
+3V_LAN
60mil
U35 C24
3
+1.2V_LAN
60mil
2 4
5
1
1
C448
1
C80
1
1
C42
C91
1
1
C112
1
C39
1
C457
1
C450
1
C41
D
C464
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 2 2 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3V_LAN +3V_LAN
U3 SPROM_DOUT SPROM_CLK
1 2 3 4
-c c
SPROM_CS
R71
+3V_LAN
2 1 LAN_PME# R514 100K_0402_5%
2 10K_0402_5% @ 1 2 1K_0402_5%
1
+3VS
R88
+3V_LAN
R89
2 1K_0402_5%
1
20 PCIE_ITX_C_PRX_P3 20 PCIE_PTX_C_IRX_N3
C38
20 PCIE_PTX_C_IRX_P3
C37
2 0.1U_0402_16V7K
1
2 0.1U_0402_16V7K
1
R67
6,18,20,22,28 PLT_RST#
1
R66 1 R511 1
20,26,27 ICH_PCIE_WAKE# 28 EC_PME#
31
PCIE_PTX_IRX_N3
25
S
ENERGY_DET GPHY_PLLVDD
LINKLED SPD100LED SPD1000LED TRAFFICLED
SCLK(EECLK) SI SO(EEDATA) CS
26
PCIE_RXD_P
REGCTL12 REGCTL25 RDAC
PCIE_TXD_N
XTALVDD VDDIO VDDIO VDDIO VDDIO VDDIO
10 12
LAN_SMBCLK
58
SMB_CLK
LAN_SMBDATA
57
SMB_DATA
PERST WAKE
VDDP VDDP
4
GPIO_0(SERIAL_DO)
7
GPIO_1(SERIAL_DI)
8
GPIO_2
9
UART_MODE
LAN_XTALI
21
XTALI
XTALO
22
XTALO
R48 200_0402_1%
16
2
24
1
1
2
2 1 67 66
65 63 64 62
14 18 37
PCIE_TXD_P
0_0402_5% LAN_PME# 0_0402_5%
pull-up to +3V on South Bridge Side
Y2
41 40 42 43 48 47 49 50
LAN_MIDI0LAN_MIDI0+ LAN_MIDI1LAN_MIDI1+ LAN_MIDI2LAN_MIDI2+ LAN_MIDI3LAN_MIDI3+
LAN_MIDI0LAN_MIDI0+ LAN_MIDI1LAN_MIDI1+ LAN_MIDI2LAN_MIDI2+ LAN_MIDI3LAN_MIDI3+
R748 1 R747 1
SPROM_CLK SPROM_DIN SPROM_DOUT SPROM_CS
25 25 25 25 25 25 25 25
0_0402_5% 2
LAN_LINK# 25
0_0402_5% 2
R78 R77
REG_GND
PCIE_GND
VDDC VDDC VDDC VDDC VDDC VDDC
BIASVDD PCIE_PLLVDD PCIE_VDD PCIE_VDD AVDD AVDD AVDD
AVDDL AVDDL AVDDL AVDDL EXPOSED PAD
23 6 15 19 56 61
LAN_REGCTL12 LAN_REGCTL25 LAN_RDAC 1 R62 1.24K_0402_1% +LAN_XTALVDD
1 2 3 4
LAN_ACTIVITY# 25
1
@ 2 4.7K_0402_5%
1
2 4.7K_0402_5%
+1.2V_LAN
36 30 27 33
+LAN_BIASVDD +LAN_PCIEPLLVDD +LAN_PCIEVDD
38 45 52
+LAN_AVDD
39 44 46 51 69
+LAN_AVDDL
25MHZ_20P
A0 A1 A2 GND
8 7 6 5
VCC WP SCL SDA
SPROM_WP SPROM_CLK SPROM_DOUT
1
1 2 BLM18AG601SN1D_0603
20mil +2.5V_LAN
+LAN_PCIEPLLVDD 1 1 C452 C451
20mil +LAN_PCIEVDD 1 1 C455 C454
L8 1 2 BLM18AG601SN1D_0603
0.1U_0402_16V4Z 2 +2.5V_LAN
20mil
C53 0.1U_0402_16V4Z
+LAN_AVDD 1 C107
2
C88
0.1U_0402_16V4Z 2
1
+LAN_AVDDL 1 C95
C463
0.1U_0402_16V4Z 2
C34 27P_0402_50V8J 2
1
0.1U_0402_16V4Z 2
3
B
L36 1 2 BLM18AG601SN1D_0603
+2.5V_LAN
L37 1 2 BLM18AG601SN1D_0603
+1.2V_LAN
L35 1 2 BLM18AG601SN1D_0603
+1.2V_LAN A
2 4.7U_0805_10V4Z
Compal Electronics, Inc.
Compal Secret Data 2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
+1.2V_LAN
2 4.7U_0805_10V4Z
20mil
A
L34 1 2 BLM18AG601SN1D_0603
2 0.1U_0402_16V4Z
+LAN_GPHYPLLVDD 1 1 C453 C456
5
+1.2V_LAN
2 4.7U_0805_10V4Z
20mil
2006/12/25
L33 1 2 BLM18AG601SN1D_0603
0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z
1
Issued Date
R740 4.7K_0402_5% @
Unpop if use Flash
L7
BCM5787MKML_QFN68
Security Classification
C
Unpop if use Flash
C43 0.1U_0402_16V4Z
20mil
+3V_LAN
R128 R102 4.7K_0402_5% 4.7K_0402_5%
Change to SA000003510(AT24C64)
2 LAN_XTALO
C35 27P_0402_50V8J
0.1U_0402_16V4Z 2 U4
AT24C64AN-10SU-2.7_SO8
2
5 13 20 34 55 60
C136
1K for BCM5906M
20mil
1
+2.5V_LAN
+3V_LAN +3V_LAN 1
2
+3V_LAN
17 68
2
Use Flash if support ASF2.0
PCIE_RXD_N
1
LAN_SMBCLK
Q42 @ 2N7002_SOT23
VAUX_PRSNT
0_0402_5% LAN_RESET#
SPROM_WP
S
D D
3
35
PCIE_ITX_C_PRX_P3
PCIE_PTX_IRX_P3
R64 4.7K_0402_5% 1 2 +3V_LAN
2 G 1
14,20,26,27 ICH_SMBCLK
54
VMAIN_PRSNT
2 @ 2
LAN_SMBDATA
+3V_LAN
53
LOW PWR
VF
2 G
R130 4.7K_0402_5% 1 2 +3V_LAN
Q41 @ 2N7002_SOT23
3
2
+3V_LAN
3
CLKREQ
PCIE_ITX_C_PRX_N3 32
20 PCIE_ITX_C_PRX_N3
1
PCIE_REFCLK_P
11
TRD0_N TRD0_P TRD1_N TRD1_P TRD2_N TRD2_P TRD3_N TRD3_P
-c o
+LAN_GPHYPLLVDD
14,20,26,27 ICH_SMBDATA
29
59
28 ENERGY_DET
B
PCIE_REFCLK_N
2
1
28 LAN_LOWPWR
C
0_0402_5% 2
28
C114 0.1U_0402_16V4Z @
1
R741
+3V_LAN 1
1
14 CLK_PCIE_LAN
SPROM_DIN
8 7 6 5
SO GND VCC WP#
AT45DB011B-SU_SO8 @
U2 14 CLK_PCIE_LAN#
SI SCK RESET# CS#
2
2 0_1206_5%
1
1 R19
2
+3VALW
2
Title
LAN BCM5787M Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
24
of
44
5
4
3
2
3
2
2
LAN_ACTIVITY#
3
LAN_LINK#
LAN BCM5787M
1
1
@ PSOT24C-LF-T7_SOT23-3 D31
1
@ PSOT24C-LF-T7_SOT23-3 D30 D
D
1 +2.5V_LAN
2
+3V_LAN
C
24 24
LAN_MIDI0+ LAN_MIDI0-
LAN_MIDI0+ LAN_MIDI0-
24 24
LAN_MIDI1+ LAN_MIDI1-
LAN_MIDI1+ LAN_MIDI1-
24 24
LAN_MIDI2+ LAN_MIDI2-
LAN_MIDI2+ LAN_MIDI2-
24 24
LAN_MIDI3+ LAN_MIDI3-
LAN_MIDI3+ LAN_MIDI3-
24 LAN_ACTIVITY#
TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4-
MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4-
24 23 22 21 20 19 18 17 16 15 14 13
RJ45_MIDI0+ RJ45_MIDI0RJ45_MIDI1+ RJ45_MIDI1RJ45_MIDI2+ RJ45_MIDI2RJ45_MIDI3+ RJ45_MIDI3-
1
C138
2
Pop for BCM5906
1
C121
1
C152
1
0.1U_0402_16V4Z
2
2
PR3-
RJ45_MIDI2+
4
PR3+
RJ45_MIDI1+
3
PR2+
RJ45_MIDI0-
2
PR1-
RJ45_MIDI0+
1
PR1+
9
2
15
SHLD2
14
SHLD1
13
Guide Pin
C
Green LEDGreen LED+ FOX_JM36113-L2R8-7F CONN@ 2
1
C151 220P_0402_50V7K
R153 75_0402_1%
RJ45_GND
1
1 C108
2
40mil
VF
LANGND 1
2
C154 1000P_1206_2KV7K
RJ45_GND
0.1U_0402_16V4Z
Place close to TCT pin
B
PR2-
5
10
16
SHLD1
1
1
2
R132 75_0402_1%
C106
6
RJ45_MIDI2-
2
1 C134 0.1U_0402_16V4Z 2 @
2
1 C146 0.1U_0402_16V4Z 2 @
0.1U_0402_16V4Z
RJ45_MIDI1-
1 1K_0402_5%
SHLD2 PR4PR4+
R115 75_0402_1%
2
1
1
0.1U_0402_16V4Z
Amber LED-
7
1
1
-c o R101 75_0402_1%
2
2
1
1 2
2
R152 49.9_0402_1% @
8
RJ45_MIDI3+
2 R154
+3V_LAN
R118 49.9_0402_1% @
11
LAN_LINK#
24 LAN_LINK#
350uH_GSL5009LF R129 49.9_0402_1% R148 @ 49.9_0402_1% @
1 1K_0402_5%
RJ45_MIDI3-
T4
1 2 3 4 5 6 7 8 9 10 11 12
2 R70 LAN_ACTIVITY#
-c c
1
L12 BLM18AG601SN1D_0603
2
C94 220P_0402_50V7K JP18 12 Amber LED+
2
40mil
C96 4.7U_0805_10V4Z
0.1U_0402_16V4Z
LAN_ACTIVITY#
1 2 C186 220P_0402_50V7K @
LAN_LINK#
1 2 C187 220P_0402_50V7K @
B
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2006/12/25
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
LAN Magnetic & RJ45/RJ11 Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
25
of
44
A
B
C
D
E
For Wireless LAN +3VS_WL
C906 10U_0805_6.3V6M
1
1
2
2
+1.5VS
1
C139 4.7U_0805_10V4Z
2
1
C480 0.1U_0402_16V4Z
2
+3VAux_WL
1
C147 4.7U_0805_10V4Z
2
1
C140 0.1U_0402_16V4Z
2
1
C133 0.1U_0402_16V4Z
2
1
C137 0.1U_0402_16V4Z
2
C907 10U_0805_6.3V6M
1
1
20,24,27 ICH_PCIE_WAKE# 27 WLAN_BT_DATA 27 WLAN_BT_CLK 14 MINI1_CLKREQ# 14 CLK_PCIE_MINI1# 14 CLK_PCIE_MINI1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
20 PCIE_PTX_C_IRX_N4 20 PCIE_PTX_C_IRX_P4 20 PCIE_ITX_C_PRX_N4 20 PCIE_ITX_C_PRX_P4 +3VS_WL
E51TXD_P80DATA E51RXD_P80CLK
28 E51TXD_P80DATA 28 E51RXD_P80CLK
JP21 2 4 6 8 10 12 14 16
17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
+3VS_WL +1.5VS
LPC Debug Port +5VS WL_OFF# PLT_RST_BUF#
53 54 55 56
For MINICARD Port80 Debug
+3VS
WL_OFF# 28 PLT_RST_BUF# 18
+3VAux_WL ICH_SMBCLK ICH_SMBDATA
JP40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ICH_SMBCLK 14,20,24,27 ICH_SMBDATA 14,20,24,27 USB20_N7 20 USB20_P7 20
(MINI1_LED#) MINI1_LED# 29
(9~16mA)
G1 G2 G3 G3
2
1 3 5 7 9 11 13 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-c c
R755 @ 0_0402_5% ICH_PCIE_WAKE# 1 2 WLAN_BT_DATA WLAN_BT_CLK
FOX_AS0B226-S99N-7F CONN@
CLK_14M_SIO LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ#1 PCI_RST# 1 2 R690 @ 0_0402_5% SIRQ
CLK_14M_Dbg 14 LPC_AD0 19,28 LPC_AD1 19,28 LPC_AD2 19,28 LPC_AD3 19,28 LPC_FRAME# 19,28 LPC_DRQ#1 19 PCI_RST# 18,23,27
CLK_PCI_Dbg
2
CLK_PCI_Dbg 14 SERIRQ 20,28
close to RAM Door
@ ACES_85201-2005
Primary Power (mA) Peak
Normal
+3VS
1000
750
+3V
330
250
+1.5VS
500
375
+3V
Auxiliary Power (mA) Normal
+3VS
250 (wake enable)
+3V
5 (Not wake enable)
@
2 0_0805_5% 2 0_0805_5%
+3VAux_WL 20 mil
-c o
+3VS
Mini Card Power Rating Power
1 R756 1 R757
1 R758 1 R759 @
2 0_1206_5% 2 0_1206_5%
+3VS_WL
40 mil
To USB/B Connector
JP11 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12
VF
3
GND1 GND2
3
+5VALW
+5VALW USB20_N4 USB20_P4 USB20_N6 USB20_P6
USB20_N4 20 USB20_P4 20 USB20_N6 20 USB20_P6 20 SYSON#
C368
1
4.7U_0805_10V4Z 2
24,27,34
13 14
ACES_87213-1200G CONN@
4
4
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
MINI CARD (WLAN & TV-Tuner) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
26
of
44
A
B
C
D
E
New Card Power Switch
New Card Socket (Left/TOP)
U16
CPUSB# CPPE# STBY# SHDN# SYSRST#
OC#
1
C387
C362
1
+3VS
TPS2231PWPR_PWP24
USB20_N1 USB20_P1
CP_USB#
10U_0805_10V4Z 2 2 0.1U_0402_16V4Z
2
1
D
3
S
1
2
2
B
1
A
NC7SZ32P5X_NL_SC70-5 Q15 2N7002_SOT23
10U_0805_10V4Z 2
PERST1#
+3VS_CARD
+3VS
R336 10K_0402_5%
1
C365
20 20
C401
20,24,26 ICH_PCIE_WAKE# +3VALW_CARD RCLKEN1 PERST1#
+1.5VS
10U_0805_10V4Z 2
1
CLKREQ1# CP_PE#
20 CP_PE# 14 CLK_PCIE_CARD# 14 CLK_PCIE_CARD
C357 0.1U_0402_16V4Z
20 PCIE_PTX_C_IRX_N1 20 PCIE_PTX_C_IRX_P1
U15
4
Y
20 PCIE_ITX_C_PRX_N1 20 PCIE_ITX_C_PRX_P1
EXP_CLKREQ# 14
-c o
1
1
23 22 9
2 C363
10U_0805_10V4Z 2
C412
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
14,20,24,26 ICH_SMBCLK 14,20,24,26 ICH_SMBDATA +1.5VS_CARD
RCLKEN1 2 G
2
C367
+1.5VS_CARD
CLKREQ1#
+3V
1
10U_0805_10V4Z 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R338 10K_0402_5%
+3VS
1
C366
+3VS
1 10 12 13 24
11
1
10U_0805_10V4Z 2
40mil
NC1 NC2 NC3 NC4 NC5
RCLKEN PERST#
16 17
+3VALW_CARD
JP9
Imax = 0.75A
-c c
14 15 4 3 2
1.5Vout1 1.5Vout2
C390
40mil
Imax = 1.35A
5
1.5Vin1 1.5Vin2
GND
23,28,30,34,40 SUSP# 28,34,40 SYSON 18,23,26 PCI_RST#
20
Imax = 0.275A
+3VS_CARD
G Vcc
2 100K_0402_5% CP_USB# 2 100K_0402_5% CP_PE# SUSP# SYSON PCI_RST#
R341 1 R340 1
+3V
Aux_out
3.3Vaux_in
18 19
+1.5VS
7 8
GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND
27 28
3
21
+3V
3.3Vout1 3.3Vout2
+1.5VS_CARD
1
1
3.3Vin1 3.3Vin2
+3VS_CARD
1
5 6
+3VS
+3VALW_CARD
60mils
GND GND
1
GND GND
29 30
FOX_1CH4110C_LT CONN@
2
USB CONN. (Stack-up Type)
Bluetooth Conn.
+USB_VCCA
+
3 G
2
1
1U_0603_10V4Z 2 Q32 AO3413_SOT23-3
20 20
C597
VF
W=40mils
+BT_VCC
20 20
C598
2 1
Q34 2N7002_SOT23
3
S
R742 @ 22 1 G 10K_0402_5%
20 20
4
USB20_P5 USB20_N5
26 WLAN_BT_DATA 26 WLAN_BT_CLK
1 GND 2 3 4 5 6 7 8 GND
4
+USB_VCCA
2
I/O
I/O
USB20_N0_R
3
JP23 1 2 3 4
R736 0_0402_5% USB20_N0 1 2 USB20_N0_R USB20_P0 1 2 USB20_P0_R
5 6 7 8
VCC D1D1+ GND
9 10
GND1 GND2
0_0402_5%
VCC D0D0+ GND
D11 1 USB20_P2_R
2
GND
VCC
I/O
I/O
4
3
+USB_VCCA USB20_N2_R
3
@ PRTR5V0U2X_SOT143
SUYIN_020122MR008S505ZL CONN@ +3V
80mil
D
+5VALW
@ Q51 2N7002_SOT23
+USB_VCCA U6
S
C171
1
JP12
1 2 3 4 5 6 7 8
VCC
@ PRTR5V0U2X_SOT143
R733 0_0402_5% USB20_N2 1 2 USB20_N2_R USB20_P2 1 2 USB20_P2_R R734 0_0402_5%
BT_LED# 28,29
+BT_VCC
USB20_P0_R
470P_0402_50V7K 2 2 470P_0402_50V7K
R735
GND
C167
D
2 G
+BT_VCC
USB20_N0 USB20_P0
2
1
C164
R492 300_0603_5%
4.7U_0805_10V4Z 2 0.1U_0402_16V4Z
1
C590
1
3
0.1U_0402_16V4Z
USB20_N2 USB20_P2
1
2 10K_0402_5%
D
1 R482
S
0.1U_0402_16V4Z BT_ON#
150U_Y_6.3VM
C600
1
1
1
C592
28
D12 1
1
C173
3
W=80mils
+USB_VCCA
+3VS
1 2 3 4
GND IN IN EN#
OUT OUT OUT FLG
8 7 6 5
R164 100K_0402_5% 2
+3VALW
R162 1
2 10K_0402_5%
R167 1
2 10K_0402_5%
USB_OC#0 20
TPS2061DRG4_SO8 4.7U_0805_10V4Z 2
9
C169
1
C161
USB_OC#2 20
1
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2
24,26,34 SYSON#
4
10
ACES_87213-0800G CONN@
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
NEW CARD & USB Connector Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
27
of
44
4
3
2
1
For EC Tools
+3VALW L46
C557
2 2 0.1U_0402_16V4Z
C536 1000P_0402_50V7K 1 1
C544 1000P_0402_50V7K
20 PM_SLP_S3# 20 PM_SLP_S5# 20 EC_SMI# 29 LID_SW # 23,27,30,34,40 SUSP# 20 PBTN_OUT# 24 EC_PME# 20 EC_THERM# 33 FAN_SPEED1 27 BT_ON#
PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW # SUSP# PBTN_OUT# EC_PME#
67
9 22 33 96 111 125
AVCC
68 70 71 72
DAC_BRIG EN_DFAN1 IREF
PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F
83 84 85 86 87 88
EC_MUTE LAN_LOW PW R W L_LED# BT_LED# TP_CLK TP_DATA
SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0
97 98 99 109
3S/4S# 65W /90W # SBPW R_EN
SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS#
119 120 126 128
EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS#/FSEL#
CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59
73 74 89 90 91 92 93 95 121 127
EC_RCIRRX
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11
100 101 102 103 104 105 106 107 108
PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7
110 112 114 115 116 117 118
V18R
124
DA Output
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82
KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49
77 78 79 80
SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47
PS2 Interface
BATT_OVP 37 ADP_I 37
ENERGY_DET
POUT
FAN_SPEED1 BT_ON# E51TXD_P80DATA E51RXD_P80CLK ON/OFF PW R_SUSP_LED NUM_LED#
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
EC_CRY1 EC_CRY2
122 123
SPI Flash ROM
GPIO
SM Bus
PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
GPI
XCLK1 XCLK0
11 24 35 94 113 A
KB926QFA1_LQFP128_14X14 L48 ECAGND 2 1 FBM-L11-160808-800LMT_0603
2007/1/15
Issued Date
R449
3
C
LAN_LOW PW R 24
BT_LED#
27,29
TP_CLK 29 TP_DATA 29
3S/4S# 37 65W /90W # 37 SBPW R_EN 34
Analog Board ID definition, Please see page 3.
EC_SI_SPI_SO 29 EC_SO_SPI_SI 29 EC_SPICLK 29 EC_SPICS#/FSEL# 29
+3VALW
R465 @ 100K_0402_5%
Ra ENCODER_PULSE 32 FSTCHG 37 BATT_GRN_LED# 29 CAPS_LED# 29 BATT_AMB_LED# 29 PW R_LED 29 SYSON 27,34,40 VR_ON 42 ACIN 20,38 EC_RSMRST# 20 EC_LID_OUT# 20 EC_ON 30,37 EC_SW I# 20 EC_PW ROK 30 BKOFF# 16 W L_OFF# 26 MEDIA_LED# 29 CALIBRATE 37
EC_PW ROK BKOFF# W L_OFF# MEDIA_LED#
IDE_LED#
AD_BID0
Rb
C565
18K_0402_5% 2 0.1U_0402_16V4Z
EC_CRY1 C538
B
EC_CRY2
1
1
10P_0402_50V8J 2
C540
10P_0402_50V8J 2
X2 32.768KHZ_12.5P_MC-306
For KB926 C0 reversion
C891 2
100P_0402_50V8J
C892 BATT_TEMP 1 2
100P_0402_50V8J
C893 1 2
100P_0402_50V8J
ACIN
2 0.1U_0402_16V4Z
BATT_OVP
Deciphered Date
1
R464
PM_SLP_S4# 20 ENBKL 8,15 EAPD 31 SATA_LED# 19 5IN1_LED# 23 IDE_LED# 22 ARCADE# 29
ENBKL EAPD SATA_LED#
C908
1 100K_0402_5%
W L_LED# 29
EC_LID_OUT# EC_ON
1
2
EC_MUTE 32
1
A
Compal Electronics, Inc. 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
+3VALW 65W /90W #
Compal Secret Data
Security Classification
5
24
DAC_BRIG 16 EN_DFAN1 33 IREF 37 CHGSEL 37
FSTCHG BATT_GRN_LED# CAPS_LED# BATT_AMB_LED# PW R_LED SYSON VR_ON
@
2 4.7K_0402_5%
42
SPI Device Interface
GND GND GND GND GND
30 ON/OFF 29 PW R_SUSP_LED 29 NUM_LED#
AD_BID0
1 R521
1
EC_SMB_CK1 2 4.7K_0402_5% EC_SMB_DA1 2 4.7K_0402_5% EC_SMB_CK2 2 4.7K_0402_5% EC_SMB_DA2 2 4.7K_0402_5%
DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F
3S/4S# BATT_TEMP 38
NC
1 R460 1 R458 1 R456 1 R454
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
AD
VF
B
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
BATT_TEMP BATT_OVP
2
15,29,38 15,29,38 4 4
63 64 65 66 75 76
2
2 TP_CLK 4.7K_0402_5% 2 TP_DATA 4.7K_0402_5%
BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43
PWM Output
ACES_85205-0400 @
INVT_PW M 16 BEEP# 31 ENCODER_DIR 32 ACOFF 35,37 ECAGND 2 1 C567 0.01U_0402_16V7K
1
+5VS
PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D
INVT_PW M BEEP#
2
2 1 EC_RCIRRX
12 13 37 20 38
21 23 26 27
INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13
D
E51RXD_P80CLK E51TXD_P80DATA
1
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17
R466 10K_0402_5%
+5VALW
EC_SCI#
GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC
E51RXD_P80CLK 26 E51TXD_P80DATA 26
+3VALW
1 2 3 4
1 2 3 4
-c c
20 EC_SCI# 20 PM_CLKRUN#
+3VALW
1 R448 1 R444
E51RXD_P80CLK E51TXD_P80DATA
JP35
-c o
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
6,18,20,22,24 PLT_RST#
2 1 R441 47K_0402_5% 2 1 C548 0.1U_0402_16V4Z
C
KSO[0..17] 29
0.1U_0402_16V4Z
AGND
1 @ 33_0402_5%
1 2 3 4 5 7 8 10
69
19 EC_GA20 19 EC_KBRST# 20,26 SERIRQ 19,26 LPC_FRAME# 19,26 LPC_AD3 19,26 LPC_AD2 19,26 LPC_AD1 19,26 LPC_AD0
14 CLK_PCI_LPC
+3VALW
1 2 3 4
1 2 3 4
ECAGND
VCC VCC VCC VCC VCC VCC
U28
R447 2
29
ACES_85205-0400 @
D
C555 @ 22P_0402_50V8J 2 1
KSO[0..17]
C559
2
KSI[0..7]
4
2 2 0.1U_0402_16V4Z
EC_PME# 2 10K_0402_5% @
JP10 KSI[0..7]
1
IN
C552
1 R459
+3VALW
1 2+EC_VCCA 2 FBM-L11-160808-800LMT_0603
0.1U_0402_16V4Z 1 2
OUT
0.1U_0402_16V4Z 1 C537 1
C560
NC
1 +3VALW
3
5
2
Title
EC ENE KB926 Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
28
of
44
+3VALW
reserve for debug +5VALW
1 3 7 4
1
2
R738 @ 1K_0402_5% R442
CE# WP# HOLD# VSS
VDD SCK SI SO
8 6 5 2
SPICLK EC_SO_SPI_SI_R EC_SI_SPI_SO_R JP6 +5VS
@ MX25L8005M2C-15G_SOP8 C551 1
2 0.1U_0402_16V4Z
28 28
100K_0402_5% 8 7 6 5
15,28,38 EC_SMB_CK1 15,28,38 EC_SMB_DA1
TP_DATA TP_CLK
6 5 4 3 2 1
2
U26
TP_DATA TP_CLK
VCC WP SCL SDA
A0 A1 A2 GND
1 2 3 4
U27 EC_SPICS#/FSEL#
28 EC_SPICS#/FSEL#
AT24C16AN-10SI-2.7_SO8
2 R739
1
1
1K_0402_5%
1 3 7 4
CE# WP# HOLD# VSS
C130 VDD SCK SI SO
8 6 5 2
SPICLK R443 1 EC_SO_SPI_SI_R R445 1 EC_SI_SPI_SO_R R438 1
2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
EC_SPICLK 28 EC_SO_SPI_SI 28 EC_SI_SPI_SO 28
100P_0402_50V8J
1
1
2
2
+5VS
TP_CLK 2
ENE suggestion SPI Frequency over 66MHz SST: 50MHz MXIC: 70MHz ST: 40MHz
C149 D9 @ PSOT24C_SOT23
0.1U_0402_16V4Z
KSI[0..7]
INT_KBD Conn.
KSI[0..7]
KSO[0..17]
-c c
1
2
ACES_85201-0605 CONN@
TP_DATA
MX25L8005M2C-15G_SOP8 R437 100K_0402_5%
C129 100P_0402_50V8J
3
2 0.1U_0402_16V4Z
1
C550 1
To TP/B Conn.
U45 EC_SPICS#/FSEL#
+3VALW
+5VALW
28
KSO[0..17] 28
JP5 G2 G1
To BTN/B Conn.
28 27
+3VS
17 18
C74
1
2
100P_0402_50V8J
KSO7
C66
1
2
100P_0402_50V8J
KSO14
C73
1
2
100P_0402_50V8J
KSO6
C65
1
2
100P_0402_50V8J
KSO13
C72
1
2
100P_0402_50V8J
KSO5
C64
1
2
100P_0402_50V8J
KSO12
C71
1
2
100P_0402_50V8J
KSO4
C63
1
2
100P_0402_50V8J
KSI0
C75
1
2
100P_0402_50V8J
KSO3
C62
1
2
100P_0402_50V8J
KSO11
C70
1
2
100P_0402_50V8J
KSI4
C54
1
2
100P_0402_50V8J
KSO10
C69
1
2
100P_0402_50V8J
KSO2
C61
1
2
100P_0402_50V8J
KSI1
C76
1
2
100P_0402_50V8J
KSO1
C60
1
2
100P_0402_50V8J
KSI2
C77
1
2
100P_0402_50V8J
KSO0
C59
1
2
100P_0402_50V8J
KSO9
C68
1
2
100P_0402_50V8J
KSI5
C55
1
2
100P_0402_50V8J
KSI3
C78
1
2
100P_0402_50V8J
KSI6
C56
1
2
100P_0402_50V8J
R358 300_0402_5% 1 2 R495 1 2 453_0402_1%
LED1 3 4
C57
1
2
1
PWR_LED#
A
+5VALW
KSI7
100P_0402_50V8J
YG
+5VS
2
G17 G18
C21
PWR_LED#
0.1U_0402_16V4Z
ON/OFFBTN# 30
WL_R_LED# BT_LED# PWR_SUSP_LED# KSO0 KSI1 KSI2 KSI3 KSI4
1 R16
2 +3VALW 100K_0402_5%
D6 2
ARCADE_BTN# 1
3
BT_LED# 27,28
2
PWR_SUSP_LED#
100P_0402_50V8J
28
ARCADE# 28 51ON#
51ON#
30,35
DAN202UT106_SC70-3
+3VALW
C22 PWR_LED#
0.1U_0402_16V4Z
KSI5 KSO0 ARCADE_BTN#
PWR_LED
PWR_SUSP_LED#
+5VS +3VALW LID_SW# 28
NUM_LED# 28 CAPS_LED# 28 MEDIA_LED# 28
D
2 G S Q4 2N7002_SOT23
KSO0 WL_BTN#
KSI2
BT_BTN#
KSI3
EMAIL_BTN#
KSI4
IE_BTN#
KSI5
E-KEY_BTN#
S Q37 2N7002_SOT23
@ R584 WL_R_LED#
1
ACES_85201-1205 CONN@
KSI1
D
2 G
28 PWR_SUSP_LED 3
1 2 3 4 5 6 7 8 9 10 11 12
VF
KSO15
1
+5VALW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
JP36
CONN@
C67
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ACES_85201-16051 CONN@
ACES_85201-26051
1 R669
PWR_LED#
C895 1
2 @ 100P_0402_50V8J
ON/OFFBTN#
C896 1
2 @ 100P_0402_50V8J
WL_R_LED#
C898 1
2 @ 100P_0402_50V8J
BT_LED#
C899 1
2 @ 100P_0402_50V8J
PWR_SUSP_LED#C900 1
2 @ 100P_0402_50V8J
2 0_0402_5% 2 0_0402_5%
WL_LED# 28 MINI1_LED# 26
FOR EMI LID_SW#
C897 1
2 @ 100P_0402_50V8J
ARCADE_BTN# C901 1
2 @ 100P_0402_50V8J
NUM_LED#
C902 1
2 @ 100P_0402_50V8J
CAPS_LED#
C903 1
2 @ 100P_0402_50V8J
MEDIA_LED#
C904 1
2 @ 100P_0402_50V8J
PWR_LED# PWR_SUSP_LED#
HT-297DQ/GQ_AMB/YG_0603
+5VALW
R357 300_0402_5% 1 2 R494 1 2 453_0402_1%
LED2 3
1
BATT_GRN_LED#
BATT_GRN_LED# 28
4
2
BATT_AMB_LED#
HT-297DQ/GQ_AMB/YG_0603
BATT_AMB_LED# 28
Compal Electronics, Inc.
Compal Secret Data
Security Classification Issued Date
A
+5VALW
YG
KSO8
+5VS
+5VS
JP2
1
(Right)
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1
KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7
-c o
(Left)
2007/1/15
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
BIOS, I/O Port & K/B Connector Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet
29
of
44
A
B
C
D
E
Power Button ON/OFF switch
HDA MDC Conn.
TOP Side 1
2 @ 10K_0603_5% 2 @ 10K_0603_5%
R749 1 R750
+3VALW +3V
Bottom Side 2
1
R434 100K_0402_5% 1
D27 2
ON/OFF
1
51ON#
3
51ON#
19 HDA_SYNC_MDC 19 HDA_SDIN1 19 HDA_RST_MDC#
28 29,35
1 R117
HDA_SDIN1_MDC 2 39_0402_5%
1 3 5 7 9 11
GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK
2 4 6 8 10 12
1 R522
2
2 0_0402_5%
1
C127 1U_0603_10V4Z
+3V HDA_BITCLK_MDC 19 1
ON/OFFBTN#
29 ON/OFFBTN#
19 HDA_SDOUT_MDC
1
20mil
JP17
DAN202UT106_SC70-3
2
ACES_88018-124G CONN@
13 14 15 16 17 18
1 C545
D26
2
GND GND GND GND GND GND
R509 0_0402_5% 1
C128
1
D Q27
2 G 3
S 2N7002_SOT23
10K_0402_5%
Power ON Circuit +3VS
O
6
O
9
O
8
VS_ON
+RTCVCC
41
For +VCCP/+1.05VS
BAS40-04_SOT23-3 1
11
I
0.1U_0402_16V4Z
Change BATT1 P/N : SP093PA0200 (Panasonic) SP093MX0000 (MAXELL)
U14F SN74LVC14APWLE_TSSOP14
P
14
U14E SN74LVC14APWLE_TSSOP14 O
10
13
I
O
12
1 R761 PM@
2 0_0402_5%
VGA_ON
15
7
7
2
2
+CHGRTC C20
+3VALW
P
14
D16
D5
2 0.1U_0402_16V4Z
G
R307 PM@ 200K_0402_5% SUSP# 1 2 1
14
C319
4
SUSP#
RB751V_SOD323 2 PM@ C330 PM@ 0.1U_0402_16V4Z 1
1 R762
2 @ 0_0402_5%
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
3
R15 1K_0402_5%
1
1
+3VS
I
G
I
G
2
+3VALW
4
+RTCBATT
2 0_0402_5%
U14D SN74LVC14APWLE_TSSOP14
G
0.1U_0402_16V4Z
U14C SN74LVC14APWLE_TSSOP14
7
C333
EC_PWROK
1 R318
P
14
2
5
RB751V_SOD323
SYS_PWROK 6,20
+3VALW
P
10K_0402_1% 2
2 @ 0_0402_5%
For South Bridge
7
1
+3VALW
D18
1 R324
VF
+3VS
SUSP# 1
4
28
3
23,27,28,34,40 SUSP#
U14B SN74LVC14APWLE_TSSOP14
2
14 P
G
I
1
R328
2
3
C300 1U_0805_25V4Z
S
3
7
2 G Q13 2N7002_SOT23
2
O 7
SUSP
I
2
G
2 34,39
3
1
1 D
U14A SN74LVC14APWLE_TSSOP14
P
14
R331 180K_0402_5%
For EMI
+3VALW
1
+3VALW
-c o
1
2
22P_0402_50V8J
1 1
R428
2
2
EC_ON
EC_ON
2
28,37
RLZ20A_LL34 2
1000P_0402_50V7K 1
-c c
Connector for MDC Rev1.5
B
C
D
Title
Power OK, Reset and RTC Circuit, TP Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
30
of
44
A
B
C
D
E
F
G
H
+VDDA 1
28.7K for Module Design (VDDA = 4.702)
1
1
2 1U_0402_6.3V4Z
C591 R483 10K_0402_5%
(output = 250 mA)
60mil
U32
L49 1 2 KC FBM-L11-201209-221LMAT_0805
4
VIN
1 1 L50 1 C581 C588 2 KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z 2 2 0.1U_0402_16V4Z
2
DELAY
7 8
1
VOUT
5
SENSE or ADJ
6
CNOISE
1
ERROR SD
GND
3
40mil
1
C587
2 1
R490
C 2
E
C609 1 1U_0402_6.3V4Z
2
1
R491
3
1
R470 10K_0402_1%
0.1U_0402_16V4Z 2 2.4K_0402_1%
2SC2411K_SOT23
2
560_0402_5%
1
SB_SPKR
1
20
MONO_IN
2
1 R485
Q33
2 B
560_0402_5%
1
D29 RB751V_SOD323 2
2
R493 10K_0402_5%
-c c
2
C576 10U_0805_10V4Z
2
1
C604 1 1U_0402_6.3V4Z
2
2
C599 1 1U_0402_6.3V4Z
BEEP#
4.85V
1
R467 30K_0402_1%
SI9182DH-AD_MSOP8
28
+VDDA
2
2
+5VS
1
+5VAMP
R478 10K_0402_5%
HD Audio Codec +AVDD_HDA
32
LINE_R
HP_OUT_L
39
AMP_LEFT
MIC2_R
HP_OUT_R
41
AMP_RIGHT
23
LINE1_L
NC
45
24
LINE1_R
DMIC_CLK
46
16
MIC2_L
17
MIC1_R
LINE_L
LINE_R
MIC1_L
MIC1_R
3
1 C583 1 C579
MIC1_C_L 2 4.7U_0805_10V4Z MIC1_C_R 2 4.7U_0805_10V4Z MONO_IN
R481 2
1 5.1K_0402_1%
SENSE A
4
SENSE B
CD_R
NC
CD_GND
BIT_CLK
MIC1_L
22
MIC1_R
12
19 HDA_RST_AUDIO#
19 HDA_SYNC_AUDIO
10
5
R484 1 R479 2
2 10K_0402_1% 1 20K_0402_1%
2 3 13 34
SENSE_A
28
32
Impedance
NC
SPDIF
47
EAPD
1 R480
2 SPDIF_R 48 0_0402_5% 4 7
Codec Signals
39.2K
PORT-A (PIN 39, 41)
20K
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-G (PIN 43, 44)
5.1K
PORT-H (PIN 45, 46)
SDATA_IN
PCBEEP
MONO_OUT
LINE1_VREFO
RESET#
GPIO1
SYNC
MIC1_VREFO_L
VF
32 LINEIN_PLUG# 32 MIC_PLUG#
Sense Pin
CD_L
21
11
19 HDA_SDOUT_AUDIO
32 HP_PLUG#
10U_0805_10V4Z
SDATA_OUT MIC1_VREFO_R
GPIO0 GPIO3 SENSE A SENSE B
HP_LEFT 32
HP_RIGHT 32 AMP_LEFT 32
44
8
DVSS1 DVSS2
AVSS1 AVSS2
HDA_SDIN0_AUDIO
HDA_BITCLK_AUDIO 19
1 R486
2 33_0402_5%
HDA_SDIN0 19 WOOFER_MONO
3
31
10mil
28
MIC1_VREFO_L
32
MIC1_VREFO_R MIC2_VREFO CODEC_VREF
10mil 1
40 33 26 42
ALC268-GR_LQFP48_9X9
DGND
2 C596 22P_0402_50V8J
29
27
NC
2 1 0_0402_5%
37
VREF
SPDIFO
1 R507
6
30
JDREF
AMP_RIGHT 32
For EMI
43
MIC2_VREFO
EAPD
C571 10U_0805_10V4Z 2 R476 20K_0402_1%
AGND
Issued Date
2 0_0805_5%
1 R489
2 0_0805_5%
1 R752
2 0_0805_5%
1 R463
2 0_0805_5%
1 R753
2 0_0805_5%
1 R496
2 0_0805_5%
C
D
GNDA
E
GND
GNDA
Compal Electronics, Inc.
Compal Secret Data 2006/12/25
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
1 R751
GND
Security Classification
A
2
9
HP_RIGHT
19
MIC1_L
1
HP_LEFT
20
32
DVDD
35
36
18
32
38
LINE_OUT_L
NC
2
1
LINE_L
MIC2_C_L 2 4.7U_0805_10V4Z MIC2_C_R 2 4.7U_0805_10V4Z LINE_C_L 2 4.7U_0805_10V4Z LINE_C_R 2 4.7U_0805_10V4Z
2
+3VS
C593
0.1U_0402_16V4Z
LINE_OUT_R
NC
15
1
C594
2
INT_MIC_R
32
1 C589 1 C586 1 C580 1 C577
1
L51 MBK1608121YZF_0603 1 2
-c o
32
C595
2
DVDD_IO
14
25
U33
+3VS_DVDD
0.1U_0402_16V4Z 1
AVDD2
2
40mil
0.1U_0402_16V4Z L47 1 2 FBM-L11-160808-800LMT_0603 1 1 1 C573 C569 C572 10U_0805_10V4Z 2 2 2 0.1U_0402_16V4Z
AVDD1
+VDDA
20mil
F
Title
HD Audio Codec ALC268 Size B
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Monday, April 16, 2007 G
Sheet
31 H
of
44
4
B
C
+3VS
D
E
+5VAMP R50
2
2
VOL_AMP
39K_0402_5%
2
Gain= 14dB
C561 1U_0603_10V4Z 2
1
1
C905
26
S
BIAS
2 EC_MUTE G Q58 2N7002_SOT23
C575
HP_R HP_L
INR_H INL_H /SD
8 9
SPKL+ SPKL-
17 18
HPOUT_R HPOUT_L
CVSS
15
VSS
16
GND PGND PGND CGND GND
2 23 7 13 29
BEEP
12 14
CP+ CP-
25
BIAS
1 APA2057A_TSSOP28
2.2U_0805_10V6K 2
2
2 0.01U_0402_16V7K
3
R474 100K_0402_5%
1
HP EN
4 6
28
1
VDD
24
HP_RIGHT_R 39K_0402_5% HP_LEFT_R
2
1
D
20 10
2 100K_0402_5%
HP_RIGHT_C 1 2.2U_0805_10V6K R471 HP_LEFT_C 1 2.2U_0805_10V6K R468
R472 30K_0402_5%
VOL_AMP
19
R469 1
LOUT+ LOUT-
+5VAMP
To AUDIO/B Connector
1
C563 1U_0603_10V4Z
SPDIF_PLUG#
2
2
SPDIF_PLUG# 2 G Q60
Q17 AO3413_SOT23-3
+5VSPDIF
C543
HPOUT_L 1
2
HPOUT_R 1
2
2
1
20mil
R351 HPOUT_L_1 1 47_0603_5% L27 HPOUT_R_1 1 47_0603_5% L28 R352
HPOUT_L_2 2 FBM-11-160808-700T_0603 HPOUT_R_2 2 FBM-11-160808-700T_0603
31 HP_PLUG#
31
G1 G2
R764 1
3 4
2
HP_PLUG#1 @ R765 2 0_0402_5% 1 2 6 3 SPDIF_PLUG#
4 7 8 10
SPDIF
9
2 100P_0402_50V8J
SINGA_2SJ-E373-T01 CONN@
LINE-IN JACK JP33 8 7 LINEIN_PLUG#
31 LINEIN_PLUG#
5
2
2
1 L55
LINE_L_R 2 FBM-11-160808-700T_0603 1 1
1
R488 2.2K_0402_5%
14 13 12 11 10 09 08
1
TC74LCX74FT_TSSOP14
2
31
MIC1_R
31
MIC1_L
C345 0.1U_0402_16V4Z
1 L52 1 L53
31
R487 2.2K_0402_5%
2 FBM-11-160808-700T_0603
1
2
MIC_PLUG#
MIC_PLUG#
MIC1_R_1
1 C602 220P_0402_50V7K
SINGA_2SJ-E351-S01 CONN@
2
Compal Electronics, Inc. 2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
C
4
(HDA Jack)
Compal Secret Data 2006/12/25
Issued Date
5
3 6 2 1
MIC1_L_1
ENCODER_DIR 28 ENCODER_PULSE 28
Security Classification
A
8 7
4
2 FBM-11-160808-700T_0603
C603 220P_0402_50V7K
JP32
MIC1_VREFO_R
U13
VCC CD2# D2 CP2 SD2# Q2 Q2#
(HDA Jack)
MIC JACK MIC1_VREFO_L
C349 0.1U_0402_16V4Z
CD1# D1 CP1 SD1# Q1 Q1# GND
SINGA_2SJ-E351-S03 CONN@
C601 220P_0402_50V7K
FOR EMI
2
NC7SZ14P5X_NL_SC70-5
2
1
4
3
3 6 2 1
+3VS
1
Y
1
1 2 3 4 5 6 7
1 C329
LINE_L
2
2 10K_0402_5% 1 C341
U12
5 4
LINE_R
2
3
1 R446
LINE_L
R330 100K_0402_5%
1
G
A
1
5
XRE094PHDINB1-2-12-E-7016_3P 4
3
2
0.01U_0402_16V7K
GND
B
1
1 2 R436 10K_0402_5%
0.01U_0402_16V7K
COM
2
@ 31 PSOT24C-LF-T7_SOT23-3 D32
0.1U_0402_16V4Z
P
2
2 A
LINE_R
FBM-11-160808-700T_0603 LINE_R_R 2
C613 220P_0402_50V7K 2
2
R435 10K_0402_5%
31
L54 1
1
C347 2
+3VS
NC
4
R450 10K_0402_5%
GND
U29
1
1
+3VS
5
220P_0402_50V7K
3
2
VF +3VS
2
JP31
INT_MIC_R2
Volume Control Circuit
S
2 0_0402_5%
C416
0.1U_0402_16V4Z
3
D
2N7002_SOT23
ACES_88266-02001 CONN@
C614
G1 G2
S
1
R523 FBMA-L11-160808-121LMT_0603 INT_MIC_R2 INT_MIC_R 1 2 INT_MIC_R 31 1 2 R524 FBMA-L11-160808-121LMT_0603 1 C36
1 2
1
2N7002_SOT23
SPDIF +5VSPDIF
2
1 2
Right
330P_0402_50V7K
15mil
JP4
1 2
S/PDIF Out JACK LINE Out/Headphone Out
C415
R51 2.2K_0402_5%
+3VALW
D
2
1
+5VAMP
0.1U_0402_16V4Z
2 G Q59
MIC2_VREFO
C612
1 2
+5VSPDIF
-c o
0.1U_0402_16V4Z
Left
HP_PLUG# R760 100K_0402_5%
R350 100K_0402_5%
330P_0402_50V7K 1
Int MIC Conn.
G1 G2
ACES_88266-02001 CONN@
+5VAMP
C418
2
3 4
JP34
FBMA-L11-160808-121LMT_0603 SPK_R+ 2 SPK_R2 FBMA-L11-160808-121LMT_0603
2
HP_LEFT
/AMP EN
1 1
HP_RIGHT
31
2
ROUT+ ROUT-
27
1 2
3 4
2
1
31
HP_RIGHT 1 C574 HP_LEFT 1 C570
INR_A INL_A
2 100K_0402_5%
SPKR+ SPKR-
-c c
+5VAMP +5VAMP
1 1 R26
R473 1
2
HPF Fc = 604Hz
SPKR+ SPKR-
22 21
1 2
ACES_88266-02001 CONN@
20mil R28
3
3 5
Int. Speaker Conn.
1
560_0402_5%
2
560_0402_5%
U31
PVDD PVDD
1
1
AMP_LEFT
11
2
HVDD
AMP_LEFT_C-1 1 2 1 C584 C585 0.47U_0603_16V4Z R477 R475
AMP_RIGHT_C 1U_0402_6.3V4Z AMP_LEFT_C 1U_0402_6.3V4Z
CVDD
2
D
1
S
31
AMP_RIGHT_C-1 C582
1
1
C568 C564 0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z
C578 0.47U_0603_16V4Z 1 2
AMP_RIGHT
1
2 0_0402_5%
R38
G
31
@
JP3
FBMA-L11-160808-121LMT_0603 SPK_L+ 2 SPK_L2 FBMA-L11-160808-121LMT_0603
1 1
3
R745 1
SPKL+ SPKL-
W=40mil
2 0_0402_5%
1
R744 1
1
+5VAMP
3
A
D
Title
Amplifier & Audio Jack Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
32
of
44
@
H4 H_S354D138
@
1
@
H30 H_S354D138
1
@
H10 H_S354D138
1
@
H11 H_S354D138
1
@
H2 H_S354D138
1
@
H18 H_S354D138
1
@
H3 H_S354D138
1
1
FAN1 Conn
H20 H_S354D138
1
H29 H_S354D138
@
+5VS +5VS
Change to SC1BAS16000
JP16
@
@
1
1
@
1
@
H21 H8 H_C236BC131D128 H_C236BC131D128
1 2 3 ACES_85205-03001 CONN@
2
@
H5 H_C158D158N
H26 H_C205D98
@
@
H27 H_O197X158D197X158N
For MDC
@
H25 H_C205D98
For FAN and MXM
@
H22 H_O89X58D59X28
@
1
C442 1000P_0402_50V7K
@
@
1
1
@
-c c 1
FAN_SPEED1
@
H23 H_O89X58D59X28
FD6 @
FD8
FD9
FD10
FD11
@
@
@
@
1
FD7
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
FD13
FD14
FD15
FD16
@
FIDUCIAL_C40M80
@
FIDUCIAL_C40M80
@
FIDUCIAL_C40M80
1
FD12
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
@
@
FIDUCIAL_C40M80
Compal Electronics, Inc.
Compal Secret Data 2007/1/15
Deciphered Date
@
FIDUCIAL_C40M80
@
FIDUCIAL_C40M80
FIDUCIAL_C40M80
1
FD5 @
1
FD4 @
1
FD3
@
FIDUCIAL_C40M80
Security Classification Issued Date
@
1
1
FD2
@
1
1
FD1
@
1
1
-c o
1
For DDR Metal Cage
VF
28
1
40mil
@
H13 H14 H32 H33 H31 H_C236BC131D128 H_C236BC131D128 H_C236BC131D128 H_C236BC131D128 H_C236BC131D128
R365 10K_0402_5% +VCC_FAN1
@
1
1
C445 1000P_0402_50V7K 1 2
@
1
+3VS
@
H28 H_C335BC140D138
For CPU Support Breket
BAS16_SOT23-3 C446 10U_0805_10V4Z 1 2
1
2
@
H24 H_S354BC140D138
H6 H16 H17 H7 H_C236BC168D165 H_C236BC168D165 H_C236BC168D165 H_C236BC168D165
1
1
G993P1UF_SOP8
@
1
1
D21
1
8 7 6 5
2
GND GND GND GND
1
EN_DFAN1
VEN VIN VO VSET
2
28
1 2 3 4
+VCC_FAN1 EN_DFAN1
H19 H1 H_C315BC236D138 H_C315BC236D138
1
H15 H_S354D138 D22 1SS355_SOD323-2
1
U20
1
10U_0805_10V4Z 2
1
C443 1
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
FAN & Screw Hole Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet
33
of
44
A
B
C
+3VALW TO +3V_SB(ICH8M AUX Power) +3VALW
+5VS
C631
1
1 2 3 4
C633
AO4468_SO8
1
C629
10U_0805_10V4Z 2 2 1U_0603_10V4Z
1
2 10U_0805_10V4Z
D
27,28,40
SYSON
SYSON#
SYSON
+VSB
3V_GATE
2 1 R505 200K_0402_5%
1 1
C506 SBPWR_EN# 2 Q39G 2N7002_SOT23
0.1U_0603_25V7K
S
D 2
2 SBPWR_EN# G Q38 2N7002_SOT23
D
S
1
Q29 2N7002_SOT23
2 G
R440 100K_0402_5%
C632 0.1U_0603_25V7K
+5VALW
S 2
3
2
S
SYSON#
2
3
1
D
2 SUSP G Q23 2N7002_SOT23
SUSP
2 Q24G 2N7002_SOT23
24,26,27
D
3
1
S
R506 470_0603_5%
3
5VS_GATE
2 1 R412 200K_0402_5%
+VSB
1
1
2
S S S G
1
R411 470_0603_5%
D D D D
3
C495
10U_0805_10V4Z 2 2 1U_0603_10V4Z
10U_0805_10V4Z 2 2 10U_0805_10V4Z
1
8 7 6 5
2 C503
AO4468_SO8
1
1
1
1
1
C504
1 2 3 4
1
1
R455 100K_0402_5%
U34 S S S G
1
C498
D D D D
+5VALW
+3V
U22 8 7 6 5
E
2
+5VALW TO +5VS +5VALW
D
+3VALW
+3VS
D
+1.8V to +1.8VS +1.8V
+1.8VS
1 2 3 4
C533
1.8VS_GATE
S
3
3
1
1
+5VALW
R379 100K_0402_5%
21
SBPWR_EN#
SBPWR_EN#
D
2 G Q43 S 2N7002_SOT23
28 SBPWR_EN
R510 100K_0402_5%
3
2
VF S
D
2 SUSP G Q22 2N7002_SOT23
S
R424 470_0603_5% @
1
1
R342 470_0603_5% @
1
2 1
D
2 SUSP G Q19 2N7002_SOT23
+1.8V
R403 470_0603_5%
1
D
+0.9VS 2
3
1
1
1
R374 470_0603_5%
1
R204 470_0603_5%
S
C542
+1.05VS
2
2
+2.5VS
2 SUSP G Q11 2N7002_SOT23
2 SUSP G Q26 2N7002_SOT23 PM@
0.1U_0603_25V7K 2 PM@
Q28 S 2N7002_SOT23 PM@
D
S 1
D
2 G
+1.5VS
D
1
SUSP
10U_0805_10V4Z 2 PM@ 2 1U_0603_10V4Z PM@
R427 470_0603_5% PM@
3
3
2 1 R439 510K_0402_5% PM@
1
3
+VSB
C531
1
C547 SI4856ADY_SO8 10U_0805_10V4Z PM@ 2 PM@ 2 10U_0805_10V4Z PM@ SI4856/AO4430
1
1
S S S G
3
1
1
C553
1
D D D D
2
U24 8 7 6 5
2
2
3
S 5VS_GATE
2 SUSP G Q12 2N7002_SOT23
R457 100K_0402_5%
1
10U_0805_10V4Z 2 2 1U_0603_10V4Z
R306 470_0603_5%
Q31 2N7002_SOT23
1
1
S
3
C299
1
AO4468_SO8
1
D
2 G
2
2 C301
10U_0805_10V4Z 2 2 10U_0805_10V4Z
2
SUSP
2
1
-c o
C343
1 2 3 4
D
2 SUSP G Q16 2N7002_SOT23 @
S
3
1
S S S G
1 1
C344
D D D D
SUSP
23,27,28,30,40 SUSP#
U10 8 7 6 5
30,39
1
+3VALW TO +3VS
3
-c c
R462 100K_0402_5%
2 SYSON# G Q25 2N7002_SOT23 @
4
4
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
DC Interface Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
34
of
44
A
B
PD1 RLZ24B_LL34
1
3
2
2
VL
2
B+
PR12 2.2M_0402_5% 1
1
2
2
PQ3 DTC115EUA_SC70-3
PR13 499K_0402_1%
2
ACIN
2
1
ML1220T13RE 45@ 4
1
D
1
1
2
Compal Electronics, Inc.
Compal Secret Data 2007/01/16
Deciphered Date
2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
+5VALW
2
4
Security Classification
A
PACIN 37,38
PQ6 DTC115EUA_SC70-3
@ PR22 66.5K_0402_1%
BATT ONLY Precharge detector Min. typ. Max. H-->L 6.138V 6.214V 6.359V L-->H 7.196V 7.349V 7.505V
Issued Date
1
3
S
+RTCBATT
+RTCBATT
PQ5 PR21 RHU002N06_SOT323-3 47K_0402_5% 2 2 1 G
3
+
PBJ1
PR20 34K_0402_1% 2 1
RTCVREF
PR19 499K_0402_1%
2
-
Precharge detector Min. typ. Max. H-->L 14.589V 14.84V 15.243V L-->H 15.562V 15.97V 16.388V
PR18 191K_0402_1%
2
2
PC10 0.1U_0603_25V7K
1
RB715F_SOT323-3
3
1
2
PRG++ 2
3
-
32.8
PC7 1U_0805_25V4Z
+
O
1
8 1
3
4
ACON
VF
GND 1
2
1
37
PU2A LM393DT_SO8
PC11 1000P_0402_50V7K
2
1
IN
1 2
560_0603_5% 560_0603_5%
OUT
PD5
2
3
2
19,36,38 MAINPWON
2
PR17
2 1
2
1
PC8 1
+CHGRTC
4.7U_0805_6.3V6K
PR16
3
PR14 100K_0402_1%
P
PR15 200_0805_5% PU1 G920AT24U_SOT89-3
G
RTCVREF
3.3V
2
1
1
VS
PC9 0.01U_0402_25V7K
-c o
PC6 0.1U_0603_25V7K
1 2
ACOFF
3
1 2 2
2
PR11 22K_0402_5% 1 2
1
0.22U_1206_25V7K
PC5 2 1
1
3
PR10 100K_0402_5%
51ON#
28,37
VS
3
CHGRTCP
PR8 100K_0402_5%
1
1 1 PR9 33_1206_5% PQ4 TP0610K-T1-E3_SOT23-3
29,30
PQ2 DTC115EUA_SC70-3
2
BATT+ 2
1
2 PD3 RLS4148_LLDS2 PD4 RB751V-40TE17_SOD323-2 2 1
2
2
-c c
PR7 1K_1206_5% 1 2
1
E&T_4510-E04C-01R
VIN
B+
1
PR4 1K_1206_5% 1 2
RLS4148_LLDS2
100K_0402_5%
2
PR6
1
PQ1 TP0610K-T1-E3_SOT23-3
PR5 1
1
1
PR3 1K_1206_5% 1 2
PD2
VIN
2
2
1
2
PR2 1K_1206_5% 1 2
1 2
2
PR1 10_1206_5%
560P_0402_50V7K
3
PC4 2 1
3
1
12P_0402_50V8J
4
PC3 2 1
4
VIN
12P_0402_50V8J
5
FBMA-L18-453215-900LMA90T_1812 1 2
PC2 2 1
G1
PL1
ADPIN
560P_0402_50V7K
6
PC1 1
G2
D
100K_0402_5%
PJP1
C
C
Title
DCIN/DECTOR Size B Date:
Document Number
JDW50/JDY70
Sheet
Monday, April 16, 2007 D
Rev 0.2
LA3771P 35
of
44
A
B
C
D
MAX8744_B+ MAX8744_B+
B+
PL2
5 6 7 8 G S S S
13
30
CSL5
CSL5
FB3
FB3
11
FB5
7
REF
FB5
OUTA
1
2
PR41 @ 47K_0402_5%
PC29 1U_0603_6.3V6M
fESR3.3V starts up delay 2ms after 5V starts up
22
PGOOD3
27
PGOOD5
14
1
ILM
3
38
+
2
PR36 0_0402_5% 2 12VREF_8744
@ PR37 499K_0402_1% 1 2
GND
ILIM
@ PR196 2.2_1206_5%
2
0_0402_5% 12VREF_8744 0_0402_5% 2
SPOK
8
ONA
ON3
1
2
PGOODA
PR182 1
ON5
PR40 0_0402_5% 1 2
PR179 0_0402_5% 2 1
PC30 0.047U_0402_16V7K 2 1
19,35,38 MAINPW ON
PR39 0_0402_5%
2
5
@ PR38 0_0402_5%
@ PR32 2
SHDN
FSEL
6
10
FBA
9
PC28 0.22U_0603_25V7K
SKIP
2VREF_8744
4
PC26 4.7U_0805_6.3V6K 1 2
VL
LDO5
20
2
+5VALWP
PR33 10K_0402_1% 1 2
2
PC25 1000P_0402_50V7K
2
CSH5
CSH5
PL4 10UH_SIL104R-100PF_4.4A_30%
CSL3
12
1
28
PC27 150U_D2_6.3VM
CSL3
PR29 6.49K_0402_1%
CSH3
PR31 15.4K_0402_1% 1 2
PGND
19
29
2
CSH3
@
1
DL5
PR27 2.61K_0402_1% 2 1
PC22 0.22U_0603_16V7K 1 2
18
1 2
1
DL5
2
DL3
PC162 680P_0402_50V7K
17
1
LX5
2
PQ9 SI4810BDY-T1-E3_SO8 4 G D 5 3 S D 6 2 S D 7 1 S D 8
LX3
32
2
Notes :
1
PC20
23
DRVA
1
Delta I=((Vin-Vo)*D)/(F*L) =((19-3.3)*(3.3/19))/(300K*10U) =0.908A
PR25
24
PC24 0.22U_0603_10V7K 2
VF
Ilimit = 185mV/24.96m ~ 215mV/20.68m = 7.41A ~ 10.39A Iocp(mean) = Ilimit -Delta I/2 =6.956A~9.936A
DH5 BST5A 2
DL3
31
2
1
16 15
LX3
PR34 100K_0402_5% 21 2
DCR = 29m ohm(typical) ; Rcs = 20.68m ohm
DH5 BST5
1
PZD1 RLZ5.1B_LL34 VS
PR35 200K_0402_5% 1 2
DCR = 35m ohm(max) ; Rcs = 24.96m ohm
BST3
-c o
+3VALWP Ipeak = 5.5A; Imax = 4A
DH3
26
1
2 1
1
3
PC17 1U_1206_25V7K 1 2
21
2VREF_8744
2
PC23 1000P_0402_50V7K
25
IN
0.1U_0603_25V7K LX5
1
PC21 0.22U_0603_16V7K
EP
0_0603_5%
@
2
33
-c c
8 7 6 5 D D D D S S S G
PC19 0.1U_0603_25V7K
1 2 3 4
PQ10 SI4810BDY-T1-E3_SO8
DH3 PR24 1 BST3A 0_0603_5%
2VREF_8744 1
1
2
2
1
1
PC161 680P_0402_50V7K 2 1
PR23 2.61K_0402_1% 1 2
PR28 6.49K_0402_1% 2 1
PR30 10K_0402_1%
2
PR26 6.81K_0402_1% 1 2
+
2
PC18 330U_D3L_6.3VM_R25M
1
PU3 MAX8744ETJ+_TQFN32_5X5
2 @ PR195 2.2_1206_5% 2 1
1
PQ8 SI4800BDY-T1-E3_SO8
4 3 2 1
1 2 3 4 PL3 10UH_SIL104R-100PF_4.4A_30%
+3VALWP
1
D D D D
PC16 2200P_0402_50V7K 2 1
PC15 4.7U_1206_25V6K 2 1
PC14 4.7U_1206_25V6K 2 1
8 7 6 5 PQ7 SI4800BDY-T1-E3_SO8
S S S G
1
D D D D
PC13 4.7U_1206_25V6K 2 1
PC12 2200P_0402_50V7K 2 1
FBMA-L18-453215-900LMA90T_1812 1 2
+5VALWP Ipeak = 5.5A ; Imax = 4A
3
DCR = 35m ohm(max) ; Rcs = 24.96m ohm DCR = 29m ohm(typical) ; Rcs = 20.68m ohm Ilimit = 185mV/24.96m ~ 215mV/20.68m = 7.41A ~ 10.39A Iocp(mean) = Ilimit -Delta I/2 =6.796A~9.776A Delta I=((Vin-Vo)*D)/(F*L) =((19-5)*(5/19))/(300K*10U) 1.228A
@
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/01/16
Deciphered Date
2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title
+5VALWP/+3VALWP Size Document Number Custom JDW50/JDY70 Date:
Rev 0.1
LA3771P Sheet
Monday, April 16, 2007 D
36
of
44
A
B
Iada=0~4.74A(90W)
PL15
CSIN
17
DH_CHG
10
ACLIM
VDDP
15
14
GND
PGND
13
7
+ -
6
0
4 1 1
5 6 7 8
G S S S
4 3 2 1
1 2
PR192 11.5K_0402_1% 2
6251aclim
2 UMA@ PQ47 RHU002N06_SOT323-3
2
1
PC147 0.01U_0402_25V7K
D
S
PR194 20K_0402_1%
2
PR178 200K_0402_1%
1
1
1
1
-
6251VREF
2
0
PR176 300K_0603_0.1%
1
PU11A LM358ADT_SO8 + 3
BATT-OVP=0.1487*BATT+
2 G
28 65W/90W#
4
4
4
1
LI-3S :13.50V--BATT-OVP=2.007V PR175 845K_0603_1%
2
1 PR177 10K_0402_5% 1 2
2
@ PR187 20K_0402_1%
8
@
PC145 0.01U_0402_25V7K
3
E
1
12.90V
@ PQ46 2SC2411K_SOT23-3
3
LOW
1 2
2 1 CSON
PU11B LM358ADT_SO8 5
BATT-OVP=0.1487*BATT+
C
2
8
HIGH
3
LI-4S :18.0V--BATT-OVP=2.677V
BATT+
VS
6251_EN
2 B
28 BATT_OVP
P
13050mV
2
BATT+
3
1
PQ45 RHU002N06_SOT323-3
CV mode 17.20V
@PR186 @PR186 100K_0402_1%
1
S
2 G
CALIBRATE
G
2800mAH 3S pack
4
OVP voltage :
1
2 1
28
D
VS
LOW
PC144 4.7U_0805_6.3V6K
1
ISL6251AHAZ-T_QSOP24
2
LOW
CHGSEL
CHGSEL
26251VDD
PR171 4.7_0603_5%
P
17400mV
DL_CHG
1
2
LGATE
PQ40 SI4800BDY-T1-E3_SO8
VADJ
PD14 RB751V-40TE17_SOD323-2
6251VDDP
PR199 4.7_1206_5% 2 1
16
1
BOOT
5 6 7 8
CHLIM
PC140 0.1U_0603_25V7K BST_CHGA 2 1
D D D D
9
PR167 2.2_0603_5% BST_CHG 1 2
2
PR165 0.02_2512_1%
PL16 10UH_PCMB104T-100MS_6A_20% CHG 1 2
G S S S
VREF
1
UGATE
8
3
PHASE
ICM
S
PC141 10U_1206_25V6M 2 1
19
18
1
CSIP
PQ38 SI4800BDY-T1-E3_SO8
2
VCOMP
7
PC132 0.1U_0603_25V7K
6
20
PQ36 RHU002N06_SOT323-3 2 PACIN G
D 3
CSIN
PD13 1SS355TE-17_SOD323-2 1 2
D D D D
ICOMP
2
5
CSOP
4 3 2 1
21
PC146 0.01U_0402_25V7K
3S/4S#
-c c
CSOP
1
1
3 CELLS
CSON
1
Charging Voltage (0x15)
2800mAH 4S pack
4
PR197 20_0603_5% 1 2 PC133 0.047U_0603_16V7K 1 2 PR161 20_0603_5% 2 1 PR162 20_0603_5% PC136 0.1U_0603_25V7K 1 2 PR198 2.2_0603_5% LX_CHG
2
UMA@ PR193 2.37K_0402_1%
BATT Type
22
PC154 0.01U_0402_25V7K
IREF=0.43V~3.24V
CSON
VF
IREF=0.7224*Icharge
EN
PQ33 DTC115EUA_SC70-3
6251VREF
2 28
CC=0.6~4.48A
23
BATT+
VIN
PR183 274K_0402_1%
Vaclim=2.39*((10K//152K)/((5.76K//152K)+(10K//152K))) =1.502V
2
1
2 2
1
PQ42 SI2301BDS-T1-E3_SOT23-3
2
1
PR173 274K_0402_1% 1 2
D
3
PR174 100K_0402_1%
CP mode Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A
ACSET ACPRN
3
12
G
3
2
11
S
6251VREF
DCIN
24
2
2
6251aclim
3
ACOFF
2
ACOFF
3
28,35
PC139 1 2
0.1U_0402_16V7K
PR170 100K_0402_1%
DCIN
2
PQ41 DTC115EUA_SC70-3
PR164 100_0402_1% 1 2 6251VREF
ADP_I
PR156 200K_0402_1% 1 2
1
IREF
10K_0402_1% 2
2 PC138 100P_0402_50V8J
PR168 80.6K_0402_1% 2 1 1
28
6251_EN
VDD
PC131 0.1U_0603_25V7K 2 1
-c o
PQ39 RHU002N06_SOT323-3 28
1
6800P_0402_25V7K 2
1
PC143 0.01U_0402_25V7K 2 1
S
2 G
ACON
ACON
1
PACIN
1
35
PACIN
D
3
35,38
PR166 22K_0402_5% 1 2
PU10
2
PR163 1
EC_ON 28,30
RB715F_SOT323-3
1
PC137 1 2 0.01U_0402_25V7K
EC_ON
3
100K_0402_1%
2
PC135 1
21
1
2
3S/4S#
2
28
@ PC134 680P_0402_50V7K CSON 1 2 3
PR160 150K_0402_1%
100K_0402_1%
PQ35 DTC115EUA_SC70-3
1
3
S PQ37 RHU002N06_SOT323-3
3
1
D
2 G 2
PR158 47K_0402_5%
PQ34 DTC115EUA_SC70-3
1
VIN
PD11 1SS355TE-17_SOD323-2 ACOFF 1 2
PR155 10K_0402_1%
2FSTCHG
PR185
6251VDD
2
1 2 PC153 0.1U_0402_16V7K
2
PQ44 DTC115EUA_SC70-3
PR154 47K_0402_1% 1 2
PD17
PR159 2
6251VDD 1
1
PR184 100K_0402_1% 2 1
FSTCHG
PC129 0.1U_0603_25V7K
2
PR157 10K_0402_5% 2 1
1
1
1
28
DCIN
1
PC130 2.2U_0603_6.3V6K 2 1
PC128 5600P_0402_25V7K 1 2
PD16 1SS355TE-17_SOD323-2 1
2
2
3
VIN
PC163 680P_0402_50V7K
4 2
1 2 3
PC127 0.1U_0603_25V7K
1
4 1 2 PQ32 DTA144EUA_SC70-3
PR153 200K_0402_1%
1
CSIP
PQ43 TP0610K-T1-E3_SOT23-3
8 7 6 5
PC126 2200P_0402_25V7K 2 1
3
1
PR152 47K_0402_1%
1 2 3 PC125 0.1U_0603_25V7K 2 1
2
PQ31 AO4407_SO8
CHG_B+
FBMA-L18-453215-900LMA90T_1812 1 2
4
PC124 10U_1206_25V6M 2 1
1
PC142 10U_1206_25V6M 2 1
B+
PR151 0.02_2512_1%
P3 8 7 6 5
PC123 10U_1206_25V6M 2 1
PQ30 AO4407_SO8 1 2 3
G
P2 1 2 3
4
PQ29 AO4407_SO8 8 7 6 5
D
CP = 85%*Iada ; CP = 4.07A
ADP_I = 19.9*Iadapter*Rsense
VIN
C
Normal 4S LI-ON Cells
16800mV
LOW
HIGH
16.80V
Normal 3S LI-ON Cells
12600mV
HIGH
HIGH
12.60V
HIGH
HIGH
12.60V
Wake up charge while no communication
-
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/01/16
Deciphered Date
2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
C
Title
CHARGER Size
Document Number
JDW50/JDY70 Date:
Rev 1.0
LA3771P
Monday, April 16, 2007
Sheet D
37
of
44
A
B
C
D
PH1 under CPU botten side : CPU thermal protection at 90 degree C Recovery at 70 degree C
2 PH1 100K_0603_1%_TH11-4H104FT 2 1
2
1
2 TM_REF1
+
6
-
P
8
PU2B LM393DT_SO8
5
O
MAINPW ON 19,35,36
7
1
PR49 150K_0402_1% 2 1 VL
PR51 150K_0402_1%
2
BATT_TEMP 28
-c o
BATT_TEMP
PR42 150K_0402_1%
2
PR50 1K_0603_1% 2
PR45 82.5K_0603_1% 1 2
PC35 1U_0805_16V7K 2 1
1
PC34 1000P_0402_50V7K
2
+3VALW P
PR44 442K_0603_1% 2
1
-c c
PR48 6.49K_0603_1% 1 2
PC33 0.01U_0603_50V7K
PC31 0.1U_0603_25V7K
4
1 2
2
PC32 1000P_0603_50V7K
1
PR47 100_0603_1% 2 1
PR46 100_0603_1% 2 1
1
2
PR43 9.76K_0402_1%
G
BATT+
TSA EC_SMC1 EC_SMD1
1
BATT++
1
VL
VS PL5 FBMA-L18-453215-900LMA90T_1812 1 2
1
SUYIN_200275MR007G161ZL PJP2
1 2 3 4 5 6 7
VL
BATT++
1
EC_SMB_CK1 15,28,29 EC_SMB_DA1 15,28,29
PR52 1M_0402_1% 1 2 VIN
1
1
VIN
1
SPOK
D
S
8
20,28
PACIN
35,37
3
1
G
P
ACIN
PR58 10K_0402_5%
2
PZD2 RLZ4.3B_LL34
RTCVREF
2
2
ACIN
PACIN
1
1
1
PU4B LM393DT_SO8
+
6
-
P
8
Vin Detector Min. typ. Max. H-->L 16.976V 17.257V 17.728V L-->H 17.430V 17.901V 18.384V
5
O
7
G
2
4 PR60 10K_0402_5% 2 1
PC39 0.1U_0603_25V7K
PQ12 RHU002N06_SOT323-3
2 G 1
36
PR63 0_0402_5% 1 2
3
1
PR62 100K_0402_5%
PC38 0.22U_1206_25V7K
-
PR55 10K_0402_5% 1 2
4
2
VL
2
PR61 22K_0402_5% 1 2
+
2
1 PC37 0.1U_0603_25V7K
1
PR59 100K_0402_5%
3
PU4A LM393DT_SO8 O 1
2
+VSBP
1
2
1
2
3
B+
PC36 1000P_0402_50V7K
PR57 20K_0402_1% 2 1
PQ11 TP0610K-T1-E3_SOT23-3
2
VF
3
PR56 22K_0402_5% 1 2
PR54 10K_0402_5%
2
VS
PR53 84.5K_0402_1%
4
@ PC40 0.1U_0402_16V7K
2
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/01/16
Deciphered Date
2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title
BATTERY CONN. / OTP Size B Date:
Document Number
JDW50/JDY70
Rev 0.2
LA3771P Sheet
Monday, April 16, 2007 D
38
of
44
5
4
3
2
1
1
1
+3VALW
PJP3 JUMP_43X118
PC73 10U_0805_6.3V6M 1 2
PJP4 JUMP_43X118
2
PU6
9
1
PJP5 2
PJP6 1
1
+3VALW
+1.8VP
JUMP_43X118
2
1
+5VALW
+2.5VSP
2
1
+0.9VS
+1.5VSP
2
2
1
1
1
PR112 60.4K_0402_1% PC80 0.047U_0402_16V7K
D
PQ20 RHU002N06_SOT323-3 2 G
PR116 0_0402_5% 1 2
SUSP C
S
+1.8V
2
2
1
1
+2.5VS
2
2
1
1
+1.5VS
PJP12
1
1
JUMP_43X118
+1.05VS
+VSBP
2
2
1
1
VF
2
2
JUMP_43X118
PJP13
+1.05VSP
REFEN
VTT
PJP10
1
JUMP_43X118
B
6 5
JUMP_43X118
PJP9 2
VCCA
PJP8
1
JUMP_43X118
+0.9VSP
VTT
JUMP_43X118
PJP7 2
+5VALWP
2
4
-c o
2
3
7
-c c
C
+3VALWP
AGND
2 1
PC79 22U_1206_10V6M
2
1
1
PC77 22U_1206_10V6M
2
+0.9VSP 2
S
2 G
RT9173DPSP_SO8 PC78 0.1U_0402_16V7K 2 1
D
PQ19 RHU002N06_SOT323-3 PR114 1K_0402_1% 2 1
1
30,34 SUSP
PR113 0_0402_5% 1 2
VFB
PC76 1U_0603_16V6K 1 2
GND
+2.5VSP
1
8
PGND
3
NC
8
VIN
2
NC
VOUT
2
1
REFEN
2
4
1
PC75 1U_0603_6.3V6M
7 2
PR110 1K_0402_1%
3
SUSP
5
PU7
CM8562IS_PSOP8
1
NC
+3VALW
2
GND
3
6
PR115 200K_0402_1%
VCNTL
PR111 10_0603_1%
1
1
2
2
PC74 10U_0805_6.3V6M
VIN
RTCVREF
1
1
AGND
2
+1.8V
D
+5VALW
9
D
PC81 0.1U_0603_25V7K
1
1
2
2
+1.8V
B
+VSB
JUMP_43X118
PJP14
+1.05VSP
2
2
1
1
+1.05VS
JUMP_43X118
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/01/16
2008/01/16
Deciphered Date
+0.9VSP/+2.5VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
Title
2
Size Document Number Custom JDW50/JDY70 Date:
Rev
LA3771P
Monday, April 16, 2007
0.1 Sheet
1
39
of
44
5
4
3
2
1
+5VALW
D
23,27,28,30,34 SUSP#
1 +5VALW
1 PR132 100K_0402_5%
VFB=0.5V Vo=VFB*(1+PR122/PR127)=1.805V Ipeak=12.17A, Imax=8.519A
BST2
21
TON2
DH2
20
10
VOUT2
LX2
19
11
VCCA2
12
FB2
13
PGD2
BST_1.5V1 2 0_0603_5% DH_1.5V
FB_1.5V
VSSA2
DH_1.5V-1
PC93 1 2
PR126 0_0603_5% 1 2
0.1U_0603_25V7K
ILIM2
18
VDDP2
17
DL2
16
DL_1.5V
PGND2
15
PC97 33P_0402_50V8K FB_1.5V
PC100 1U_0603_10V6K
PR133 0_0402_5% 1
A
1 +
2
Close to IC Side
B
Differential routing of feedback to VSSA2 and VOUT2 PIN
2
2
@ PC102 0.1U_0402_16V7K
VFB=0.5V Vo=VFB*(1+PR129/PR130)=1.5V Ipeak=5.16A, Imax=3.612A Ton=(3.3E-12*(PR125+37K)*(Vout/VBat))+50ns =0.3201us
=3.3*10e-12*(820K+37K)*(1.8/19)+50ns=0.3179us
Max:11.5 mOhm
+1.5VSP
Vout_1.5V
PR130 10K_0402_1%
Ton=(3.3E-12*(PR121+37K)*(Vout/VBat))+50ns
FDS6670AS:Rds(on)=>Typ:9 mOhm
Maximum continuous current=>6A PL11 2.2UH_SIQB74B-2R2-R_6.5A_20% 1 2
VFB=0.5V
@ PC101 0.1U_0402_16V7K
C
AO4916_SO8
LX_1.5V
PR128 ILIM_1.5V1 2 29.4K_0402_1% +5VALW
1 2 3 4
1
EN/PSV2
9
PR124
G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A
PC98 330U_D2E_2.5VM
22
8 7 6 5
1 PR129 20K_0402_1%
EN/PSV1
BST1
PR121 2 1 B+_1.8/1.5 820K_0402_5%
B+_1.8/1.5
2
Vout_1.8V
23
1
24
TON1
2
VOUT1
DH1
PQ22
PC90 4.7U_1206_25V6K
LX1
PGOOD1_1.8V
PC89 4.7U_1206_25V6K 2 1
VCCA_1.8V
PC88 1000P_0402_50V7K 1 2
VF
PGOOD2_1.5V
25
27,28,34 SYSON
2
B
VCCA1
SC413TSTRT_TSSOP28
2
2
to VSSA1 and VOUT1 PIN
ILIM1
8
14
Close to IC Side
FB_1.8V
2
PC96 1000P_0402_50V7K
Differential routing of feedback
26
1
Vout_1.5V VCCA_1.5V
27
FB1
VDDP1
2
PR125 1M_0402_5%
PR131 0_0402_5% 1
1 2
0_0603_5%
1
28
-c o
D D D D PQ23 SI4810BDY-T1-E3_SO8
2
VSSA1
PGD1
DL1
1
8 7 6 5
1
0.1U_0603_25V7K B+_1.8/1.5
1 2 3 4
PR127 10K_0402_1%
PC91 2
PGND1
1
1 2
PR122 26.1K_0402_1%
1
S S S G
2
FB_1.8V
1
+
2
1
PC92 33P_0402_50V8K
2
PC94 330U_D2E_2.5VM
C
DH_1.8V 6 PR123 2 BST_1.8V 7
-c c
PR119 0_0603_5% DH_1.8V-1 1 2
1
Vout_1.8V
3
1 2
DL_1.8V 2 PC87 1 2 +5VALW 3 1U_0603_10V6K 1 2 ILIM_1.8V4 PR120 34.8K_0402_1% LX_1.8V 5
1
PL10 1UH_SIL104-1R0-R_11A_30% 1 2
PU8
1
2
D D D D
8 7 6 5
BST_1.8V-1
2
+1.8VP
1 2 3 4
Maximum continuous current=>6A
PR118 100K_0402_5%
BST_1.5V-1
PQ21 SI4800BDY-T1-E3_SO8
S S S G
PC85 4.7U_1206_25V6K 2 1
PC86 4.7U_1206_25V6K 2 1
2
VCCA_1.5V
2
B+_1.8/1.5
PL9 FBMA-L11-322513-151LMA50T_1210 1 2
2
1 2
B+
PD9 CHP202UPT_SOT323-3
VCCA_1.8V PC149 1U_0603_10V6K
PR117 10_0603_5%
1
PR180 10_0603_5%
1
PC82 2.2U_0603_6.3V6K
PC83 1U_0603_10V6K
2
1
1
D
AO4916 Rds(on)=>Typ:21 mOhm Max:27 mOhm Ivalleymin=9*10u*(29.4K/0.027*1.4)=7A
Iocp=Ivalley+Iripple/2
Ivalleymax=11*E-6*(29.4K/0.021*1.1)=12.833A
Iripple=(vin-vout)*(Ton/L)=5.467A, 1/2 Iripple=2.734A.
Iripple=(vin-vout)*(Ton/L)=2.546A, 1/2Iriiple=1.273A
Ivalleymin=10E-6*(PR120/Rds(ON)max*1.5)
Iocp=Ivalley+Iripple/2
=9*10e-6*(27.4K/0.0115*1.5)=14.295A>11.73*1.2=14.076A
OCP==>8.273A~14.106A
A
Ivalleymax=10E-6*(PR120/Rds(ON)typ*1.2) =11*10e-6*(27.4K/0.009*1.2)=27.907A.
Compal Electronics, Inc.
Compal Secret Data
Security Classification
OCP==>17.029A~30.641A
2007/01/16
Issued Date
Deciphered Date
2008/01/16
+1.5VSP/+1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
Title
2
Size Document Number Custom JDW50/JDY70 Date:
Monday, April 16, 2007
Rev
LA3771P Sheet 1
0.1 40
of
44
5
4
3
2
1
D
D
1
1
+5VALW
PR134 10_0603_5%
FB
4
PGD
LX
11
LX_1.05V
10
ILIM_1.05V
9
+5VALW
ILIM
0.1U_0603_25V7K
1 2 34K_0402_1%
2
PC110 4.7U_1206_25V6K
PR147 10K_0402_1%
1 +
2
2
PC120 1U_0603_10V6K
+1.05VSP
Vout_1.05V
1
G S S S
FB_1.05V
1
DL_1.05V
Close to IC Side
B
Differential routing of feedback to VSSA2 and VOUT2 PIN
VF
B
2
PC117 PQ28 33P_0402_50V8K SI4810BDY-T1-E3_SO8
4 3 2 1
VFB=0.5V
Maximum continuous current=>6A
1 5 6 7 8 D D D D
DL
VDDP
C
PL14 1UH_SIL104-1R0-R_11A_30% 1 2
PR145
8
PGND
7
NC
VSSA
6
TP
17
PU9 SC411MLTRT_MLPQ16_4X4
5
PGOOD2_1.05V
1
1
1 2 0_0603_5%
PC109 4.7U_1206_25V6K 2 1
15
14
13
DH_1.05V
B+
1 PR146 11K_0402_1%
3
12
PL12 FBMA-L11-322513-151LMA50T_1210 1 2
2
VCCA
BST
2
BST_1.05V
DH
PC113 1 2
-c o
2
FB_1.05V
VOUT
PR141
2
VCCA_1.05V
1
NC
16
PR149 100K_0402_5%
TON
1
Vout_1.05V
EN/PSV
+5VALW
B+_1.05
PQ26 SI4800BDY-T1-E3_SO8 4 G D 5 3 S D 6 2 S D 7 1 S D 8
1 2
C
BST_1.05V-1
PC116 1000P_0402_50V7K
PD10 1SS355TE-17_SOD323-2
PC118 330U_D2E_2.5VM
VCCA_1.05V
1
PR142 1M_0402_5% B+_1.05 2 1
2
@ PC121 @PC121 0.1U_0402_16V7K
PC104 1U_0603_10V6K
2
-c c
2
PC103 2.2U_0603_6.3V6K
2 1 2
30 VS_ON
PR148 0_0402_5% 1 2
VFB=0.5V, Ipeak=9.37A, Imax=6.559A The current rating of +1.05VSP include +VCC_GFX current. Vo=VFB*(1+PR146/PR147)=1.05V Ton=(3.3E-12*(PR142+37K)*(Vout/VBat))+50ns=0.2391us SI4810BDY:Rds(on)=>Typ:16mOhm Max:20mOhm Ivalleymin=9*10E-6*(PR145/Rds(ON)max*1.5) =9*10E-6*(34K/(0.02*1.5))=10.200A Ivalleymax=11*10E-6*(PR145/Rds(ON)min*1.3) =11*10E-6*(34K/(0.016*1.3))=17.981A Iripple=(vin-vout)*(Ton/L)=4.292A, 1/2Iripple=2.146A Iocp=Ivalley+Iripple/2
OCP==>12.346A~20.127A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/01/16
Issued Date
Deciphered Date
2008/01/16
4
3
Title
+1.05VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
A
2
Size Document Number Custom JDW50/JDY70 Date:
Monday, April 16, 2007
Rev
LA3771P Sheet 1
0.1 41
of
44
5
4
3
2
1
+5VS
B+
CPU_B+
PR64 0_1206_5% 5VS1 2 1
DL1_CPU
5
CPU_VID4
2
1
35
D4
PGND1
27
5
CPU_VID5
2
1
36
D5
GND
18
5
CPU_VID6
1
2
37
D6
CSP1
17
CSP1_CPU
71.5K_0402_1% 1 7
TIME
CSN1
16
CSN1_CPU
2
CCV
FB
12
FB_CPU
BST2
20
BST2_CPU
3
PSI
LX2
22
LX2_CPU
2
PWRGD
DL2
24
DL2_CPU
1
CLKEN
PGND2
23
POUT
CSN2_CPU
GNDS
13
2
2
+3VS
PR100 100_0402_5%
Iload = Ivalley + delta IL/2 Per phase, Iocp=23.279A~30.288A
PC69 1000P_0402_50V7K 1 2 CSP1_CPU
A
PC70 1000P_0402_50V7K 1 2 CSN1_CPU
@ PC42 100U_25V_M
PC47 0.1U_0603_25V7K 2 1
PC48 2200P_0402_50V7K 2 1
R2
R3
PR108 3.48K_0402_1% 1 2
A
Compal Electronics, Inc. 2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3
2
Ceq
Compal Secret Data Deciphered Date
PH4 10KB_0603_5%_ERTJ1VR103J 2
NTC 1
PC68 0.22U_0603_16V7K 放放Choke附附
2007/01/16
放放Choke附附
R1
1
Issued Date
4
Rdcr
PR109 0_0402_5% 1 2
Security Classification
5
PC46 10U_1206_25VAK 2 1
PC45 10U_1206_25VAK 2 1 1
25.5mV
B
PL8 0.36UH_PCMC104T-R36MN1R17_30A_20% 2 1
3 2 1
4
2
Rcs = Rdcr*(R2+R3)/(R1+R2+R3) Ivalley = VIlim / Rcs
PQ16 SI7686DP-T1-E3_SO8
PQ17 FDS6676AS_SO8
Valley current limit threshold : 19.5mV ~
2 100_0402_5%
CPU_B+
2
PC66 0.1U_0402_16V7K
PR85 0_0402_5%
PR97 20K_0402_1%
PC72 1000P_0402_50V7K 1 2 CSN2_CPU
1
PR105 10_0402_5%
PC71 1000P_0402_50V7K 1 2 CSP2_CPU
POUT
C
放放Choke附附
PC58 470P_0603_50V8J 1 2
2
PR103 0_0603_5% 1 2
1
PR104 10K_0402_5% 1 2 2
28
VSSSENSE
VF
5
VSSSENSE
0.22U_0603_16V7K
PC57 4700P_0402_25V7K
1
2
B
1
1
PR101 56_0402_5%
2
PR92
5 6 7 8
@ PR99 10K_0402_5% 1
PR98 0_0402_5%
VRHOT
1
1
VR_ON
2
28
MAX8770GTL+_TQFN40
41
14 CLK_ENABLE#
1
PC54
1
@ PR95 3K_0603_1% 1 2
@ PR94 3K_0603_1%
10KB_0603_5%_ERTJ1VR103J 1 2
@ PC56 1000P_0402_50V7K CPU_VCC_SENSE 1 2
3.65K_0402_1% 2 2
15
PR88
14
TP
6,14,20 VGATE
CSP2
CSN2
1
VRHOT
1K_0402_1% 2
PR91 1
BSTM2_CPU
1
4
SHDN
PC60 2 1
5
@ PR87 1
-c o
38
@ PR90 2K_0402_1%
PC59 4700P_0402_25V7K 1 2
2
2 1
PR89 2K_0402_1%
CSP2_CPU
PH3 2
放放Choke附附
PR86 0_0402_5% 1 2
1
DPRSTP
PC62 10U_1206_25VAK 2 1
40
2
DH2_CPU
PC61 10U_1206_25VAK 2 1
21
5
10
DH2
2
+3VS
2 0_0402_5% 2 0_0402_5%
CCI
DPRSLPVR
D D D D
PSI#
REF
G S S S
5
11
0.22U_0603_16V7K 39
CCI_CPU
4 3 2 1
1 PR83 1 PR84
4,19 H_DPRSTP#
PC55
9
PQ18 FDS6676AS_SO8
6,20 PM_DPRSLPVR
1 PC53 2
NTC PR79 3.48K_0402_1% 1 2 1
+CPU_CORE
5
LX1_CPU
26
VCCSENSE
28
DL1
1
LX1
D3
2
D2
34
PR80 10_0402_5% 2 1
33
1
PC65 2200P_0402_50V7K 2 1
1
2
PC64 0.1U_0603_25V7K 2 1
2
CPU_VID3
PL7 0.36UH_PCMC104T-R36MN1R17_30A_20% 2 1
PR107 2.1K_0402_1% 2 1
CPU_VID2
5
C
D
+CPU_CORE
PR71 0_0603_5% 1 2
2
PC63 10U_1206_25VAK 2 1
5
BSTM1_CPU 1
PR76 2.1K_0402_1% 1 2
DH1_CPU
PR106 4.7_1206_5%
29
PC67 680P_0402_50V7K
DH1
PR74 4.7_1206_5% 2 1
D1
PC52 680P_0402_50V7K 2 1
32
3 2 1
1
5 6 7 8
2
D D D D
BST1_CPU
CPU_VID1
G S S S
30
5
4 3 2 1
BST1
PQ15 FDS6676AS_SO8
D0
5 6 7 8
31
D D D D
1
G S S S
2
47P_0603_50V8J 1
2
4
-c c
CPU_VID0
PR82 499_0402_1% 1 2
PC44 10U_1206_25VAK 2 1
2
5
PR81 2
+
Use one 220uF or two 100uF PC51 0.22U_0603_16V7K
PR69 0_0603_5% 1 2
PQ14 FDS6676AS_SO8
TON
8
4 3 2 1
PR78 0_0402_5%
25
5 6 7 8
PR77 0_0402_5%
THRM
VDD
D D D D
PR75 0_0402_5%
Vcc
G S S S
PR73 0_0402_5%
6
4 3 2 1
PR72 0_0402_5%
19
0_0603_5%
PR70 0_0402_5%
VCC
0.22U_0603_16V7K
PR68 0_0402_5%
PQ13 SI7686DP-T1-E3_SO8
1
PU5
1
NTC PH2 @PH2 @ 100K_0603_1%_TH11-4H104FT 1 2
5
1
PR67 13K_0402_1%
1
2
2
PC49 PC50 2.2U_0603_6.3V6K 1U_0603_6.3V6M
PR66 200K_0402_5% 2 1
D
2
2
1
PR65 10_0402_5%
PC43 0.01U_0402_25V7K
1
PL6 FBMA-L18-453215-900LMA90T_1812 1 2
2
Title
+CPU_CORE Size Document Number Custom JDW50/JDY70 Date:
Rev 0.2
LA3771P
Monday, April 16, 2007
Sheet 1
42
of
44
5
4
3
2
Version change list (P.I.R. List) Item
Reason for change
EC GPIO pin modify
EC GPIO pin modify
2
clk frequency error
3 4
Rev.
PG#
Modify List
0.1 ==> 0.2
8
DPST_PWM net modify
pin error
0.1 ==> 0.2
14
Q48,Q49,Q50 pin error
EC add a GPIO pin
EC GPIO pin modify
0.1 ==> 0.2
16
del DPST_PWM net from North Bridge
follow ICL50
follow ICL50
20
CRT_DET# net modify
0.1 ==> 0.2
Date
EMI request
0.1 ==> 0.2
24
Add R477, R748
ESD request
ESD request
0.1 ==> 0.2
25
reserve D30,D31
7
test
test
0.1 ==> 0.2
26
reserve MINI1_LED#
8
Blue LED issue
Blue LED issue
0.1 ==> 0.2
27
BT_LED# schematic modify
0.1 ==> 0.2
28
EC GPIO pin define modify
0.1 ==> 0.2
29
reserve C895 to C904
0.1 ==> 0.2
30
change J1,J2 jumper sybmol to 0603 symbol
0.1 ==> 0.2
31
Add R751,R752,R753
0.1 ==> 0.2
32
U31 chip update version
-c c
EMI request
6
EC GPIO pin modify
EC GPIO pin modify
10
ESD request
ESD request
11
easy short
easy short
12
ESD request
ESD request
13
chip issue
chip issue
14
voice too small
modify gain value
0.1 ==> 0.2
32
change R472 form 39k to 30k ohm
15
EMI request
EMI request
0.1 ==> 0.2
32
change R523,R524,R50,R38,R26,R28 for 0 ohm to bead
16
DFX request
DFX request
0.1 ==> 0.2
33
del pjp15
17
Wireless Lan S4 fail
Wireless Lan fail
0.2 ==> 0.3
26
del R756, add R757
18
Wireless Lan S4 fail
Wireless Lan fail
0.2 ==> 0.3
26
change C906,C907 from 22u_1206 to 10u_0805
19
Lead Free
non LF==>Lead Free
0.2 ==> 0.3
17
change C211,C510,C514,C216,C508,C515
20
KBC version update
KBC version update
0.2 ==> 0.3
28
reserve 0.1u at pin 124
21
SPDIF udpate
SPDIF circuit udpate
0.2 ==> 0.3
32
add q59,q60
22
DFX
DFX issue
0.2 ==> 0.3
32
del JP13
24 25 26 27
D
3/19
5
23
Phase
C
-c o
B
Fixed Issue
1
9 C
Page 1 of 1 for PWR
VF
D
1
B
28 29 A
A
30 Compal Electronics, Inc. Title
PIR (HW)
5
4
3
2
Size
Document Number
Date:
Monday, April 16, 2007
LA-3771P
JDW50
Sheet 1
43
of
44
Rev 0.2
5
4
3
2
Version change list (P.I.R. List) Item
Page 1 of 1 for PWR
Fixed Issue
Reason for change
1
Charger IC damage issue
Charger IC damage issue
2
Charger IC damage issue
3 4
Modify List
Date
Phase
Change PR161 from SD013220B80 to SD013200A80
D
40
Charger IC damage issue
0.2
40
Charger IC damage issue
Charger IC damage issue
0.2
40
Charger IC damage issue
Charger IC damage issue
0.2
40
5
Charger IC damage issue
Charger IC damage issue
0.2
40
Add PC133 SE026473K80
6
Add EMI solution in charger.
Add EMI solution in charger.
0.3
40
Add PR199 SD001470B80(S RES 1/4 4.7 1206 5%).
04/01/07
PVT
7
Add EMI solution in charger.
Add EMI solution in charger.
0.3
40
Add PC163 SE074681K80(S CER CAP 680P 50V K X7R 0402)
04/01/07
PVT
9 10 11 12
Change PR162 from SD013180A80 to SD013200A80 Add PR197 SD013200A80 Add PR198 SD013220B80
C
-c o
13 14 15 16 17 18 19 20
B
VF
B
PG#
0.2
8
C
Rev.
-c c
D
1
21 22 23 24 25 26 27 28 29 A
A
30 Compal Electronics, Inc. Title
PIR (PWR)
5
4
3
2
Size
Document Number
Date:
Monday, April 16, 2007
LA-3121P
HCW51
Sheet 1
44
of
44
Rev 0.2
B
C
D
E
1
1
-c c
Compal Confidential 2
2
-c o
JDW50/JDY70 Schematics Document
Intel Merom Processor with Crestline(PM945/GM945) + DDRII + ICH7M (With ATI MXM/B)
2007-4-12
3
VF
3
REV: 0.3
4
4
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Cover Page Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
1
of
44
A
B
C
Compal Confidential page 33
uPGA-478 Package (Socket M) page
1
DVI-D Conn.
LCD Conn.
CRT & TV-out
page 16
page 16
page 4
4,5 1
H_D#(0..63)
533/667MHz
Intel 945/PM/GM/943GML
LVDS SDVO
Memory BUS(DDRII) Dual Channel
PCI-Express
-c c
DMI
page 15
Intel ICH7-M
USB port 1
WLAN
Boardcom page 26
page 24
USB port 7
3.3V 33 MHz
Bluetooth Conn page
CMOS Camera
27
USB port 5
page 16
USB port 3 2
USB
3.3V ATA-100
BGA-652
HD Audio
IDE
S-ATA
page 20,21,22,23
-c o
page 27
3.3V 48MHz
3.3V 24.576MHz/48Mhz
PCI BUS LAN(GbE)
USB conn x2
USB port 0, 2
PCI-Express
MINI Card x1
C-Link
page 26
IDSEL:AD20 (PIRQA#, GNT#2, REQ#2)
page 12,13
BANK 0, 1, 2, 3
page 6,7,8,9,10,11
MXM II VGA/B
New Card Socket
200pin DDRII-SO-DIMM X2
1.8V DDRII 533/667
uFCBGA-1466
2
page 14
page 17
LVDS
DVI
Clock Generator
ADM1032
FSB
H_A#(3..35)
E
Thermal Sensor
Intel Merom Processor
Fan Control
Model Name : JDW50/70 File Name : LA-3771P
D
Card Reader
CDROM Conn. page 22
port 0, 1
MDC 1.5 Conn page 30
HDA Codec ALC268 page 31
ENE MR510
page 23
RJ45 page 25
4 in 1 socket
LS3553P
Power On/Off CKT. page 30
DC/DC Interface CKT.
LED/B Conn.
page 29
page 32
page 29
EC I/O Buffer
LS3551P
3
Phone Jack x3
Int.KBD
Touch Pad
LS3557P
page 29
USB Conn.
page 32
page 28
page 29
page 30
Audio AMP
ENE KB926
VF
BTN/B Conn.
RTC CKT.
22
LPC BUS
page 23
3
SATA HDD Conn. page
BIOS
page 29
page 29
USB port 4, 6 page 34
Power Circuit DC/DC 4
page 35
page 26
AUDIO/B Conn. w/Woofer(JDY70)
LS3558P 4
page 32
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Block Diagrams Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
2
of
44
A
B
C
D
SIGNAL
STATE
Voltage Rails
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
Description
S1
S3
S5
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
VIN
Adapter power supply (19V)
N/A
N/A
N/A
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
+0.9VS
0.9V switched power rail for DDR terminator
ON
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
+1.05VS
1.05V switched power rail
ON
OFF
OFF
+1.25VS
1.25V switched power rail
ON
OFF
OFF
+1.5VS
1.5V switched power rail
ON
OFF
OFF
+1.8V
1.8V power rail for DDR
ON
ON
OFF
+1.8VS
1.8V switched power rail
ON
OFF
OFF
Vcc Ra/Rc/Re
+2.5VS
2.5V switched power rail
ON
OFF
OFF
Board ID
+3VALW
3.3V always on power rail
ON
ON
ON*
+3V
3.3V power rail for SB
ON
ON
X
+3V_LAN
3.3V power rail for LAN
ON
ON
X
+3VS
3.3V switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
0 1 2 3 4 5 6 7
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC
V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V
V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V
BOARD ID Table Board ID 0 1 2 3 4 5 6 7
IDSEL# AD16
Address
Smart Battery
0001 011X b
EEPROM(24C16/02)
1010 000X b
GMT G781-1
1001 101X b
Interrupts PIRQE
0
EC SM Bus1 address Device
REQ#/GNT#
Device
Device
Address
Clock Generator (ICS9LPRS365)
1101 001Xb
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
BTO Item Discrete UMA DVI SATA*1 SATA*2 Dbg
BOM Structure PM@ GM@ DVI@ SATA*1@ SATA*2@ Dbg@
EC SM Bus2 address
3
Address
ADI ADM1032
ICH7M SM Bus address
2
1001 100X b
VF
Device
V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V
BTO Option Table
PCB Revision 0.1
-c o
External PCI Devices Card Reader
1
Board ID / SKU ID Table for AD channel
2
3
Clock
Power Plane
-c c
1
Full ON
E
4
4
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Notes List Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
3
of
44
5
4
3
2
1
JP22A
6 6
J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31#
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
K3 H2 K2 J3 L5
REQ0# REQ1# REQ2# REQ3# REQ4#
L2 V4
ADSTB0# ADSTB1#
H_ADSTB#0 H_ADSTB#1
YONAH
ADDR GROUP
DATA GROUP
C
6 6 6 6
H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRDY# H_HIT# H_HITM#
H_IERR#
H_LOCK# H_RESET#
H_RESET# H_RS#0 H_RS#1 H_RS#2
6
H_TRDY#
B
XDP_DBRESET#
20 XDP_DBRESET# 6 H_DBSY# 19 H_DPSLP# 19,42 H_DPRSTP# 6 H_DPW R#
XDP_BPM#5 H_PROCHOT# H_PW RGOOD H_CPUSLP# XDP_TCK XDP_TDI XDP_TDO TEST1 TEST2 XDP_TMS XDP_TRST#
19 H_PW RGOOD 6 H_CPUSLP#
THERMDA THERMDC 6,19 H_THERMTRIP# A
BCLK0 BCLK1
H1 E2 G5 F1 H5 F21 G6 E4 D20 H4 B1
ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT# HITM# IERR# LOCK# RESET#
F3 F4 G3 G2
HOST CLK
CONTROL
RS0# RS1# RS2# TRDY#
AD4 AD3 AD1 AC4
BPM0# BPM1# BPM2# BPM3#
C20 E1 B5 E5 D24 AC2 AC1 D21
DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT#
D6 D7 AC5 AA6 AB3 C26 D25 AB5 AB6
PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST#
DINV0# DINV1# DINV2# DINV3# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3#
MISC
A20M# FERR# IGNNE# INIT# LINT0 LINT1
THERMAL
A24 A25 C7
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
H_D#[0..63]
H_A#[3..31] H_REQ#[0..4] H_RS#[0..2]
H_D#[0..63]
H_A#[3..31]
6
6
H_REQ#[0..4] H_RS#[0..2]
6
6
D
XDP_TDI
J26 M26 V23 AC20
H23 M24 W24 AD23 G22 N25 Y25 AE24
A6 A5 C4 B3 C6 B4
LEGACY CPU
THERMDA DIODE THERMDC THERMTRIP#
STPCLK# SMI#
D5 A3
R59
XDP_TDO
XDP_TMS
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
6 6 6 6
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI
+1.05VS
2
1
56_0402_5%
R525 2
1
56_0402_5%
R63
H_PROCHOT#
-c o
6 6 6 6 6 6
A22 A21
E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26
VF
14 CLK_CPU_BCLK 14 CLK_CPU_BCLK#
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
-c c
D
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
R114
C
2
1
56_0402_5%
2
1
75_0402_5%
XDP_BPM#5
R46
2
1
56_0402_5%
H_IERR#
R113 2
1
56_0402_5%
XDP_TRST#
R57
2
1
56_0402_5%
XDP_TCK
R37
2
1
56_0402_5%
TEST1
R526
2
1 @ 1K_0402_5%
TEST2
R527
2
1
51_0402_5% B
6 6 6 6 6 6 6 6
+3VS C485 0.1U_0402_16V4Z 1 2
19 19 19 19 19 19
U21
1 C484 2200P_0402_50V7K 2
1
VDD
SCLK
8
EC_SMB_CK2 28
THERMDA
2
D+
SDATA
7
EC_SMB_DA2 28
THERMDC
3
D-
ALERT#
6
4
THERM#
GND
5
H_STPCLK# 19 H_SMI# 19
ADM1032ARMZ_MSOP8 A
FOX_PZ47903-2741-42_YONAH
Layout Note: THERMDA & THERMDC Trace / Space = 10 / 10 mil
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Merom (1/2) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
4
of
44
5
4
3
2
1
+CPU_CORE
VCCSENSE VSSSENSE
R20
2 1 R21 100_0402_1%
VCCSENSE AF7 VSSSENSE AE7
+1.5VS D
C148 10U_0805_10V4Z
1
1
2
2
+1.05VS
C153
0.01U_0402_16V7K
Layout Note: Place C626 near Pin B26
+1.05VS
42
PSI#
2
42 42 42 42 42 42 42
B26
VCCA
K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
AE6
PSI#
AD6 AF5 AE5 AF4 AE3 AF2 AE2
VID0 VID1 VID2 VID3 VID4 VID5 VID6
1
R366 1K_0402_1%
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
VCCSENSE VSSSENSE
Trace Close CPU < 0.5' 14 14 14
2
C
1
R369 2K_0402_1%
27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1%
GTL_REF0
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
1 R376 1 R375 1 R54 1 R56
2 2 2 2
+CPU_CORE
B
COMP0 COMP1 COMP2 COMP3
AD26
GTLREF
B22 B23 C21
BSEL0 BSEL1 BSEL2
R26 U26 U1 V1
COMP0 COMP1 COMP2 COMP3
E7 AB20 AA20 AF20 AE20 AB18 AB17 AA18 AA17 AD18 AD17 AC18 AC17 AF18 AF17
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 AC16 AF16 AE16 AB13 AA14 AD13 AC14 AF13 AE14 AB11 AA11 AD11 AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 F5 E6 H6 J5 M5 L6 P6 R5 V5 U6 Y6 A4 D4 E3 H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1
1
1
+ C669
2
1
+ C670
330U_D2E_2.5VM_R9
2
+ C671
@
330U_D2E_2.5VM_R9
2
330U_D2E_2.5VM_R9
South Side Secondary +CPU_CORE
3 x 330uF(9mOhm/3) 1
1
+ C672
2
330U_D2E_2.5VM_R9
1
+ C673 @ 330U_D2E_2.5VM_R9 2
+ C674
2
330U_D2E_2.5VM_R9
North Side Secondary +CPU_CORE
1
10U_0805_6.3V6M 1 C676
C675
2 10U_0805_6.3V6M
1
+CPU_CORE
10U_0805_6.3V6M 1 1 C685 C682
2 10U_0805_6.3V6M
10U_0805_6.3V6M 1 C678
1
C677
10U_0805_6.3V6M 1 C680
10U_0805_6.3V6M 1 1 C686 C683
1
C679
2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on South side,Secondary Layer)
2
10U_0805_6.3V6M 1 C649
C681
2 10U_0805_6.3V6M
2
10U_0805_6.3V6M 1 1 C684 C687
2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on South side,Secondary Layer)
2
+CPU_CORE
1
10U_0805_6.3V6M 1 C689
1
C688
2 10U_0805_6.3V6M
10U_0805_6.3V6M 1 C691
1
C690
10U_0805_6.3V6M 1 C693
C692
2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on North side,Secondary Layer)
2
+CPU_CORE
1
10U_0805_6.3V6M 1 C695
1
C694
2 10U_0805_6.3V6M
2
VF
D2 F6 D3 C1 AF1 D22 C23 C24 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 T22 B25
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
YONAH
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE18 AE17 AB15 AA15 AD15 AC15 AF15 AE15 AB14 AA13 AD14 AC13 AF14 AE13 AB12 AA12 AD12 AC12 AF12 AE12 AB10 AB9 AA10 AA9 AD10 AD9 AC10 AC9 AF10 AF9 AE10 AE9 AB7 AA7 AD7 AC7 B20 A20 F20 E20 B18 B17 A18 A17 D18 D17 C18 C17 F18 F17 E18 E17 B15 A15 D15 C15 F15 E15 B14 A13 D14 C13 F14 E13 B12 A12 D12 C12 F12 E12 B10 B9 A10 A9 D10 D9 C10 C9 F10 F9 E10 E9 B7 A7 F7
-c c
20mils
42 42
JP22C
3 x 330uF(9mOhm/3)
-c o
+CPU_CORE
+CPU_CORE JP22B
POWER, GROUNG, RESERVED SIGNALS AND NC
100_0402_1% 2 1
10U_0805_6.3V6M 1 C697
1
C696
10U_0805_6.3V6M 1 C699
1
C698
2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on North side,Secondary Layer)
10U_0805_6.3V6M 1 C668
C700
2 10U_0805_6.3V6M
+CPU-CORE Decoupling SPCAP,Polymer
C,uF
ESR, mohm
6X330uF
9m ohm/6
1.8nH/6
MLCC 0805 X5R
32X22uF
3m ohm/32
0.6nH/32
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
ESL,nH
+1.05VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C701
+
1
C702
1
C703
1
C704
1
C705
1
C706
1
C707
1
FOX_PZ47903-2741-42_YONAH
220U_D2_2VMR15
2
2
2
2
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
2
C708 @
2
0.1U_0402_16V4Z
1
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
YONAH
POWER, GROUND
K1 J2 M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 A19 D19 C19 F19 E19 B16 A16 D16 C16 F16 E16 B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 G23 K23 L24 P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
D
C
B
FOX_PZ47903-2741-42_YONAH C709 @
2 0.1U_0402_16V4Z
A
A
TRACE CLOSELY CPU < 0.5'
Compal Electronics, Inc.
Compal Secret Data
Security Classification
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Space 25mils (55Ohms)
2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Merom (2/2) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
5
of
44
H_A#[3..31]
D8 G8 B8 F8 A8
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
HADSTB#0 HADSTB#1
B9 C13
H_ADSTB#0 H_ADSTB#1
HCLKN HCLKP
AG1 AG2
CLK_MCH_BCLK# CLK_MCH_BCLK
HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3
K4 T7 Y5 AC4 K3 T6 AA5 AC5
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
J7 W8 U3 AB10
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_ADSTB#0 4 H_ADSTB#1 4 CLK_MCH_BCLK# 14 CLK_MCH_BCLK 14 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
4 4 4 4 4 4 4 4
DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3
20 20 20 20
DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3
20 20 20 20
DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
AE35 AF39 AG35 AH39
DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3
DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3
AC35 AE39 AF35 AG39
DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3
DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3
AE37 AF41 AG37 AH41
DMITXN0 DMITXN1 DMITXN2 DMITXN3
DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
AC37 AE41 AF37 AG41
DMITXP0 DMITXP1 DMITXP2 DMITXP3
12 12 13 13
AY35 AR1 AW7 AW40
DDRA_CLK0 DDRA_CLK1 DDRB_CLK0 DDRB_CLK1
DDRA_CLK0# DDRA_CLK1# DDRB_CLK0# DDRB_CLK1#
AW35 AT1 AY7 AY40
SM_CK0# SM_CK1# SM_CK2# SM_CK3#
12 12 13 13
DDRA_CKE0 DDRA_CKE1 DDRB_CKE0 DDRB_CKE1
AU20 AT20 BA29 AY29
SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3
12 12 13 13
DDRA_SCS#0 DDRA_SCS#1 DDRB_SCS#0 DDRB_SCS#1
AW13 AW12 AY21 AW21
SM_CS0# SM_CS1# SM_CS2# SM_CS3#
T37 T38
12 12 +1.8V13 13
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
PAD PAD
4 4 4 4
DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1
R426 180.6_0402_1% 2 R425 1 2 80.6_0402_1%
HVREF0 HVREF1 HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING
B7 E8 E7 J9 H8 C3 D4 D3 B3 C7 C6 F6 A7 E3
HRS0# HRS1# HRS2#
B4 E6 D6
H_ADS# H_TRDY# H_DPW R# H_DRDY# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# H_CPUSLP#
H_RESET# 4 H_ADS# 4 20 PM_BMBUSY# H_TRDY# 4 PM_EXTTS#0 H_DPW R# 4 12,13 PM_EXTTS#0 PM_EXTTS#1 H_DRDY# 4 R5301 0_0402_5% 2 4,19 H_THERMTRIP# H_DEFER# 4 GMCH_PW ROK H_HITM# 4 MCH_RSTIN# H_HIT# 4 H_LOCK# 4 18 MCH_ICH_SYNC# H_BR0# 4 H_BNR# 4 H_BPRI# 4 H_DBSY# 4 H_CPUSLP# 4 H_RS#[0..2]
H_RS#0 H_RS#1 H_RS#2
AL20 AF10
SM_OCDCOMP0 SM_OCDCOMP1
BA13 BA12 AY20 AU21
SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3
SMRCOMP SMRCOMP#
SM_VREF
HCPURST# HADS# HTRDY# HDPWR# HDRDY# HDEFER# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP#
SM_CK0 SM_CK1 SM_CK2 SM_CK3
12 12 13 13
AV9 AT9
SM_VREF0 SM_VREF1
G28 F25 H26 G6 AH33 AH34
PM_BMBUSY# PM_EXTTS0# PM_EXTTS1# PM_THERMTRIP# PWROK RSTIN#
18,20,22,24,28 PLT_RST#
R326
ICH_SYNC#
CALISTOGA_FCBGA1466~D PM@
4
MCH_RSTIN# 100_0402_5%
Layout Note: H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 10/20. 5
2
0.1U_0402_16V4Z C712
100_0402_1%
1
R539
2
0.1U_0402_16V4Z C711
2
C40 D41
CLK_REQ#
H32
MCH_CLKREQ#
CLK_DREF_96M# 14 CLK_DREF_96M 14 CLK_DREF_SSC# 14 CLK_DREF_SSC 14 MCH_CLKREQ# 14 C
NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18
A3 A39 A4 A40 AW1 AW41 AY1 BA1 BA2 BA3 BA39 BA40 BA41 C1 AY41 B2 B41 C41 D1
RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13
T32 R32 F3 F7 AG11 AF11 H7 J19 A41 A34 D28 D27 A35
VGATE 1 R333 SYS_PW ROK 1 R332
2 SM_VREF
1 C894 @ 0.1U_0402_16V4Z 2
20,30 SYS_PW ROK
C354
1
0.1U_0402_16V4Z 2
R335 100_0402_1% 20,42 PM_DPRSLPVR
1 R536
B
GMCH_PW ROK 2 @ 0_0402_5% 2 0_0402_5%
2007/1/15
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3
PM_EXTTS#0 R183 PM_EXTTS#1 2 0_0402_5% R196
+3VS
10K_0402_5% @
A
10K_0402_5%
Compal Electronics, Inc.
Compal Secret Data
Security Classification Issued Date
4
D_REF_SSCLKN D_REF_SSCLKP
CLK_DREF_SSC# CLK_DREF_SSC
CLK_MCH_3GPLL 14 CLK_MCH_3GPLL# 14
1
20/20mil
H_SW NG1
1
CLK_DREF_96M# CLK_DREF_96M
D
2
1
221_0603_1%
R535
2
1
R534
2 2 R538
1
0.1U_0402_16V4Z C710
200_0603_1%
2
100_0402_1%
2
100_0402_1%
R533
1 1 R537
1
1
A27 A26
D_REF_CLKN D_REF_CLKP
MCH_CLKSEL0 14 MCH_CLKSEL1 14 MCH_CLKSEL2 14 T17 T22 CFG5 10 T20 CFG7 10 T19 CFG9 10 T18 CFG11 10 CFG12 10 CFG13 10 T15 T21 CFG16 10 T16 CFG18 10 CFG19 10 CFG20 10
reserve VGATE for GMCH_PWROK
R334 100_0402_1%
H_VREF
A
2
H_SW NG0
CLK_MCH_3GPLL CLK_MCH_3GPLL#
14,20,42 VGATE
+1.05VS
221_0603_1%
+1.05VS
AG33 AF33
G_CLKP G_CLKN
+1.8V
CALISTOGA_FCBGA1466~D PM@ +1.05VS
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 CFG3 PAD CFG4 PAD CFG5 CFG6 PAD CFG7 CFG8 PAD CFG9 CFG10 PAD CFG11 CFG12 CFG13 CFG14 PAD CFG15 PAD CFG16 CFG17 PAD CFG18 CFG19 CFG20
SM_RCOMPN SM_RCOMPP
AK1 AK41
K28
K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
CFG
20 20 20 20
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3
CLK
4
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3
NC
H_REQ#[0..4]
20 20 20 20
RESERVED
HDINV#0 HDINV#1 HDINV#2 HDINV#3
Description at page10
U41B
-c o
HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4
4
1
R532 24.9_0402_1% 2 1
R531 24.9_0402_1% 2 1
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
VF
J13 H_VREF K13 H_XRCOMP E1 H_XSCOMP E2 H_YRCOMP Y1 H_YSCOMP U1 H_SW NG0 E4 H_SW NG1 W1
B
H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#
PM
R529 54.9_0402_1% 1 2
+1.05VS
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
1
DDR MUXING
C
F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8
2
DMI
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
D
R528 54.9_0402_1% 1 2
3
U41A
H_D#[0..63]
HOST
4
4
-c c
5
2
Title
Calistoga (1/6) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
6
of
44
5
4
3
2
1
13 DDRB_SDQ[0..63] 12 DDRA_SDQ[0..63] 12 DDRA_SMA[0..13]
DDRB_SDQ[0..63]
DDRA_SDQ[0..63] 13 DDRB_SMA[0..13]
DDRB_SMA[0..13]
DDRA_SMA[0..13]
D
D
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
C
12 12 12 12 12 12 12 12
DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7
DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7
AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7
12 12 12 12 12 12 12 12
DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7#
DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7#
AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5
SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#
DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13
AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13
B
12 DDRA_SCAS# 12 DDRA_SRAS# 12 DDRA_SW E# T28 T30
SA_RCVENIN# SA_RCVENOUT#
AY13 AW14 AY14 AK23 AK24
SA_CAS# SA_RAS# SA_WE# SA_RCVENIN# SA_RCVENOUT#
PAD PAD
AT24 AV23 AY28
SB_BS0 SB_BS1 SB_BS2
DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7
AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7
AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7
DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7#
AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5
SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#
DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13
AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13
SB_RCVENIN# SB_RCVENOUT#
AR24 AU23 AR27 AK16 AK18
SB_CAS# SB_RAS# SB_WE# SB_RCVENIN# SB_RCVENOUT#
13 DDRB_SBS0# 13 DDRB_SBS1# 13 DDRB_SBS2# 13 DDRB_SDM[0..7]
-c c
AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4
DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63
13 13 13 13 13 13 13 13
DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7
-c o
DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7
AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8
13 13 13 13 13 13 13 13
VF
12 DDRA_SDM[0..7]
U41E
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
DDR SYS MEMORY A
SA_BS0 SA_BS1 SA_BS2
DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7#
13 DDRB_SCAS# 13 DDRB_SRAS# 13 DDRB_SW E# T29 T31
PAD PAD
CALISTOGA_FCBGA1466~D PM@
DDR SYS MEMORY B
U41D
AU12 AV14 BA20
12 DDRA_SBS0# 12 DDRA_SBS1# 12 DDRA_SBS2#
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3
DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63
C
B
CALISTOGA_FCBGA1466~D PM@
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Calistoga (2/6) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
7
of
44
5
4
3
2
1
U41C
16 GMCH_TXOUT016 GMCH_TXOUT116 GMCH_TXOUT2-
D
16 GMCH_TZOUT016 GMCH_TZOUT116 GMCH_TZOUT216 16 16 16 15,28
C
R541 GM@ 0_0402_5% 1 2 LBKLT_EN
ENBKL
LA_DATA0 LA_DATA1 LA_DATA2
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-
C37 B35 A37
LA_DATA#0 LA_DATA#1 LA_DATA#2
GMCH_TZOUT0+ GMCH_TZOUT1+ GMCH_TZOUT2+
F30 D29 F28
LB_DATA0 LB_DATA1 LB_DATA2
GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-
G30 D30 F29
LB_DATA#0 LB_DATA#1 LB_DATA#2
GMCH_TXCLK+ GMCH_TXCLKGMCH_TZCLK+ GMCH_TZCLK-
A32 A33 E26 E27
LA_CLK LA_CLK# LB_CLK LB_CLK#
D32 J30 H30 H29 G26 G25 F32 B38 C35 C33 C32
LBKLT_CTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL
A16 C18 A19
TVDAC_A TVDAC_B TVDAC_C
J20
TV_IREF
B16 B18 B19
TV_IRTNA TV_IRTNB TV_IRTNC
R7372 1@ 0_0402_5% LBKLT_EN LCTLA_CLK LCTLB_DATA GMCH_LCD_CLK 16 GMCH_LCD_CLK GMCH_LCD_DATA 16 GMCH_LCD_DATA GMCH_ENVDD 16 GMCH_ENVDD LIBG DPST_PW M
GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA
2 TV_IREF 4.99K_0402_1%
17 GMCH_CRT_VSYNC 17 GMCH_CRT_HSYNC 17 GMCH_CRT_B 17 GMCH_CRT_G 17 GMCH_CRT_R
GMCH_CRT_CLK GMCH_CRT_DATA
2 R543 2 R544 2 R545
1 1 1
150_0402_1% 150_0402_1% 150_0402_1%
2 CRT_IREF 255_0402_1%
1 R546
B
J29 K30
TV_DCONSEL1 TV_DCONSEL0
C26 C25
DDCCLK DDCDATA
H23 G23 E23 D23 C22 B22 A21 B21
VSYNC HSYNC BLUE BLUE# GREEN GREEN# RED RED#
J22
CRT_IREF
CRT
17 GMCH_CRT_CLK 17 GMCH_CRT_DATA
A
VF
10mils +3VS
R547 1
2 10K_0402_5%
GMCH_LCD_CLK
R548 1
2 10K_0402_5%
GMCH_LCD_DATA
R549 1
2 10K_0402_5%
LCTLB_DATA
R550 1
2 10K_0402_5%
LCTLA_CLK
R551 1
2 4.7K_0402_5%
GMCH_CRT_CLK
R552 1
2 4.7K_0402_5%
GMCH_CRT_DATA
R553 1
2 100K_0402_5%
LBKLT_EN
R554 1
2 1.5K_0402_1%
LIBG
R555 1
2 150_0402_1%
GMCH_TV_COMPS
R556 1
2 150_0402_1%
GMCH_TV_LUMA
R557 1
2 150_0402_1%
GMCH_TV_CRMA
D40 D38
PEG_COMP
10mils
1 R540
EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15
F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15
EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15
D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38
PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15
EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15
F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40
PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15
EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15
D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40
PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15
-c o
1 R542
TV
17 GMCH_TV_COMPS 17 GMCH_TV_LUMA 17 GMCH_TV_CRMA
16
GMCH_TXCLK+ GMCH_TXCLKGMCH_TZCLK+ GMCH_TZCLK-
B37 B34 A36
LVDS
16 GMCH_TZOUT0+ 16 GMCH_TZOUT1+ 16 GMCH_TZOUT2+
GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+
EXP_COMPI EXP_COMPO
2
24.9_0402_1%
+1.5VS_PCIE
PCIE_MTX_C_GRX_N[0..15]
C188 1 C201 1 C217 1 C240 1 C252 1 C270 1 C285 1 C304 1 C180 1
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
C179 2 PM@ 0.1U_0402_16V7K C195 PM@ 0.1U_0402_16V7K 2 C212 2 PM@ 0.1U_0402_16V7K C229 2 PM@ 0.1U_0402_16V7K C246 2 PM@ 0.1U_0402_16V7K C261 2 PM@ 0.1U_0402_16V7K C277 2 PM@ 0.1U_0402_16V7K C296 2 PM@ 0.1U_0402_16V7K
1
C176 0.1U_0402_16V7K C189 0.1U_0402_16V7K C204 0.1U_0402_16V7K C219 0.1U_0402_16V7K C241 0.1U_0402_16V7K C253 0.1U_0402_16V7K C272 0.1U_0402_16V7K C288 0.1U_0402_16V7K
1
2 PM@
C198 1
2 PM@
C214 1
2 PM@
C232 1
2 PM@
C248 1
2 PM@
C263 1
2 PM@
C283 1
2 PM@
C297 1
2 PM@
1 1 1 1 1 1 1
1 1 1 1 1 1 1
15
PCIE_MTX_C_GRX_P[0..15] 15 15
D
PCIE_GTX_C_MRX_P[0..15] 15
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10 2 PCIE_MTX_C_GRX_N11 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14 2 PCIE_MTX_C_GRX_N15
C
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15
B
CALISTOGA_FCBGA1466~D PM@
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
-c c
16 GMCH_TXOUT0+ 16 GMCH_TXOUT1+ 16 GMCH_TXOUT2+
SDVOCTRL_DATA SDVOCTRL_CLK
PCI-EXPRESS GRAPHICS
H27 H28
4
3
2
Title
Calistoga (3/6) Size Document Number Custom
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Monday, April 16, 2007
Sheet 1
8
of
44
5
4
3
2
1
+2.5VS
2
+1.5VS A
1
2
AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12
2
close pin G41
1
2
2
220U_D2_4VM
CRTDAC: Route caps within 250mil of Alviso. Route FB within 3" of Calistoga
AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14
VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40
330U_D2E_2.5VM
+3VS_TVDACB
+3VS_TVDACC
1
1
2
2
1
2
2
+3VS L60 MBK1608301YZF_0603 2 1
1
2
1 + C727 2
220U_D2_4VM
C
+3VS L61 MBK1608301YZF_0603 2 1
1
2
close pin A38
(20mA)
+3VS_TVBG
+3VS R559 0_0603_5% 2 1
+1.5VS_TVDAC
+3VS
(40mA)
1
1
1
2
2
2
1
2
PCI-E/MEM/PSB PLL decoupling +1.5VS_3GPLL
1
2
+1.5VS
1
2
R561 0_0603_5% 2 1
1
@
2
+1.5VS_MPLL
R562 0_0603_5% 2 1
45mA Max. 1
2
+1.5VS
+1.5VS_TVDAC
1
2
1
R560 0_0603_5% 2 1
1
2
2
1
2
2
1
2
R563 0_0603_5% 2 1
45mA Max. 1
B
@
+1.5VS_HPLL +1.5VS
+1.5VS
C747 0.1U_0402_16V4Z
VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31
+3VS_TVDACA
D21 (24mA) H19
A23 B23 B25
2
+3VS_TVDACA
C746 0.022U_0402_16V7K
VCCHV0 VCCHV1 VCCHV2
C718 2
1
C745 0.1U_0402_16V4Z
VCCD_TVDAC VCCDQ_TVDAC
1
+3VS_TVDACC
AH1 (150mA) +1.5VS AH2
A28 B28 C28
+3VS L59 MBK1608301YZF_0603 2 1
C744 0.1U_0402_16V4Z
VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2
1
+ C729
C743 10U_0805_10V4Z
VCCD_HMPLL0 VCCD_HMPLL1
E19 F19 C20 D20 E20 F20
+
2
C730 0.1U_0402_16V4Z
1
+2.5VS
+3VS_TVDACB
C742 0.1U_0402_16V4Z
VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1
C717 0.1U_0402_16V4Z
C715 0.1U_0402_16V4Z
C721 10U_0805_10V4Z
C722 0.1U_0402_16V4Z
2
L58 MBK1608301YZF_0603 2 1
+2.5VS
+3VS_TVBG (120mA)
1
C726 0.022U_0402_16V7K
+1.5VS_MPLL
330U_D2E_2.5VM
C725 0.1U_0402_16V4Z
AF2 (45mA) H20 G20
2
C724 0.022U_0402_16V7K
+2.5VS
2
C735 0.022U_0402_16V7K
A38 (10mA) B39
C716
-c c
VCCA_LVDS VSSA_LVDS
2
1
C734 0.1U_0402_16V4Z
+1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_HPLL
+
+1.5VS
+2.5VS 2
C728 0.1U_0402_16V4Z
1 B26 (50mA) C39 (50mA) AF1 (45mA)
VCCA_MPLL
C720 10U_0805_10V4Z
+2.5VS_CRTDAC
1
L57 MBK1608301YZF_0603 2 1
1
C755 10U_0805_10V4Z
1
E21 (70mA) F21 G21
2
1
+1.5VS
1
C754 0.1U_0402_16V4Z
MCH_D2 C750 0.22U_0603_16V7K
2
2
+1.5VS_3GPLL +2.5VS (2mA)
VCCA_DPLLA VCCA_DPLLB VCCA_HPLL
VCCA_TVBG VSSA_TVBG
2
1
C753 10U_0805_10V4Z
1
1
C751 0.47U_0603_16V4Z MCH_AB1
C748 0.22U_0603_16V7K
B
C719 220U_D2_2VMR15
+
C752 0.1U_0402_16V4Z
C737 0.47U_0603_16V4Z
MCH_A6
1
+1.5VS
C741 0.1U_0402_16V4Z
2
P O W E R
(1500mA)
C733 0.01U_0402_16V7K
1
VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC2
R558 0_0805_5% 2 1
C739 0.022U_0402_16V7K
2
VCCA_3GPLL VCCA_3GBG VSSA_3GBG
AC33 G41 H41
+1.5VS_PCIE
W=60 mils
-c o
1
C732 2.2U_0805_10V6K
C731 4.7U_0805_10V4Z
C
AB41 AJ41 L41 N41 R41 V41 Y41
C723 0.022U_0402_16V7K
2
VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6
+2.5VS
+1.5VS_DPLLB
L56 MBK1608301YZF_0603 2 1
1 2 C714 0.1U_0402_16V4Z
(60mA) B30 C30 A30
C738 10U_0805_10V4Z
220U_D2_2VMR15
+
VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2
H22
C749 0.1U_0402_16V4Z
C713
VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35 VTT36 VTT37 VTT38 VTT39 VTT40 VTT41 VTT42 VTT43 VTT44 VTT45 VTT46 VTT47 VTT48 VTT49 VTT50 VTT51 VTT52 VTT53 VTT54 VTT55 VTT56 VTT57 VTT58 VTT59 VTT60 VTT61 VTT62 VTT63 VTT64 VTT65 VTT66 VTT67 VTT68 VTT69 VTT70 VTT71 VTT72 VTT73 VTT74 VTT75 VTT76
VF
1
VCC_SYNC AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1
C740 0.1U_0402_16V4Z
+1.05VS
(800mA)
D
+1.5VS_DPLLA
U41H
C736 0.1U_0402_16V4Z
D
+1.5VS
1
2
A
CALISTOGA_FCBGA1466~D PM@
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/10/4
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Calistoga (4/6) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
9
of
44
5
4
3
2
1
Strap Pin Table CFG[3:17] have internal pull up
+ 2
1 C770 + @ 220U_D2_2VMR15 2
B
+1.05VS
M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16
VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12
AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17 +1.8V
VCC100 VCC101 VCC102 VCC103 VCC104 VCC105 VCC106 VCC107 VCC108 VCC109 VCC110 CALISTOGA_FCBGA1466~D PM@
VCC_SM100 VCC_SM101 VCC_SM102 VCC_SM103 VCC_SM104 VCC_SM105 VCC_SM106 VCC_SM107
AR6 AP6 AN6 AL6 AK6 AJ6 AV1 MCH_AV1 AJ1 MCH_AJ1
1
2
1
2
Place near pin AV1 & AJ1
1
2
1
2
CFG5 CFG7
0 = Reserved 1 = Mobile Yonah CPU *(Default)
CFG9
0 = Lane Reversal Enable 1 = Normal Operation *(Default)
CFG11
1
2
C764 0.1U_0402_16V4Z
2
C763 0.1U_0402_16V4Z
2
C762 0.1U_0402_16V4Z
2
1
1 = Calistoga 00 01 10 11
CFG[13:12]
1
D
0 = Reserved
Place near pin AT41 & AM41
1
= 667MT/s FSB = 533MT/s FSB
0 = DMI x 2 1 = DMI x 4 *(Default)
PSB 4X CLK Enable
C761 0.1U_0402_16V4Z
P O W E R
011 001
CFG[2:0] C759 0.47U_0603_16V4Z
C758 0.47U_0603_16V4Z
MCH_AT41 MCH_AM41
= = = =
*
Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation *(Default)
CFG16
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled *(Default)
CFG18
0 = 1.05V 1 = 1.5V
CFG19
0 = Normal Operation * (Default) 1 = DMI Lane Reversal Enable
*(Default)
0 = No SDVO Device Present * (Default)
SDVO_CTRLDATA
1 = SDVO Device Present
CFG20
(PCIE/SDVO select)
0 = Only PCIE or SDVO is operational. *(Default) 1 = PCIE/SDVO are operating simu.
C
1
2
Place near pin BA23
1
2
C772 10U_0805_10V4Z
220U_D2_2VMR15
CFG[19:18] have internal pull down
-c c
1 C768
AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6
C769 0.47U_0603_16V4Z
C757 0.22U_0603_16V7K
C
VCC_SM0 VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4 VCC_SM5 VCC_SM6 VCC_SM7 VCC_SM8 VCC_SM9 VCC_SM10 VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15 VCC_SM16 VCC_SM17 VCC_SM18 VCC_SM19 VCC_SM20 VCC_SM21 VCC_SM22 VCC_SM23 VCC_SM24 VCC_SM25 VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36 VCC_SM37 VCC_SM38 VCC_SM39 VCC_SM40 VCC_SM41 VCC_SM42 VCC_SM43 VCC_SM44 VCC_SM45 VCC_SM46 VCC_SM47 VCC_SM48 VCC_SM49 VCC_SM50 VCC_SM51 VCC_SM52 VCC_SM53 VCC_SM54 VCC_SM55 VCC_SM56 VCC_SM57 VCC_SM58 VCC_SM59 VCC_SM60 VCC_SM61 VCC_SM62 VCC_SM63 VCC_SM64 VCC_SM65 VCC_SM66 VCC_SM67 VCC_SM68 VCC_SM69 VCC_SM70 VCC_SM71 VCC_SM72 VCC_SM73 VCC_SM74 VCC_SM75 VCC_SM76 VCC_SM77 VCC_SM78 VCC_SM79 VCC_SM80 VCC_SM81 VCC_SM82 VCC_SM83 VCC_SM84 VCC_SM85 VCC_SM86 VCC_SM87 VCC_SM88 VCC_SM89 VCC_SM90 VCC_SM91 VCC_SM92 VCC_SM93 VCC_SM94 VCC_SM95 VCC_SM96 VCC_SM97 VCC_SM98 VCC_SM99
C771 10U_0805_10V4Z
2
VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99
C774 0.47U_0603_16V4Z
2
1
U41G AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19
-c o
1
2
AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15
+1.8V
VF
2
2
1
VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57
C776 0.47U_0603_16V4Z
1
1
C767 1U_0603_10V4Z
2
C760 0.22U_0603_16V7K
1
C766 10U_0805_10V4Z
C765 10U_0805_10V4Z
C756 0.22U_0603_16V7K
D
VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72
P O W E R
(3500mA)
U41F AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18
+1.05VS
+1.5VS
C775 0.47U_0603_16V4Z
+1.05VS
1 1
2
+ C773 2
330U_D2E_2.5VM_R9
6
CFG5
6
CFG7
6
CFG9
6
CFG11
6
CFG12
6
CFG13
6
CFG16
6
CFG18
6
CFG19
6
CFG20
R564
1
2 @
2.2K_0402_5%
R565
1
2 @
2.2K_0402_5%
R566
1
2 @
2.2K_0402_5%
R567
1
2 @
2.2K_0402_5%
R568
1
2 @
2.2K_0402_5%
R569
1
2 @
2.2K_0402_5%
R570
1
2 @
2.2K_0402_5%
R571
1
2 @ 1K_0402_5%
R572
1
2 @ 1K_0402_5%
R573
1
2 @ 1K_0402_5%
+3VS
1
B
2
Place near pin BA15
CALISTOGA_FCBGA1466~D PM@
A
A
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/10/4
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Calistoga (5/6) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
10
of
44
5
4
3
2
U41I
C
P O W E R
AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21
AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11 J11 D11 B11 AV10 AP10 AL10 AJ10
VF
B
U41J VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199
VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS265 VSS264 VSS263 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279
VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS292 VSS291 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 VSS353 VSS354 VSS355 VSS356 VSS357 VSS358 VSS359 VSS360
AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1
D
-c c
D
VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99
P O W E R
-c o
AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34 AK34 AG34 AF34
1
C
B
CALISTOGA_FCBGA1466~D PM@
CALISTOGA_FCBGA1466~D PM@
A
A
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/10/4
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Calistoga (6/6) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
11
of
44
5
4
+1.8V
3
2
+1.8V
+1.8V
DDRA_SDQ8 DDRA_SDQ14 DDRA_SDQS1# DDRA_SDQS1
7 DDRA_SDQS1# 7 DDRA_SDQS1
DDRA_SDQ9 DDRA_SDQ15
DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQS2# DDRA_SDQS2
7 DDRA_SDQS2# 7 DDRA_SDQS2
DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ29 DDRA_SDQ24 DDRA_SDM3 DDRA_SDQ26 DDRA_SDQ27 C
6 7
DDRA_CKE0
DDRA_CKE0
DDRA_SBS2#
DDRA_SBS2#
DDRA_SMA12 DDRA_SMA9 DDRA_SMA8 DDRA_SMA5 DDRA_SMA3 DDRA_SMA1
7 7
DDRA_SBS0# DDRA_SWE#
7 6
DDRA_SCAS# DDRA_SCS#1
6
DDRA_SMA10 DDRA_SBS0# DDRA_SWE# DDRA_SCAS# DDRA_SCS#1 DDRA_ODT1
DDRA_ODT1
DDRA_SDQ37 DDRA_SDQ36 DDRA_SDQS4# DDRA_SDQS4
7 DDRA_SDQS4# 7 DDRA_SDQS4
DDRA_SDQ35 DDRA_SDQ32 DDRA_SDQ40 DDRA_SDQ44 B
DDRA_SDM5 DDRA_SDQ41 DDRA_SDQ46 DDRA_SDQ49 DDRA_SDQ48
DDRA_SDQS6# DDRA_SDQS6
7 DDRA_SDQS6# 7 DDRA_SDQS6
DDRA_SDQ54 DDRA_SDQ50 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDM7 DDRA_SDQ59 DDRA_SDQ58 D_CK_SDATA D_CK_SCLK
13,14 D_CK_SDATA 13,14 D_CK_SCLK
+3VS
A
1
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204
DDRA_SDQ6 DDRA_SDQ0
R345
+DIMM_VREF
1K_0402_1% 2
DDRA_SDM0
1
DDRA_SDQ5 DDRA_SDQ7
R344 DDRA_SDQ13 DDRA_SDQ12
1K_0402_1%
DDRA_SDM1
+DIMM_VREF 1 C376
2
20mils 1
2.2U_0805_10V6K
2
C410 D
0.1U_0402_16V4Z
DDRA_CLK0 6 DDRA_CLK0# 6 DDRA_SDQ11 DDRA_SDQ10 DDRA_SMA[0..13]
7 DDRA_SMA[0..13]
DDRA_SDQ[0..63]
7 DDRA_SDQ[0..63] DDRA_SDQ20 DDRA_SDQ21 DDRA_SDM2
R1191 0_0402_5% 2
C611
DDRA_SDQS3# 7 DDRA_SDQS3 7
DDRA_ODT0 DDRA_SMA13
DDRA_SDQ39 DDRA_SDQ38 DDRA_SDM4 DDRA_SDQ34 DDRA_SDQ33 DDRA_SDQ45 DDRA_SDQ43 DDRA_SDQS5# DDRA_SDQS5 DDRA_SDQ47 DDRA_SDQ42
1
C608
1
C606
1
C389
1
C400
1
C388
1
+0.9VS
DDRA_CKE0 1 DDRA_SBS2# 2 RP19
DDRA_CKE1 6
DDRA_SMA11 DDRA_SMA7 DDRA_SMA6
DDRA_SBS1# DDRA_SRAS# DDRA_SCS#0
C605
+1.8V
DDRA_SDQ31 DDRA_SDQ30
DDRA_SMA4 DDRA_SMA2 DDRA_SMA0
1
2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2 2 2 2 2 2 2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z
DDRA_SDQ28 DDRA_SDQ25
DDRA_CKE1
+1.8V
PM_EXTTS#0 6,13
DDRA_SDQ23 DDRA_SDQ22
DDRA_SDQS3# DDRA_SDQS3
DDRA_SDM[0..7]
7 DDRA_SDM[0..7]
4 3 56_0404_4P2R_5%
DDRA_SMA12 1 DDRA_SMA9 2 RP20
4 3 56_0404_4P2R_5%
DDRA_SMA5 DDRA_SMA8
4 3 56_0404_4P2R_5%
1 2 RP21
DDRA_SMA1 DDRA_SMA3
DDRA_SBS1# 7 DDRA_SRAS# 7 DDRA_SCS#0 6 DDRA_ODT0 6
DDRA_SDQS5# 7 DDRA_SDQS5 7
DDRA_SDQ52 DDRA_SDQ53
DDRA_CLK1 6 DDRA_CLK1# 6
1 2 RP22
4 3 56_0404_4P2R_5%
DDRA_SMA10 1 DDRA_SBS0# 2 RP23
4 3 56_0404_4P2R_5%
DDRA_SWE# 1 DDRA_SCS#1 2 RP24
4 3 56_0404_4P2R_5%
DDRA_SCAS# 1 DDRA_ODT1 2 RP25
4 3 56_0404_4P2R_5%
DDRA_SMA11 1 DDRA_CKE1 2 RP26
4 3 56_0404_4P2R_5%
C411
1
C414
1
C417
1
C413
C
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+0.9VS
C427
1
C404
1
C407
1
C425
1
1 C403 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+0.9VS
C422
1
1 C405
C409
1
C408
1
C406
1 B
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA6 DDRA_SMA7
1 2 RP27
4 3 56_0404_4P2R_5%
DDRA_SMA2 DDRA_SMA4
1 2 RP28
4 3 56_0404_4P2R_5%
DDRA_SBS1# 1 DDRA_SMA0 2 RP29
4 3 56_0404_4P2R_5%
C424
DDRA_SCS#0 1 DDRA_SRAS# 2 RP30
4 3 56_0404_4P2R_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z
DDRA_SMA13 1 DDRA_ODT0 2 RP31
4 3 56_0404_4P2R_5%
+0.9VS
1
C423
1
C426
1
DDRA_SDM6
DDRA_SDQ51 DDRA_SDQ55 DDRA_SDQ57 DDRA_SDQ56
DDRA_SDQS7# DDRA_SDQS7
DDRA_SDQS7# 7 DDRA_SDQS7 7
DDRA_SDQ62 DDRA_SDQ63
R3531 R3541
2 10K_0402_5% 2 10K_0402_5%
FOX_AS0A426-M2RN-7F CONN@
+3VS
C607
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
2
D
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
-c c
DDRA_SDQ2 DDRA_SDQ3
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
-c o
DDRA_SDQS0# DDRA_SDQS0
7 DDRA_SDQS0# 7 DDRA_SDQS0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
VF
DDRA_SDQ4 DDRA_SDQ1
1
JP28 +DIMM_VREF
1
C402
1
A
DIMM0 REV H:5.2mm (BOT)
0.1U_0402_16V4Z 2 2 2.2U_0805_10V6K
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
DDRII-SODIMM0 Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Sheet
Monday, April 16, 2007 1
12
of
44
A
B
C
D
+DIMM_VREF +1.8V
1
DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQS1# DDRB_SDQS1
7 DDRB_SDQS1# 7 DDRB_SDQS1
DDRB_SDQ10 DDRB_SDQ11
DDRB_SDQ17 DDRB_SDQ20 DDRB_SDQS2# DDRB_SDQS2
7 DDRB_SDQS2# 7 DDRB_SDQS2
DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ28 DDRB_SDQ25 DDRB_SDM3 2
DDRB_SDQ30 DDRB_SDQ31 6
DDRB_CKE0
7
DDRB_SBS2#
DDRB_CKE0 DDRB_SBS2# DDRB_SMA12 DDRB_SMA9 DDRB_SMA8 DDRB_SMA5 DDRB_SMA3 DDRB_SMA1
7 7
DDRB_SBS0# DDRB_SWE#
7 6
DDRB_SCAS# DDRB_SCS#1
6
DDRB_SMA10 DDRB_SBS0# DDRB_SWE# DDRB_SCAS# DDRB_SCS#1 DDRB_ODT1
DDRB_ODT1
DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQS4# DDRB_SDQS4
7 DDRB_SDQS4# 7 DDRB_SDQS4
DDRB_SDQ34 DDRB_SDQ35
3
DDRB_SDQ40 DDRB_SDQ41 DDRB_SDM5 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ48 DDRB_SDQ49
DDRB_SDQS6# DDRB_SDQS6
7 DDRB_SDQS6# 7 DDRB_SDQS6
DDRB_SDQ51 DDRB_SDQ50 DDRB_SDQ56 DDRB_SDQ61 DDRB_SDM7 DDRB_SDQ59 DDRB_SDQ58 D_CK_SDATA D_CK_SCLK
12,14 D_CK_SDATA 12,14 D_CK_SCLK
+3VS
4
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND
DDRB_SDQ5 DDRB_SDQ4
1
C386
1
1
C519 +
2.2U_0805_10V6K 2 2 0.1U_0402_16V4Z
C556+ 2
DDRB_SDM0
2
330U_D2E_2.5VM_R9
1
C420
C429
1
C385
1
C374
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
150U_D2_6.3VM @ 1
DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ12 DDRB_SDQ13
For EMI
DDRB_SDM1 +1.8V
+1.8V
+1.8V
+1.8V
DDRB_CLK1 6 DDRB_CLK1# 6 DDRB_SDQ14 DDRB_SDQ15
7 DDRB_SMA[0..13] 7 DDRB_SDQ[0..63] 7 DDRB_SDM[0..7]
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202
DDRB_SDQ21 DDRB_SDQ16 0_0402_5% R356 1 2 DDRB_SDM2
PM_EXTTS#0 6,12
DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ26 DDRB_SDQ24 DDRB_SDQS3# DDRB_SDQS3
C615
1
C617
DDRB_SDM[0..7]
+1.05VS
DDRB_CKE1 6
DDRB_SMA4 DDRB_SMA2 DDRB_SMA0
DDRB_ODT0 DDRB_SMA13
C616
1
C618
1
C619
1
C620
1
C622
1
C621
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+5VALW
+1.5VS
+0.9VS
DDRB_SMA11 DDRB_SMA7 DDRB_SMA6
DDRB_SBS1# DDRB_SRAS# DDRB_SCS#0
1
DDRB_SDQ[0..63]
+1.8V
DDRB_SDQS3# 7 DDRB_SDQS3 7
DDRB_SDQ29 DDRB_SDQ27 DDRB_CKE1
DDRB_SMA[0..13]
-c c
DDRB_SDQS0# DDRB_SDQS0
7 DDRB_SDQS0# 7 DDRB_SDQS0
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
C373 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
DDRB_CKE0 DDRB_SBS2#
1 2 RP32
4 3 56_0404_4P2R_5%
DDRB_SMA12 DDRB_SMA9
1 2 RP33
4 3 56_0404_4P2R_5%
DDRB_SMA8 DDRB_SMA5
1 2 RP34
4 3 56_0404_4P2R_5%
DDRB_SMA3 DDRB_SMA1
1 2 RP35
4 3 56_0404_4P2R_5%
DDRB_SMA10 DDRB_SBS0#
1 2 RP36
4 3 56_0404_4P2R_5%
DDRB_SWE# DDRB_SCAS#
1 2 RP37
4 3 56_0404_4P2R_5%
DDRB_SCS#1 DDRB_ODT1
1 2 RP38
4 3 56_0404_4P2R_5%
DDRB_SMA11 DDRB_CKE1
1 2 RP39
4 3 56_0404_4P2R_5%
DDRB_SMA6 DDRB_SMA7
1 2 RP40
4 3 56_0404_4P2R_5%
DDRB_SMA2 DDRB_SMA4
1 2 RP41
4 3 56_0404_4P2R_5%
DDRB_SBS1# DDRB_SMA0
1 2 RP42
4 3 56_0404_4P2R_5%
-c o
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
DDRB_SBS1# 7 DDRB_SRAS# 7 DDRB_SCS#0 6 DDRB_ODT0 6
DDRB_SDQ36 DDRB_SDQ37
1
C372
C369
1
C370
2
1
C371
1
C421
1
C419
1
C428
1
2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2 2 2 2 2 2 2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z
+1.8V
1
C384
C398
1
C375
1
C399
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+0.9VS
DDRB_SDM4
DDRB_SDQ39 DDRB_SDQ38 DDRB_SDQ44 DDRB_SDQ45
VF
DDRB_SDQ0 DDRB_SDQ1
+1.8V
+1.8V JP29
+DIMM_VREF
E
DDRB_SDQS5# DDRB_SDQS5
DDRB_SDQS5# 7 DDRB_SDQS5 7
DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ52 DDRB_SDQ53
DDRB_CLK0 6 DDRB_CLK0# 6
DDRB_SDM6
DDRB_SDQ54 DDRB_SDQ55
DDRB_SCS#0 DDRB_SRAS#
1 2 RP43
4 3 56_0404_4P2R_5%
DDRB_SMA13 DDRB_ODT0
1 2 RP44
4 3 56_0404_4P2R_5%
DDRB_SDQ60 DDRB_SDQ57
DDRB_SDQS7# DDRB_SDQS7
2 2 10K_0402_5% 10K_0402_5%
C391
1
C392
1
C378
1
C393
1 3
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+0.9VS
1
C397
C396
1
C383
1
C379
1
C394
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+0.9VS
C381
DDRB_SDQS7# 7 DDRB_SDQS7 7
1
C395
1
C380
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z
DDRB_SDQ62 DDRB_SDQ63 1 R3481 R349
1
C382
+3VS
4
FOX_AS0A426-MARG-7F CONN@
DIMM1 REV H:9.2mm (BOT)
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
DDRII-SODIMM1 Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
13
of
44
FSLC
B
FSLB
FSLA
CLKSEL2 CLKSEL1 CLKSEL0
C
CPU MHz
SRC MHz
PCI MHz
1
2
0
0
1
133
100
33.3
0
1
1
166
100
33.3
D
+CLK_VDD48
+CLK_VDDREF 1
C777 10U_0805_10V4Z
2
1
C778 0.047U_0402_16V7K
2
0 **SEL_PCI5/REF1
CLKREQ3#
33.3MHz PCICLK5
**SEL_PCI6/PCICLK1
CLKREQ5#
33.3MHz PCICLK6
**SEL_24M/PCICLK2
TESTMODE
24MHz Output
**SEL_48M/PCICLK3
CLKREQ7#
48MHz_1 Output
ITP_EN/PCICLK_F0
SRC pair
+CLK_VDD2
C790 33P_0402_50V8J 1 2
1 R578 1 R580
1
**SEL_24M/PCICLK2=0=TESTMODE **SEL_PCI6/PCICLK1=0=CLKREQ5#
+3VS
CLK_XTALIN
1 R586
CLK_PCI0 2 10K_0402_5%
CLK_48M_SD R693 1 CLK_ICH_48M R694 1
23 CLK_48M_SD 20 CLK_ICH_48M
2 CLK_PCI4 10K_0402_5%
28 CLK_PCI_LPC 20 CLK_ICH_14M
2 33_0402_5%
R688 1 Dbg@
26 CLK_PCI_Dbg
23 CLK_PCI_card
2 12_0402_5% 2 12_0402_5%
R687 1 Dbg@
26 CLK_14M_Dbg 1 R592
20
VDDSRC VDDSRC VDDSRC VDDSRC
VDDA GNDA PCI_SRC_STOP#
VDDPCI VDDPCI
2 33_0402_5%
19
X1 X2
CLK_MCH_BCLK
CLK_CPU1# R579 1
2 0_0402_5%
CLK_MCH_BCLK#
CPUCLKT0LP
14
CLK_CPU0
2 0_0402_5%
CLK_CPU_BCLK
R594 1
2 33_0402_5%
CLK_PCI2
32
SEL_24M/PCICLK2
CLK_PCI_LPC
R596 1
2 33_0402_5%
CLK_PCI1
27
SEL_PCI6/PCICLK1
2 0_0402_5%
CLK_DOT
CLK_REF
43
CLK_DREF_96M#
R601 1 GM@
2 0_0402_5%
CLK_DOT#
44
22
CLK_PCI_ICH
18 CLK_PCI_ICH
R605 1
2 33_0402_5%
CLK_PCI0
42 CLK_ENABLE#
CLK_ENABLE#_R
37
R743 2 0_0402_5% @
R612 1
+3VS
2 0_0402_5%
CLKIREF
9
15mil
CLK_ENABLE#_R 2 10K_0402_5%
1 R617
D_CK_SCLK
12,13 D_CK_SCLK
D_CK_SDATA
12,13 D_CK_SDATA
SRCCLKT9LP
CLK_SRC9
R588 1
2 0_0402_5%
CLK_PCIE_CARD
SRCCLKC9LP
2
CLK_SRC9# R590 1
2 0_0402_5%
CLK_PCIE_CARD#
CLKREQ9#
72
SRCCLKT8LP
70
SRCCLKC8LP
69
CLKREQ8#
71
SRCCLKT7LP
DOTT_96MHz/27MHz_NonspreadCLKREQ7#/48Mhz_1 DOTC_96MHz/27MHz_spread
SRCCLKT6LP
SRCCLKC6LP
ITP_EN/PCICLK_F0 VTT_PWRGD#/PD
SRCCLKT5LP
SRCCLKC5LP
GND
CLKREQ5#/PCICLK6
16
17
1
3
D
S
2 G
R638 4.7K_0402_5% 1 2 +3VS
Q50
D_CK_SCLK
2N7002_SOT23
1 2 R655 @ 1K_0402_5%
3
Q49 2N7002_SOT23
2
R642 @ 56_0402_5% R646 1K_0402_5% 1 2 1 2 R651 0_0402_5%
MCH_CLKSEL0 6 CPU_BSEL0 5
CLKSEL1 1 2 R650 @ 0_0402_5%
1 2 R652 0_0402_5%
CLK_PCIE_SATA#
CLK_PCIE_SATA 19
R607 1 R609 1
2 10K_0402_5% CLK_PCIE_ICH 2 0_0402_5%
60
CLK_SRC5
61
CLK_SRC5# R611 1
29
R614 1
2 10K_0402_5%
SATA_CLKREQ# 20 +3VS CLK_PCIE_ICH 20
CLK_PCIE_ICH#
2 0_0402_5%
CLK_PCIE_ICH# 20 +3VS
CLK_PCIE_LAN CLK_PCIE_LAN#
CLKREQ4#
57
R621 1
2 @ 10K_0402_5%
CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24 +3VS
2 0_0402_5%
CLK_PCIE_VGA
2 0_0402_5%
CLK_PCIE_VGA#
CLKREQ3#/PCICLK5
28
CLK_PCI5
R627 1
2 @ 10K_0402_5%
SRCCLKT2LP
52
CLK_SRC2
R630 1
2 0_0402_5%
CLK_MCH_3GPLL
GNDPCI
SRCCLKC2LP
53
CLK_SRC2# R632 1
2 0_0402_5%
CLK_MCH_3GPLL#
GNDPCI
CLKREQ2#
26
GNDREF
31 35
R634 1 R636 1
GND48
SRCCLKT1LP
50
CLK_SRC1
68
GNDSRC
SRCCLKC1LP
51
CLK_SRC1# R637 1
CLKREQ1#
46
LCD100/96/SRC0_TLP
47
CLK_SRC0
LCD100/96/SRC0_CLP
48
CLK_SRC0# R641 1 GM@
1 2 R653 @ 0_0402_5%
CPU_BSEL1 5
CLK_PCIE_VGA# 15 +3VS
2 0_0402_5%
R639 1 R640 1 GM@
CLK_PCIE_MINI1#
2 10K_0402_5% +3VS CLK_DREF_SSC 2 0_0402_5% 2 0_0402_5%
CLK_DREF_SSC#
R649 1K_0402_5% 1 2 1 2 R654 0_0402_5%
B
C
D
CLK_MCH_3GPLL 6 CLK_MCH_3GPLL# 6 MCH_CLKREQ# 6 CLK_PCIE_MINI1 26
3
CLK_PCIE_MINI1# 26 MINI1_CLKREQ# 26 CLK_DREF_SSC 6 CLK_DREF_SSC# 6
4
MCH_CLKSEL2 6 CPU_BSEL2 5
Compal Electronics, Inc.
Compal Secret Data 2007/1/15
2007/10/4
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1%
R644 @ 1K_0402_5%
Security Classification Issued Date
1 R600 1 R603 CLK_PCIE_MINI1 1 R606 CLK_PCIE_MINI1# 1 R608 CLK_PCIE_SATA 1 R610 CLK_PCIE_SATA# 1 R613 CLK_DREF_SSC 1 R615 CLK_DREF_SSC# 1 R618 CLK_DREF_96M 1 R620 CLK_DREF_96M# 1 R622 CLK_PCIE_CARD 1 R624 CLK_PCIE_CARD# 1 R626 CLK_MCH_3GPLL 1 R628 CLK_MCH_3GPLL# 1 R631 CLK_PCIE_LAN 1 R633 CLK_PCIE_LAN# 1 R635
+1.05VS
R648 8.2K_0402_5% CLKSEL2 1 2
MCH_CLKSEL1 6
CLK_PCIE_VGA 15
2 10K_0402_5% +3VS CLK_PCIE_MINI1 2 0_0402_5%
42
THRM_PAD THRM_PAD THRM_PAD THRM_PAD
2 @ 49.9_0402_1% 2 @ 49.9_0402_1%
CLK_PCIE_ICH#
CLK_PCIE_SATA# 19
62
2 0_0402_5%
R643 @ 1K_0402_5% R647 1K_0402_5% 1 2
CLK_PCIE_SATA
2 0_0402_5%
2 0_0402_5%
ICS9LPR325AKLFT_MLF72
+1.05VS
2 0_0402_5%
R623 1 PM@
GNDCPU
73 74 75 76
1
R645 8.2K_0402_5% CLKSEL0 1 2
1
2
+1.05VS
1
R602 1
CLK_SRC6# R604 1
R616 1
2
CLK_ENABLE#_R
+3VS
CLK_SRC6
CLK_SRC3# R625 1 PM@
21
1 R595 1 R597
CLK_PCIE_ICH
63
64
CLK_SRC3
15
CLK_PCIE_VGA
2
67
CLK_SRC4# R619 1
SRCCLKC3LP
2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1% 2 @ 49.9_0402_1%
CLK_PCIE_VGA#
38
55
GNDSRC
CLK_PCIE_CARD# 27
1 R585 CLK_MCH_BCLK# 1 R587 CLK_CPU_BCLK 1 R589 CLK_CPU_BCLK# 1 R591
66
CLK_SRC4
1
2 G
2N7002_SOT23
20,24,26,27 ICH_SMBCLK
6,20,42
CLK_PCIE_CARD 27
56
4
CLK_MCH_BCLK
+3VS
58
SMBDAT
CLK_CPU_BCLK# 4
EXP_CLKREQ# 27
2 10K_0402_5%
59
SRCCLKT4LP
VF VGATE
D_CK_SDATA
S
3
D
1
S
20,24,26,27 ICH_SMBDATA
D
2 G
+3VS R629 4.7K_0402_5% Q48 1 2 +3VS
R593 1
SRCCLKC4LP
SMBCLK
SRCCLKT3LP
3
4
39
CLK_CPU_BCLK 4
3
CLKREQ6#
CLK_ENABLE# 1
2
CLK_MCH_BCLK# 6
CLK_CPU_BCLK#
5
SEL_PCI5/REF1
R581 1
-c o
6 CLK_DREF_96M#
C789 10U_0805_10V4Z
CLK_MCH_BCLK 6
2 0_0402_5%
SRCCLKC7LP
6 CLK_DREF_96M
2
1
+3VS
1
PM_STP_CPU# 20
CLK_CPU0# R582 1
13 6
PCICLK4/FCTSEL1
CLK_PCI_card
2 33_0402_5%
C788
0.047U_0402_16V7K 2
1
PM_STP_PCI# 20
10
CPUCLKT2_ITP/SRCCLKT10LP
REF0/FSLC/TEST_SEL
SEL_48M/PCICLK3
R599 1 GM@
PM_STP_PCI#
1
VDD48
33
R598 1
C787
CPUCLKC1LP
FSLB/TEST_MODE/24Mhz
CLK_DREF_96M
25
R576 0_0805_5% 1 2
40mil
0.047U_0402_16V7K
2 0_0402_5%
USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
CLK_ICH_14M
2
C786 0.047U_0402_16V7K
R577 1
45
34
C784 0.047U_0402_16V7K
+CLK_VDD1
CLK_CPU1
VDDREF
2
+CLK_VDD2 1 2 R575 2.2_0603_5%
CPUCLKT1LP
41
CLK_PCI4
1 C783 0.047U_0402_16V7K
PM_STP_CPU#
CLKSEL1
23
2
24
CLKSEL0
CLKSEL2
2
8
1 C782 0.047U_0402_16V7K
+CLK_VCCA 1
C785 10U_0805_10V4Z
7
2
11
CPU_STOP#
VDDCPU
CPUCLKC0LP
CLK_XTALOUT
1 C781 0.047U_0402_16V7K
20mil
14.31818MHz_20P_1BX14318BE1A
2
1 R583
CLK_REF 2 10K_0402_5%
ITP_EN/PCICLK_F0=0=SRC pair
2
2 +CLK_VDDREF 18 1_0603_5% 15mil 2 +CLK_VDD48 40 2.2_0603_5% 15mil
Y1 C791 33P_0402_50V8J 1 2
**SEL_PCI5=1=PCICLK5
2
1
12
+CLK_VDD1
1 C780 10U_0805_10V4Z
U1
30 36
CPU_ITP pair
2
H
Clock Generator
+CLK_VDD1
1
1 49 54 65
G
40mil
0.047U_0402_16V7K
+CLK_VDD1
1
F
R574 0_0805_5% 1 2
+3VS
C779
Table : ICS9LPR325 1
E
-c c
A
E
F
Title
Clock Generator Size B
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Monday, April 16, 2007 G
Sheet
14 H
of
44
5
4
2
PCIE_MTX_C_GRX_P[0..15]
8 PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
8 PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
D
PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P6
B
PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P2
CLK_PCIE_VGA# CLK_PCIE_VGA
18 PLTRST_VGA#
D_EC_SMB_DA1 D_EC_SMB_CK1
26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108
17 VGA_CRT_HSYNC 17 VGA_CRT_VSYNC 17 VGA_DDC_CLK 17 VGA_DDC_DATA
PCIE_MTX_C_GRX_N15 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12
VGA_CRT_HSYNC VGA_CRT_VSYNC VGA_DDC_CLK VGA_DDC_DATA
PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P6
16 DVI_DET 16 VGA_DVI_TXC16 VGA_DVI_TXC+
DVI_DET VGA_DVI_TXCVGA_DVI_TXC+
PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P4
16 VGA_DVI_TXD216 VGA_DVI_TXD2+
VGA_DVI_TXD2VGA_DVI_TXD2+
PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P3
16 VGA_DVI_TXD116 VGA_DVI_TXD1+
VGA_DVI_TXD1VGA_DVI_TXD1+
PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P2
16 VGA_DVI_TXD016 VGA_DVI_TXD0+
VGA_DVI_TXD0VGA_DVI_TXD0+
PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P5
ACES_88990-2D08 CONN@
L44 2 1 KC FBM-L11-201209-221LMAT_0805 PM@ L43 2 1 KC FBM-L11-201209-221LMAT_0805 PM@ 1 C527
A
1 C526 PM@ 680P_0603_50V7K 68P_0402_50V8J 2 2
2
PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P0 VGA_TV_CRMA
+2.5VS
C471
C520
0.1U_0402_16V4Z PM@ 2
1 0.1U_0603_25V7K
VGA_TV_COMPS 17
VGA_CRT_R
VGA_CRT_R 17
VGA_CRT_G
VGA_CRT_G 17
VGA_CRT_B
VGA_CRT_B 17
VGA_TZCLKVGA_TZCLK+
VGA_TZCLK- 16 VGA_TZCLK+ 16
VGA_TZOUT2VGA_TZOUT2+
VGA_TZOUT2- 16 VGA_TZOUT2+ 16
VGA_TZOUT1VGA_TZOUT1+
VGA_TZOUT1- 16 VGA_TZOUT1+ 16
VGA_TZOUT0VGA_TZOUT0+
VGA_TZOUT0- 16 VGA_TZOUT0+ 16
VGA_TXCLKVGA_TXCLK+
VGA_TXCLK- 16 VGA_TXCLK+ 16
VGA_TXOUT2VGA_TXOUT2+
VGA_TXOUT2- 16 VGA_TXOUT2+ 16
VGA_TXOUT1VGA_TXOUT1+
VGA_TXOUT1- 16 VGA_TXOUT1+ 16
VGA_TXOUT0VGA_TXOUT0+
VGA_TXOUT0- 16 VGA_TXOUT0+ 16
I2CC_SDA I2CC_SCL ENVDD
I2CC_SDA 16 I2CC_SCL 16 ENVDD 16
ENBKL VGA_DVI_SDATA VGA_DVI_SCLK
C
B
ENBKL 8,28 VGA_DVI_SDATA 16 VGA_DVI_SCLK 16
+2.5VS +3VS
+5VS
1
VGA_TV_LUMA 17
VGA_TV_COMPS
+3VS
28,29,38 EC_SMB_DA1
160mil(4A)
VGA_TV_CRMA 17
VGA_TV_LUMA
ACES_88990-2D08 CONN@
B+
C525
PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P1
1
D_EC_SMB_DA1
3
Q46 PM@ 2N7002_SOT23
1
2 G
+MXM_B+
160mil(4A)
110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232
2 0.1U_0402_16V4Z PM@
28,29,38 EC_SMB_CK1
1
3 S
PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P10
VGA_ON 30 +5VS
14 CLK_PCIE_VGA# 14 CLK_PCIE_VGA
PEX_RX1# GND PEX_RX1 PEX_TX1# GND PEX_TX1 PEX_RX0# GND PEX_RX0 PEX_TX0# GND PEX_TX0 PEX_REFCLK# PRSNT1# PEX_REFCLK TV_C/HDTV_Pr CLK_REQ# GND PEX_RST# TV_Y/HDTV_Y RSVD GND RSVD TV_CVBS/HDTV_Pb SMB_DAT GND SMB_CLK VGA_RED THERM# GND VGA_HSYNC VGA_GRN VGA_VSYNC GND DDCA_CLK VGA_BLU DDCA_DAT GND IGP_UCLK# LVDS_UCLK# IGP_UCLK LVDS_UCLK GND GND RSVD LVDS_UTX3# RSVD LVDS_UTX3 RSVD GND IGP_UTX2# LVDS_UTX2# IGP_UTX2 LVDS_UTX2 GND GND IGP_UTX1# LVDS_UTX1# IGP_UTX1 LVDS_UTX1 GND GND IGP_UTX0# LVDS_UTX0# IGP_UTX0 LVDS_UTX0 GND GND IGP_LCLK#/DVI_B_CLK# LVDS_LCLK# IGP_LCLK/DVI_B_CLK LVDS_LCLK DVI_B_HPD/GND GND RSVD LVDS_LTX3# RSVD LVDS_LTX3 GND GND IGP_LTX2#/DVI_B_TX2# LVDS_LTX2# IGP_LTX2/DVI_B_TX2 LVDS_LTX2 GND GND IGP_LTX1#/DVI_B_TX1# LVDS_LTX1# IGP_LTX1/DVI_B_TX1 LVDS_LTX1 GND GND IGP_LTX0#/DVI_B_TX0# LVDS_LTX0# IGP_LTX0/DVI_B_TX0 LVDS_LTX0 DVI_A_HPD GND DVI_A_CLK# DDCC_DAT DVI_A_CLK DDCC_CLK GND LVDS_PPEN DVI_A_TX2# LVDS_BL_BRGHT DVI_A_TX2 LVDS_BLEN GND DDCB_DAT DVI_A_TX1# DDCB_CLK DVI_A_TX1 2V5RUN GND GND DVI_A_TX0# 3V3RUN DVI_A_TX0 3V3RUN GND 3V3RUN GND GND
D
PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P11
109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P0
2 G
PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P12
PRSNT2# PEX_TX15# PEX_TX15 GND PEX_TX14# PEX_TX14 GND PEX_TX13# PEX_TX13 GND PEX_TX12# PEX_TX12 GND PEX_TX11# PEX_TX11 GND PEX_TX10# PEX_TX10 GND PEX_TX9# PEX_TX9 GND PEX_TX8# PEX_TX8 GND PEX_TX7# PEX_TX7 GND PEX_TX6# PEX_TX6 GND PEX_TX5# PEX_TX5 GND PEX_TX4# PEX_TX4 GND PEX_TX3# PEX_TX3 GND PEX_TX2# PEX_TX2
PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P1
+1.8VS
140mil(3.5A)
S
PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P13
PEX_RX15# PEX_RX15 GND PEX_RX14# PEX_RX14 GND PEX_RX13# PEX_RX13 GND PEX_RX12# PEX_RX12 GND PEX_RX11# PEX_RX11 GND PEX_RX10# PEX_RX10 GND PEX_RX9# PEX_RX9 GND PEX_RX8# PEX_RX8 GND PEX_RX7# PEX_RX7 GND PEX_RX6# PEX_RX6 GND PEX_RX5# PEX_RX5 GND PEX_RX4# PEX_RX4 GND PEX_RX3# PEX_RX3 GND PEX_RX2# PEX_RX2 GND
2 4 6 8 10 12 14 16 18 20 22 24
-c c
PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P14
25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107
1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN RUNPWROK 5VRUN GND GND GND
-c o
PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P15
PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC GND GND GND GND
VF
1 3 5 7 9 11 13 15 17 19 21 23
+MXM_B+
JP19B
D
8 PCIE_GTX_C_MRX_P[0..15]
JP19A
C
1
PCIE_MTX_C_GRX_N[0..15]
8 PCIE_MTX_C_GRX_N[0..15]
D
3
PM@
D_EC_SMB_CK1 A
Q47 2N7002_SOT23
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
MXM Connector Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
15
of
44
5
4
3
2
TXOUT0TXOUT0+
LCD POWER CIRCUIT +LCDVDD
3
2
1 2
2
1
3
R13
TZOUT2TZOUT2+
+LCDVDD
1
S
1
C17
4.7U_0805_10V4Z 2
R12 100K_0402_5%
TZCLKTZCLK+
W=60mils
0.047U_0402_16V7K 2
Q3 2N7002_SOT23
2 G 1
ENVDD
1
3
15
GM@ 2 0_0402_5% PM@ 2 0_0402_5%
D
4.7U_0805_10V4Z
Q1 AO3413_SOT23-3
2
1
1 1K_0402_5% 1 C16
S
1
G
2 R9
TZOUT0TZOUT0+ TZOUT1TZOUT1+
D
2 G
1 2 RP10 1 2 RP12 1 2 RP14 1 2 RP16 1 2 RP18
C19
S
D Q2 2N7002_SOT23
R14
RP8 1
R10 100K_0402_5%
1 2
TXCLKTXCLK+
1
1 R11 300_0603_5%
8 GMCH_ENVDD
TXOUT2TXOUT2+
W=60mils
D
1 2 RP6
+3VS
+3V
1 2 RP4
TXOUT1TXOUT1+
2
4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@
1
VGA_TXOUT0VGA_TXOUT0+ 0_0404_4P2R_5% VGA_TXOUT1VGA_TXOUT1+ 0_0404_4P2R_5% VGA_TXOUT2VGA_TXOUT2+ 0_0404_4P2R_5% VGA_TXCLKVGA_TXCLK+ 0_0404_4P2R_5% VGA_TZOUT0VGA_TZOUT0+ 0_0404_4P2R_5% VGA_TZOUT1VGA_TZOUT1+ 0_0404_4P2R_5% VGA_TZOUT2VGA_TZOUT2+ 0_0404_4P2R_5% VGA_TZCLKVGA_TZCLK+ 0_0404_4P2R_5%
VGA_TXOUT0- 15 VGA_TXOUT0+ 15 VGA_TXOUT1- 15 VGA_TXOUT1+ 15 VGA_TXOUT2- 15 VGA_TXOUT2+ 15 VGA_TXCLK- 15 VGA_TXCLK+ 15 VGA_TZOUT0- 15 VGA_TZOUT0+ 15
D
VGA_TZOUT1- 15 VGA_TZOUT1+ 15 VGA_TZOUT2- 15 VGA_TZOUT2+ 15 VGA_TZCLK- 15 VGA_TZCLK+ 15
C10 I2CC_SCL I2CC_SDA
0.1U_0402_16V4Z
1 2
GMCH_LCD_CLK 4 GMCH_LCD_DATA 3 GM@ 0_0404_4P2R_5%
GMCH_LCD_CLK 8 GMCH_LCD_DATA 8
-c c
2
RP2
TXOUT0TXOUT0+
+3VS
2 1
RP3
1
TXOUT1TXOUT1+
DAC_BRIG
R8
1
4.7K_0402_5%
INVTPWM
DISPOFF#
DISPOFF#
1
2
1
2
C15
220P_0402_50V7K
C11
2 1
RP7
TXCLKTXCLK+
220P_0402_50V7K
2 1
RP9
C
TZOUT0TZOUT0+ TZOUT1TZOUT1+
LCD/PANEL BD. Conn.
TZOUT2TZOUT2+
JP1
5 P
1
Y
A
2
R501 1
15 VGA_DVI_TXD015 VGA_DVI_TXD0+
1 2 RP45
15 VGA_DVI_TXD115 VGA_DVI_TXD1+
2 1
+3VS
1
RP1
2 1 RP46
1
10K_0402_5% @
@
2 180_0402_1% DVI_TXD1@ DVI_TXD1+ DVI_TXD2DVI_TXD2+ 180_0402_1% @
1 2 RP47
4 3 0_0404_4P2R_5% DVI@
2 180_0402_1% @ DVI_TXC+ DVI_TXC-
Optional for ATI M66M/M7x
For GMCH DPST
1 2
4 5
23 24
25 26 27 28 31 32 8
1
1.1A_6VDC_FUSE C23 DVI@ 0.1U_0402_16V4Z DVI@
TMDS_DATA0TMDS_DATA0+
+5V
14
R17 4.7K_0402_5% DVI@
TMDS_DATA1TMDS_DATA1+ DDC_CLOCK
TMDS_DATA3TMDS_DATA3+
DDC_DATA
R18 4.7K_0402_5% DVI@
B
3
Q35 2N7002_SOT23 DVI@ 1
6 7
VGA_DVI_SCLK 15
3
VGA_DVI_SDATA 15
Q36 2N7002_SOT23 DVI@
TMDS_DATA4TMDS_DATA4+ R360
TMDS_DATA5TMDS_DATA5+
Hot Plug Detect
16
TMDS_Clock+ TMDS_Clock-
Shield Shield Shield Shield Shield Shield
+5VS
+3VS
1
TMDS_DATA2TMDS_DATA2+
2
RB411DT146_SOT23-3 DVI@
TMDS_DATA2/4 shield TMDS_DATA1/3 shield TMDS_DATA0/5 shield TMDS_Clock shield
Analog VSYNC
GND
3 11 19 22
1
2 20K_0402_5% DVI@ R361
DVI_DET
DVI_DET
15
100K_0402_5% DVI@
D20 SKS10-04AT_TSMA @
15
SUYIN_070939FR024S531PL CONN@
A
+INVPWR_B+
9 10
D7 2
+DVI_VCC
JP15 17 18
12 13
2
2
DVI-D Connector
2 180_0402_1% DVI_TXD0@ DVI_TXD0+
3
Q56 2N7002_SOT23
F2 1 1
20 21 R504 1
2 G
2
INVTPWM
D
+3VS
4 3 0_0404_4P2R_5% DVI@ R502 1 3 4 0_0404_4P2R_5% DVI@ 3 4 0_0404_4P2R_5% DVI@ 1 R503
W=40mils +DVI_VCC
2 G
TXCLKTXCLK+
S
R746
GMCH_TZCLK- 8 GMCH_TZCLK+ 8
0_0404_4P2R_5%
S
TXOUT2+ TXOUT2-
15 VGA_DVI_TXC+ 15 VGA_DVI_TXC-
3
NC7SZ14P5X_NL_SC70-5 @
GMCH_TZCLKGMCH_TZCLK+
2 G
TXOUT1TXOUT1+
DPST_PWM 8
G
4
NC
U48 INVTPWM
GMCH_TZOUT2- 8 GMCH_TZOUT2+ 8
0_0404_4P2R_5%
W=60mils TXOUT0TXOUT0+
15 VGA_DVI_TXD215 VGA_DVI_TXD2+
+3VS
GMCH_TZOUT2GMCH_TZOUT2+
+LCDVDD
ACES_88242-4001 CONN@
B
GMCH_TZOUT1- 8 GMCH_TZOUT1+ 8
0_0404_4P2R_5%
S
USB20_N3_R USB20_P3_R
2 2
GMCH_TZOUT1GMCH_TZOUT1+
D
0_0603_5% R3 1 R4 1 0_0603_5%
USB20_N3 USB20_P3
INVT_PWM 28
VF
20 20
2 0_0402_5%
C
GMCH_TZOUT0- 8 GMCH_TZOUT0+ 8
0_0404_4P2R_5%
D
TZCLKTZCLK+
1
GMCH_TZOUT0GMCH_TZOUT0+
1
TZOUT2+ TZOUT2-
R7
GMCH_TXCLK- 8 GMCH_TXCLK+ 8
0_0404_4P2R_5%
2
TZOUT1+ TZOUT1-
DAC_BRIG 28
INVTPWM DISPOFF#
GMCH_TXCLKGMCH_TXCLK+
1
TZOUT0TZOUT0+
GND 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
GMCH_TXOUT2- 8 GMCH_TXOUT2+ 8
0_0404_4P2R_5%
2
I2CC_SCL I2CC_SDA
15 I2CC_SCL 15 I2CC_SDA
GND 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
TZCLKTZCLK+
GMCH_TXOUT2GMCH_TXOUT2+
1
+3VS
DAC_BRIG
GMCH_TXOUT1- 8 GMCH_TXOUT1+ 8
0_0404_4P2R_5%
2
+INVPWR_B+
41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
-c o
42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
2 1 RP11 2 1 RP13 2 1 RP15 2 1 RP17
GMCH_TXOUT0- 8 GMCH_TXOUT0+ 8
GMCH_TXOUT1GMCH_TXOUT1+
1
D4 2 RB751V_SOD323
1
2
BKOFF#
BKOFF#
TXOUT2TXOUT2+
220P_0402_50V7K
GMCH_TXOUT0GMCH_TXOUT0+
0_0404_4P2R_5%
2
28
RP5
2
C9
2 1
3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@
+LCDVDD
A
+3VS L31 2 1 KC FBM-L11-201209-221LMAT_0805
W=40mils
L29 2 1 KC FBM-L11-201209-221LMAT_0805 C432
1
1
B+ 1
2
C433
1
C18 0.1U_0402_16V4Z
2
680P_0603_50V7K 68P_0402_50V8J 2 2
5
C14 10U_0805_10V4Z
1
2
C8 0.1U_0402_16V4Z
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
2
Title
LVDS & DVI Connector Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
16
of
44
B
C
D
CRT Connector
E
W=40mils +5VS
+R_CRT_VCC D19
1
1
D3 D2 D1 @ @ @ DAN217_SC59 DAN217_SC59 DAN217_SC59 1
A
2
1
1
W=40mils
2 1.1A_6VDC_FUSE 1
C430 0.1U_0402_16V4Z 2
3
2
1 R685 0_0603_5% 1 R686 0_0603_5%
3
2
2
2
@
2
@
+3VS
3
RB411DT146_SOT23-3 +2.5VS
+CRT_VCC
F1
1
1
CRT_R
2 FCM2012C-800_0805
CRT_R_2
1
2 FCM2012C-800_0805
CRT_G_2
1
2 FCM2012C-800_0805
CRT_B_2
1 L5
CRT_G L3 L1 1
R1 C12 2
1
1
C2
150_0402_1%
2 2 10P_0402_50V8J 10P_0402_50V8J
change to 47pf for ATI M66/M7x +CRT_VCC
5
2 R359
P
2
RP51
G
Y
1 L32
CRT_HSYNC_2 2 FCM1608C-121T_0603
1 L30
CRT_VSYNC_2 2 FCM1608C-121T_0603
1 10K_0402_5%
C435 10P_0402_50V8J
1
1
2
2
C436
1
CRT_DET 20 DSUB_12
R763 100K_0402_5%
1
C434
10P_0402_50V8J
16 17
SUYIN_070549FR015S208CR CONN@
2 100P_0402_50V8J
C437 2 68P_0402_50V8J 1
2
SN74AHCT1G125DCKR_SC70-5
DSUB_15
+CRT_VCC
2
C431 68P_0402_50V8J
+CRT_VCC
1 C438
2 0.1U_0402_16V4Z
5
1
4 3
A
C3 10P_0402_50V8J
CRT_HSYNC_1
4
P
4 3 RP50
2
2
CRT_VSYNC
2
A
+CRT_VCC
U19
Y
CRT_VSYNC_1
4
Place closed to chipset
G
8 GMCH_TV_LUMA 8 GMCH_TV_CRMA
4 3 RP49
CRT_HSYNC
U18
OE#
8 GMCH_CRT_R 8 GMCH_TV_COMPS
RP48
CRT_VSYNC CRT_HSYNC 33_0404_4P2R_5% CRT_B CRT_G 0_0404_4P2R_5% CRT_R TV_COMPS 0_0404_4P2R_5% TV_LUMA TV_CRMA 0_0404_4P2R_5%
1
-c o
8 GMCH_CRT_B 8 GMCH_CRT_G
1 2 GM@ 1 2 GM@ 1 2 GM@ 1 2 GM@
3
8 GMCH_CRT_VSYNC 8 GMCH_CRT_HSYNC
4 3
1
2 0.1U_0402_16V4Z
OE#
1 C439
1
C7 C5 10P_0402_50V8J 10P_0402_50V8J 2 2
-c c
150_0402_1%
1 C6
2 10P_0402_50V8J
2
2
150_0402_1%
2
R2
1
R6
1
1
1
CRT_B
JP14 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
VF
1
1
pull-up 2.2k on GPU side 1
VGA_DDC_DATA 15
1
3
D
S
1
GMCH_CRT_DATA 8
2 G
D
Q20 2N7002_SOT23 DSUB_15
R398 GM@ 0_0402_5% 2 1
3 S
4.7K_0402_5% 1
DSUB_12
2 R391 PM@ 0_0402_5%
2 G
2
R384 2
3
TV-OUT Conn.
Place closed to chipset
3
+3VS
Q21 2N7002_SOT23
2 1 R399 GM@ 0_0402_5%
GMCH_CRT_CLK 8 3
1
2 R392 PM@ 0_0402_5%
VGA_DDC_CLK 15
pull-up 2.2k on GPU side
3
RP55
R381 4.7K_0402_5%
D14 D24 D25 @ @ @ DAN217_SC59 DAN217_SC59 DAN217_SC59
2
1 2
1
1 2 RP54
3
RP53
2
15 VGA_TV_LUMA 15 VGA_TV_CRMA
1 2
CRT_VSYNC CRT_HSYNC 0_0404_4P2R_5% CRT_B CRT_G 0_0404_4P2R_5% CRT_R TV_COMPS 0_0404_4P2R_5% TV_LUMA TV_CRMA 0_0404_4P2R_5%
1
15 VGA_CRT_R 15 VGA_TV_COMPS
RP52
4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@
3
15 VGA_CRT_B 15 VGA_CRT_G
1 2
2
15 VGA_CRT_VSYNC 15 VGA_CRT_HSYNC
SN74AHCT1G125DCKR_SC70-5
+3VS
TV_LUMA
1
2 FCM1608C-121T_0603
1
2 FCM1608C-121T_0603
1
2 FCM1608C-121T_0603
L42
TV_CRMA
L40
TV_COMPS
R413
1
R205
1
1
L18
R416
C211
150_0402_1% 2
2
2
150_0402_1%
150_0402_1%
4
1
C510
1
C514
1
GM@ 2 2 6P_0402_50V8K GM@ GM@ 6P_0402_50V8K 6P_0402_50V8K 2
1
C216 GM@ 6P_0402_50V8K 2
JP24 TV_CRMA_1 TV_COMPS_1 TV_LUMA_1
C508
1
1
3 6 7 5 2 4 1 8 9
C515 GM@ GM@ 6P_0402_50V8K 2 2 6P_0402_50V8K
SUYIN_030107FR007SX08FU CONN@
4
change to 47pf for ATI M66/M7x P/N: SE071470J80 ( S CER CAP 47P 50V J NPO 0402 )
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
CRT & TV-OUT Connector Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
17
of
44
5
4
3
2
1
+3VS U42B
R144 1
2 8.2K_0402_5%
PCI_STOP#
R139 1
2 8.2K_0402_5%
PCI_TRDY#
R145 1
2 8.2K_0402_5%
PCI_FRAME#
R137 1
2 8.2K_0402_5%
PCI_PLOCK#
R122 1
2 8.2K_0402_5%
PCI_IRDY#
R124 1
2 8.2K_0402_5%
PCI_SERR#
R138 1
2 8.2K_0402_5%
PCI_PERR#
+3VS
PCI_PIRQA#
2 8.2K_0402_5%
PCI_PIRQB#
R136 1
2 8.2K_0402_5%
PCI_PIRQC#
R140 1
2 8.2K_0402_5%
PCI_PIRQD#
R108 1
2 8.2K_0402_5%
PCI_PIRQE#
R111 1
2 8.2K_0402_5%
PCI_PIRQF#
R112 1
2 8.2K_0402_5%
PCI_PIRQG#
R134 1
2 8.2K_0402_5%
PCI_PIRQH#
R135 1
2 8.2K_0402_5%
PCI_REQ#0
R125 1
2 8.2K_0402_5%
PCI_REQ#1
R146 1
2 8.2K_0402_5%
PCI_REQ#2
R142 1
2 8.2K_0402_5%
PCI_REQ#3
R666 1
2 8.2K_0402_5%
PCI_REQ#4
R667 1
2 8.2K_0402_5%
PCI_REQ#5
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
A3 B4 C5 B5 AE5 AD5 AG4 AH4 AD9
D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8
PCI_REQ#0 PCI_GNT#0 PCI_REQ#1
C/BE0# C/BE1# C/BE2# C/BE3#
B15 C12 D12 C15
PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
A7 E10 B18 A12 C9 E11 B10 F15 F14 F16
PCI_IRDY# PCI_PAR PCI_RST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
PLTRST# PCICLK PME#
C26 A9 B19
PLT_RST# CLK_PCI_ICH PCI_PME#
G8 F7 F8 G7
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PCI
Interrupt
PIRQA# PIRQB# PIRQC# PIRQD#
I/F
GPIO2 / PIRQE# GPIO3 / PIRQF# GPIO4 / PIRQG# GPIO5 / PIRQH#
MISC
RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]
RSVD[6] RSVD[7] RSVD[8] RSVD[9] MCH_SYNC#
PCI_REQ#0 23 PCI_GNT#0 23
PCI_REQ#2
D
PCI_REQ#3 PCI_REQ#4 PCI_GNT#4 PCI_REQ#5 PCI_GNT#5 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3
23 23 23 23
PCI_IRDY# 23 PCI_PAR 23 PCI_RST# 23,26,27 PCI_DEVSEL# 23 PCI_PERR# 23 PCI_SERR# 23 PCI_STOP# 23 PCI_TRDY# 23 PCI_FRAME# 23
Place closely pin B10 CLK_PCI_ICH
PLT_RST# 6,20,22,24,28 CLK_PCI_ICH 14 PCI_PME#
PCI_PIRQE#
AE9 AG8 AH8 F21 AH20
R123 10_0402_5% @
23
MCH_ICH_SYNC#
C126 10P_0402_50V8J @
C
1
2
6
ICH7_BGA652~D
1
0
PCI
1
1
LPC*
1
Y A
4
NC7SZ08P5X_NL_SC70-5
R316 100K_0402_5%
+3VS
U9 2 B
1
Y A
NC7SZ08P5X_NL_SC70-5
PLT_RST_BUF# 26
1
SPI
4
2 R321
1 100_0402_5% PM@
1
1
3
0
U8 2 B
2
PLT_RST#
Boot BIOS Loaction
5
+3VS
Boot BIOS Strap
PCI_GNT#5 PCI_GNT#4
B
P
2 1K_0402_5% PCI_GNT#4 @
G
1
5
2 1K_0402_5% PCI_GNT#5 @
P
1
R126
G
R121
VF
B
2 8.2K_0402_5%
R120 1
REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ4# / GPIO22 GNT4# / GPIO48 GPIO1 / REQ5# GPIO17 / GNT5#
-c o
C
R109 1
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
2
PCI_DEVSEL#
1
2 8.2K_0402_5%
E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6
3
D
R143 1
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
-c c
23 PCI_AD[0..31]
PLTRST_VGA# 15
R317 100K_0402_5% PM@
2
PM@
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
ICH7M(1/4)-PCI Size
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Date:
Monday, April 16, 2007
Sheet 1
18
of
44
5
4
3
2
1
+RTCVCC
NC
OUT
4
2
NC
IN
1
D
+RTCVCC
R281 332K_0402_1%
ICH_RTCX2
AB1 AB2
ICH_RTCRST#
AA3 ICH_INTVRMEN SM_INTRUDER#
2
W1 Y1 Y2 W3
C292 1U_0603_10V4Z 1 2
High = Internal VR Enable
INTVRMEN INTRUDER#
+3VS
EE_CS EE_SHCLK EE_DOUT EE_DIN
V3
LAN_CLK
U3
LAN_RSTSYNC
U5 V4 T5
LAN_RXD0 LAN_RXD1 LAN_RXD2
1
U7 V6 V7
R298
2
30 HDA_RST_MDC#
U1 R6
31 HDA_SDIN0 30 HDA_SDIN1
30 HDA_SDOUT_MDC
1 R279
31 HDA_SYNC_AUDIO
1 R273
HDA_SYNC_ICH 2 39_0402_5%
31 HDA_RST_AUDIO#
1 R300
HDA_RST_ICH# 2 39_0402_5%
31 HDA_SDOUT_AUDIO
1 R299
HDA_SDOUT_ICH 2 39_0402_5%
R5
ACZ_RST#
T2 T3 T1
ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2
T4
SATALED#
22 SATA_DTX_C_IRX_N0 22 SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 SATA_ITX_DRX_N0 SATA_ITX_DRX_P0
AF3 AE3 AG2 AH2
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
22 SATA_DTX_C_IRX_N1 22 SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_ITX_DRX_N1 SATA_ITX_DRX_P1
AF7 AE7 AG6 AH6
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
CLK_PCIE_SATA# CLK_PCIE_SATA
AF1 AE1
SATA_CLKN SATA_CLKP
SATA_LED#
14 CLK_PCIE_SATA# 14 CLK_PCIE_SATA
1
2 24.9_0402_1%
AH10 SATARBIAS AG10
8.2K_0402_5%
SATA_ITX_DRX_N0
1 R203
2
1 R199
2
VF
4.7K_0402_5%
IDE_IRQ
1 C290 1 C291
SATA_ITX_C_DRX_N0 2 3900P_0402_50V7K SATA_ITX_C_DRX_P0 2 3900P_0402_50V7K
SATA_ITX_DRX_N1 1 SATAX2@ C281 SATA_ITX_DRX_P1 1 SATAX2@ C280
SATA_ITX_C_DRX_N1 2 3900P_0402_50V7K SATA_ITX_C_DRX_P1 2 3900P_0402_50V7K
SATA_ITX_DRX_P0
A
22 IDE_DIORDY 22 IDE_IRQ 22 IDE_DDACK# 22 IDE_DIOW # 22 IDE_DIOR#
IDE_DIORDY
AE22 AH28
CPUSLP#
AG27
TP1 / DPRSTP# TP2 / DPSLP#
AF24 AH25
DPRSTP# R260 1 DPSLP# R261 1
IDE_DIORDY IDE_IRQ IDE_DDACK# IDE_DIOW # IDE_DIOR#
D
26,28 26,28 26,28 26,28
H_FERR#
EC_GA20 H_A20M#
AG26
AG24
H_PW RGOOD
IGNNE# INIT3_3V# INIT# INTR
AG22 AG21 AF22 AF25
H_IGNNE#
RCIN#
AG23
EC_KBRST#
AF23 AH24
H_SMI# H_NMI
STPCLK#
AH22
H_STPCLK#
THERMTRIP#
AF26
THRMTRIP_ICH#
SMI# NMI
IDE
AG16 AH16 AF16 AH15 AF15
IORDY IDEIRQ DDACK# DIOW# DIOR#
R250
1
56_0402_5%
LPC_FRAME# 26,28
2
1 R271 10K_0402_5%
H_INIT# H_INTR
DA0 DA1 DA2
AH17 AE17 AF17
IDE_DA0 IDE_DA1 IDE_DA2
DCS1# DCS3#
AE16 AD16
IDE_DCS1# IDE_DCS3#
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15
IDE_DD0 IDE_DD1 IDE_DD2 IDE_DD3 IDE_DD4 IDE_DD5 IDE_DD6 IDE_DD7 IDE_DD8 IDE_DD9 IDE_DD10 IDE_DD11 IDE_DD12 IDE_DD13 IDE_DD14 IDE_DD15
DDREQ
AE15
IDE_DDREQ
+3VS
EC_GA20 28 H_A20M# 4
0_0402_5% H_DPRSTP# 0_0402_5% H_DPSLP#
2 2
H_DPRSTP# 4,42 H_DPSLP# 4
H_FERR# 4
H_PW RGOOD 4 H_IGNNE# H_INIT# H_INTR
H_SMI# H_NMI
4
4 4
R272
1 10K_0402_5%
2
+3VS
C
EC_KBRST# 28
4 4
H_STPCLK# 4
R258 1
2 24.9_0402_1%
IDE_DA[0..2]
22
H_THERMTRIP#
2 R257
H_THERMTRIP# 4,6
1 56_0402_5%
+1.05VS
IDE_DCS1# 22 IDE_DCS3# 22 IDE_DD[0..15]
22
MAINPW ON 35,36,38 B
R189 @ 330_0402_5% 1 2
+1.05VS
C
Q10
2 B E
IDE_DDREQ
22
2SC2411K_SOT23 @
H_THERMTRIP#
ICH7_BGA652~D
SATAX1@ SATA_DTX_C_IRX_N1 1 2 R656 1K_0402_5% SATA_DTX_C_IRX_P1 1 SATAX1@ 2 1K_0402_5% R657
SATA_ITX_C_DRX_N0 22 SATA_ITX_C_DRX_P0 22
SATA_ITX_C_DRX_N1 22 SATA_ITX_C_DRX_P1 22
SATA_RXn/p need tie to ground when SATA port no used
close ICH8
2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
5
2
LPC_DRQ#1 26
FERR#
SATARBIASN SATARBIASP
10mils width less than 500mils
+3VS
A20GATE A20M#
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LPC_FRAME#
GPIO49 / CPUPWRGD
ACZ_SDOUT
AF18
R242
B
AB3
SATA
31 HDA_BITCLK_AUDIO
LFRAME#
H_FERR#
ACZ_BCLK ACZ_SYNC
SATA_LED#
28
2 HDA_BITCLK_ICH 39_0402_5%
HDA_SDOUT_ICH 2 39_0402_5%
AC3 AA5
-c o
1 R310
LDRQ0# LDRQ1# / GPIO23
AC-97/AZALIA
HDA_BITCLK_ICH 2 39_0402_5% HDA_SYNC_ICH 2 39_0402_5% HDA_RST_ICH# 2 39_0402_5%
1 R293 1 R292 1 R301
30 HDA_BITCLK_MDC 30 HDA_SYNC_MDC SATA_LED#
AA6 AB5 AC4 Y6
LAN_TXD0 LAN_TXD1 LAN_TXD2
10K_0402_5% C
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LAD0 LAD1 LAD2 LAD3
LAN
ICH_INTVRMEN
RTCRST#
W4 Y5
R754 1 2 @ 10K_0603_5%
close to RAM door
RTXC1 RTCX2
3
1
+RTCVCC
1 2 R264 20K_0402_5%
+1.05VS U42A
RTC
C286 18P_0402_50V8J 2 1
1
SM_INTRUDER#
3
-c c
32.768KHZ_12.5P_MC-306
LPC
1M_0402_5%
2
ICH_RTCX1
X1
R263 10M_0402_5% 2 1
R265
CPU
1
C287 18P_0402_50V8J 2 1
2
Title
ICH7M(2/4)-LAN,IDELPC,RTC Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
19
of
44
5
4
3
2
1
+3V
SERIRQ
8.2K_0402_5% R270 1 2
PM_CLKRUN#
10K_0402_5% R658 1 2
ICH_VGATE
8.2K_0402_5% R309 1 2 @
EC_THERM#
R157 2.2K_0402_5%
28 PM_CLKRUN# 22 IDE_HRESET#
150_0402_1% R311 1 2
XDP_DBRESET#
1K_0402_5% R302 1 2
ICH_PCIE_WAKE#
10K_0402_5% R290 1 2
SPI_CS#1
ICH_PCIE_WAKE# SERIRQ EC_THERM#
F20 AH21 AF20
WAKE# SERIRQ THRM#
1 ICH_VGATE AD22 0_0402_5%
28
AC21 AC18 E21
EC_SMI#
EC_SMI#
PWRBTN#
C23
PBTN_OUT#
LAN_RST#
C19
RSMRST#
VRMPWRGD
GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35 / SATAREQ# GPIO38 GPIO39
GPIO
GPIO6 GPIO7 GPIO8
SPI_MOSI ICH7_BGA652~D SPI_MISO
SMBALERT#
1 2
PM_DPRSLPVR 6,42
PBTN_OUT# 28 PLT_RST# 6,18,22,24,28
No used Integrated LAN, connecting to PLT_RST#
SB_RSMRST#
Y4
EC_SCI#
E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20
EC_SCI#
100K_0402_5% +3VS 2 1 R278
28
2
EC_LID_OUT# 28
1 D15
ACIN
28,38
@ R453 2 1 0_0402_5% Q14 MMBT3906_NL_SOT23-3 SB_RSMRST#
RB751V_SOD323
SATA_CLKREQ# 14
R259 10K_0402_5%
1 R325
For Express Card
PROJECT_ID1
27 27 27 27
PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P1 PCIE_ITX_C_PRX_N1 PCIE_ITX_C_PRX_P1
+3V
26 26 26 26
PCIE_PTX_C_IRX_N4 PCIE_PTX_C_IRX_P4 PCIE_ITX_C_PRX_N4 PCIE_ITX_C_PRX_P4
1 R294 1 R320 1 R296 1 R668
1 R512 1 R513
2 USB_OC#4 10K_0402_5% 2 USB_OC#6 10K_0402_5%
2 1
1 1
C162 2 C158 2
1 1
PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PCIE_ITX_PRX_N3 PCIE_ITX_PRX_P3
K26 K25 J28 J27
PCIE_PTX_C_IRX_N4 PCIE_PTX_C_IRX_P4 PCIE_ITX_PRX_N4 PCIE_ITX_PRX_P4
M26 M25 L28 L27
0.1U_0402_16V7K 0.1U_0402_16V7K
0.1U_0402_16V7K 0.1U_0402_16V7K
2 USB_OC#1 10K_0402_5% 2 USB_OC#3 10K_0402_5% 2 USB_OC#5 10K_0402_5% 2 USB_OC#7 10K_0402_5%
R670 100K_0402_5%
D33
C166 2 C168 2
27
USB_OC#0
27
USB_OC#2
P26 P25 N28 N27 T25 T24 R28 R27
SPI_CS#1
R2 P6 P1
SPI_MOSI SPI_MISO
P5 P2
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7
D3 C4 D5 D4 E5 C3 A2 B3
CRT_DET#
PERn2 PERp2 PETn2 PETp2 PERn3 PERp3 PETn3 PETp3 PERn4 PERp4 PETn4 PETp4 PERn5 PERp5 PETn5 PETp5 PERn6 PERp6 PETn6 PETp6
SPI_CLK SPI_CS# SPI_ARB
SPI
+3VS
PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PCIE_ITX_C_PRX_N3 PCIE_ITX_C_PRX_P3
VF
For Wireless LAN
24 24 24 24
PERn1 PERp1 PETn1 PETp1
PCI-EXPRESS
For PCIE LAN
2
1 1
F26 F25 E28 E27
H26 H25 G28 G27
SUS_CLK
1
C175 2 C174 2
PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P1 PCIE_ITX_PRX_N1 0.1U_0402_16V7K PCIE_ITX_PRX_P1 0.1U_0402_16V7K
SPI_MOSI SPI_MISO OC0# OC1# OC2# OC3# OC4# OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31
USB
EC_RSMRST# 28
2 4.7K_0402_5%
+3V
D17A 6 2 BAV99DW-7_SOT363 D17B 4 3
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP
DMI_CLKN DMI_CLKP DMI_ZCOMP DMI_IRCOMP USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBRBIAS# USBRBIAS
V26 V25 U28 U27
DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_ITX_MRX_N0 DMI_ITX_MRX_P0
Y26 Y25 W28 W27
DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_ITX_MRX_N1 DMI_ITX_MRX_P1
AB26 AB25 AA28 AA27
DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_ITX_MRX_N2 DMI_ITX_MRX_P2
AD25 AD24 AC28 AC27
DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_ITX_MRX_N3 DMI_ITX_MRX_P3
AE28 AE27
5 DMI_MTX_IRX_N0 6 DMI_MTX_IRX_P0 6 DMI_ITX_MRX_N0 6 DMI_ITX_MRX_P0 6
DMI_IRCOMP
F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7
D2 D1
USBRBIAS
R329 2.2K_0402_5%
DMI_MTX_IRX_N2 6 DMI_MTX_IRX_P2 6 DMI_ITX_MRX_N2 6 DMI_ITX_MRX_P2 6 DMI_MTX_IRX_N3 6 DMI_MTX_IRX_P3 6 DMI_ITX_MRX_N3 6 DMI_ITX_MRX_P3 6
CLK_PCIE_ICH# CLK_PCIE_ICH
C25 D25
BAV99DW-7_SOT363
DMI_MTX_IRX_N1 6 DMI_MTX_IRX_P1 6 DMI_ITX_MRX_N1 6 DMI_ITX_MRX_P1 6
B
CLK_PCIE_ICH# 14 CLK_PCIE_ICH 14 R213 24.9_0402_1% 1 2 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7
Within 500 mils +1.5VS 27 27 27 27 27 27 16 16 26 26 27 27 26 26 26 26
USB Conn. New Card USB Conn. CMOS Camera USB/B Bluetooth USB/B Mini Card(WLAN)
1 2 R160 22.6_0402_1%
ICH7_BGA652~D
Within 500 mils
A
1SS355_SOD323-2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
C
1
U42D
PROJECT_ID0
B
CRT_DET
GPIO33 / AZ_DOCK_EN# GPIO34 / AZ_DOCK_RST#
CRT_DET#
100K_0402_5% PM_DPRSLPVR R285 1 2
@ 10K_0402_5% R663 1 2
GPIO32 / CLKRUN#
AC19 U2
PM_BATLOW#
@ 10K_0402_5% R269 1 2 10K_0402_5% R268 1 2
GPIO27 GPIO28
C21
TP0 / BATLOW#
SYS_PWROK 6,30 2 210K_0402_5% 100_0402_5%
2
10K_0402_5% R277 1 2
B21 E23
IDE_HRESET#
2 R267
VGATE
GPIO26
1 DPRSLPVRR2621 R286 PM_BATLOW#
AC22
D
PM_SLP_S3# 28 PM_SLP_S4# 28 PM_SLP_S5# 28
AA4 SYS_PWROK
DIRECT MEDIA INTERFACE
10K_0402_5% R660 1 2 10K_0402_5% R661 1 2 10K_0402_5% R662 1 2
6,14,42
A21
PWROK GPIO16 / DPRSLPVR
-c o
8.2K_0402_5% R287 2 1
24,26,27 ICH_PCIE_WAKE# 26,28 SERIRQ 28 EC_THERM#
GPIO18 / STPPCI# GPIO20 / STPCPU#
AG18
LINKALERT#
PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#
C298 10P_0402_50V8J @
1
PROJECT_ID0 PROJECT_ID1 PM_CLKRUN#
SUS_CLK
2
E
ICH_SMLINK1
CP_PE#
C20 B24 D23 F22
1
C165 10P_0402_50V8J @
CLK_ICH_14M 14 CLK_ICH_48M 14
C
10K_0402_5% R303 1 2
27
CP_PE#
SUSCLK SLP_S3# SLP_S4# SLP_S5#
R283 10_0402_5% @
B
ICH_SMLINK0
AC20 AF21
1
CLK_ICH_14M CLK_ICH_48M
AC1 B2
2
GPIO11 / SMBALERT#
GPIO
10K_0402_5% R312 1 2
PM_STP_PCI# PM_STP_CPU#
14 PM_STP_PCI# 14 PM_STP_CPU#
EC_SWI#
B23
GPIO0 / BM_BUSY#
R168 10_0402_5% @
2 1 R65910K_0402_5%
1
AB18
SYS
PM_BMBUSY#
SPKR SUS_STAT# SYS_RST#
CLK14 CLK48
AF19 AH18 AH19 AE19
1
SUS_STAT#
A19 A27 A22
PM_BMBUSY#
+3V
10K_0402_5% R276 1 2
CLK_ICH_14M
2
RI#
SATA GPIO
A28
GPIO21 / SATA0GP GPIO19 / SATA1GP GPIO36 / SATA2GP GPIO37 / SATA3GP
@ R284 2 1 10K_0402_5%
2
PAD T6 XDP_DBRESET#
EC_SWI#
SMBALERT# 10K_0402_5% R313 1 2
Place closely pin AC1
CLK_ICH_48M
-c c
SB_SPKR
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1
Clocks
31
EC_SWI# SB_SPKR
C22 B22 A26 B25 A25
POWER MGT
2
2 28
6
17
+3VS
ICH_SMBCLK ICH_SMBDATA LINKALERT# ICH_SMLINK0 ICH_SMLINK1
14,24,26,27 ICH_SMBCLK 14,24,26,27 ICH_SMBDATA
4 XDP_DBRESET#
A
R155 2.2K_0402_5% U42C
High: CRT Plugged
C
Place closely pin B2
1
10K_0402_5% R308 1 2
SMB
D
1
+3VS
2
Title
ICH7M(3/4)-USB,GPIO,PCIE Size Document Number Custom
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Monday, April 16, 2007
Sheet 1
20
of
44
5
4
3
2
1
+1.05VS +5VALW
0.1U_0402_16V4Z
1
1
RB751V_SOD323
C150
+ICH_V5REF
2
0.1U_0402_16V4Z 1
2
R158
D10 RB751V_SOD323
2
1
+ICH_V5REF_SUS C159 0.1U_0402_16V4Z
+3VS
C807
0.1U_0402_16V4Z
Place closely pin AG28 within 100mlis. R664 +1.5VS_DMIPLLR 0.5_0603_1% 1 2 1
+1.5VS_DMIPLL
0_0603_5%
+3V C821 0.1U_0402_16V4Z
1
+1.5VS_DMIPLL 1
+1.5VS
2
C816
0.1U_0402_16V4Z
1
2
+3VS
AG28 AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5
1
2
AD2
AH11
AB10 AB9 AC10 AD10 AE10 AF10 AF9 AG9 AH9
+1.5VS
C820
1U_0603_10V4Z
1
2
Place closely pin AG9.
E3
C1
+1.5VS
2
2
Place closely pin AG5.
0.1U_0402_16V4Z
2
2
C818
1
0.1U_0402_16V4Z
C817
+1.5VS
1
C822
0.1U_0402_16V4Z
1
T35 T36
PAD PAD
ICH_AA2 ICH_Y7
AA2 Y7
2
V5 V1 W2 W7
+3V
A
V_CPU_IO[1] V_CPU_IO[2] V_CPU_IO[3]
AE23 AE26 AH26
Vcc3_3[3] Vcc3_3[4] Vcc3_3[5] Vcc3_3[6] Vcc3_3[7] Vcc3_3[8] Vcc3_3[9] Vcc3_3[10] Vcc3_3[11]
AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19
Vcc3_3[12] Vcc3_3[13] Vcc3_3[14] Vcc3_3[15] Vcc3_3[16] Vcc3_3[17] Vcc3_3[18] Vcc3_3[19] Vcc3_3[20] Vcc3_3[21]
A5 B13 B16 B7 C10 D15 F9 G11 G12 G16
VccRTC
VccSus3_3[1] VccSus3_3[2] VccSus3_3[3] VccSus3_3[4] VccSus3_3[5] VccSus3_3[6]
Vcc3_3[1]
VccSus3_3[7] VccSus3_3[8] VccSus3_3[9] VccSus3_3[10] VccSus3_3[11] VccSus3_3[12] VccSus3_3[13] VccSus3_3[14] VccSus3_3[15] VccSus3_3[16] VccSus3_3[17] VccSus3_3[18]
VccDMIPLL
Vcc1_5_A[1] Vcc1_5_A[2] Vcc1_5_A[3] Vcc1_5_A[4] Vcc1_5_A[5] Vcc1_5_A[6] Vcc1_5_A[7] Vcc1_5_A[8] Vcc1_5_A[9]
VF
B
C815 0.01U_0402_16V7K
2
1
B27
R665 C814 10U_0805_10V4Z
+1.5VS
U6 R7
C794
2
1
+ C795
2
2
1
2
220U_D2_2VMR15
1U_0603_10V4Z
+3VS 1
+1.05VS
+3V
C800 1 2
1
2
1
2
1
2
0.1U_0402_16V4Z
C803 4.7U_0805_10V4Z
Vcc1_5_A[19] Vcc1_5_A[20]
VccSATAPLL Vcc3_3[2]
Vcc1_5_A[21] Vcc1_5_A[22] Vcc1_5_A[23]
Vcc1_5_A[10] Vcc1_5_A[11] Vcc1_5_A[12] Vcc1_5_A[13] Vcc1_5_A[14] Vcc1_5_A[15] Vcc1_5_A[16] Vcc1_5_A[17] Vcc1_5_A[18]
Vcc1_5_A[24] Vcc1_5_A[25] VccSus1_05[1] VccSus1_05[2] VccSus1_05[3]
VccSus3_3[19]
Vcc1_5_A[26] Vcc1_5_A[27] Vcc1_5_A[28] Vcc1_5_A[29] Vcc1_5_A[30]
VccUSBPLL
VccSus1_05/VccLAN1_05[1] VccSus1_05/VccLAN1_05[2]
1
2
+3VS
2005/09/12 +RTCVCC
P7
1
A24 C24 D19 D22 G19
2
K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7
1
2
1
C808 0.1U_0402_16V4Z
2
1
C812 0.1U_0402_16V4Z
AB17 AC17
2
+3V C809 0.1U_0402_16V4Z
1
1
2
2
+3V C813 0.1U_0402_16V4Z
+1.5VS
T7 F17 G17 AB8 AC8
1
2
K7
C819 0.1U_0402_16V4Z ICH_K7 PAD
C28 G20
ICH_C28 ICH_G20
A1 H6 H7 J6 J7
PAD PAD
T32 T33 T34
+1.5VS 1
2
C823 0.1U_0402_16V4Z
A4 A23 B1 B8 B11 B14 B17 B20 B26 B28 C2 C6 C27 D10 D13 D18 D21 D24 E1 E2 E4 E8 E15 F3 F4 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G18 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J1 J2 J5 J24 J25 J26 K24 K27 K28 L13 L15 L24 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M17 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N14 N15 N16 N17 N18 N24 N25 N26 P3 P4 P12 P13 P14 P15 P16 P17 P24 P27
VccSus3_3/VccLAN3_3[1] VccSus3_3/VccLAN3_3[2] VccSus3_3/VccLAN3_3[3] VccSus3_3/VccLAN3_3[4]
VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97]
VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194]
P28 R1 R11 R12 R13 R14 R15 R16 R17 R18 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U14 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V27 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA24 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB27 AB28 AC2 AC5 AC9 AC11 AD1 AD3 AD4 AD7 AD8 AD11 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27
D
C
B
ICH7_BGA652~D A
ICH7_BGA652~D C824 0.1U_0402_16V4Z
Compal Electronics, Inc.
Compal Secret Data 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
0.1U_0402_16V4Z
C801 0.1U_0402_16V4Z 1 2
C802
W5
Security Classification
5
2
C799
0.1U_0402_16V4Z 1 2
+3VS
-c o
1
10_0402_5% 10_0402_5% @ 1
C
+3V
1
R165
2
+5V
2
+5VALW
Vcc3_3 / VccHDA VccSus3_3/VccSusHDA
1
C811 1U_0402_6.3V4Z
2
Vcc1_5_B[1] Vcc1_5_B[2] Vcc1_5_B[3] Vcc1_5_B[4] Vcc1_5_B[5] Vcc1_5_B[6] Vcc1_5_B[7] Vcc1_5_B[8] Vcc1_5_B[9] Vcc1_5_B[10] Vcc1_5_B[11] Vcc1_5_B[12] Vcc1_5_B[13] Vcc1_5_B[14] Vcc1_5_B[15] Vcc1_5_B[16] Vcc1_5_B[17] Vcc1_5_B[18] Vcc1_5_B[19] Vcc1_5_B[20] Vcc1_5_B[21] Vcc1_5_B[22] Vcc1_5_B[23] Vcc1_5_B[24] Vcc1_5_B[25] Vcc1_5_B[26] Vcc1_5_B[27] Vcc1_5_B[28] Vcc1_5_B[29] Vcc1_5_B[30] Vcc1_5_B[31] Vcc1_5_B[32] Vcc1_5_B[33] Vcc1_5_B[34] Vcc1_5_B[35] Vcc1_5_B[36] Vcc1_5_B[37] Vcc1_5_B[38] Vcc1_5_B[39] Vcc1_5_B[40] Vcc1_5_B[41] Vcc1_5_B[42] Vcc1_5_B[43] Vcc1_5_B[44] Vcc1_5_B[45] Vcc1_5_B[46] Vcc1_5_B[47] Vcc1_5_B[48] Vcc1_5_B[49] Vcc1_5_B[50] Vcc1_5_B[51] Vcc1_5_B[52] Vcc1_5_B[53]
1 C792
C810 0.1U_0402_16V4Z
1
Place closely pin D28,T28,AD28.
2
2 1
C798
2
0.1U_0402_16V4Z
D8
100_0402_5%
C797
2
1
V5REF_Sus
0.1U_0402_16V4Z
C806 0.1U_0402_16V4Z
C796
2
1
V5REF[2]
L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
C805 0.1U_0402_16V4Z
G +
C793 220U_D2_2VMR15
+3VS
R149
AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28 D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 R25 R26 T22 T23 T26 T27 T28 U22 U23 V22 V23 W22 W23 Y22 Y23
1
+5V
+5VS
F6
0.1U_0402_16V4Z
0.1U_0603_25V7K 2
D
+ICH_V5REF_SUS
D
C630
+1.5VS
Q44 AO3413_SOT23-3
Vcc1_05[1] Vcc1_05[2] Vcc1_05[3] Vcc1_05[4] Vcc1_05[5] Vcc1_05[6] Vcc1_05[7] Vcc1_05[8] Vcc1_05[9] Vcc1_05[10] Vcc1_05[11] Vcc1_05[12] Vcc1_05[13] Vcc1_05[14] Vcc1_05[15] Vcc1_05[16] Vcc1_05[17] Vcc1_05[18] Vcc1_05[19] Vcc1_05[20]
C804 0.1U_0402_16V4Z
AD17
2 1
V5REF[1]
-c c
G10
S
3
+ICH_V5REF
34 SBPWR_EN#
U42E
U42F
3
2
Title
ICH7M(4/4)-POWER&GND Size Document Number Custom
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Sheet
Monday, April 16, 2007 1
21
of
44
A
B
D
E
F
G
H
Placea caps. near ODD CONN.
C183
10U_0805_10V4Z
1
1
2
2
1
C184
1
C194
+3VS
2
2
C192
1000P_0402_50V7K
10U_0805_10V4Z
1U_0402_6.3V4Z
IDE_DD[0..15]
19 IDE_DD[0..15]
1
C239 2 0.1U_0402_16V4Z
1
IDE_DA[0..2]
19 IDE_DA[0..2]
U7 20 IDE_HRESET# 6,18,20,24,28 PLT_RST#
IDE_HRESET#
2
PLT_RST#
1
1
5
C197
P
1
B
Y A
NC7SZ08P5X_NL_SC70-5
4
IDE_RST#
G
0.1U_0402_16V4Z
3
+5VS
2
C
IDE_RST# IDE_DD7 IDE_DD6 IDE_DD5 IDE_DD4 IDE_DD3 IDE_DD2 IDE_DD1 IDE_DD0 19 IDE_DIOW# 19 IDE_DIORDY 19 IDE_IRQ 19 28 2
IDE_DCS1# IDE_LED# +5VS
1 R169
IDE_DIOW# IDE_DIORDY IDE_IRQ IDE_DA1 IDE_DA0 IDE_DCS1# IDE_LED#
2 475_0402_1%
IDE_CSEL
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
IDE_DD8 IDE_DD9 IDE_DD10 IDE_DD11 IDE_DD12 IDE_DD13 IDE_DD14 IDE_DD15 IDE_DDREQ IDE_DIOR#
IDE_DDREQ 19 IDE_DIOR# 19
IDE_DDACK# IDE_PDIAG# IDE_DA2 IDE_DCS3#
IDE_DDACK# 19 1
2 R200 100K_0402_5% IDE_DCS3# 19 +5VS
+5VS
0.1U_0402_16V4Z
2 R185
1
1
C196
C182
1
2
IDE_LED# 100K_0402_5%
2
1000P_0402_50V7K
3
SATA_DTX_C_IRX_N0
1 C566
VF
19 SATA_DTX_C_IRX_N0
+3VS
C193
-c o
1
+5VS
2
+5VS
OCTEK_CDR-50JD1 CONN@
IDE_CSEL Grounding for Master (When use SATA HDD) Open or High for Slaver (Normal)
-c c
JP25
1
2
2
1U_0402_6.3V4Z
SATA_DTX_C_IRX_P0
1 C562
SATA_DTX_IRX_P0 2 3900P_0402_50V7K
19 SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_P1 1 SATAX2@ C541
SATA_DTX_IRX_P1 2 3900P_0402_50V7K
19 SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_N1 1 SATAX2@ C539
SATA_DTX_IRX_N1 2 3900P_0402_50V7K
0.1U_0402_16V4Z
SATA HDD Conn.(SAS Connector) JP27 19 SATA_ITX_C_DRX_P0 19 SATA_ITX_C_DRX_N0
1 2 3 4 5 6 7
SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 SATA_DTX_IRX_N0 SATA_DTX_IRX_P0
SATA_DTX_IRX_N0 2 3900P_0402_50V7K
19 SATA_DTX_C_IRX_P0
C245
19 SATA_ITX_C_DRX_P1 19 SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1 SATA_DTX_IRX_N1 SATA_DTX_IRX_P1
+3VS
+5VS
4
GND HTX0+ HTX0GND HRX0HRX0+ GND
First HDD for 15.4"
23 24 25 26 27 28 29
GND HTX1+ HTX1GND HRX1HRX1+ GND
2nd HDD for 17"
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND RESERVED GND VCC12 VCC12 VCC12
30 31
GND1 GND2
3
4
OCTEK_SAS-22CA1G CONN@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
E
F
Title
HDD & ODD Connector Size B
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Monday, April 16, 2007 G
Sheet
22 H
of
44
A
B
C
D
E
PS: only below need to pull high others have internal Pull high +3VS
pin 118 pin 7 pin 111 pin 21
40mil 0.1U_0402_16V4Z U46
2
@ 15P_0402_50V8J
PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 18 PCI_GNT#0 18 PCI_REQ#0 18 PCI_PAR 18 PCI_SERR# 18 PCI_PERR# 18 PCI_STOP# 18 PCI_DEVSEL# 18 PCI_TRDY# 18 PCI_IRDY# 18 PCI_FRAME# 18,26,27 PCI_RST# 14 CLK_PCI_Card
+3VS 27,28,30,34,40 SUSP# +3VS +3VS
28
5IN1_LED#
18
PCI_PIRQE#
0_0402_5% 2 @ R728 1 1 2 R73143K_0402_5% R732 1 2 10K_0402_5% SDOC# 5IN1_LED# R729 1 10K_0402_5% 2 R730 1 10K_0402_5% 2
MFUN0
MFUN1 w/o eerom pull low MFUN2
C/BE0# C/BE1# C/BE2# C/BE3#
17 16 59 58 57 56 55 54 53 49 37 38
PCIGNT# PCIREQ# PAR SERR# PERR# STOP# DEVSEL# TRDY# IRDY# FRAME# PCIRST# PCICLK
28
IDSEL
108 93
GRST#
104
MFUN3
110 107 106 105 103 102 100 94
2 13 14 15 30 31 32 44 45 50
@
2 0_0402_5%
2
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS
MSDATA0/SMDATA2 MSDATA1/SMDATA6 MSDATA2/SMDATA5 MSDATA3/SMDATA3
115 114 116 117
xDDATA2/MSDATA0 xDDATA6/MSDATAT1 xDDATA5/MSDADTA2 xDDATA3/MSDADTA3
MSCLK/SMRE#
118
MMDAT4 MMDAT5/SMWP# MMDAT6/SMBAY# MMDAT7/SMCE#
99 112 111 98
R708 2xDSMRE#/MSCLK 1 22_0402_1% XMDAT4B XMDAT5B/XDW PO# XMDAT6B_XDBSY# XMDAT7B_XDCe#
SDCLKI
SUSPEND# RIOUT#_PME#
5 4 9 8 6 7
1 121 122 89
GND_SD1 GND_SD2 NC23 GND7 GND6 GND5 GND4 GND3 GND2 GND1
3 109 12 119 97 92 80 61 43 21
MFUNC7 MFUNC6 MFUNC5 MFUNC4 MFUNC3 MFUNC2 MFUNC1 MFUNC0
NC22 NC21 NC20 NC19 NC18 NC17 NC16 NC15 NC14 NC13 NC12 NC11
128 124 123 79 78 77 76 75 64 63 62 51
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10
MFUN5
0.1U_0402_16V4Z
+3V_MCVCC 1 C882 0.1U_0402_16V4Z
1 C873 2
MS_INS#
2
1 R700 43K_0402_5% 2
xDDATA1/MSBS
1 R703 43K_0402_5% 2
xDDATA2/MSDATA0 xDDATA6/MSDATAT1 xDDATA5/MSDADTA2 xDDATA3/MSDADTA3
1 1 1 1
xDDATA4/SDDAT3 xDCLE/SDDAT2 xDDATA0/SDDAT1 xDDATA7/SDDAT0 xDALE/SDCMD R721 2xDSMW E#/SDCLK 1 22_0402_1%
41
SDPWREN33# SDWP/SMWPD# SDCD# SMCD#
1
xD PU and PD. Close to Socket
MS_INS# MSSMXD_PW REN# xDDATA1/MSBS
SDDAT3/SMDATA4 SDDAT2/SMCLE SDDAT1/SMDATA0 SDDAT0/SMDATA7 SDCMD/SMALE SDCLK/SMWE#
0.1U_0402_16V4Z
SD_PW REN#
PCI_RST#
xDSMRE#/MSCLK
R704 R705 R706 R707
+3VS
MS signal
43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2
1 R709 43K_0402_5% 2
XMDAT4B xDSMW E#/SDCLK XMDAT6B_XDBSY# XMDAT7B_XDCe# xDDATA4/SDDAT3 xDCLE/SDDAT2 xDDATA0/SDDAT1 xDDATA7/SDDAT0 xDALE/SDCMD
1 1 1 1
R710 R711 R712 R713
SD_PW REN# SMW PD#/SDW P SDCD# xDSMCD#
1 R723 43K_0402_5% 2 1 R724 43K_0402_5% 2 R725 1 2 8.2K_0402_5%
8 7 6 5
40mil
GND OUT IN OUT IN OUT MC_PW REN# EN# FLG 1 C890 TPS2061DRG4_SO8 @ R716 0.1U_0402_16V4Z SDOC# 300_0603_5% 2
43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2
MSSMXD_PW REN# R699 20_0402_5% MC_PW REN#2 1 G SD_PW REN# 1 2 R701 0_0402_5%
SD signal
C885
1 C886 1 C887 1
R714 150K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z @ 2 2 2 0.1U_0402_16V4Z
D
S
Q55 2N7002_SOT23
+3VS
4 IN 1 Socket Push Type(New) 3
JP30
xD PU and PD. Close to Socket
33
XD-VCC
xDDATA0/SDDAT1 xDDATA1/MSBS xDDATA2/MSDATA0 xDDATA3/MSDADTA3 xDDATA4/SDDAT3 xDDATA5/MSDADTA2 xDDATA6/MSDATAT1 xDDATA7/SDDAT0
8 9 26 27 28 30 31 32
XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7
xDSMW E#/SDCLK XMDAT5B/XDW PO# xDALE/SDCMD xDSMCD# XMDAT6B_XDBSY# xDSMRE#/MSCLK XMDAT7B_XDCe# xDCLE/SDDAT2
6 7 5 34 1 2 3 4
XD-WE XD-WP XD-ALE XD-CD XD-R/B XD-RE XD-CE XD-CLE
13 22
4IN1 GND 4IN1 GND
+3V_MCVCC
Reserve for SD,MS CLK. Close to Socket
MR510QFA1_LQFP128_14X14
+3V_MCVCC U47
1 2 3 4
R702
xd signal 1 1 1 1 1
Memory Card Power Switch
+3V_MCVCC
43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2 43K_0402_5% 2
R715 R717 R718 R719 R720
2
+3VS
CLK_48M_SD 14
MFUN4 w/o eerom pull low 4
1 C881
1 R722 43K_0402_5% 2
90 95 96
MSINS# MSPWREN#/SMPWREN# MSBS/SMDATA1
1 C880
4.7U_0805_10V4Z
VF
3
R726 100_0402_5% PCI_AD16 1 2 10K_0402_5% 2 R727 1
74 60 48 27
127 R696 1 126
1 C879
1
@ 15P_0402_50V8J
PMPWR_ENI# PMPWR_OUT
2
1 C878
2
2
C884
125 120 101 81 69 52 42 29 11 113 10
1 C877
1
2
1
C883
PMPWR_VCC VCC8 VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 NC24 VCC_SD2 VCC_SD1
1 C876
SMRE# SMWE# BSY# CE#
1 2
1
2
R698 @ 10_0402_5%
2
R695 @ 10_0402_5%
MR510
1 C875
XD XD XD XD
3
1
CLK_48M_SD
1
CLK_PCI_card
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
0.1U_0402_16V4Z
-c c
PCI_CBE#[0..3]
18 PCI_CBE#[0..3]
18 19 20 22 23 24 25 26 33 34 35 36 39 40 46 47 65 66 67 68 70 71 72 73 82 83 84 85 86 87 88 91
C874
-c o
PCI_AD[0..31]
18 PCI_AD[0..31]
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
1
0.1U_0402_16V4Z
8.2K_0402_5% 1 2
1
0.1U_0402_16V4Z
xDSMW E#/SDCLK 1 C888
2 10P_0402_50V8K
xDSMRE#/MSCLK 1 C889
2 10P_0402_50V8K
37 38
4 IN 1 CONN
SD-VCC MS-VCC
23 14
SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-CMD SD-CD-SW
24 25 29 10 11 12 36
xDSMW E#/SDCLK xDDATA7/SDDAT0 xDDATA0/SDDAT1 xDCLE/SDDAT2 xDDATA4/SDDAT3 xDALE/SDCMD SDCD#
SD-WP-SW
35
SMW PD#/SDW P
MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-INS MS-BS
15 19 20 18 16 17 21
xDSMRE#/MSCLK xDDATA2/MSDATA0 xDDATA6/MSDATAT1 xDDATA5/MSDADTA2 xDDATA3/MSDADTA3 MS_INS# xDDATA1/MSBS
+3V_MCVCC
4IN1 GND 4IN1 GND
4
TAITW _R015-312-LM CONN@
MFUN6 MFUN7
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/1/15
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
R5C833 5IN1 & IEEE1394 Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
23
of
44
4
+3VALW
+3V_LAN
4.7U_0805_10V4Z 2
+VSB
@
1 2 3 4
1
2 13VLAN_GATE R508 200K_0402_5%
1
1
D
2 G
SYSON#
1
C29
1
C58
1
C89
C111
2
1
C28
Q18 MMJT9435T1G_SOT223
C634 @ 0.1U_0603_25V7K
C447
R23
1
2 1_1206_1%
R24
1
2 1_1206_1%
C30
0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z
LAN_REGCTL25 1
4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
D
26,27,34
+3V_LAN 1
AO4468_SO8 @
2
+2.5V_LAN
1
1
1
C52
1
C449
Q6 MMJT9435T1G_SOT223
C110
C31
10U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
3
Q40 S @ 2N7002_SOT23
1
LAN BCM5787M C26
0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z
LAN_REGCTL12 1
20mil
1
60mil +3V_LAN_R 1 C25
3
S S S G
3
1
D D D D
2 4
8 7 6 5
+3V_LAN
60mil
U35 C24
3
+1.2V_LAN
60mil
2 4
5
1
1
C448
1
C80
1
1
C42
C91
1
1
C112
1
C39
1
C457
1
C450
1
C41
D
C464
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 2 2 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3V_LAN +3V_LAN
U3 SPROM_DOUT SPROM_CLK
1 2 3 4
-c c
SPROM_CS
R71
+3V_LAN
2 1 LAN_PME# R514 100K_0402_5%
2 10K_0402_5% @ 1 2 1K_0402_5%
1
+3VS
R88
+3V_LAN
R89
2 1K_0402_5%
1
20 PCIE_ITX_C_PRX_P3 20 PCIE_PTX_C_IRX_N3
C38
20 PCIE_PTX_C_IRX_P3
C37
2 0.1U_0402_16V7K
1
2 0.1U_0402_16V7K
1
R67
6,18,20,22,28 PLT_RST#
1
R66 1 R511 1
20,26,27 ICH_PCIE_WAKE# 28 EC_PME#
31
PCIE_PTX_IRX_N3
25
S
ENERGY_DET GPHY_PLLVDD
LINKLED SPD100LED SPD1000LED TRAFFICLED
SCLK(EECLK) SI SO(EEDATA) CS
26
PCIE_RXD_P
REGCTL12 REGCTL25 RDAC
PCIE_TXD_N
XTALVDD VDDIO VDDIO VDDIO VDDIO VDDIO
10 12
LAN_SMBCLK
58
SMB_CLK
LAN_SMBDATA
57
SMB_DATA
PERST WAKE
VDDP VDDP
4
GPIO_0(SERIAL_DO)
7
GPIO_1(SERIAL_DI)
8
GPIO_2
9
UART_MODE
LAN_XTALI
21
XTALI
XTALO
22
XTALO
R48 200_0402_1%
16
2
24
1
1
2
2 1 67 66
65 63 64 62
14 18 37
PCIE_TXD_P
0_0402_5% LAN_PME# 0_0402_5%
pull-up to +3V on South Bridge Side
Y2
41 40 42 43 48 47 49 50
LAN_MIDI0LAN_MIDI0+ LAN_MIDI1LAN_MIDI1+ LAN_MIDI2LAN_MIDI2+ LAN_MIDI3LAN_MIDI3+
LAN_MIDI0LAN_MIDI0+ LAN_MIDI1LAN_MIDI1+ LAN_MIDI2LAN_MIDI2+ LAN_MIDI3LAN_MIDI3+
R748 1 R747 1
SPROM_CLK SPROM_DIN SPROM_DOUT SPROM_CS
25 25 25 25 25 25 25 25
0_0402_5% 2
LAN_LINK# 25
0_0402_5% 2
R78 R77
REG_GND
PCIE_GND
VDDC VDDC VDDC VDDC VDDC VDDC
BIASVDD PCIE_PLLVDD PCIE_VDD PCIE_VDD AVDD AVDD AVDD
AVDDL AVDDL AVDDL AVDDL EXPOSED PAD
23 6 15 19 56 61
LAN_REGCTL12 LAN_REGCTL25 LAN_RDAC 1 R62 1.24K_0402_1% +LAN_XTALVDD
1 2 3 4
LAN_ACTIVITY# 25
1
@ 2 4.7K_0402_5%
1
2 4.7K_0402_5%
+1.2V_LAN
36 30 27 33
+LAN_BIASVDD +LAN_PCIEPLLVDD +LAN_PCIEVDD
38 45 52
+LAN_AVDD
39 44 46 51 69
+LAN_AVDDL
25MHZ_20P
A0 A1 A2 GND
8 7 6 5
VCC WP SCL SDA
SPROM_WP SPROM_CLK SPROM_DOUT
1
1 2 BLM18AG601SN1D_0603
20mil +2.5V_LAN
+LAN_PCIEPLLVDD 1 1 C452 C451
20mil +LAN_PCIEVDD 1 1 C455 C454
L8 1 2 BLM18AG601SN1D_0603
0.1U_0402_16V4Z 2 +2.5V_LAN
20mil
C53 0.1U_0402_16V4Z
+LAN_AVDD 1 C107
2
C88
0.1U_0402_16V4Z 2
1
+LAN_AVDDL 1 C95
C463
0.1U_0402_16V4Z 2
C34 27P_0402_50V8J 2
1
0.1U_0402_16V4Z 2
3
B
L36 1 2 BLM18AG601SN1D_0603
+2.5V_LAN
L37 1 2 BLM18AG601SN1D_0603
+1.2V_LAN
L35 1 2 BLM18AG601SN1D_0603
+1.2V_LAN A
2 4.7U_0805_10V4Z
Compal Electronics, Inc.
Compal Secret Data 2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
+1.2V_LAN
2 4.7U_0805_10V4Z
20mil
A
L34 1 2 BLM18AG601SN1D_0603
2 0.1U_0402_16V4Z
+LAN_GPHYPLLVDD 1 1 C453 C456
5
+1.2V_LAN
2 4.7U_0805_10V4Z
20mil
2006/12/25
L33 1 2 BLM18AG601SN1D_0603
0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z
1
Issued Date
R740 4.7K_0402_5% @
Unpop if use Flash
L7
BCM5787MKML_QFN68
Security Classification
C
Unpop if use Flash
C43 0.1U_0402_16V4Z
20mil
+3V_LAN
R128 R102 4.7K_0402_5% 4.7K_0402_5%
Change to SA000003510(AT24C64)
2 LAN_XTALO
C35 27P_0402_50V8J
0.1U_0402_16V4Z 2 U4
AT24C64AN-10SU-2.7_SO8
2
5 13 20 34 55 60
C136
1K for BCM5906M
20mil
1
+2.5V_LAN
+3V_LAN +3V_LAN 1
2
+3V_LAN
17 68
2
Use Flash if support ASF2.0
PCIE_RXD_N
1
LAN_SMBCLK
Q42 @ 2N7002_SOT23
VAUX_PRSNT
0_0402_5% LAN_RESET#
SPROM_WP
S
D D
3
35
PCIE_ITX_C_PRX_P3
PCIE_PTX_IRX_P3
R64 4.7K_0402_5% 1 2 +3V_LAN
2 G 1
14,20,26,27 ICH_SMBCLK
54
VMAIN_PRSNT
2 @ 2
LAN_SMBDATA
+3V_LAN
53
LOW PWR
VF
2 G
R130 4.7K_0402_5% 1 2 +3V_LAN
Q41 @ 2N7002_SOT23
3
2
+3V_LAN
3
CLKREQ
PCIE_ITX_C_PRX_N3 32
20 PCIE_ITX_C_PRX_N3
1
PCIE_REFCLK_P
11
TRD0_N TRD0_P TRD1_N TRD1_P TRD2_N TRD2_P TRD3_N TRD3_P
-c o
+LAN_GPHYPLLVDD
14,20,26,27 ICH_SMBDATA
29
59
28 ENERGY_DET
B
PCIE_REFCLK_N
2
1
28 LAN_LOWPWR
C
0_0402_5% 2
28
C114 0.1U_0402_16V4Z @
1
R741
+3V_LAN 1
1
14 CLK_PCIE_LAN
SPROM_DIN
8 7 6 5
SO GND VCC WP#
AT45DB011B-SU_SO8 @
U2 14 CLK_PCIE_LAN#
SI SCK RESET# CS#
2
2 0_1206_5%
1
1 R19
2
+3VALW
2
Title
LAN BCM5787M Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
24
of
44
5
4
3
2
3
2
2
LAN_ACTIVITY#
3
LAN_LINK#
LAN BCM5787M
1
1
@ PSOT24C-LF-T7_SOT23-3 D31
1
@ PSOT24C-LF-T7_SOT23-3 D30 D
D
1 +2.5V_LAN
2
+3V_LAN
C
24 24
LAN_MIDI0+ LAN_MIDI0-
LAN_MIDI0+ LAN_MIDI0-
24 24
LAN_MIDI1+ LAN_MIDI1-
LAN_MIDI1+ LAN_MIDI1-
24 24
LAN_MIDI2+ LAN_MIDI2-
LAN_MIDI2+ LAN_MIDI2-
24 24
LAN_MIDI3+ LAN_MIDI3-
LAN_MIDI3+ LAN_MIDI3-
24 LAN_ACTIVITY#
TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4-
MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4-
24 23 22 21 20 19 18 17 16 15 14 13
RJ45_MIDI0+ RJ45_MIDI0RJ45_MIDI1+ RJ45_MIDI1RJ45_MIDI2+ RJ45_MIDI2RJ45_MIDI3+ RJ45_MIDI3-
1
C138
2
Pop for BCM5906
1
C121
1
C152
1
0.1U_0402_16V4Z
2
2
PR3-
RJ45_MIDI2+
4
PR3+
RJ45_MIDI1+
3
PR2+
RJ45_MIDI0-
2
PR1-
RJ45_MIDI0+
1
PR1+
9
2
15
SHLD2
14
SHLD1
13
Guide Pin
C
Green LEDGreen LED+ FOX_JM36113-L2R8-7F CONN@ 2
1
C151 220P_0402_50V7K
R153 75_0402_1%
RJ45_GND
1
1 C108
2
40mil
VF
LANGND 1
2
C154 1000P_1206_2KV7K
RJ45_GND
0.1U_0402_16V4Z
Place close to TCT pin
B
PR2-
5
10
16
SHLD1
1
1
2
R132 75_0402_1%
C106
6
RJ45_MIDI2-
2
1 C134 0.1U_0402_16V4Z 2 @
2
1 C146 0.1U_0402_16V4Z 2 @
0.1U_0402_16V4Z
RJ45_MIDI1-
1 1K_0402_5%
SHLD2 PR4PR4+
R115 75_0402_1%
2
1
1
0.1U_0402_16V4Z
Amber LED-
7
1
1
-c o R101 75_0402_1%
2
2
1
1 2
2
R152 49.9_0402_1% @
8
RJ45_MIDI3+
2 R154
+3V_LAN
R118 49.9_0402_1% @
11
LAN_LINK#
24 LAN_LINK#
350uH_GSL5009LF R129 49.9_0402_1% R148 @ 49.9_0402_1% @
1 1K_0402_5%
RJ45_MIDI3-
T4
1 2 3 4 5 6 7 8 9 10 11 12
2 R70 LAN_ACTIVITY#
-c c
1
L12 BLM18AG601SN1D_0603
2
C94 220P_0402_50V7K JP18 12 Amber LED+
2
40mil
C96 4.7U_0805_10V4Z
0.1U_0402_16V4Z
LAN_ACTIVITY#
1 2 C186 220P_0402_50V7K @
LAN_LINK#
1 2 C187 220P_0402_50V7K @
B
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2006/12/25
Issued Date
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
LAN Magnetic & RJ45/RJ11 Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
25
of
44
A
B
C
D
E
For Wireless LAN +3VS_WL
C906 10U_0805_6.3V6M
1
1
2
2
+1.5VS
1
C139 4.7U_0805_10V4Z
2
1
C480 0.1U_0402_16V4Z
2
+3VAux_WL
1
C147 4.7U_0805_10V4Z
2
1
C140 0.1U_0402_16V4Z
2
1
C133 0.1U_0402_16V4Z
2
1
C137 0.1U_0402_16V4Z
2
C907 10U_0805_6.3V6M
1
1
20,24,27 ICH_PCIE_WAKE# 27 WLAN_BT_DATA 27 WLAN_BT_CLK 14 MINI1_CLKREQ# 14 CLK_PCIE_MINI1# 14 CLK_PCIE_MINI1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
20 PCIE_PTX_C_IRX_N4 20 PCIE_PTX_C_IRX_P4 20 PCIE_ITX_C_PRX_N4 20 PCIE_ITX_C_PRX_P4 +3VS_WL
E51TXD_P80DATA E51RXD_P80CLK
28 E51TXD_P80DATA 28 E51RXD_P80CLK
JP21 2 4 6 8 10 12 14 16
17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
+3VS_WL +1.5VS
LPC Debug Port +5VS WL_OFF# PLT_RST_BUF#
53 54 55 56
For MINICARD Port80 Debug
+3VS
WL_OFF# 28 PLT_RST_BUF# 18
+3VAux_WL ICH_SMBCLK ICH_SMBDATA
JP40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ICH_SMBCLK 14,20,24,27 ICH_SMBDATA 14,20,24,27 USB20_N7 20 USB20_P7 20
(MINI1_LED#) MINI1_LED# 29
(9~16mA)
G1 G2 G3 G3
2
1 3 5 7 9 11 13 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-c c
R755 @ 0_0402_5% ICH_PCIE_WAKE# 1 2 WLAN_BT_DATA WLAN_BT_CLK
FOX_AS0B226-S99N-7F CONN@
CLK_14M_SIO LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ#1 PCI_RST# 1 2 R690 @ 0_0402_5% SIRQ
CLK_14M_Dbg 14 LPC_AD0 19,28 LPC_AD1 19,28 LPC_AD2 19,28 LPC_AD3 19,28 LPC_FRAME# 19,28 LPC_DRQ#1 19 PCI_RST# 18,23,27
CLK_PCI_Dbg
2
CLK_PCI_Dbg 14 SERIRQ 20,28
close to RAM Door
@ ACES_85201-2005
Primary Power (mA) Peak
Normal
+3VS
1000
750
+3V
330
250
+1.5VS
500
375
+3V
Auxiliary Power (mA) Normal
+3VS
250 (wake enable)
+3V
5 (Not wake enable)
@
2 0_0805_5% 2 0_0805_5%
+3VAux_WL 20 mil
-c o
+3VS
Mini Card Power Rating Power
1 R756 1 R757
1 R758 1 R759 @
2 0_1206_5% 2 0_1206_5%
+3VS_WL
40 mil
To USB/B Connector
JP11 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12
VF
3
GND1 GND2
3
+5VALW
+5VALW USB20_N4 USB20_P4 USB20_N6 USB20_P6
USB20_N4 20 USB20_P4 20 USB20_N6 20 USB20_P6 20 SYSON#
C368
1
4.7U_0805_10V4Z 2
24,27,34
13 14
ACES_87213-1200G CONN@
4
4
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
MINI CARD (WLAN & TV-Tuner) Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
26
of
44
A
B
C
D
E
New Card Power Switch
New Card Socket (Left/TOP)
U16
CPUSB# CPPE# STBY# SHDN# SYSRST#
OC#
1
C387
C362
1
+3VS
TPS2231PWPR_PWP24
USB20_N1 USB20_P1
CP_USB#
10U_0805_10V4Z 2 2 0.1U_0402_16V4Z
2
1
D
3
S
1
2
2
B
1
A
NC7SZ32P5X_NL_SC70-5 Q15 2N7002_SOT23
10U_0805_10V4Z 2
PERST1#
+3VS_CARD
+3VS
R336 10K_0402_5%
1
C365
20 20
C401
20,24,26 ICH_PCIE_WAKE# +3VALW_CARD RCLKEN1 PERST1#
+1.5VS
10U_0805_10V4Z 2
1
CLKREQ1# CP_PE#
20 CP_PE# 14 CLK_PCIE_CARD# 14 CLK_PCIE_CARD
C357 0.1U_0402_16V4Z
20 PCIE_PTX_C_IRX_N1 20 PCIE_PTX_C_IRX_P1
U15
4
Y
20 PCIE_ITX_C_PRX_N1 20 PCIE_ITX_C_PRX_P1
EXP_CLKREQ# 14
-c o
1
1
23 22 9
2 C363
10U_0805_10V4Z 2
C412
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
14,20,24,26 ICH_SMBCLK 14,20,24,26 ICH_SMBDATA +1.5VS_CARD
RCLKEN1 2 G
2
C367
+1.5VS_CARD
CLKREQ1#
+3V
1
10U_0805_10V4Z 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R338 10K_0402_5%
+3VS
1
C366
+3VS
1 10 12 13 24
11
1
10U_0805_10V4Z 2
40mil
NC1 NC2 NC3 NC4 NC5
RCLKEN PERST#
16 17
+3VALW_CARD
JP9
Imax = 0.75A
-c c
14 15 4 3 2
1.5Vout1 1.5Vout2
C390
40mil
Imax = 1.35A
5
1.5Vin1 1.5Vin2
GND
23,28,30,34,40 SUSP# 28,34,40 SYSON 18,23,26 PCI_RST#
20
Imax = 0.275A
+3VS_CARD
G Vcc
2 100K_0402_5% CP_USB# 2 100K_0402_5% CP_PE# SUSP# SYSON PCI_RST#
R341 1 R340 1
+3V
Aux_out
3.3Vaux_in
18 19
+1.5VS
7 8
GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND
27 28
3
21
+3V
3.3Vout1 3.3Vout2
+1.5VS_CARD
1
1
3.3Vin1 3.3Vin2
+3VS_CARD
1
5 6
+3VS
+3VALW_CARD
60mils
GND GND
1
GND GND
29 30
FOX_1CH4110C_LT CONN@
2
USB CONN. (Stack-up Type)
Bluetooth Conn.
+USB_VCCA
+
3 G
2
1
1U_0603_10V4Z 2 Q32 AO3413_SOT23-3
20 20
C597
VF
W=40mils
+BT_VCC
20 20
C598
2 1
Q34 2N7002_SOT23
3
S
R742 @ 22 1 G 10K_0402_5%
20 20
4
USB20_P5 USB20_N5
26 WLAN_BT_DATA 26 WLAN_BT_CLK
1 GND 2 3 4 5 6 7 8 GND
4
+USB_VCCA
2
I/O
I/O
USB20_N0_R
3
JP23 1 2 3 4
R736 0_0402_5% USB20_N0 1 2 USB20_N0_R USB20_P0 1 2 USB20_P0_R
5 6 7 8
VCC D1D1+ GND
9 10
GND1 GND2
0_0402_5%
VCC D0D0+ GND
D11 1 USB20_P2_R
2
GND
VCC
I/O
I/O
4
3
+USB_VCCA USB20_N2_R
3
@ PRTR5V0U2X_SOT143
SUYIN_020122MR008S505ZL CONN@ +3V
80mil
D
+5VALW
@ Q51 2N7002_SOT23
+USB_VCCA U6
S
C171
1
JP12
1 2 3 4 5 6 7 8
VCC
@ PRTR5V0U2X_SOT143
R733 0_0402_5% USB20_N2 1 2 USB20_N2_R USB20_P2 1 2 USB20_P2_R R734 0_0402_5%
BT_LED# 28,29
+BT_VCC
USB20_P0_R
470P_0402_50V7K 2 2 470P_0402_50V7K
R735
GND
C167
D
2 G
+BT_VCC
USB20_N0 USB20_P0
2
1
C164
R492 300_0603_5%
4.7U_0805_10V4Z 2 0.1U_0402_16V4Z
1
C590
1
3
0.1U_0402_16V4Z
USB20_N2 USB20_P2
1
2 10K_0402_5%
D
1 R482
S
0.1U_0402_16V4Z BT_ON#
150U_Y_6.3VM
C600
1
1
1
C592
28
D12 1
1
C173
3
W=80mils
+USB_VCCA
+3VS
1 2 3 4
GND IN IN EN#
OUT OUT OUT FLG
8 7 6 5
R164 100K_0402_5% 2
+3VALW
R162 1
2 10K_0402_5%
R167 1
2 10K_0402_5%
USB_OC#0 20
TPS2061DRG4_SO8 4.7U_0805_10V4Z 2
9
C169
1
C161
USB_OC#2 20
1
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2
24,26,34 SYSON#
4
10
ACES_87213-0800G CONN@
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
NEW CARD & USB Connector Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
27
of
44
4
3
2
1
For EC Tools
+3VALW L46
C557
2 2 0.1U_0402_16V4Z
C536 1000P_0402_50V7K 1 1
C544 1000P_0402_50V7K
20 PM_SLP_S3# 20 PM_SLP_S5# 20 EC_SMI# 29 LID_SW # 23,27,30,34,40 SUSP# 20 PBTN_OUT# 24 EC_PME# 20 EC_THERM# 33 FAN_SPEED1 27 BT_ON#
PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW # SUSP# PBTN_OUT# EC_PME#
67
9 22 33 96 111 125
AVCC
68 70 71 72
DAC_BRIG EN_DFAN1 IREF
PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F
83 84 85 86 87 88
EC_MUTE LAN_LOW PW R W L_LED# BT_LED# TP_CLK TP_DATA
SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0
97 98 99 109
3S/4S# 65W /90W # SBPW R_EN
SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS#
119 120 126 128
EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS#/FSEL#
CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59
73 74 89 90 91 92 93 95 121 127
EC_RCIRRX
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11
100 101 102 103 104 105 106 107 108
PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7
110 112 114 115 116 117 118
V18R
124
DA Output
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82
KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49
77 78 79 80
SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47
PS2 Interface
BATT_OVP 37 ADP_I 37
ENERGY_DET
POUT
FAN_SPEED1 BT_ON# E51TXD_P80DATA E51RXD_P80CLK ON/OFF PW R_SUSP_LED NUM_LED#
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
EC_CRY1 EC_CRY2
122 123
SPI Flash ROM
GPIO
SM Bus
PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
GPI
XCLK1 XCLK0
11 24 35 94 113 A
KB926QFA1_LQFP128_14X14 L48 ECAGND 2 1 FBM-L11-160808-800LMT_0603
2007/1/15
Issued Date
R449
3
C
LAN_LOW PW R 24
BT_LED#
27,29
TP_CLK 29 TP_DATA 29
3S/4S# 37 65W /90W # 37 SBPW R_EN 34
Analog Board ID definition, Please see page 3.
EC_SI_SPI_SO 29 EC_SO_SPI_SI 29 EC_SPICLK 29 EC_SPICS#/FSEL# 29
+3VALW
R465 @ 100K_0402_5%
Ra ENCODER_PULSE 32 FSTCHG 37 BATT_GRN_LED# 29 CAPS_LED# 29 BATT_AMB_LED# 29 PW R_LED 29 SYSON 27,34,40 VR_ON 42 ACIN 20,38 EC_RSMRST# 20 EC_LID_OUT# 20 EC_ON 30,37 EC_SW I# 20 EC_PW ROK 30 BKOFF# 16 W L_OFF# 26 MEDIA_LED# 29 CALIBRATE 37
EC_PW ROK BKOFF# W L_OFF# MEDIA_LED#
IDE_LED#
AD_BID0
Rb
C565
18K_0402_5% 2 0.1U_0402_16V4Z
EC_CRY1 C538
B
EC_CRY2
1
1
10P_0402_50V8J 2
C540
10P_0402_50V8J 2
X2 32.768KHZ_12.5P_MC-306
For KB926 C0 reversion
C891 2
100P_0402_50V8J
C892 BATT_TEMP 1 2
100P_0402_50V8J
C893 1 2
100P_0402_50V8J
ACIN
2 0.1U_0402_16V4Z
BATT_OVP
Deciphered Date
1
R464
PM_SLP_S4# 20 ENBKL 8,15 EAPD 31 SATA_LED# 19 5IN1_LED# 23 IDE_LED# 22 ARCADE# 29
ENBKL EAPD SATA_LED#
C908
1 100K_0402_5%
W L_LED# 29
EC_LID_OUT# EC_ON
1
2
EC_MUTE 32
1
A
Compal Electronics, Inc. 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
+3VALW 65W /90W #
Compal Secret Data
Security Classification
5
24
DAC_BRIG 16 EN_DFAN1 33 IREF 37 CHGSEL 37
FSTCHG BATT_GRN_LED# CAPS_LED# BATT_AMB_LED# PW R_LED SYSON VR_ON
@
2 4.7K_0402_5%
42
SPI Device Interface
GND GND GND GND GND
30 ON/OFF 29 PW R_SUSP_LED 29 NUM_LED#
AD_BID0
1 R521
1
EC_SMB_CK1 2 4.7K_0402_5% EC_SMB_DA1 2 4.7K_0402_5% EC_SMB_CK2 2 4.7K_0402_5% EC_SMB_DA2 2 4.7K_0402_5%
DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F
3S/4S# BATT_TEMP 38
NC
1 R460 1 R458 1 R456 1 R454
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
AD
VF
B
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
BATT_TEMP BATT_OVP
2
15,29,38 15,29,38 4 4
63 64 65 66 75 76
2
2 TP_CLK 4.7K_0402_5% 2 TP_DATA 4.7K_0402_5%
BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43
PWM Output
ACES_85205-0400 @
INVT_PW M 16 BEEP# 31 ENCODER_DIR 32 ACOFF 35,37 ECAGND 2 1 C567 0.01U_0402_16V7K
1
+5VS
PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D
INVT_PW M BEEP#
2
2 1 EC_RCIRRX
12 13 37 20 38
21 23 26 27
INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13
D
E51RXD_P80CLK E51TXD_P80DATA
1
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17
R466 10K_0402_5%
+5VALW
EC_SCI#
GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC
E51RXD_P80CLK 26 E51TXD_P80DATA 26
+3VALW
1 2 3 4
1 2 3 4
-c c
20 EC_SCI# 20 PM_CLKRUN#
+3VALW
1 R448 1 R444
E51RXD_P80CLK E51TXD_P80DATA
JP35
-c o
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
6,18,20,22,24 PLT_RST#
2 1 R441 47K_0402_5% 2 1 C548 0.1U_0402_16V4Z
C
KSO[0..17] 29
0.1U_0402_16V4Z
AGND
1 @ 33_0402_5%
1 2 3 4 5 7 8 10
69
19 EC_GA20 19 EC_KBRST# 20,26 SERIRQ 19,26 LPC_FRAME# 19,26 LPC_AD3 19,26 LPC_AD2 19,26 LPC_AD1 19,26 LPC_AD0
14 CLK_PCI_LPC
+3VALW
1 2 3 4
1 2 3 4
ECAGND
VCC VCC VCC VCC VCC VCC
U28
R447 2
29
ACES_85205-0400 @
D
C555 @ 22P_0402_50V8J 2 1
KSO[0..17]
C559
2
KSI[0..7]
4
2 2 0.1U_0402_16V4Z
EC_PME# 2 10K_0402_5% @
JP10 KSI[0..7]
1
IN
C552
1 R459
+3VALW
1 2+EC_VCCA 2 FBM-L11-160808-800LMT_0603
0.1U_0402_16V4Z 1 2
OUT
0.1U_0402_16V4Z 1 C537 1
C560
NC
1 +3VALW
3
5
2
Title
EC ENE KB926 Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet 1
28
of
44
+3VALW
reserve for debug +5VALW
1 3 7 4
1
2
R738 @ 1K_0402_5% R442
CE# WP# HOLD# VSS
VDD SCK SI SO
8 6 5 2
SPICLK EC_SO_SPI_SI_R EC_SI_SPI_SO_R JP6 +5VS
@ MX25L8005M2C-15G_SOP8 C551 1
2 0.1U_0402_16V4Z
28 28
100K_0402_5% 8 7 6 5
15,28,38 EC_SMB_CK1 15,28,38 EC_SMB_DA1
TP_DATA TP_CLK
6 5 4 3 2 1
2
U26
TP_DATA TP_CLK
VCC WP SCL SDA
A0 A1 A2 GND
1 2 3 4
U27 EC_SPICS#/FSEL#
28 EC_SPICS#/FSEL#
AT24C16AN-10SI-2.7_SO8
2 R739
1
1
1K_0402_5%
1 3 7 4
CE# WP# HOLD# VSS
C130 VDD SCK SI SO
8 6 5 2
SPICLK R443 1 EC_SO_SPI_SI_R R445 1 EC_SI_SPI_SO_R R438 1
2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
EC_SPICLK 28 EC_SO_SPI_SI 28 EC_SI_SPI_SO 28
100P_0402_50V8J
1
1
2
2
+5VS
TP_CLK 2
ENE suggestion SPI Frequency over 66MHz SST: 50MHz MXIC: 70MHz ST: 40MHz
C149 D9 @ PSOT24C_SOT23
0.1U_0402_16V4Z
KSI[0..7]
INT_KBD Conn.
KSI[0..7]
KSO[0..17]
-c c
1
2
ACES_85201-0605 CONN@
TP_DATA
MX25L8005M2C-15G_SOP8 R437 100K_0402_5%
C129 100P_0402_50V8J
3
2 0.1U_0402_16V4Z
1
C550 1
To TP/B Conn.
U45 EC_SPICS#/FSEL#
+3VALW
+5VALW
28
KSO[0..17] 28
JP5 G2 G1
To BTN/B Conn.
28 27
+3VS
17 18
C74
1
2
100P_0402_50V8J
KSO7
C66
1
2
100P_0402_50V8J
KSO14
C73
1
2
100P_0402_50V8J
KSO6
C65
1
2
100P_0402_50V8J
KSO13
C72
1
2
100P_0402_50V8J
KSO5
C64
1
2
100P_0402_50V8J
KSO12
C71
1
2
100P_0402_50V8J
KSO4
C63
1
2
100P_0402_50V8J
KSI0
C75
1
2
100P_0402_50V8J
KSO3
C62
1
2
100P_0402_50V8J
KSO11
C70
1
2
100P_0402_50V8J
KSI4
C54
1
2
100P_0402_50V8J
KSO10
C69
1
2
100P_0402_50V8J
KSO2
C61
1
2
100P_0402_50V8J
KSI1
C76
1
2
100P_0402_50V8J
KSO1
C60
1
2
100P_0402_50V8J
KSI2
C77
1
2
100P_0402_50V8J
KSO0
C59
1
2
100P_0402_50V8J
KSO9
C68
1
2
100P_0402_50V8J
KSI5
C55
1
2
100P_0402_50V8J
KSI3
C78
1
2
100P_0402_50V8J
KSI6
C56
1
2
100P_0402_50V8J
R358 300_0402_5% 1 2 R495 1 2 453_0402_1%
LED1 3 4
C57
1
2
1
PWR_LED#
A
+5VALW
KSI7
100P_0402_50V8J
YG
+5VS
2
G17 G18
C21
PWR_LED#
0.1U_0402_16V4Z
ON/OFFBTN# 30
WL_R_LED# BT_LED# PWR_SUSP_LED# KSO0 KSI1 KSI2 KSI3 KSI4
1 R16
2 +3VALW 100K_0402_5%
D6 2
ARCADE_BTN# 1
3
BT_LED# 27,28
2
PWR_SUSP_LED#
100P_0402_50V8J
28
ARCADE# 28 51ON#
51ON#
30,35
DAN202UT106_SC70-3
+3VALW
C22 PWR_LED#
0.1U_0402_16V4Z
KSI5 KSO0 ARCADE_BTN#
PWR_LED
PWR_SUSP_LED#
+5VS +3VALW LID_SW# 28
NUM_LED# 28 CAPS_LED# 28 MEDIA_LED# 28
D
2 G S Q4 2N7002_SOT23
KSO0 WL_BTN#
KSI2
BT_BTN#
KSI3
EMAIL_BTN#
KSI4
IE_BTN#
KSI5
E-KEY_BTN#
S Q37 2N7002_SOT23
@ R584 WL_R_LED#
1
ACES_85201-1205 CONN@
KSI1
D
2 G
28 PWR_SUSP_LED 3
1 2 3 4 5 6 7 8 9 10 11 12
VF
KSO15
1
+5VALW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
JP36
CONN@
C67
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ACES_85201-16051 CONN@
ACES_85201-26051
1 R669
PWR_LED#
C895 1
2 @ 100P_0402_50V8J
ON/OFFBTN#
C896 1
2 @ 100P_0402_50V8J
WL_R_LED#
C898 1
2 @ 100P_0402_50V8J
BT_LED#
C899 1
2 @ 100P_0402_50V8J
PWR_SUSP_LED#C900 1
2 @ 100P_0402_50V8J
2 0_0402_5% 2 0_0402_5%
WL_LED# 28 MINI1_LED# 26
FOR EMI LID_SW#
C897 1
2 @ 100P_0402_50V8J
ARCADE_BTN# C901 1
2 @ 100P_0402_50V8J
NUM_LED#
C902 1
2 @ 100P_0402_50V8J
CAPS_LED#
C903 1
2 @ 100P_0402_50V8J
MEDIA_LED#
C904 1
2 @ 100P_0402_50V8J
PWR_LED# PWR_SUSP_LED#
HT-297DQ/GQ_AMB/YG_0603
+5VALW
R357 300_0402_5% 1 2 R494 1 2 453_0402_1%
LED2 3
1
BATT_GRN_LED#
BATT_GRN_LED# 28
4
2
BATT_AMB_LED#
HT-297DQ/GQ_AMB/YG_0603
BATT_AMB_LED# 28
Compal Electronics, Inc.
Compal Secret Data
Security Classification Issued Date
A
+5VALW
YG
KSO8
+5VS
+5VS
JP2
1
(Right)
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1
KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7
-c o
(Left)
2007/1/15
Deciphered Date
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
BIOS, I/O Port & K/B Connector Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet
29
of
44
A
B
C
D
E
Power Button ON/OFF switch
HDA MDC Conn.
TOP Side 1
2 @ 10K_0603_5% 2 @ 10K_0603_5%
R749 1 R750
+3VALW +3V
Bottom Side 2
1
R434 100K_0402_5% 1
D27 2
ON/OFF
1
51ON#
3
51ON#
19 HDA_SYNC_MDC 19 HDA_SDIN1 19 HDA_RST_MDC#
28 29,35
1 R117
HDA_SDIN1_MDC 2 39_0402_5%
1 3 5 7 9 11
GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK
2 4 6 8 10 12
1 R522
2
2 0_0402_5%
1
C127 1U_0603_10V4Z
+3V HDA_BITCLK_MDC 19 1
ON/OFFBTN#
29 ON/OFFBTN#
19 HDA_SDOUT_MDC
1
20mil
JP17
DAN202UT106_SC70-3
2
ACES_88018-124G CONN@
13 14 15 16 17 18
1 C545
D26
2
GND GND GND GND GND GND
R509 0_0402_5% 1
C128
1
D Q27
2 G 3
S 2N7002_SOT23
10K_0402_5%
Power ON Circuit +3VS
O
6
O
9
O
8
VS_ON
+RTCVCC
41
For +VCCP/+1.05VS
BAS40-04_SOT23-3 1
11
I
0.1U_0402_16V4Z
Change BATT1 P/N : SP093PA0200 (Panasonic) SP093MX0000 (MAXELL)
U14F SN74LVC14APWLE_TSSOP14
P
14
U14E SN74LVC14APWLE_TSSOP14 O
10
13
I
O
12
1 R761 PM@
2 0_0402_5%
VGA_ON
15
7
7
2
2
+CHGRTC C20
+3VALW
P
14
D16
D5
2 0.1U_0402_16V4Z
G
R307 PM@ 200K_0402_5% SUSP# 1 2 1
14
C319
4
SUSP#
RB751V_SOD323 2 PM@ C330 PM@ 0.1U_0402_16V4Z 1
1 R762
2 @ 0_0402_5%
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
3
R15 1K_0402_5%
1
1
+3VS
I
G
I
G
2
+3VALW
4
+RTCBATT
2 0_0402_5%
U14D SN74LVC14APWLE_TSSOP14
G
0.1U_0402_16V4Z
U14C SN74LVC14APWLE_TSSOP14
7
C333
EC_PWROK
1 R318
P
14
2
5
RB751V_SOD323
SYS_PWROK 6,20
+3VALW
P
10K_0402_1% 2
2 @ 0_0402_5%
For South Bridge
7
1
+3VALW
D18
1 R324
VF
+3VS
SUSP# 1
4
28
3
23,27,28,34,40 SUSP#
U14B SN74LVC14APWLE_TSSOP14
2
14 P
G
I
1
R328
2
3
C300 1U_0805_25V4Z
S
3
7
2 G Q13 2N7002_SOT23
2
O 7
SUSP
I
2
G
2 34,39
3
1
1 D
U14A SN74LVC14APWLE_TSSOP14
P
14
R331 180K_0402_5%
For EMI
+3VALW
1
+3VALW
-c o
1
2
22P_0402_50V8J
1 1
R428
2
2
EC_ON
EC_ON
2
28,37
RLZ20A_LL34 2
1000P_0402_50V7K 1
-c c
Connector for MDC Rev1.5
B
C
D
Title
Power OK, Reset and RTC Circuit, TP Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
30
of
44
A
B
C
D
E
F
G
H
+VDDA 1
28.7K for Module Design (VDDA = 4.702)
1
1
2 1U_0402_6.3V4Z
C591 R483 10K_0402_5%
(output = 250 mA)
60mil
U32
L49 1 2 KC FBM-L11-201209-221LMAT_0805
4
VIN
1 1 L50 1 C581 C588 2 KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z 2 2 0.1U_0402_16V4Z
2
DELAY
7 8
1
VOUT
5
SENSE or ADJ
6
CNOISE
1
ERROR SD
GND
3
40mil
1
C587
2 1
R490
C 2
E
C609 1 1U_0402_6.3V4Z
2
1
R491
3
1
R470 10K_0402_1%
0.1U_0402_16V4Z 2 2.4K_0402_1%
2SC2411K_SOT23
2
560_0402_5%
1
SB_SPKR
1
20
MONO_IN
2
1 R485
Q33
2 B
560_0402_5%
1
D29 RB751V_SOD323 2
2
R493 10K_0402_5%
-c c
2
C576 10U_0805_10V4Z
2
1
C604 1 1U_0402_6.3V4Z
2
2
C599 1 1U_0402_6.3V4Z
BEEP#
4.85V
1
R467 30K_0402_1%
SI9182DH-AD_MSOP8
28
+VDDA
2
2
+5VS
1
+5VAMP
R478 10K_0402_5%
HD Audio Codec +AVDD_HDA
32
LINE_R
HP_OUT_L
39
AMP_LEFT
MIC2_R
HP_OUT_R
41
AMP_RIGHT
23
LINE1_L
NC
45
24
LINE1_R
DMIC_CLK
46
16
MIC2_L
17
MIC1_R
LINE_L
LINE_R
MIC1_L
MIC1_R
3
1 C583 1 C579
MIC1_C_L 2 4.7U_0805_10V4Z MIC1_C_R 2 4.7U_0805_10V4Z MONO_IN
R481 2
1 5.1K_0402_1%
SENSE A
4
SENSE B
CD_R
NC
CD_GND
BIT_CLK
MIC1_L
22
MIC1_R
12
19 HDA_RST_AUDIO#
19 HDA_SYNC_AUDIO
10
5
R484 1 R479 2
2 10K_0402_1% 1 20K_0402_1%
2 3 13 34
SENSE_A
28
32
Impedance
NC
SPDIF
47
EAPD
1 R480
2 SPDIF_R 48 0_0402_5% 4 7
Codec Signals
39.2K
PORT-A (PIN 39, 41)
20K
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-G (PIN 43, 44)
5.1K
PORT-H (PIN 45, 46)
SDATA_IN
PCBEEP
MONO_OUT
LINE1_VREFO
RESET#
GPIO1
SYNC
MIC1_VREFO_L
VF
32 LINEIN_PLUG# 32 MIC_PLUG#
Sense Pin
CD_L
21
11
19 HDA_SDOUT_AUDIO
32 HP_PLUG#
10U_0805_10V4Z
SDATA_OUT MIC1_VREFO_R
GPIO0 GPIO3 SENSE A SENSE B
HP_LEFT 32
HP_RIGHT 32 AMP_LEFT 32
44
8
DVSS1 DVSS2
AVSS1 AVSS2
HDA_SDIN0_AUDIO
HDA_BITCLK_AUDIO 19
1 R486
2 33_0402_5%
HDA_SDIN0 19 WOOFER_MONO
3
31
10mil
28
MIC1_VREFO_L
32
MIC1_VREFO_R MIC2_VREFO CODEC_VREF
10mil 1
40 33 26 42
ALC268-GR_LQFP48_9X9
DGND
2 C596 22P_0402_50V8J
29
27
NC
2 1 0_0402_5%
37
VREF
SPDIFO
1 R507
6
30
JDREF
AMP_RIGHT 32
For EMI
43
MIC2_VREFO
EAPD
C571 10U_0805_10V4Z 2 R476 20K_0402_1%
AGND
Issued Date
2 0_0805_5%
1 R489
2 0_0805_5%
1 R752
2 0_0805_5%
1 R463
2 0_0805_5%
1 R753
2 0_0805_5%
1 R496
2 0_0805_5%
C
D
GNDA
E
GND
GNDA
Compal Electronics, Inc.
Compal Secret Data 2006/12/25
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
1 R751
GND
Security Classification
A
2
9
HP_RIGHT
19
MIC1_L
1
HP_LEFT
20
32
DVDD
35
36
18
32
38
LINE_OUT_L
NC
2
1
LINE_L
MIC2_C_L 2 4.7U_0805_10V4Z MIC2_C_R 2 4.7U_0805_10V4Z LINE_C_L 2 4.7U_0805_10V4Z LINE_C_R 2 4.7U_0805_10V4Z
2
+3VS
C593
0.1U_0402_16V4Z
LINE_OUT_R
NC
15
1
C594
2
INT_MIC_R
32
1 C589 1 C586 1 C580 1 C577
1
L51 MBK1608121YZF_0603 1 2
-c o
32
C595
2
DVDD_IO
14
25
U33
+3VS_DVDD
0.1U_0402_16V4Z 1
AVDD2
2
40mil
0.1U_0402_16V4Z L47 1 2 FBM-L11-160808-800LMT_0603 1 1 1 C573 C569 C572 10U_0805_10V4Z 2 2 2 0.1U_0402_16V4Z
AVDD1
+VDDA
20mil
F
Title
HD Audio Codec ALC268 Size B
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P
Date:
Monday, April 16, 2007 G
Sheet
31 H
of
44
4
B
C
+3VS
D
E
+5VAMP R50
2
2
VOL_AMP
39K_0402_5%
2
Gain= 14dB
C561 1U_0603_10V4Z 2
1
1
C905
26
S
BIAS
2 EC_MUTE G Q58 2N7002_SOT23
C575
HP_R HP_L
INR_H INL_H /SD
8 9
SPKL+ SPKL-
17 18
HPOUT_R HPOUT_L
CVSS
15
VSS
16
GND PGND PGND CGND GND
2 23 7 13 29
BEEP
12 14
CP+ CP-
25
BIAS
1 APA2057A_TSSOP28
2.2U_0805_10V6K 2
2
2 0.01U_0402_16V7K
3
R474 100K_0402_5%
1
HP EN
4 6
28
1
VDD
24
HP_RIGHT_R 39K_0402_5% HP_LEFT_R
2
1
D
20 10
2 100K_0402_5%
HP_RIGHT_C 1 2.2U_0805_10V6K R471 HP_LEFT_C 1 2.2U_0805_10V6K R468
R472 30K_0402_5%
VOL_AMP
19
R469 1
LOUT+ LOUT-
+5VAMP
To AUDIO/B Connector
1
C563 1U_0603_10V4Z
SPDIF_PLUG#
2
2
SPDIF_PLUG# 2 G Q60
Q17 AO3413_SOT23-3
+5VSPDIF
C543
HPOUT_L 1
2
HPOUT_R 1
2
2
1
20mil
R351 HPOUT_L_1 1 47_0603_5% L27 HPOUT_R_1 1 47_0603_5% L28 R352
HPOUT_L_2 2 FBM-11-160808-700T_0603 HPOUT_R_2 2 FBM-11-160808-700T_0603
31 HP_PLUG#
31
G1 G2
R764 1
3 4
2
HP_PLUG#1 @ R765 2 0_0402_5% 1 2 6 3 SPDIF_PLUG#
4 7 8 10
SPDIF
9
2 100P_0402_50V8J
SINGA_2SJ-E373-T01 CONN@
LINE-IN JACK JP33 8 7 LINEIN_PLUG#
31 LINEIN_PLUG#
5
2
2
1 L55
LINE_L_R 2 FBM-11-160808-700T_0603 1 1
1
R488 2.2K_0402_5%
14 13 12 11 10 09 08
1
TC74LCX74FT_TSSOP14
2
31
MIC1_R
31
MIC1_L
C345 0.1U_0402_16V4Z
1 L52 1 L53
31
R487 2.2K_0402_5%
2 FBM-11-160808-700T_0603
1
2
MIC_PLUG#
MIC_PLUG#
MIC1_R_1
1 C602 220P_0402_50V7K
SINGA_2SJ-E351-S01 CONN@
2
Compal Electronics, Inc. 2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
C
4
(HDA Jack)
Compal Secret Data 2006/12/25
Issued Date
5
3 6 2 1
MIC1_L_1
ENCODER_DIR 28 ENCODER_PULSE 28
Security Classification
A
8 7
4
2 FBM-11-160808-700T_0603
C603 220P_0402_50V7K
JP32
MIC1_VREFO_R
U13
VCC CD2# D2 CP2 SD2# Q2 Q2#
(HDA Jack)
MIC JACK MIC1_VREFO_L
C349 0.1U_0402_16V4Z
CD1# D1 CP1 SD1# Q1 Q1# GND
SINGA_2SJ-E351-S03 CONN@
C601 220P_0402_50V7K
FOR EMI
2
NC7SZ14P5X_NL_SC70-5
2
1
4
3
3 6 2 1
+3VS
1
Y
1
1 2 3 4 5 6 7
1 C329
LINE_L
2
2 10K_0402_5% 1 C341
U12
5 4
LINE_R
2
3
1 R446
LINE_L
R330 100K_0402_5%
1
G
A
1
5
XRE094PHDINB1-2-12-E-7016_3P 4
3
2
0.01U_0402_16V7K
GND
B
1
1 2 R436 10K_0402_5%
0.01U_0402_16V7K
COM
2
@ 31 PSOT24C-LF-T7_SOT23-3 D32
0.1U_0402_16V4Z
P
2
2 A
LINE_R
FBM-11-160808-700T_0603 LINE_R_R 2
C613 220P_0402_50V7K 2
2
R435 10K_0402_5%
31
L54 1
1
C347 2
+3VS
NC
4
R450 10K_0402_5%
GND
U29
1
1
+3VS
5
220P_0402_50V7K
3
2
VF +3VS
2
JP31
INT_MIC_R2
Volume Control Circuit
S
2 0_0402_5%
C416
0.1U_0402_16V4Z
3
D
2N7002_SOT23
ACES_88266-02001 CONN@
C614
G1 G2
S
1
R523 FBMA-L11-160808-121LMT_0603 INT_MIC_R2 INT_MIC_R 1 2 INT_MIC_R 31 1 2 R524 FBMA-L11-160808-121LMT_0603 1 C36
1 2
1
2N7002_SOT23
SPDIF +5VSPDIF
2
1 2
Right
330P_0402_50V7K
15mil
JP4
1 2
S/PDIF Out JACK LINE Out/Headphone Out
C415
R51 2.2K_0402_5%
+3VALW
D
2
1
+5VAMP
0.1U_0402_16V4Z
2 G Q59
MIC2_VREFO
C612
1 2
+5VSPDIF
-c o
0.1U_0402_16V4Z
Left
HP_PLUG# R760 100K_0402_5%
R350 100K_0402_5%
330P_0402_50V7K 1
Int MIC Conn.
G1 G2
ACES_88266-02001 CONN@
+5VAMP
C418
2
3 4
JP34
FBMA-L11-160808-121LMT_0603 SPK_R+ 2 SPK_R2 FBMA-L11-160808-121LMT_0603
2
HP_LEFT
/AMP EN
1 1
HP_RIGHT
31
2
ROUT+ ROUT-
27
1 2
3 4
2
1
31
HP_RIGHT 1 C574 HP_LEFT 1 C570
INR_A INL_A
2 100K_0402_5%
SPKR+ SPKR-
-c c
+5VAMP +5VAMP
1 1 R26
R473 1
2
HPF Fc = 604Hz
SPKR+ SPKR-
22 21
1 2
ACES_88266-02001 CONN@
20mil R28
3
3 5
Int. Speaker Conn.
1
560_0402_5%
2
560_0402_5%
U31
PVDD PVDD
1
1
AMP_LEFT
11
2
HVDD
AMP_LEFT_C-1 1 2 1 C584 C585 0.47U_0603_16V4Z R477 R475
AMP_RIGHT_C 1U_0402_6.3V4Z AMP_LEFT_C 1U_0402_6.3V4Z
CVDD
2
D
1
S
31
AMP_RIGHT_C-1 C582
1
1
C568 C564 0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z
C578 0.47U_0603_16V4Z 1 2
AMP_RIGHT
1
2 0_0402_5%
R38
G
31
@
JP3
FBMA-L11-160808-121LMT_0603 SPK_L+ 2 SPK_L2 FBMA-L11-160808-121LMT_0603
1 1
3
R745 1
SPKL+ SPKL-
W=40mil
2 0_0402_5%
1
R744 1
1
+5VAMP
3
A
D
Title
Amplifier & Audio Jack Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
32
of
44
@
H4 H_S354D138
@
1
@
H30 H_S354D138
1
@
H10 H_S354D138
1
@
H11 H_S354D138
1
@
H2 H_S354D138
1
@
H18 H_S354D138
1
@
H3 H_S354D138
1
1
FAN1 Conn
H20 H_S354D138
1
H29 H_S354D138
@
+5VS +5VS
Change to SC1BAS16000
JP16
@
@
1
1
@
1
@
H21 H8 H_C236BC131D128 H_C236BC131D128
1 2 3 ACES_85205-03001 CONN@
2
@
H5 H_C158D158N
H26 H_C205D98
@
@
H27 H_O197X158D197X158N
For MDC
@
H25 H_C205D98
For FAN and MXM
@
H22 H_O89X58D59X28
@
1
C442 1000P_0402_50V7K
@
@
1
1
@
-c c 1
FAN_SPEED1
@
H23 H_O89X58D59X28
FD6 @
FD8
FD9
FD10
FD11
@
@
@
@
1
FD7
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
FD13
FD14
FD15
FD16
@
FIDUCIAL_C40M80
@
FIDUCIAL_C40M80
@
FIDUCIAL_C40M80
1
FD12
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
1
FIDUCIAL_C40M80
@
@
FIDUCIAL_C40M80
Compal Electronics, Inc.
Compal Secret Data 2007/1/15
Deciphered Date
@
FIDUCIAL_C40M80
@
FIDUCIAL_C40M80
FIDUCIAL_C40M80
1
FD5 @
1
FD4 @
1
FD3
@
FIDUCIAL_C40M80
Security Classification Issued Date
@
1
1
FD2
@
1
1
FD1
@
1
1
-c o
1
For DDR Metal Cage
VF
28
1
40mil
@
H13 H14 H32 H33 H31 H_C236BC131D128 H_C236BC131D128 H_C236BC131D128 H_C236BC131D128 H_C236BC131D128
R365 10K_0402_5% +VCC_FAN1
@
1
1
C445 1000P_0402_50V7K 1 2
@
1
+3VS
@
H28 H_C335BC140D138
For CPU Support Breket
BAS16_SOT23-3 C446 10U_0805_10V4Z 1 2
1
2
@
H24 H_S354BC140D138
H6 H16 H17 H7 H_C236BC168D165 H_C236BC168D165 H_C236BC168D165 H_C236BC168D165
1
1
G993P1UF_SOP8
@
1
1
D21
1
8 7 6 5
2
GND GND GND GND
1
EN_DFAN1
VEN VIN VO VSET
2
28
1 2 3 4
+VCC_FAN1 EN_DFAN1
H19 H1 H_C315BC236D138 H_C315BC236D138
1
H15 H_S354D138 D22 1SS355_SOD323-2
1
U20
1
10U_0805_10V4Z 2
1
C443 1
2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
FAN & Screw Hole Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet
33
of
44
A
B
C
+3VALW TO +3V_SB(ICH8M AUX Power) +3VALW
+5VS
C631
1
1 2 3 4
C633
AO4468_SO8
1
C629
10U_0805_10V4Z 2 2 1U_0603_10V4Z
1
2 10U_0805_10V4Z
D
27,28,40
SYSON
SYSON#
SYSON
+VSB
3V_GATE
2 1 R505 200K_0402_5%
1 1
C506 SBPWR_EN# 2 Q39G 2N7002_SOT23
0.1U_0603_25V7K
S
D 2
2 SBPWR_EN# G Q38 2N7002_SOT23
D
S
1
Q29 2N7002_SOT23
2 G
R440 100K_0402_5%
C632 0.1U_0603_25V7K
+5VALW
S 2
3
2
S
SYSON#
2
3
1
D
2 SUSP G Q23 2N7002_SOT23
SUSP
2 Q24G 2N7002_SOT23
24,26,27
D
3
1
S
R506 470_0603_5%
3
5VS_GATE
2 1 R412 200K_0402_5%
+VSB
1
1
2
S S S G
1
R411 470_0603_5%
D D D D
3
C495
10U_0805_10V4Z 2 2 1U_0603_10V4Z
10U_0805_10V4Z 2 2 10U_0805_10V4Z
1
8 7 6 5
2 C503
AO4468_SO8
1
1
1
1
1
C504
1 2 3 4
1
1
R455 100K_0402_5%
U34 S S S G
1
C498
D D D D
+5VALW
+3V
U22 8 7 6 5
E
2
+5VALW TO +5VS +5VALW
D
+3VALW
+3VS
D
+1.8V to +1.8VS +1.8V
+1.8VS
1 2 3 4
C533
1.8VS_GATE
S
3
3
1
1
+5VALW
R379 100K_0402_5%
21
SBPWR_EN#
SBPWR_EN#
D
2 G Q43 S 2N7002_SOT23
28 SBPWR_EN
R510 100K_0402_5%
3
2
VF S
D
2 SUSP G Q22 2N7002_SOT23
S
R424 470_0603_5% @
1
1
R342 470_0603_5% @
1
2 1
D
2 SUSP G Q19 2N7002_SOT23
+1.8V
R403 470_0603_5%
1
D
+0.9VS 2
3
1
1
1
R374 470_0603_5%
1
R204 470_0603_5%
S
C542
+1.05VS
2
2
+2.5VS
2 SUSP G Q11 2N7002_SOT23
2 SUSP G Q26 2N7002_SOT23 PM@
0.1U_0603_25V7K 2 PM@
Q28 S 2N7002_SOT23 PM@
D
S 1
D
2 G
+1.5VS
D
1
SUSP
10U_0805_10V4Z 2 PM@ 2 1U_0603_10V4Z PM@
R427 470_0603_5% PM@
3
3
2 1 R439 510K_0402_5% PM@
1
3
+VSB
C531
1
C547 SI4856ADY_SO8 10U_0805_10V4Z PM@ 2 PM@ 2 10U_0805_10V4Z PM@ SI4856/AO4430
1
1
S S S G
3
1
1
C553
1
D D D D
2
U24 8 7 6 5
2
2
3
S 5VS_GATE
2 SUSP G Q12 2N7002_SOT23
R457 100K_0402_5%
1
10U_0805_10V4Z 2 2 1U_0603_10V4Z
R306 470_0603_5%
Q31 2N7002_SOT23
1
1
S
3
C299
1
AO4468_SO8
1
D
2 G
2
2 C301
10U_0805_10V4Z 2 2 10U_0805_10V4Z
2
SUSP
2
1
-c o
C343
1 2 3 4
D
2 SUSP G Q16 2N7002_SOT23 @
S
3
1
S S S G
1 1
C344
D D D D
SUSP
23,27,28,30,40 SUSP#
U10 8 7 6 5
30,39
1
+3VALW TO +3VS
3
-c c
R462 100K_0402_5%
2 SYSON# G Q25 2N7002_SOT23 @
4
4
2007/1/15
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2007/12/25
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
DC Interface Size B Date:
Document Number
Rev 0.2
JDW50/JDYL70 M/B LA-3771P Monday, April 16, 2007
Sheet E
34
of
44
A
B
PD1 RLZ24B_LL34
1
3
2
2
VL
2
B+
PR12 2.2M_0402_5% 1
1
2
2
PQ3 DTC115EUA_SC70-3
PR13 499K_0402_1%
2
ACIN
2
1
ML1220T13RE 45@ 4
1
D
1
1
2
Compal Electronics, Inc.
Compal Secret Data 2007/01/16
Deciphered Date
2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
+5VALW
2
4
Security Classification
A
PACIN 37,38
PQ6 DTC115EUA_SC70-3
@ PR22 66.5K_0402_1%
BATT ONLY Precharge detector Min. typ. Max. H-->L 6.138V 6.214V 6.359V L-->H 7.196V 7.349V 7.505V
Issued Date
1
3
S
+RTCBATT
+RTCBATT
PQ5 PR21 RHU002N06_SOT323-3 47K_0402_5% 2 2 1 G
3
+
PBJ1
PR20 34K_0402_1% 2 1
RTCVREF
PR19 499K_0402_1%
2
-
Precharge detector Min. typ. Max. H-->L 14.589V 14.84V 15.243V L-->H 15.562V 15.97V 16.388V
PR18 191K_0402_1%
2
2
PC10 0.1U_0603_25V7K
1
RB715F_SOT323-3
3
1
2
PRG++ 2
3
-
32.8
PC7 1U_0805_25V4Z
+
O
1
8 1
3
4
ACON
VF
GND 1
2
1
37
PU2A LM393DT_SO8
PC11 1000P_0402_50V7K
2
1
IN
1 2
560_0603_5% 560_0603_5%
OUT
PD5
2
3
2
19,36,38 MAINPWON
2
PR17
2 1
2
1
PC8 1
+CHGRTC
4.7U_0805_6.3V6K
PR16
3
PR14 100K_0402_1%
P
PR15 200_0805_5% PU1 G920AT24U_SOT89-3
G
RTCVREF
3.3V
2
1
1
VS
PC9 0.01U_0402_25V7K
-c o
PC6 0.1U_0603_25V7K
1 2
ACOFF
3
1 2 2
2
PR11 22K_0402_5% 1 2
1
0.22U_1206_25V7K
PC5 2 1
1
3
PR10 100K_0402_5%
51ON#
28,37
VS
3
CHGRTCP
PR8 100K_0402_5%
1
1 1 PR9 33_1206_5% PQ4 TP0610K-T1-E3_SOT23-3
29,30
PQ2 DTC115EUA_SC70-3
2
BATT+ 2
1
2 PD3 RLS4148_LLDS2 PD4 RB751V-40TE17_SOD323-2 2 1
2
2
-c c
PR7 1K_1206_5% 1 2
1
E&T_4510-E04C-01R
VIN
B+
1
PR4 1K_1206_5% 1 2
RLS4148_LLDS2
100K_0402_5%
2
PR6
1
PQ1 TP0610K-T1-E3_SOT23-3
PR5 1
1
1
PR3 1K_1206_5% 1 2
PD2
VIN
2
2
1
2
PR2 1K_1206_5% 1 2
1 2
2
PR1 10_1206_5%
560P_0402_50V7K
3
PC4 2 1
3
1
12P_0402_50V8J
4
PC3 2 1
4
VIN
12P_0402_50V8J
5
FBMA-L18-453215-900LMA90T_1812 1 2
PC2 2 1
G1
PL1
ADPIN
560P_0402_50V7K
6
PC1 1
G2
D
100K_0402_5%
PJP1
C
C
Title
DCIN/DECTOR Size B Date:
Document Number
JDW50/JDY70
Sheet
Monday, April 16, 2007 D
Rev 0.2
LA3771P 35
of
44
A
B
C
D
MAX8744_B+ MAX8744_B+
B+
PL2
5 6 7 8 G S S S
13
30
CSL5
CSL5
FB3
FB3
11
FB5
7
REF
FB5
OUTA
1
2
PR41 @ 47K_0402_5%
PC29 1U_0603_6.3V6M
fESR3.3V starts up delay 2ms after 5V starts up
22
PGOOD3
27
PGOOD5
14
1
ILM
3
38
+
2
PR36 0_0402_5% 2 12VREF_8744
@ PR37 499K_0402_1% 1 2
GND
ILIM
@ PR196 2.2_1206_5%
2
0_0402_5% 12VREF_8744 0_0402_5% 2
SPOK
8
ONA
ON3
1
2
PGOODA
PR182 1
ON5
PR40 0_0402_5% 1 2
PR179 0_0402_5% 2 1
PC30 0.047U_0402_16V7K 2 1
19,35,38 MAINPW ON
PR39 0_0402_5%
2
5
@ PR38 0_0402_5%
@ PR32 2
SHDN
FSEL
6
10
FBA
9
PC28 0.22U_0603_25V7K
SKIP
2VREF_8744
4
PC26 4.7U_0805_6.3V6K 1 2
VL
LDO5
20
2
+5VALWP
PR33 10K_0402_1% 1 2
2
PC25 1000P_0402_50V7K
2
CSH5
CSH5
PL4 10UH_SIL104R-100PF_4.4A_30%
CSL3
12
1
28
PC27 150U_D2_6.3VM
CSL3
PR29 6.49K_0402_1%
CSH3
PR31 15.4K_0402_1% 1 2
PGND
19
29
2
CSH3
@
1
DL5
PR27 2.61K_0402_1% 2 1
PC22 0.22U_0603_16V7K 1 2
18
1 2
1
DL5
2
DL3
PC162 680P_0402_50V7K
17
1
LX5
2
PQ9 SI4810BDY-T1-E3_SO8 4 G D 5 3 S D 6 2 S D 7 1 S D 8
LX3
32
2
Notes :
1
PC20
23
DRVA
1
Delta I=((Vin-Vo)*D)/(F*L) =((19-3.3)*(3.3/19))/(300K*10U) =0.908A
PR25
24
PC24 0.22U_0603_10V7K 2
VF
Ilimit = 185mV/24.96m ~ 215mV/20.68m = 7.41A ~ 10.39A Iocp(mean) = Ilimit -Delta I/2 =6.956A~9.936A
DH5 BST5A 2
DL3
31
2
1
16 15
LX3
PR34 100K_0402_5% 21 2
DCR = 29m ohm(typical) ; Rcs = 20.68m ohm
DH5 BST5
1
PZD1 RLZ5.1B_LL34 VS
PR35 200K_0402_5% 1 2
DCR = 35m ohm(max) ; Rcs = 24.96m ohm
BST3
-c o
+3VALWP Ipeak = 5.5A; Imax = 4A
DH3
26
1
2 1
1
3
PC17 1U_1206_25V7K 1 2
21
2VREF_8744
2
PC23 1000P_0402_50V7K
25
IN
0.1U_0603_25V7K LX5
1
PC21 0.22U_0603_16V7K
EP
0_0603_5%
@
2
33
-c c
8 7 6 5 D D D D S S S G
PC19 0.1U_0603_25V7K
1 2 3 4
PQ10 SI4810BDY-T1-E3_SO8
DH3 PR24 1 BST3A 0_0603_5%
2VREF_8744 1
1
2
2
1
1
PC161 680P_0402_50V7K 2 1
PR23 2.61K_0402_1% 1 2
PR28 6.49K_0402_1% 2 1
PR30 10K_0402_1%
2
PR26 6.81K_0402_1% 1 2
+
2
PC18 330U_D3L_6.3VM_R25M
1
PU3 MAX8744ETJ+_TQFN32_5X5
2 @ PR195 2.2_1206_5% 2 1
1
PQ8 SI4800BDY-T1-E3_SO8
4 3 2 1
1 2 3 4 PL3 10UH_SIL104R-100PF_4.4A_30%
+3VALWP
1
D D D D
PC16 2200P_0402_50V7K 2 1
PC15 4.7U_1206_25V6K 2 1
PC14 4.7U_1206_25V6K 2 1
8 7 6 5 PQ7 SI4800BDY-T1-E3_SO8
S S S G
1
D D D D
PC13 4.7U_1206_25V6K 2 1
PC12 2200P_0402_50V7K 2 1
FBMA-L18-453215-900LMA90T_1812 1 2
+5VALWP Ipeak = 5.5A ; Imax = 4A
3
DCR = 35m ohm(max) ; Rcs = 24.96m ohm DCR = 29m ohm(typical) ; Rcs = 20.68m ohm Ilimit = 185mV/24.96m ~ 215mV/20.68m = 7.41A ~ 10.39A Iocp(mean) = Ilimit -Delta I/2 =6.796A~9.776A Delta I=((Vin-Vo)*D)/(F*L) =((19-5)*(5/19))/(300K*10U) 1.228A
@
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/01/16
Deciphered Date
2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title
+5VALWP/+3VALWP Size Document Number Custom JDW50/JDY70 Date:
Rev 0.1
LA3771P Sheet
Monday, April 16, 2007 D
36
of
44
A
B
Iada=0~4.74A(90W)
PL15
CSIN
17
DH_CHG
10
ACLIM
VDDP
15
14
GND
PGND
13
7
+ -
6
0
4 1 1
5 6 7 8
G S S S
4 3 2 1
1 2
PR192 11.5K_0402_1% 2
6251aclim
2 UMA@ PQ47 RHU002N06_SOT323-3
2
1
PC147 0.01U_0402_25V7K
D
S
PR194 20K_0402_1%
2
PR178 200K_0402_1%
1
1
1
1
-
6251VREF
2
0
PR176 300K_0603_0.1%
1
PU11A LM358ADT_SO8 + 3
BATT-OVP=0.1487*BATT+
2 G
28 65W/90W#
4
4
4
1
LI-3S :13.50V--BATT-OVP=2.007V PR175 845K_0603_1%
2
1 PR177 10K_0402_5% 1 2
2
@ PR187 20K_0402_1%
8
@
PC145 0.01U_0402_25V7K
3
E
1
12.90V
@ PQ46 2SC2411K_SOT23-3
3
LOW
1 2
2 1 CSON
PU11B LM358ADT_SO8 5
BATT-OVP=0.1487*BATT+
C
2
8
HIGH
3
LI-4S :18.0V--BATT-OVP=2.677V
BATT+
VS
6251_EN
2 B
28 BATT_OVP
P
13050mV
2
BATT+
3
1
PQ45 RHU002N06_SOT323-3
CV mode 17.20V
@PR186 @PR186 100K_0402_1%
1
S
2 G
CALIBRATE
G
2800mAH 3S pack
4
OVP voltage :
1
2 1
28
D
VS
LOW
PC144 4.7U_0805_6.3V6K
1
ISL6251AHAZ-T_QSOP24
2
LOW
CHGSEL
CHGSEL
26251VDD
PR171 4.7_0603_5%
P
17400mV
DL_CHG
1
2
LGATE
PQ40 SI4800BDY-T1-E3_SO8
VADJ
PD14 RB751V-40TE17_SOD323-2
6251VDDP
PR199 4.7_1206_5% 2 1
16
1
BOOT
5 6 7 8
CHLIM
PC140 0.1U_0603_25V7K BST_CHGA 2 1
D D D D
9
PR167 2.2_0603_5% BST_CHG 1 2
2
PR165 0.02_2512_1%
PL16 10UH_PCMB104T-100MS_6A_20% CHG 1 2
G S S S
VREF
1
UGATE
8
3
PHASE
ICM
S
PC141 10U_1206_25V6M 2 1
19
18
1
CSIP
PQ38 SI4800BDY-T1-E3_SO8
2
VCOMP
7
PC132 0.1U_0603_25V7K
6
20
PQ36 RHU002N06_SOT323-3 2 PACIN G
D 3
CSIN
PD13 1SS355TE-17_SOD323-2 1 2
D D D D
ICOMP
2
5
CSOP
4 3 2 1
21
PC146 0.01U_0402_25V7K
3S/4S#
-c c
CSOP
1
1
3 CELLS
CSON
1
Charging Voltage (0x15)
2800mAH 4S pack
4
PR197 20_0603_5% 1 2 PC133 0.047U_0603_16V7K 1 2 PR161 20_0603_5% 2 1 PR162 20_0603_5% PC136 0.1U_0603_25V7K 1 2 PR198 2.2_0603_5% LX_CHG
2
UMA@ PR193 2.37K_0402_1%
BATT Type
22
PC154 0.01U_0402_25V7K
IREF=0.43V~3.24V
CSON
VF
IREF=0.7224*Icharge
EN
PQ33 DTC115EUA_SC70-3
6251VREF
2 28
CC=0.6~4.48A
23
BATT+
VIN
PR183 274K_0402_1%
Vaclim=2.39*((10K//152K)/((5.76K//152K)+(10K//152K))) =1.502V
2
1
2 2
1
PQ42 SI2301BDS-T1-E3_SOT23-3
2
1
PR173 274K_0402_1% 1 2
D
3
PR174 100K_0402_1%
CP mode Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A
ACSET ACPRN
3
12
G
3
2
11
S
6251VREF
DCIN
24
2
2
6251aclim
3
ACOFF
2
ACOFF
3
28,35
PC139 1 2
0.1U_0402_16V7K
PR170 100K_0402_1%
DCIN
2
PQ41 DTC115EUA_SC70-3
PR164 100_0402_1% 1 2 6251VREF
ADP_I
PR156 200K_0402_1% 1 2
1
IREF
10K_0402_1% 2
2 PC138 100P_0402_50V8J
PR168 80.6K_0402_1% 2 1 1
28
6251_EN
VDD
PC131 0.1U_0603_25V7K 2 1
-c o
PQ39 RHU002N06_SOT323-3 28
1
6800P_0402_25V7K 2
1
PC143 0.01U_0402_25V7K 2 1
S
2 G
ACON
ACON
1
PACIN
1
35
PACIN
D
3
35,38
PR166 22K_0402_5% 1 2
PU10
2
PR163 1
EC_ON 28,30
RB715F_SOT323-3
1
PC137 1 2 0.01U_0402_25V7K
EC_ON
3
100K_0402_1%
2
PC135 1
21
1
2
3S/4S#
2
28
@ PC134 680P_0402_50V7K CSON 1 2 3
PR160 150K_0402_1%
100K_0402_1%
PQ35 DTC115EUA_SC70-3
1
3
S PQ37 RHU002N06_SOT323-3
3
1
D
2 G 2
PR158 47K_0402_5%
PQ34 DTC115EUA_SC70-3
1
VIN
PD11 1SS355TE-17_SOD323-2 ACOFF 1 2
PR155 10K_0402_1%
2FSTCHG
PR185
6251VDD
2
1 2 PC153 0.1U_0402_16V7K
2
PQ44 DTC115EUA_SC70-3
PR154 47K_0402_1% 1 2
PD17
PR159 2
6251VDD 1
1
PR184 100K_0402_1% 2 1
FSTCHG
PC129 0.1U_0603_25V7K
2
PR157 10K_0402_5% 2 1
1
1
1
28
DCIN
1
PC130 2.2U_0603_6.3V6K 2 1
PC128 5600P_0402_25V7K 1 2
PD16 1SS355TE-17_SOD323-2 1
2
2
3
VIN
PC163 680P_0402_50V7K
4 2
1 2 3
PC127 0.1U_0603_25V7K
1
4 1 2 PQ32 DTA144EUA_SC70-3
PR153 200K_0402_1%
1
CSIP
PQ43 TP0610K-T1-E3_SOT23-3
8 7 6 5
PC126 2200P_0402_25V7K 2 1
3
1
PR152 47K_0402_1%
1 2 3 PC125 0.1U_0603_25V7K 2 1
2
PQ31 AO4407_SO8
CHG_B+
FBMA-L18-453215-900LMA90T_1812 1 2
4
PC124 10U_1206_25V6M 2 1
1
PC142 10U_1206_25V6M 2 1
B+
PR151 0.02_2512_1%
P3 8 7 6 5
PC123 10U_1206_25V6M 2 1
PQ30 AO4407_SO8 1 2 3
G
P2 1 2 3
4
PQ29 AO4407_SO8 8 7 6 5
D
CP = 85%*Iada ; CP = 4.07A
ADP_I = 19.9*Iadapter*Rsense
VIN
C
Normal 4S LI-ON Cells
16800mV
LOW
HIGH
16.80V
Normal 3S LI-ON Cells
12600mV
HIGH
HIGH
12.60V
HIGH
HIGH
12.60V
Wake up charge while no communication
-
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/01/16
Deciphered Date
2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
C
Title
CHARGER Size
Document Number
JDW50/JDY70 Date:
Rev 1.0
LA3771P
Monday, April 16, 2007
Sheet D
37
of
44
A
B
C
D
PH1 under CPU botten side : CPU thermal protection at 90 degree C Recovery at 70 degree C
2 PH1 100K_0603_1%_TH11-4H104FT 2 1
2
1
2 TM_REF1
+
6
-
P
8
PU2B LM393DT_SO8
5
O
MAINPW ON 19,35,36
7
1
PR49 150K_0402_1% 2 1 VL
PR51 150K_0402_1%
2
BATT_TEMP 28
-c o
BATT_TEMP
PR42 150K_0402_1%
2
PR50 1K_0603_1% 2
PR45 82.5K_0603_1% 1 2
PC35 1U_0805_16V7K 2 1
1
PC34 1000P_0402_50V7K
2
+3VALW P
PR44 442K_0603_1% 2
1
-c c
PR48 6.49K_0603_1% 1 2
PC33 0.01U_0603_50V7K
PC31 0.1U_0603_25V7K
4
1 2
2
PC32 1000P_0603_50V7K
1
PR47 100_0603_1% 2 1
PR46 100_0603_1% 2 1
1
2
PR43 9.76K_0402_1%
G
BATT+
TSA EC_SMC1 EC_SMD1
1
BATT++
1
VL
VS PL5 FBMA-L18-453215-900LMA90T_1812 1 2
1
SUYIN_200275MR007G161ZL PJP2
1 2 3 4 5 6 7
VL
BATT++
1
EC_SMB_CK1 15,28,29 EC_SMB_DA1 15,28,29
PR52 1M_0402_1% 1 2 VIN
1
1
VIN
1
SPOK
D
S
8
20,28
PACIN
35,37
3
1
G
P
ACIN
PR58 10K_0402_5%
2
PZD2 RLZ4.3B_LL34
RTCVREF
2
2
ACIN
PACIN
1
1
1
PU4B LM393DT_SO8
+
6
-
P
8
Vin Detector Min. typ. Max. H-->L 16.976V 17.257V 17.728V L-->H 17.430V 17.901V 18.384V
5
O
7
G
2
4 PR60 10K_0402_5% 2 1
PC39 0.1U_0603_25V7K
PQ12 RHU002N06_SOT323-3
2 G 1
36
PR63 0_0402_5% 1 2
3
1
PR62 100K_0402_5%
PC38 0.22U_1206_25V7K
-
PR55 10K_0402_5% 1 2
4
2
VL
2
PR61 22K_0402_5% 1 2
+
2
1 PC37 0.1U_0603_25V7K
1
PR59 100K_0402_5%
3
PU4A LM393DT_SO8 O 1
2
+VSBP
1
2
1
2
3
B+
PC36 1000P_0402_50V7K
PR57 20K_0402_1% 2 1
PQ11 TP0610K-T1-E3_SOT23-3
2
VF
3
PR56 22K_0402_5% 1 2
PR54 10K_0402_5%
2
VS
PR53 84.5K_0402_1%
4
@ PC40 0.1U_0402_16V7K
2
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/01/16
Deciphered Date
2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title
BATTERY CONN. / OTP Size B Date:
Document Number
JDW50/JDY70
Rev 0.2
LA3771P Sheet
Monday, April 16, 2007 D
38
of
44
5
4
3
2
1
1
1
+3VALW
PJP3 JUMP_43X118
PC73 10U_0805_6.3V6M 1 2
PJP4 JUMP_43X118
2
PU6
9
1
PJP5 2
PJP6 1
1
+3VALW
+1.8VP
JUMP_43X118
2
1
+5VALW
+2.5VSP
2
1
+0.9VS
+1.5VSP
2
2
1
1
1
PR112 60.4K_0402_1% PC80 0.047U_0402_16V7K
D
PQ20 RHU002N06_SOT323-3 2 G
PR116 0_0402_5% 1 2
SUSP C
S
+1.8V
2
2
1
1
+2.5VS
2
2
1
1
+1.5VS
PJP12
1
1
JUMP_43X118
+1.05VS
+VSBP
2
2
1
1
VF
2
2
JUMP_43X118
PJP13
+1.05VSP
REFEN
VTT
PJP10
1
JUMP_43X118
B
6 5
JUMP_43X118
PJP9 2
VCCA
PJP8
1
JUMP_43X118
+0.9VSP
VTT
JUMP_43X118
PJP7 2
+5VALWP
2
4
-c o
2
3
7
-c c
C
+3VALWP
AGND
2 1
PC79 22U_1206_10V6M
2
1
1
PC77 22U_1206_10V6M
2
+0.9VSP 2
S
2 G
RT9173DPSP_SO8 PC78 0.1U_0402_16V7K 2 1
D
PQ19 RHU002N06_SOT323-3 PR114 1K_0402_1% 2 1
1
30,34 SUSP
PR113 0_0402_5% 1 2
VFB
PC76 1U_0603_16V6K 1 2
GND
+2.5VSP
1
8
PGND
3
NC
8
VIN
2
NC
VOUT
2
1
REFEN
2
4
1
PC75 1U_0603_6.3V6M
7 2
PR110 1K_0402_1%
3
SUSP
5
PU7
CM8562IS_PSOP8
1
NC
+3VALW
2
GND
3
6
PR115 200K_0402_1%
VCNTL
PR111 10_0603_1%
1
1
2
2
PC74 10U_0805_6.3V6M
VIN
RTCVREF
1
1
AGND
2
+1.8V
D
+5VALW
9
D
PC81 0.1U_0603_25V7K
1
1
2
2
+1.8V
B
+VSB
JUMP_43X118
PJP14
+1.05VSP
2
2
1
1
+1.05VS
JUMP_43X118
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/01/16
2008/01/16
Deciphered Date
+0.9VSP/+2.5VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
Title
2
Size Document Number Custom JDW50/JDY70 Date:
Rev
LA3771P
Monday, April 16, 2007
0.1 Sheet
1
39
of
44
5
4
3
2
1
+5VALW
D
23,27,28,30,34 SUSP#
1 +5VALW
1 PR132 100K_0402_5%
VFB=0.5V Vo=VFB*(1+PR122/PR127)=1.805V Ipeak=12.17A, Imax=8.519A
BST2
21
TON2
DH2
20
10
VOUT2
LX2
19
11
VCCA2
12
FB2
13
PGD2
BST_1.5V1 2 0_0603_5% DH_1.5V
FB_1.5V
VSSA2
DH_1.5V-1
PC93 1 2
PR126 0_0603_5% 1 2
0.1U_0603_25V7K
ILIM2
18
VDDP2
17
DL2
16
DL_1.5V
PGND2
15
PC97 33P_0402_50V8K FB_1.5V
PC100 1U_0603_10V6K
PR133 0_0402_5% 1
A
1 +
2
Close to IC Side
B
Differential routing of feedback to VSSA2 and VOUT2 PIN
2
2
@ PC102 0.1U_0402_16V7K
VFB=0.5V Vo=VFB*(1+PR129/PR130)=1.5V Ipeak=5.16A, Imax=3.612A Ton=(3.3E-12*(PR125+37K)*(Vout/VBat))+50ns =0.3201us
=3.3*10e-12*(820K+37K)*(1.8/19)+50ns=0.3179us
Max:11.5 mOhm
+1.5VSP
Vout_1.5V
PR130 10K_0402_1%
Ton=(3.3E-12*(PR121+37K)*(Vout/VBat))+50ns
FDS6670AS:Rds(on)=>Typ:9 mOhm
Maximum continuous current=>6A PL11 2.2UH_SIQB74B-2R2-R_6.5A_20% 1 2
VFB=0.5V
@ PC101 0.1U_0402_16V7K
C
AO4916_SO8
LX_1.5V
PR128 ILIM_1.5V1 2 29.4K_0402_1% +5VALW
1 2 3 4
1
EN/PSV2
9
PR124
G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A
PC98 330U_D2E_2.5VM
22
8 7 6 5
1 PR129 20K_0402_1%
EN/PSV1
BST1
PR121 2 1 B+_1.8/1.5 820K_0402_5%
B+_1.8/1.5
2
Vout_1.8V
23
1
24
TON1
2
VOUT1
DH1
PQ22
PC90 4.7U_1206_25V6K
LX1
PGOOD1_1.8V
PC89 4.7U_1206_25V6K 2 1
VCCA_1.8V
PC88 1000P_0402_50V7K 1 2
VF
PGOOD2_1.5V
25
27,28,34 SYSON
2
B
VCCA1
SC413TSTRT_TSSOP28
2
2
to VSSA1 and VOUT1 PIN
ILIM1
8
14
Close to IC Side
FB_1.8V
2
PC96 1000P_0402_50V7K
Differential routing of feedback
26
1
Vout_1.5V VCCA_1.5V
27
FB1
VDDP1
2
PR125 1M_0402_5%
PR131 0_0402_5% 1
1 2
0_0603_5%
1
28
-c o
D D D D PQ23 SI4810BDY-T1-E3_SO8
2
VSSA1
PGD1
DL1
1
8 7 6 5
1
0.1U_0603_25V7K B+_1.8/1.5
1 2 3 4
PR127 10K_0402_1%
PC91 2
PGND1
1
1 2
PR122 26.1K_0402_1%
1
S S S G
2
FB_1.8V
1
+
2
1
PC92 33P_0402_50V8K
2
PC94 330U_D2E_2.5VM
C
DH_1.8V 6 PR123 2 BST_1.8V 7
-c c
PR119 0_0603_5% DH_1.8V-1 1 2
1
Vout_1.8V
3
1 2
DL_1.8V 2 PC87 1 2 +5VALW 3 1U_0603_10V6K 1 2 ILIM_1.8V4 PR120 34.8K_0402_1% LX_1.8V 5
1
PL10 1UH_SIL104-1R0-R_11A_30% 1 2
PU8
1
2
D D D D
8 7 6 5
BST_1.8V-1
2
+1.8VP
1 2 3 4
Maximum continuous current=>6A
PR118 100K_0402_5%
BST_1.5V-1
PQ21 SI4800BDY-T1-E3_SO8
S S S G
PC85 4.7U_1206_25V6K 2 1
PC86 4.7U_1206_25V6K 2 1
2
VCCA_1.5V
2
B+_1.8/1.5
PL9 FBMA-L11-322513-151LMA50T_1210 1 2
2
1 2
B+
PD9 CHP202UPT_SOT323-3
VCCA_1.8V PC149 1U_0603_10V6K
PR117 10_0603_5%
1
PR180 10_0603_5%
1
PC82 2.2U_0603_6.3V6K
PC83 1U_0603_10V6K
2
1
1
D
AO4916 Rds(on)=>Typ:21 mOhm Max:27 mOhm Ivalleymin=9*10u*(29.4K/0.027*1.4)=7A
Iocp=Ivalley+Iripple/2
Ivalleymax=11*E-6*(29.4K/0.021*1.1)=12.833A
Iripple=(vin-vout)*(Ton/L)=5.467A, 1/2 Iripple=2.734A.
Iripple=(vin-vout)*(Ton/L)=2.546A, 1/2Iriiple=1.273A
Ivalleymin=10E-6*(PR120/Rds(ON)max*1.5)
Iocp=Ivalley+Iripple/2
=9*10e-6*(27.4K/0.0115*1.5)=14.295A>11.73*1.2=14.076A
OCP==>8.273A~14.106A
A
Ivalleymax=10E-6*(PR120/Rds(ON)typ*1.2) =11*10e-6*(27.4K/0.009*1.2)=27.907A.
Compal Electronics, Inc.
Compal Secret Data
Security Classification
OCP==>17.029A~30.641A
2007/01/16
Issued Date
Deciphered Date
2008/01/16
+1.5VSP/+1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
Title
2
Size Document Number Custom JDW50/JDY70 Date:
Monday, April 16, 2007
Rev
LA3771P Sheet 1
0.1 40
of
44
5
4
3
2
1
D
D
1
1
+5VALW
PR134 10_0603_5%
FB
4
PGD
LX
11
LX_1.05V
10
ILIM_1.05V
9
+5VALW
ILIM
0.1U_0603_25V7K
1 2 34K_0402_1%
2
PC110 4.7U_1206_25V6K
PR147 10K_0402_1%
1 +
2
2
PC120 1U_0603_10V6K
+1.05VSP
Vout_1.05V
1
G S S S
FB_1.05V
1
DL_1.05V
Close to IC Side
B
Differential routing of feedback to VSSA2 and VOUT2 PIN
VF
B
2
PC117 PQ28 33P_0402_50V8K SI4810BDY-T1-E3_SO8
4 3 2 1
VFB=0.5V
Maximum continuous current=>6A
1 5 6 7 8 D D D D
DL
VDDP
C
PL14 1UH_SIL104-1R0-R_11A_30% 1 2
PR145
8
PGND
7
NC
VSSA
6
TP
17
PU9 SC411MLTRT_MLPQ16_4X4
5
PGOOD2_1.05V
1
1
1 2 0_0603_5%
PC109 4.7U_1206_25V6K 2 1
15
14
13
DH_1.05V
B+
1 PR146 11K_0402_1%
3
12
PL12 FBMA-L11-322513-151LMA50T_1210 1 2
2
VCCA
BST
2
BST_1.05V
DH
PC113 1 2
-c o
2
FB_1.05V
VOUT
PR141
2
VCCA_1.05V
1
NC
16
PR149 100K_0402_5%
TON
1
Vout_1.05V
EN/PSV
+5VALW
B+_1.05
PQ26 SI4800BDY-T1-E3_SO8 4 G D 5 3 S D 6 2 S D 7 1 S D 8
1 2
C
BST_1.05V-1
PC116 1000P_0402_50V7K
PD10 1SS355TE-17_SOD323-2
PC118 330U_D2E_2.5VM
VCCA_1.05V
1
PR142 1M_0402_5% B+_1.05 2 1
2
@ PC121 @PC121 0.1U_0402_16V7K
PC104 1U_0603_10V6K
2
-c c
2
PC103 2.2U_0603_6.3V6K
2 1 2
30 VS_ON
PR148 0_0402_5% 1 2
VFB=0.5V, Ipeak=9.37A, Imax=6.559A The current rating of +1.05VSP include +VCC_GFX current. Vo=VFB*(1+PR146/PR147)=1.05V Ton=(3.3E-12*(PR142+37K)*(Vout/VBat))+50ns=0.2391us SI4810BDY:Rds(on)=>Typ:16mOhm Max:20mOhm Ivalleymin=9*10E-6*(PR145/Rds(ON)max*1.5) =9*10E-6*(34K/(0.02*1.5))=10.200A Ivalleymax=11*10E-6*(PR145/Rds(ON)min*1.3) =11*10E-6*(34K/(0.016*1.3))=17.981A Iripple=(vin-vout)*(Ton/L)=4.292A, 1/2Iripple=2.146A Iocp=Ivalley+Iripple/2
OCP==>12.346A~20.127A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2007/01/16
Issued Date
Deciphered Date
2008/01/16
4
3
Title
+1.05VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
A
2
Size Document Number Custom JDW50/JDY70 Date:
Monday, April 16, 2007
Rev
LA3771P Sheet 1
0.1 41
of
44
5
4
3
2
1
+5VS
B+
CPU_B+
PR64 0_1206_5% 5VS1 2 1
DL1_CPU
5
CPU_VID4
2
1
35
D4
PGND1
27
5
CPU_VID5
2
1
36
D5
GND
18
5
CPU_VID6
1
2
37
D6
CSP1
17
CSP1_CPU
71.5K_0402_1% 1 7
TIME
CSN1
16
CSN1_CPU
2
CCV
FB
12
FB_CPU
BST2
20
BST2_CPU
3
PSI
LX2
22
LX2_CPU
2
PWRGD
DL2
24
DL2_CPU
1
CLKEN
PGND2
23
POUT
CSN2_CPU
GNDS
13
2
2
+3VS
PR100 100_0402_5%
Iload = Ivalley + delta IL/2 Per phase, Iocp=23.279A~30.288A
PC69 1000P_0402_50V7K 1 2 CSP1_CPU
A
PC70 1000P_0402_50V7K 1 2 CSN1_CPU
@ PC42 100U_25V_M
PC47 0.1U_0603_25V7K 2 1
PC48 2200P_0402_50V7K 2 1
R2
R3
PR108 3.48K_0402_1% 1 2
A
Compal Electronics, Inc. 2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3
2
Ceq
Compal Secret Data Deciphered Date
PH4 10KB_0603_5%_ERTJ1VR103J 2
NTC 1
PC68 0.22U_0603_16V7K 放放Choke附附
2007/01/16
放放Choke附附
R1
1
Issued Date
4
Rdcr
PR109 0_0402_5% 1 2
Security Classification
5
PC46 10U_1206_25VAK 2 1
PC45 10U_1206_25VAK 2 1 1
25.5mV
B
PL8 0.36UH_PCMC104T-R36MN1R17_30A_20% 2 1
3 2 1
4
2
Rcs = Rdcr*(R2+R3)/(R1+R2+R3) Ivalley = VIlim / Rcs
PQ16 SI7686DP-T1-E3_SO8
PQ17 FDS6676AS_SO8
Valley current limit threshold : 19.5mV ~
2 100_0402_5%
CPU_B+
2
PC66 0.1U_0402_16V7K
PR85 0_0402_5%
PR97 20K_0402_1%
PC72 1000P_0402_50V7K 1 2 CSN2_CPU
1
PR105 10_0402_5%
PC71 1000P_0402_50V7K 1 2 CSP2_CPU
POUT
C
放放Choke附附
PC58 470P_0603_50V8J 1 2
2
PR103 0_0603_5% 1 2
1
PR104 10K_0402_5% 1 2 2
28
VSSSENSE
VF
5
VSSSENSE
0.22U_0603_16V7K
PC57 4700P_0402_25V7K
1
2
B
1
1
PR101 56_0402_5%
2
PR92
5 6 7 8
@ PR99 10K_0402_5% 1
PR98 0_0402_5%
VRHOT
1
1
VR_ON
2
28
MAX8770GTL+_TQFN40
41
14 CLK_ENABLE#
1
PC54
1
@ PR95 3K_0603_1% 1 2
@ PR94 3K_0603_1%
10KB_0603_5%_ERTJ1VR103J 1 2
@ PC56 1000P_0402_50V7K CPU_VCC_SENSE 1 2
3.65K_0402_1% 2 2
15
PR88
14
TP
6,14,20 VGATE
CSP2
CSN2
1
VRHOT
1K_0402_1% 2
PR91 1
BSTM2_CPU
1
4
SHDN
PC60 2 1
5
@ PR87 1
-c o
38
@ PR90 2K_0402_1%
PC59 4700P_0402_25V7K 1 2
2
2 1
PR89 2K_0402_1%
CSP2_CPU
PH3 2
放放Choke附附
PR86 0_0402_5% 1 2
1
DPRSTP
PC62 10U_1206_25VAK 2 1
40
2
DH2_CPU
PC61 10U_1206_25VAK 2 1
21
5
10
DH2
2
+3VS
2 0_0402_5% 2 0_0402_5%
CCI
DPRSLPVR
D D D D
PSI#
REF
G S S S
5
11
0.22U_0603_16V7K 39
CCI_CPU
4 3 2 1
1 PR83 1 PR84
4,19 H_DPRSTP#
PC55
9
PQ18 FDS6676AS_SO8
6,20 PM_DPRSLPVR
1 PC53 2
NTC PR79 3.48K_0402_1% 1 2 1
+CPU_CORE
5
LX1_CPU
26
VCCSENSE
28
DL1
1
LX1
D3
2
D2
34
PR80 10_0402_5% 2 1
33
1
PC65 2200P_0402_50V7K 2 1
1
2
PC64 0.1U_0603_25V7K 2 1
2
CPU_VID3
PL7 0.36UH_PCMC104T-R36MN1R17_30A_20% 2 1
PR107 2.1K_0402_1% 2 1
CPU_VID2
5
C
D
+CPU_CORE
PR71 0_0603_5% 1 2
2
PC63 10U_1206_25VAK 2 1
5
BSTM1_CPU 1
PR76 2.1K_0402_1% 1 2
DH1_CPU
PR106 4.7_1206_5%
29
PC67 680P_0402_50V7K
DH1
PR74 4.7_1206_5% 2 1
D1
PC52 680P_0402_50V7K 2 1
32
3 2 1
1
5 6 7 8
2
D D D D
BST1_CPU
CPU_VID1
G S S S
30
5
4 3 2 1
BST1
PQ15 FDS6676AS_SO8
D0
5 6 7 8
31
D D D D
1
G S S S
2
47P_0603_50V8J 1
2
4
-c c
CPU_VID0
PR82 499_0402_1% 1 2
PC44 10U_1206_25VAK 2 1
2
5
PR81 2
+
Use one 220uF or two 100uF PC51 0.22U_0603_16V7K
PR69 0_0603_5% 1 2
PQ14 FDS6676AS_SO8
TON
8
4 3 2 1
PR78 0_0402_5%
25
5 6 7 8
PR77 0_0402_5%
THRM
VDD
D D D D
PR75 0_0402_5%
Vcc
G S S S
PR73 0_0402_5%
6
4 3 2 1
PR72 0_0402_5%
19
0_0603_5%
PR70 0_0402_5%
VCC
0.22U_0603_16V7K
PR68 0_0402_5%
PQ13 SI7686DP-T1-E3_SO8
1
PU5
1
NTC PH2 @PH2 @ 100K_0603_1%_TH11-4H104FT 1 2
5
1
PR67 13K_0402_1%
1
2
2
PC49 PC50 2.2U_0603_6.3V6K 1U_0603_6.3V6M
PR66 200K_0402_5% 2 1
D
2
2
1
PR65 10_0402_5%
PC43 0.01U_0402_25V7K
1
PL6 FBMA-L18-453215-900LMA90T_1812 1 2
2
Title
+CPU_CORE Size Document Number Custom JDW50/JDY70 Date:
Rev 0.2
LA3771P
Monday, April 16, 2007
Sheet 1
42
of
44
5
4
3
2
Version change list (P.I.R. List) Item
Reason for change
EC GPIO pin modify
EC GPIO pin modify
2
clk frequency error
3 4
Rev.
PG#
Modify List
0.1 ==> 0.2
8
DPST_PWM net modify
pin error
0.1 ==> 0.2
14
Q48,Q49,Q50 pin error
EC add a GPIO pin
EC GPIO pin modify
0.1 ==> 0.2
16
del DPST_PWM net from North Bridge
follow ICL50
follow ICL50
20
CRT_DET# net modify
0.1 ==> 0.2
Date
EMI request
0.1 ==> 0.2
24
Add R477, R748
ESD request
ESD request
0.1 ==> 0.2
25
reserve D30,D31
7
test
test
0.1 ==> 0.2
26
reserve MINI1_LED#
8
Blue LED issue
Blue LED issue
0.1 ==> 0.2
27
BT_LED# schematic modify
0.1 ==> 0.2
28
EC GPIO pin define modify
0.1 ==> 0.2
29
reserve C895 to C904
0.1 ==> 0.2
30
change J1,J2 jumper sybmol to 0603 symbol
0.1 ==> 0.2
31
Add R751,R752,R753
0.1 ==> 0.2
32
U31 chip update version
-c c
EMI request
6
EC GPIO pin modify
EC GPIO pin modify
10
ESD request
ESD request
11
easy short
easy short
12
ESD request
ESD request
13
chip issue
chip issue
14
voice too small
modify gain value
0.1 ==> 0.2
32
change R472 form 39k to 30k ohm
15
EMI request
EMI request
0.1 ==> 0.2
32
change R523,R524,R50,R38,R26,R28 for 0 ohm to bead
16
DFX request
DFX request
0.1 ==> 0.2
33
del pjp15
17
Wireless Lan S4 fail
Wireless Lan fail
0.2 ==> 0.3
26
del R756, add R757
18
Wireless Lan S4 fail
Wireless Lan fail
0.2 ==> 0.3
26
change C906,C907 from 22u_1206 to 10u_0805
19
Lead Free
non LF==>Lead Free
0.2 ==> 0.3
17
change C211,C510,C514,C216,C508,C515
20
KBC version update
KBC version update
0.2 ==> 0.3
28
reserve 0.1u at pin 124
21
SPDIF udpate
SPDIF circuit udpate
0.2 ==> 0.3
32
add q59,q60
22
DFX
DFX issue
0.2 ==> 0.3
32
del JP13
24 25 26 27
D
3/19
5
23
Phase
C
-c o
B
Fixed Issue
1
9 C
Page 1 of 1 for PWR
VF
D
1
B
28 29 A
A
30 Compal Electronics, Inc. Title
PIR (HW)
5
4
3
2
Size
Document Number
Date:
Monday, April 16, 2007
LA-3771P
JDW50
Sheet 1
43
of
44
Rev 0.2
5
4
3
2
Version change list (P.I.R. List) Item
Page 1 of 1 for PWR
Fixed Issue
Reason for change
1
Charger IC damage issue
Charger IC damage issue
2
Charger IC damage issue
3 4
Modify List
Date
Phase
Change PR161 from SD013220B80 to SD013200A80
D
40
Charger IC damage issue
0.2
40
Charger IC damage issue
Charger IC damage issue
0.2
40
Charger IC damage issue
Charger IC damage issue
0.2
40
5
Charger IC damage issue
Charger IC damage issue
0.2
40
Add PC133 SE026473K80
6
Add EMI solution in charger.
Add EMI solution in charger.
0.3
40
Add PR199 SD001470B80(S RES 1/4 4.7 1206 5%).
04/01/07
PVT
7
Add EMI solution in charger.
Add EMI solution in charger.
0.3
40
Add PC163 SE074681K80(S CER CAP 680P 50V K X7R 0402)
04/01/07
PVT
9 10 11 12
Change PR162 from SD013180A80 to SD013200A80 Add PR197 SD013200A80 Add PR198 SD013220B80
C
-c o
13 14 15 16 17 18 19 20
B
VF
B
PG#
0.2
8
C
Rev.
-c c
D
1
21 22 23 24 25 26 27 28 29 A
A
30 Compal Electronics, Inc. Title
PIR (PWR)
5
4
3
2
Size
Document Number
Date:
Monday, April 16, 2007
LA-3121P
HCW51
Sheet 1
44
of
44
Rev 0.2
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