HP COMPAL LA-4732P UMA - REV 1.0
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Compal confidential
2
2
Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M core logic 3
3
2009-02-16 REV:1.0 4
4
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cover Sheet Rev 0.1
Montevina UMA
Date:
A
B
C
D
Wednesday, February 18, 2009
Sheet E
1
of
46
A
B
C
Compal confidential
D
E
Montevina Consumer UMA CK505
Mobile Penryn
Thermal Sensor EMC1402
1
72QFN
Clock Generator SLG8SP553V
uFCPGA-478 CPU
P06
1
P17
P6, 7, 8
Fan conn
P06
H_A#(3..35)
FSB
H_D#(0..63)
LVDS Panel Interface CRT
DDR2 800MHz 1.8V P19
Intel Cantiga MCH
HDMI
DDR2 SO-DIMM X2 BANK 0, 1, 2, 3
USB conn x1
P35
BT Conn
USB2.0 X12
PCI-E BUS*4
WLAN
Mini-Card WWAN
P26
P26
P19
Azalia
Intel ICH9-M Mini-Card
2
P30
C-Link USB Camera
P25
P30
P9,10, 11, 12, 13, 14
DMI X4
RTL8103EL (10/100M)
P15, 16
Dual Channel
FCBGA 1329 GM47
P18
Support V1.3 2
667/800/1066 MHz 1.05V
P30
SATA Slave
mBGA-676 New Card
Finger print
SATA Master-1
CardReader
SATA Slave
P20,21,22,23
P26
5 in1 Slot P27
Audio CKT
P27
AMP & Audio Jack
Codec_IDT92HD75B
TPA6047
P28
RJ45/11 CONN
LPC BUS
P25
3
P29
MDC
3
P28
SATA HDD Connector
P24
ENE KB926 P32
RTC CKT. P21
P30
P32
P33
P33
e-SATA Connector
Int.KBD
Touch Pad CONN.
LED
SATA ODD ConnectorP24
SPI
USB Board Conn USB port x2
SPI ROM SST25VF080P31
ACCELEROMETER-1 P24 ST
P30
4
4
K/B backlight Conn
Capsense switch Conn
P33
P33
Compal Secret Data
Security Classification
DC/DC Interface CKT.
2006/02/13
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P36
Block Diagram Rev 0.1
Montevina UMA
Date:
A
B
C
D
Wednesday, February 18, 2009
Sheet E
2
of
46
A
Voltage Rails
Symbol Note : O MEANS ON
X MEANS OFF
USB assignment:
: means Digital Ground : means Analog Ground
power plane +5VALW
+B
+1.5V
+5VS +3VS +1.5VS +0.75V +VCCP +CPU_CORE +2.5VS +1.8V
+3VALW
State
S0
O
O
O
O
S1
O
O
O
O
S3
O
O
O
X
S5 S4/AC
O
O
X
X
S5 S4/ Battery only
O
X
X
X
X
X
X
X
S5 S4/AC & Battery don't exist 1
@ : means just reserve , no build 45@ : means need be mounted when 45 level assy or rework stage. DEBUG@ : means just reserve for debug. BATT @ : means need be mounted when 45 level assy or rework stage. CONN@ : means ME part ESATA @ : means just reserve for ESATA GS @ : means just reserve for G sensor FP @ : means just reserve for Finger Print Multi @ : means just reserve for Multi Bay NewC@ : means just reserve for New card Main@ : means just reserve for Main stream OPP@ : means just reserve for OPP 2MiniC@ : means just reserve for 2nd Mini card slot PA @ : means just reserve for PA PR @ : means just reserve for PR
SMBUS Control Table SOURCE INVERTER BATT SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMB_CK_CLK1 SMB_CK_DAT1 LCD_CLK LCD_DAT
KB926 KB926 ICH9 Cantiga
USB-0 Right side(with eSATA) USB-1 Left side USB-2 Left side USB-3 Cardreader USB-4 Camera USB-5 WLAN USB-6 Bluetooth USB-7 Finger Printer USB-8 MiniCard(WWAN/TV) USB-9 Express card USB-10 X USB-11 X
X X X X
V X X X
SERIAL Thermal EEPROM Sensor
V X X X
X V X X
SODIMM CLK CHIP
X X V X
X X V X
MINI CARD
X X V X
LCD
X X X V
Cap sensor board
NEW CARD
V X X X
X X V X
PCIe-1 PCIe-2 PCIe-3 PCIe-4 PCIe-5 PCIe-6
WWAN X WLAN GLAN (Realtek) X New Card
I2C / SMBUS ADDRESSING DEVICE
HEX ADDRESS
DDR SO-DIMM 0 DDR SO-DIMM 1 CLOCK GENERATOR (EXT.)
A0 A4 D2
10100000 10100100 11010010
X X V X
Compal Secret Data 2007/08/28
Deciphered Date
2006/03/10
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Notes List Rev 0.1
Montevina UMA
Date:
A
1
G sensor
Security Classification Issued Date
PCIe assignment:
Wednesday, February 18, 2009
Sheet
3
of
46
5
4
3
2
1
60mA
50mA
25mA 1A D
+V_BATTERY
10mA 177mA
INVPWR_B+
ICH9
1.7A
+3VALW
278mA
LAN
VIN 2A
1A
LVDS CON 300mA
AC
5.89A
3.39A
B++
+3VS
1.5A
657mA
C
0.3A
0.58A
+1.5VS
+5VALW
2.2A 1.56A
1.3A
ICH_VCC1_5 ICH9
1A
ICH9
1A
35mA
+5VS
B+ 7A
10mA
1.8A
700mA B
3.7A
3.7 X 3=11.1V
1.9A
B+++
12.11A
DDR2
+1.8V 50mA
800Mhz
4.7A
New card ICH9 +LCDVDD
LVDS CON
1.05V_B+
10mA
+VCC_CORE
1.26A
+VCCP
34A/1.025V
+3VS_CK505 C
Mini card (WLAN) Mini card (TV tu/WWAN/Robeson)
+VDDA IDT 9275B +5VAMP ODD SATA
B
PC Camera(4.75V)
+0.9V
2.3A
CPU_B+
SPI ROM
4G x2
1.17A
2A
+3VALW_EC
MCH 50mA
BATT
+3VS_DVDD ALC268
RT5158 250mA
DC
Finger printer
D
20mA
0.3A
+3VAUX_BT
ICH9 MCH CPU
CPU
A
A
Compal Secret Data
Security Classification Issued Date
2007/08/28
Deciphered Date
2006/03/10
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Power delevry Size C Date:
5
4
3
2
Compal Electronics, Inc. Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009 1
Sheet
4
of
46
A
1
1
Compal Secret Data
Security Classification 2007/08/28
Issued Date
Deciphered Date
2006/03/10
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Notes List Rev 0.1
Montevina UMA
Date:
A
Wednesday, February 18, 2009
Sheet
5
of
46
5
4
3
2
1
ITP-XDP Connector +VCCP
XDP_TDI
R2
1
2
54.9_0402_1%
XDP_TMS
R3
1
2
54.9_0402_1%
XDP_TDO
R4
1
2
54.9_0402_1%
XDP_TRST#
R7
1
2
54.9_0402_1%
XDP_TCK
R8
1
2
54.9_0402_1%
D
9 H_A#[3..16]
JCPU1A
9 H_ADSTB#1
H_STPCLK# H_INTR H_NMI H_SMI#
H_A20M# H_FERR# H_IGNNE#
A6 A5 C4
H_STPCLK# H_INTR H_NMI H_SMI#
D5 C6 B4 A3
A20M# FERR# IGNNE#
B
RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]
H_BR0#
D20 B3
H_IERR# H_INIT#
LOCK#
H4
H_LOCK#
RESET# RS[0]# RS[1]# RS[2]# TRDY#
C1 F3 F4 G3 G2
H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY#
G6 E4
H_HIT# H_HITM#
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#
BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
THERMAL PROCHOT# THERMDA THERMDC THERMTRIP#
STPCLK# LINT0 LINT1 SMI#
M4 N5 T2 V3 B2 D2 D22 D3 F6
F1
IERR# INIT#
HIT# HITM#
A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
ICH
21 H_A20M# 21 H_FERR# 21 H_IGNNE#
H_DEFER# H_DRDY# H_DBSY#
BR0#
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
H5 F21 E1
DEFER# DRDY# DBSY#
ADDR GROUP_1
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1
C
H_ADS# H_BNR# H_BPRI#
D21 A24 B25 C7
A22 A21
This shall place near CPU
H_DEFER# 9 H_DRDY# 9 H_DBSY# 9 H_BR0# 9 T1 H_INIT# 21
Place TP with a GND 0.1" away
H_LOCK# 9 H_RESET# 9 H_RS#0 9 H_RS#1 9 H_RS#2 9 H_TRDY# 9 H_HIT# 9 H_HITM# 9
H_PROCHOT#
H CLK BCLK[0] BCLK[1]
H_ADS# 9 H_BNR# 9 H_BPRI# 9
H_THERMDA_R H_THERMDC_R H_THERMTRIP#
CLK_CPU_BCLK CLK_CPU_BCLK#
C
+3VS
0.1U_0402_16V4Z
K3 H2 K2 J3 L1
H1 E2 G5
ADS# BNR# BPRI#
CONTROL
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
XDP/ITP SIGNALS
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
XDP_DBRESET# 22
R13 R14 R15
1 1 1
2 56_0402_1% 2 0_0402_5% 2 0_0402_5%
+VCCP H_THERMDA H_THERMDC C3 1
H_THERMTRIP# 9,21
+3VS
CLK_CPU_BCLK 17 CLK_CPU_BCLK# 17
1 C2 U1
2 1 H_THERMDA
2
H_THERMDC 2 2200P_0402_50V7K THERM#
3
R16 1 2 10K_0402_5%
4
VDD
SMCLK
DP
SMDATA
DN
ALERT#
THERM#
GND
8
SMB_EC_CK2
7
SMB_EC_DA2
6
R6 1
SMB_EC_CK2 32 SMB_EC_DA2 32 2 10K_0402_5%
+3VS
5
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
RESERVED
9 H_REQ#0 9 H_REQ#1 9 H_REQ#2 9 H_REQ#3 9 H_REQ#4 9 H_A#[17..35]
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0
ADDR GROUP_0
9 H_ADSTB#0
21 21 21 21
D
B
Fan Control circuit SI-1 Change to voltage control circuit
Penryn +5VS +VCCP +3VS
FAN_SPEED
E
C
OCP# 3 1 @ Q1 MMBT3904_NL_SOT23-3
2.2U_0603_6.3V4Z
1
2
B
32 FAN_SPEED H_PROCHOT#
1
OCP# 22
C1510 1000P_0402_50V7K
2
U51
1
R1209 10K_0402_5%
2 2
1
C4 @ R17 56_0402_5%
1
9 8 7 6 5
Thermal Pad VEN GND VIN GND VO GND VSET GND
C5 0.1U_0402_16V4Z
2
1 2 3 4
+5VS_FAN 1
G996RD1U_TDFN8_3X3
2
CONN@ JFAN1
C1509
1 2 3
2.2U_0603_6.3V4Z
ACES_85204-03001
FAN_SPEED
+5VS
1 2 3
G1 G2
4 5
D63 2
3 2 1
32 FAN_SET
+VCCP A
Vcc Line to be protected GND
A
2
DLPT05-7-F_SOT23-3
1
R18 56_0402_5%
Compal Secret Data
Security Classification
H_IERR#
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. Penryn(1/3)-AGTL+/ITP-XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
6
of
46
4
3
2
1
+VCC_CORE
2 1K_0402_5% 2 1K_0402_5% T2 T3 T4 T5 T6 17 CPU_BSEL0 17 CPU_BSEL1 17 CPU_BSEL2
+V_CPU_GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]
MISC
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3
COMP[0] COMP[1] COMP[2] COMP[3]
R26 U26 AA1 Y1
COMP0 COMP1 COMP2 COMP3
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
E5 B5 D24 D6 D7 AE6
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI#
DATA GRP 2
Penryn
* Route the TEST3 and TEST5 signals through a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
166
0
1
1
200
0
1
0
266
0
0
0
H_DPRSTP# 9,21,42 H_DPSLP# 21 H_DPWR# 9 H_PWRGOOD 21 H_CPUSLP# 9 H_PSI# 42
R23
R24
R25
R26
Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
D
+VCCP R19
G21 +VCCPA +VCCPB V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
1 1
2 2
0_0402_5% 0_0402_5%
C
R20 1 + C6 330U_D2E_2.5VM_R7 2
B26 C26
VCCA[01] VCCA[02]
+1.5VS
AD6 AF5 AE5 AF4 AE3 AF3 AE2
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
AF7
VCCSENSE
AE7
VSSSENSE
42 42 42 42 42 42 42
1 C7 2
1 C8 2
Near pin B26
VCCSENSE 42 VSSSENSE 42
B
Penryn .
Length match within 25 mils. The trace width/space/other is 20/7/25. +VCCP 1
B
H_DSTBN#3 9 H_DSTBP#3 9 H_DINV#3 9
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
0.01U_0402_16V7K
1 1
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#
H_DSTBN#2 9 H_DSTBP#2 9 H_DINV#2 9 H_D#[48..63] 9
27.4_0402_1% 2 1
@ R21 @ R22
D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]#
JCPU1C
54.9_0402_1% 2 1
9 H_DSTBN#1 9 H_DSTBP#1 9 H_DINV#1
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
DATA GRP 1
C
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2
27.4_0402_1% 2 1
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16..31]
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
DATA GRP 3
9 9 9 9
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#
DATA GRP 0
D
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
+VCC_CORE
H_D#[32..47] 9
JCPU1B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0
54.9_0402_1% 2 1
9 H_D#[0..15]
10U_0805_6.3V6M
5
2
+V_CPU_GTLREF
+VCC_CORE
1
R27 1K_0402_1%
R28
1
2 100_0402_1%
VCCSENSE
R30
1
2 100_0402_1%
VSSSENSE
2
R29 2K_0402_1%
Close to CPU pin within 500mils.
Close to CPU pin AD26 within 500mils.
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
A
Compal Electronics, Inc. Penryn(2/3)-AGTL+/ITP-XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
7
of
46
5
4
3
2
1
+VCC_CORE
1
Place these capacitors on L8 (North side,Secondary Layer)
2
1
C9 10U_0805_6.3V6M
2
1
C10 10U_0805_6.3V6M
2
1
C11 10U_0805_6.3V6M
2
1
C12 10U_0805_6.3V6M
2
1
C13 10U_0805_6.3V6M
2
C14 10U_0805_6.3V6M
1
2
1
C15 10U_0805_6.3V6M
2
C16 10U_0805_6.3V6M
D
D
+VCC_CORE JCPU1D
B
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
Place these capacitors on L8 (North side,Secondary Layer)
1
2
1
C17 10U_0805_6.3V6M
2
1
C18 10U_0805_6.3V6M
2
1
C19 10U_0805_6.3V6M
2
1
C20 10U_0805_6.3V6M
2
1
C21 10U_0805_6.3V6M
2
C22 10U_0805_6.3V6M
1
2
1
C23 10U_0805_6.3V6M
2
C24 10U_0805_6.3V6M
+VCC_CORE
Place these capacitors on L8 (North side,Secondary Layer)
1
2
1
C25 10U_0805_6.3V6M
2
1
C26 10U_0805_6.3V6M
2
1
C27 10U_0805_6.3V6M
2
1
C28 10U_0805_6.3V6M
2
1
C29 10U_0805_6.3V6M
2
C30 10U_0805_6.3V6M
1
2
1
C31 10U_0805_6.3V6M
2
C32 10U_0805_6.3V6M
+VCC_CORE
Place these capacitors on L8 (North side,Secondary Layer)
1
2
1
C33 10U_0805_6.3V6M
2
1
C34 10U_0805_6.3V6M
2
1
C35 10U_0805_6.3V6M
2
1
C36 10U_0805_6.3V6M
2
1
C37 10U_0805_6.3V6M
2
C38 10U_0805_6.3V6M
1
2
1
C39 10U_0805_6.3V6M
2
C40 10U_0805_6.3V6M C
Mid Frequence Decoupling
ESR 1980uF
Near CPU CORE regulator
1 C41
+ 2
@ C42
1 + 2
1 +
C43
2
1 +
C44
2
330U_D2_2VY_R7M
+VCC_CORE
330U_D2_2VY_R7M
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
330U_D2_2VY_R7M
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
330U_D2_2VY_R7M
C
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
B
+VCCP
1
2
C45 0.1U_0402_10V6K
Inside CPU center cavity in 2 rows 1
2
1
C46 0.1U_0402_10V6K
2
1
C47 0.1U_0402_10V6K
2
1
C48 0.1U_0402_10V6K
2
1
C49 0.1U_0402_10V6K
2
C50 0.1U_0402_10V6K
Penryn .
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. Penryn(3/3)-AGTL+/ITP-XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
8
of
46
4
3
B15 K13 F13 B13 B14
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_CPURST# H_CPUSLP#
B6 F12 C8
H_RS#0 H_RS#1 H_RS#2
H_RS#_0 H_RS#_1 H_RS#_2
2 1 2
1
2 10K_0402_5%
CLKREQ#_7
R40
1
2 10K_0402_5%
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
7 7 7 7
C54
H_RS#0 6 H_RS#1 6 H_RS#2 6
2
PLT_RST#
within 100 mils from NB
0.1U_0402_16V4Z
R41 R42
22 PM_BMBUSY# 7,21,42 H_DPRSTP# 15 PM_EXTTS#0 16 PM_EXTTS#1 22,32 PM_PWROK 1 2 1 2 100_0402_5% 0_0402_5%
PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_PWROK THERMTRIP# DPRSLPVR
1 @ C55 2
1
+1.8V
R55
C59
2 1
1
2
R48 10K_0402_1%
C57 2
221_0603_1% 2 1
+H_SWNG
1
V_DDR_MCH_REF 0.1U_0402_16V4Z
R54
CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
R45 10K_0402_1%
15,16 V_DDR_MCH_REF
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
BA17 AY16 AV16 AR13
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
BD17 AY17 BF15 AY13
M_ODT0 M_ODT1 M_ODT2 M_ODT3
BG22 BH21
SMRCOMP SMRCOMP#
BF28 BH28
SMRCOMP_VOH SMRCOMP_VOL
AV42 AR36 BF17 BC36
V_DDR_MCH_REF SM_PWROK SM_REXT TP_SM_DRAMRST#
B38 A38 E41 F41
CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK#
F43 E43
CLK_MCH_3GPLL CLK_MCH_3GPLL#
AE41 AE37 AE47 AH39
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
AE40 AE38 AE48 AH40
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
AE35 AE43 AE46 AH42
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
AD35 AE44 AF46 AH43
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST#
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
11 CFG5 11 CFG6 11 CFG7 11 CFG8 11 CFG9 11 CFG10 11 CFG11 11 CFG12 11 CFG13 11 CFG14 11 CFG15 11 CFG16 11 CFG17 11 CFG18 11 CFG19 11 CFG20
6 6 6 6 6
R47
BC28 AY28 AY36 BB36
PEG_CLK PEG_CLK#
2
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
R29 B7 N33 P32 AT40 AT11 T20 R32
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
15 15 16 16
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
15 15 16 16
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
15 15 16 16
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
15 15 16 16
M_ODT0 M_ODT1 M_ODT2 M_ODT3 R34 R35
D
15 15 16 16
+1.8V
1 1
2 80.6_0402_1% 2 80.6_0402_1%
1 1
2 0_0402_5% 2 499_0402_1%
Follow Design Guide For Cantiga: 80.6ohm
R36 R37 T29
CLK_MCH_DREFCLK 17 CLK_MCH_DREFCLK# 17 MCH_SSCDREFCLK 17 MCH_SSCDREFCLK# 17 CLK_MCH_3GPLL 17 CLK_MCH_3GPLL# 17 C
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
T85 T86 7 7 7 7
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1
CLK
R39
17 MCH_CLKSEL0 17 MCH_CLKSEL1 17 MCH_CLKSEL2
+V_DDR_MCH_REF generated by DC-DC
0.1U_0402_16V4Z
C58
100_0402_1% 2 1
0.1U_0402_16V4Z
24.9_0402_1% 2 1
1K_0402_1% 1 2 2K_0402_1% 2 1
PM_EXTTS#1
7 7 7 7
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
2 10K_0402_5%
AR24 AR21 AU24 AV20
SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
DMI
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
1
NC
H_RCOMP
RESERVED RESERVED RESERVED RESERVED
PM
+H_VREF
R52
0.01U_0402_25V7K
2.2U_0603_6.3V4Z C53 H_ADS# 6 H_ADSTB#0 6 H_ADSTB#1 6 H_BNR# 6 H_BPRI# 6 H_BR0# 6 H_DEFER# 6 H_DBSY# 6 CLK_MCH_BCLK 17 CLK_MCH_BCLK# 17 H_DPWR# 7 H_DRDY# 6 H_HIT# 6 H_HITM# 6 H_LOCK# 6 H_TRDY# 6
+VCCP
R46
T25 T26 T27 T28
BG23 BF23 BH18 BF18
R38
Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20. +VCCP
RESERVED
+3VS
20,25,26 PLT_RST# 6,21 H_THERMTRIP# 22,42 DPRSLPVR
Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20
AY21
PM_EXTTS#0
H_AVREF H_DVREF
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
1
2
CANTIGA ES_FCBGA1329
Layout note:
A
2
T24 R33 1K_0402_1%
SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
GFX_VR_EN
B33 B32 G33 F33 E33
T30 T31
C34
T35
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
22 22 22 22
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
22 22 22 22
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
22 22 22 22
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
22 22 22 22
B
+VCCP 1
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
1
RESERVED RESERVED RESERVED
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
AH37 AH36 AN36 AJ35 AH34
CL_CLK0 CL_DATA0 M_PWROK CL_RST# +CL_VREF
0621 add CLK and DAT for DVI DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN#
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
N28 M28 G36 E36 K36 H36 B12
T36 T37
HDMICLK_NB HDMIDAT_NB CLKREQ#_7 MCH_ICH_SYNC# TSATN#
R43 1K_0402_1%
CL_CLK0 22 CL_DATA0 22 M_PWROK 22,32 CL_RST# 22
B28 B30 B29 HDA_SDIN2_NB C29 A28
C56 0.1U_0402_16V4Z HDMICLK_NB 34 HDMIDAT_NB 34 CLKREQ#_7 17 MCH_ICH_SYNC#
1 R737
2
H_SWING H_RCOMP
SMRCOMP_VOL
1
T22 T23
B31 B2 M1
DDR CLK/ CONTROL/COMPENSATION
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
1
L9 M8 AA6 AE5
20% of 1.8V VCC_SM
1
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
R32 3.01K_0402_1%
2
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
C52
L10 M7 AA5 AE6
2.2U_0603_6.3V4Z C51
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
80% of 1.8V VCC_SM
AP24 AT21 AV24 AU20
1
A11 B11
J8 L3 Y13 Y1
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
B
+H_VREF
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
2
SMRCOMP_VOH
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1
1
22
2 56_0402_5% +VCCP TSATN# 32
HDA_BITCLK_NB 21 R210 HDA_RST#_NB 21 1 HDA_SDOUT_NB 21 HDA_SYNC_NB 21
R44 499_0402_1%
2
2
C12 E11
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
2
R31 1K_0402_1%
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
GRAPHICS VID
H_RESET# H_CPUSLP#
6 H_RESET# 7 H_CPUSLP#
H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
1
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24
ME
C5 E3
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
1
+1.8V
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20
CFG
+H_SWNG H_RCOMP
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
1
MISC
C
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
HOST
D
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6
RSVD
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
0.01U_0402_25V7K
U2A
7 H_D#[0..63]
2
U2B
H_A#[3..35] 6
HDA
5
*R44*Follow Intel feedback
2
HDA_SDIN2 21
33_0402_5%
0830 Add pull-up and pull-down resistor.
CANTIGA ES_FCBGA1329
Compal Secret Data
Security Classification
Near B3 pin
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. Cantiga(1/6)-AGTL/DMI/DDR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
9
of
46
A
5
4
3
2
1
D
D
16 DDR_B_D[0..63]
B
BB20 BD20 AY20
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
SA_RAS# SA_CAS# SA_WE#
DDR_A_RAS# 15 DDR_A_CAS# 15 DDR_A_WE# 15
A
DDR_A_DM[0..7] SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_A_BS0 15 DDR_A_BS1 15 DDR_A_BS2 15
15
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
15
15
DDR_A_MA[0..14] 15
CANTIGA ES_FCBGA1329
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE#
B
DDR_A_BS0 DDR_A_BS1 DDR_A_BS2
MEMORY
BD21 BG18 AT25
SA_BS_0 SA_BS_1 SA_BS_2
MEMORY
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SYSTEM
C
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
DDR
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
U2E
SYSTEM
U2D
DDR
15 DDR_A_D[0..63]
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
BC16 BB17 BB33
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
AU17 BG16 BF14
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
DDR_B_BS0 16 DDR_B_BS1 16 DDR_B_BS2 16 DDR_B_RAS# 16 DDR_B_CAS# 16 DDR_B_WE# 16
DDR_B_DM[0..7] 16
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
16
16
C
DDR_B_MA[0..14] 16
B
CANTIGA ES_FCBGA1329
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. Cantiga(2/6)-DDR2 A/B CH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
10
of
46
5
4
2
1
Strap Pin Table
ENBKL
2 10K_0402_5%
ENAVDD R60 1
H47 E46 G40 A40
LVDS_A0+ LVDS_A1+ LVDS_A2+ LVDS_A3+
H48 D45 F40 B40
LVDS_B0LVDS_B1LVDS_B2LVDS_B3-
A41 H38 G37 J37
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3
LVDS_B0+ LVDS_B1+ LVDS_B2+ LVDS_B3+ TV_COMPS TV_LUMA TV_CRMA
B42 G38 F37 K37
LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
1 R66
R67
E28 G28 J28 G29
18 3VDDCCL 18 3VDDCDA 18 CRT_HSYNC
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3
TVA_DAC TVB_DAC TVC_DAC TV_RTN
2
HSYNC
2
VSYNC
H32 J32 J29 E29 L29
TV_DCONSEL_0 TV_DCONSEL_1
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
CRT_BLUE
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
1
18 CRT_VSYNC
3VDDCCL 3VDDCDA CRT_HSYNC R68 1 30.1_0402_1% CRT_VSYNC R69 1 30.1_0402_1%
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
VGA
2
C31 E32
150_0402_1%
150_0402_1%
R65
150_0402_1%
Follow Intel DG & Checklist
H24
2.2K_0402_5% 0_0402_5%
2 2
1
1 1
1
18 M_BLUE 18 M_GREEN 18 M_RED
@ R64 R406 M_BLUE M_GREEN M_RED
2
2 +3VS
R63
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3
TV
R62
75_0402_1%
R61
75_0402_1%
75_0402_1%
Follow Intel DG & Checklist
C
F25 H25 K25
1
T41 T48 T49 T50
LVDS_A0LVDS_A1LVDS_A2LVDS_A3-
L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
2
T40
LVDS_ACLKLVDS_ACLK+ LVDS_BCLKLVDS_BCLK+
1
T39
L_CTRL_DATA L_DDC_CLK L_DDC_DATA
PEG_COMPI PEG_COMPO
LVDS
T38
M33 K33 J33 M29 C44 B43 E37 E38 C41 C40 B37 A37
2 4.75K_0402_1%
2
19 ENAVDD
Follow Intel DG & Checklist
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK
R70 1.02K_0402_1%
T37 T36
CFG[2:0] FSB Freq select
PEGCOMP trace width and spacing is 20/25 mils.
H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40
000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved Reserved CFG[4:3] 0 = DMI x 12 = DMI x CFG5 (DMI select) * Interface is 40 = The iTPM Host CFG6 enable 1 = The iTPM Host Interface is disable 0 =(TLS)chiper suite with no CFG7 (Intel Management confidentiality =(TLS)chiper suite with Engine Crypto strap) 1confidentiality Reserved CFG8
+VCC_PEG
R57 1 2 49.9_0402_1%
TMDS_B_HPD#
CFG9 (PCIE Graphics Lane Reversal)
TMDS_B_HPD# 34
TMDS_BDATA2# TMDS_BDATA1# TMDS_BDATA0# TMDS_BCLK#
J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
TMDS_BDATA2 TMDS_BDATA1 TMDS_BDATA0 TMDS_BCLK
C274 C275 C276 C277
1 1 1 1
2 2 2 2
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
TMDS_B_DATA2# 34 TMDS_B_DATA1# 34 TMDS_B_DATA0# 34 TMDS_B_CLK# 34
CFG[13:12] (XOR/ALLZ) CFG[15:14]
CFG16 (FSB Dynamic ODT) 01 == Disabled
Enabled Reserved
CFG[18:17] 1 1 1 1
2 2 2 2
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
*
CFG20 (PCIE/SDVO concurrent)
C
*
(Lane number in Operation 1 = Order) Reverse Lane
TMDS_B_DATA2 34 TMDS_B_DATA1 34 TMDS_B_DATA0 34 TMDS_B_CLK 34
*
*
CFG19 (DMI Lane Reversal) 0 = Normal C278 C279 C280 C281
*
0 = Reverse Lane,15->0, 114->1 = Normal Operation,Lane Number in order 0= Enable 1 = Disable * Reserved 00 = Reserved 01 = XOR Mode 10 = All Z Mode Enabled 11 = Normal (Default) Enabled * Operation Reserved
CFG10 (PCIE Lookback CFG11 enable)
J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46
D
0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.
*
+3VS
1
R59 1 DDC2_CLK DDC2_DATA
19 DDC2_CLK 19 DDC2_DATA
D
2 10K_0402_5%
GRAPHICS
19 NB_BKLT_CTRL 32 ENBKL +3VS
100K_0402_5%
L32 G32 M32
PCI-EXPRESS
NB_BKLT_CTRL ENBKL R58 1
1
2
2
1
3
U2C
R148
+3VS
@ R71 4.02K_0402_1%
CANTIGA ES_FCBGA1329 B
2
B
9 CFG16
2
CFG5
1
9 CFG5
9 CFG19
@ R74 2.21K_0402_1%
1 2 4.02K_0402_1%
@ R73
1 2 4.02K_0402_1%
@R75
1 2 4.02K_0402_1%
2
9 CFG20
@ R72
For 3G WWAN
LVDS_ACLK+
19 LVDS_ACLK+
LVDS_ACLKLVDS_A0+
19 LVDS_ACLK19 LVDS_A0+ 19 LVDS_A019 LVDS_A1+ 19 LVDS_A119 LVDS_A2+
2 1
LVDS_A0LVDS_A1+
2 1
LVDS_A1LVDS_A2+
2 1
LVDS_A2-
19 LVDS_A2-
1
2
@ C60 0.1U_0402_10V6K @ C61 0.1U_0402_10V6K @ C62 0.1U_0402_10V6K @ C63 0.1U_0402_10V6K
For 3G WWAN
19 LVDS_BCLK+ 19 LVDS_BCLK19 LVDS_B0+ 19 LVDS_B019 LVDS_B1+ 19 LVDS_B119 LVDS_B2+ 19 LVDS_B2-
9 CFG11 LVDS_BCLK+ LVDS_BCLKLVDS_B0+
1
2 1
LVDS_B0LVDS_B1+
2 1
LVDS_B1LVDS_B2+
2 1
LVDS_B2-
2
9 CFG12
@ C1500 0.1U_0402_10V6K
9 CFG13
@ C1501 0.1U_0402_10V6K
9 CFG6 9 CFG7
@ C1502 0.1U_0402_10V6K
9 CFG8
@ C1503 0.1U_0402_10V6K
9 CFG9
A
9 CFG10
1 2 2.21K_0402_1%
2007/08/28
2006/03/10
Deciphered Date
9 CFG14
@ R81
1 2 2.21K_0402_1%
@R83
1 2 2.21K_0402_1%
@R84
1 2 2.21K_0402_1%
9 CFG17
@R86
1 2 2.21K_0402_1%
9 CFG18
Compal Secret Data
Security Classification Issued Date
@R79
Title
9 CFG15
@R76
1 2 2.21K_0402_1%
@ R77
1 2 2.21K_0402_1%
@ R78
1 2 2.21K_0402_1%
@R80
1 2 2.21K_0402_1%
@R82
1 2 2.21K_0402_1%
@R85
1 2 2.21K_0402_1%
@R87
1 2 2.21K_0402_1%
Compal Electronics, Inc. Cantiga(3/6)-VGA/LVDS/TV
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
A
2
Wednesday, February 18, 2009
Sheet 1
11
of
46
5
4
+3VS_DAC_BG
C82
C81
VTT
C80
CRT PLL A LVDS A PEG A SM
AXF SM CK
A CK
0.1U_0402_16V4Z
VCCD_LVDS VCCD_LVDS
60.31mA
PEG DMI
K47
+1.8V_TXLVDS
2
2
+ C100
2
10U_0805_10V4Z
+1.05VS_PEGPLL
VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG
V48 U48 V47 U47 U46
+VCC_PEG
VCC_DMI VCC_DMI VCC_DMI VCC_DMI
AH48 AF48 AH47 AG47
+1.05VS_DMI
1
2
1
2
1
1
2 2
+VCCP_D
VTTLF VTTLF VTTLF
A8 L1 AB2
D3 2
+VCCP
R105 1 2 10_0402_5%
1
2
1
2
0.47U_0603_10V7K C112
1
1
2
2006/03/10
Deciphered Date
Title
R108 1 2 0_0603_5%
1
+1.8V
C116
2007/08/28
+1.8V
2
Compal Secret Data
Security Classification Issued Date
1
+1.8V_TXLVDS
1000P_0402_50V7K
2
2
R107 1 2 0_0603_5% C114
1
C113
2
C120
1
R112 1 2 100_0603_1%
1
40 mils 1U_0603_10V4Z
10U_0805_10V4Z
+1.5VS
0.1U_0402_16V4Z
2
C119
1
0.022U_0402_16V7K
C118
2
R111 1 2 BLM18PG181SN1D_0603
+3VS_HV
+3VS
+3VS
0.1U_0402_16V4Z
C117
1
0.022U_0402_16V7K
A
R106 1 2 0_0402_5%
CH751H-40PT_SOD323-2 0.47U_0603_10V7K C111
+1.5VS_QDAC
+VCCP R104 1 2 0_0603_5%
B
+1.8V_LVDS
+3VS_TVDAC
1
2
+1.05VS_DMI
+VCCP L1 1 2 BLM18PG121SN1D_0603
+3VS_HV
C35 B35 A35
0.47U_0603_10V7K C110
CANTIGA ES_FCBGA1329
+1.8V_SM_CK
1
456mA
VTTLF
50mA
LVDS
VCCD_PEG_PLL
VCC_HV VCC_HV VCC_HV
HV
TV HDA
157.2mA
BF21 BH20 BG20 BF20
1
R102 1 2 0_0805_5%
1
118.8mA
1732mA
48.363mA
C99
VCC_TX_LVDS
D TV/CRT
VCCD_HPLL
+V1.05VS_AXF
10U_0805_10V4Z
+1.8V_LVDS
M38 L37
VCCD_QDAC
B22 B21 A21
124mA
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
105.3mA
58.67mA
+VCCP
0.1U_0402_16V4Z C109
AA47
VCCD_TVDAC
2
C101
+1.05VS_PEGPLL
50mA
VCC_AXF VCC_AXF VCC_AXF
+VCCP R101 1 2 MBK2012121YZF_0805
C108
AF1
C85
+1.05VS_MPLL
10U_0805_10V4Z
L28
+1.5VS_QDAC +1.05VS_HPLL
VCC_HDA
2
1
+VCC_PEG
TVA 24.15mA TVB 39.48mA TVX 24.15mA VCCA_TV_DAC VCCA_TV_DAC
1
R99 1 2 0_0805_5%
C
C107
M25
VCCA_SM_CK VCCA_SM_CK 26mA VCCA_SM_CK VCCA_SM_CK 26mA VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF
1
2
C106
A32
1
2
0.1U_0402_16V4Z
+1.5VS
C79
POWER
0.1U_0402_16V4Z
+3VS_TVDAC
B24 A24
+1.5VS_TVDAC B
720mA
+1.5VS
220U_D2_4VM
2
2
+1.5VS_TVDAC
+VCCP R98 1 2 MBK2012121YZF_0805
C98
C105
2
1
0.1U_0402_16V4Z
C104
2
1
1U_0603_10V4Z
2
1
10U_0805_10V4Z
1U_0603_10V4Z
1
C103
C102
VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM
+1.05VS_HPLL
321.35mA AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23
+1.05VS_A_SM_CK
R103 1 2 0_0603_5%
VCCA_PEG_PLL
C97
2 1U_0603_10V4Z
1
0.1U_0402_16V4Z
2
2
R95 1 2 0_0805_5%
0.1U_0402_16V4Z
4.7U_0805_10V4Z
1U_0603_10V4Z
2
1
2
1
C93
2
1
C96
1
C92
220U_D2_4VM
1
@
10U_0805_10V4Z
C95
C94
+
10U_0805_10V4Z
1
2
C91
+1.05VS_A_SM R100 1 2 0_0805_5%
2
1
C90
+VCCP
AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
2
+1.8V
0.022U_0402_16V7K
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
AA48
+1.05VS_PEGPLL
C89
1
VCCA_PEG_BG
50mA 1
2
10U_0805_10V4Z
AD48
+1.5VS_PEG_BG
VSSA_LVDS
1
C78
R97 1 2 0_0603_5%
VCCA_LVDS
414uA
2
+VCCP R94 1 2 10U_FLC-453232-100K_0.25A_10%
C84
+1.5VS
J47
2
10U_0805_10V4Z
+3VS
C88
+VCCP R93 1 2 0_0603_5%
+1.8V_SM_CK +1.05VS_DPLLB
C83
1
1000P_0402_50V7K 2
2
1
10U_0805_10V4Z
+1.8V_TXLVDS
@ R96 1 2 0_0603_5%
C
139.2mA
VCCA_MPLL
13.2mA J48
1
10U_0805_10V4Z
AE1
VCCA_HPLL
1
2
10U_0805_10V4Z
+1.05VS_MPLL
24mA
C74
2
64.8mA
C87
VCCA_DPLLB
AD1
0.1U_0402_16V4Z
L48
+1.05VS_HPLL
1
1 2 R90 10U_FLC-453232-100K_0.25A_10%
D
C86
+1.05VS_DPLLB
64.8mA
2
1
2
0.1U_0402_16V4Z
VCCA_DPLLA
2
1
2.2U_0805_16V4Z
F47
+1.05VS_DPLLA
0.1U_0402_16V4Z
C76
0.022U_0402_16V7K
C75
2
R91 1 2 BLM18PG181SN1D_0603
+
4.7U_0805_10V4Z
VCCA_DAC_BG VSSA_DAC_BG
1
C72
A25 B25
+3VS_DAC_BG
U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
0.47U_0603_10V7K
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
VCCA_CRT_DAC VCCA_CRT_DAC
+3VS
1
+VCCP +V1.05VS_AXF
C71
+3VS_DAC_CRT
+3VS_DAC_CRT
1
+1.05VS_DPLLA
C73
852mA 73mA B27 A26
2.68mA D
+VCCP
1
U2H 4.7U_0805_10V4Z
2
2
220U_D2_4VM
2
1
R88 2 BLM18PG181SN1D_0603
10U_0805_10V4Z
1
C70 0.1U_0402_16V4Z
C69
2
0.022U_0402_16V7K
C68
1
1
3
**RED Mark: Means UMA & dis@ Power select** ~It check by INTEL Graphics Disable Guidelines~
+3VS
2 A
Compal Electronics, Inc. Cantiga(4/6)-PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
12
of
46
5
4
3
2
1
+VCCP
U2G
1
BA36 BB24 BD16 BB21 AW16 AW13 AT13
VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC
1U_0603_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
1 GM47@ C134 + C1508 2
2
330U_D2E_2.5VM_R7
1
1 C138
2
2
2
10U_0805_10V4Z
1 @ C1491 2
1 @ C1494 2
22P_0402_25V8K
2
1 C137
2
22P_0402_25V8K
22P_0402_25V8K
1 @ C1493
1 C136
22P_0402_25V8K
2
+ C135
22P_0402_25V8K
1 @ C1490
1
1 @ C1492 2
1 @ C1495 2
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
Reserve for WWAN
1
4.7U_0603_6.3V6M 1
C127
2
2
0.22U_0402_10V4Z
C
2
1
2
Compal Secret Data 2007/08/28
2006/03/10
Deciphered Date
Title
1
2
1
2
1U_0603_10V4Z
1
1U_0603_10V4Z
2
C145
1
0.47U_0402_6.3V6K
2
C144
1
C143
2
0.22U_0603_10V7K
1
0.22U_0603_10V7K
AV44 VCCSM_LF1 BA37 VCCSM_LF2 AM40 VCCSM_LF3 AV21 VCCSM_LF4 AY5 VCCSM_LF5 AM10 VCCSM_LF6 BB13 VCCSM_LF7
C142
VCC_AXG_SENSE VSS_AXG_SENSE
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
CANTIGA ES_FCBGA1329
Issued Date
C129 D
2
A
Security Classification
1
C128
C141
AJ14 AH14
0.1U_0402_16V4Z
C140 0.1U_0402_16V4Z
PAD T42 PAD T43
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
C139 0.1U_0402_16V4Z
CANTIGA ES_FCBGA1329
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
B
VCC GFX
+VCCP
SI-1 Add C for GM47
Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14
VCC GFX NCTF
6326.84mA
22P_0402_25V8K
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
330U_D2E_2.5VM_R7
B
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
VCC SM LF
2
2
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29
VCC SM
2
1
+VCCP
POWER
VCC
2
1
0317 change value
VCC NCTF
T32
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
+
VCC CORE
AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23
1
C123
2
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
10U_0805_10V4Z C122
2
1
C125
C
2
1
0.1U_0402_16V4Z C133
2
1
0.22U_0402_10V4Z C132
2
1
0.22U_0402_10V4Z C124
+
10U_0805_10V4Z C131
220U_D2_4VM
1
AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33
10U_0805_10V4Z C126
D
+1.8V 0.01U_0402_16V7K C130
+VCCP
Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA
330U_D2E_2.5VM_R7
U2F
POWER
3000mA
Compal Electronics, Inc. Cantiga(5/6)-PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
A
2
Wednesday, February 18, 2009
Sheet 1
13
of
46
5
4
3
2
1
U2J
C
B
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6
BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13
CANTIGA ES_FCBGA1329
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS NCTF
D
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS SCB
AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36
BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17
NC
U2I
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4
D
BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1
C
U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17
B
BH48 BH1 A48 C1 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48
CANTIGA ES_FCBGA1329
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. Cantiga(6/6)-PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
14
of
46
5
4
3
2
1
+1.8V
+1.8V V_DDR_MCH_REF
10 DDR_A_DQS#[0..7]
2
DDR_A_D18 DDR_A_D19 DDR_A_D29 DDR_A_D24 DDR_A_DM3 DDR_A_D26 DDR_A_D27
C
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
9 DDR_CKE0_DIMMA 10 DDR_A_BS2
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
2
1
2
10 DDR_A_BS0 10 DDR_A_WE# 1
10 DDR_A_CAS# 9 DDR_CS1_DIMMA#
DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# M_ODT1
9 M_ODT1 2
DDR_A_D37 DDR_A_D36
C170
C169
C168
C167
C166
C165
C164
C163
C162
C161
C160
C159
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
C158
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8
+0.9V
1
DDR_CKE0_DIMMA
DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D39 DDR_A_D38 DDR_A_D45 DDR_A_D44
B
Layout Note: Place these resistor closely JP3,all trace length Max=1.5"
+0.9V RP30
1 2 3 4
8 7 6 5
1 2 3 4
8 7 6 5
56_8P4R_0.05
56_8P4R_0.05
RP31
RP32
DDR_A_MA8 DDR_A_MA5 DDR_A_MA1 DDR_A_MA3
1 2 3 4
8 7 6 5
1 2 3 4
DDR_A_MA14 DDR_CKE1_DIMMA DDR_A_MA6 DDR_A_MA7
DDR_A_D47 DDR_A_D46 DDR_A_D49 DDR_A_D48
DDR_A_DQS#6 DDR_A_DQS6 8 7 6 5
DDR_A_MA2 DDR_A_MA4 DDR_A_BS1 DDR_A_MA0
DDR_A_D54 DDR_A_D50
56_8P4R_0.05
56_8P4R_0.05
DDR_A_D61 DDR_A_D60
RP33
RP34
DDR_A_DM7
DDR_A_BS0 DDR_A_MA10 DDR_A_CAS# DDR_A_WE#
1 2 3 4
8 7 6 5
56_8P4R_0.05
1 2 3 4
8 7 6 5
DDR_A_MA13 M_ODT0 DDR_CS0_DIMMA# DDR_A_RAS#
DDR_A_D59 DDR_A_D58 16,17,24 CLK_SMBDATA 16,17,24 CLK_SMBCLK +3VS
56_8P4R_0.05
A
56_0404_4P2R_5% RP11 DDR_CS1_DIMMA# 2 M_ODT1 1
3 4
DDR_A_MA11
2
1
2.2U_0603_6.3V4Z
+0.9V
CLK_SMBDATA CLK_SMBCLK
1
1 C171 C172
2
R117 56_0402_5%
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
FOX_ASOA426-M4R-TR CONN@
SO-DIMM A
DDR_A_D6 DDR_A_D7
2006/02/13
2006/03/10
Deciphered Date
1
2
1
2
D
DDR_A_D13 DDR_A_D12 DDR_A_DM1 M_CLK_DDR0 M_CLK_DDR#0
M_CLK_DDR0 9 M_CLK_DDR#0 9
DDR_A_D15 DDR_A_D14
DDR_A_D20 DDR_A_D21 PM_EXTTS#0 9
DDR_A_DM2 DDR_A_D23 DDR_A_D22 DDR_A_D28 DDR_A_D25 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D31 DDR_A_D30 DDR_CKE1_DIMMA
C
DDR_CKE1_DIMMA 9
DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 DDR_A_MA13
DDR_A_BS1 10 DDR_A_RAS# 10 DDR_CS0_DIMMA# 9 M_ODT0 9
DDR_A_D32 DDR_A_D33 DDR_A_DM4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 B
DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D43 DDR_A_D42 DDR_A_D52 DDR_A_D53 M_CLK_DDR1 M_CLK_DDR#1
M_CLK_DDR1 9 M_CLK_DDR#1 9
DDR_A_DM6 DDR_A_D51 DDR_A_D55 DDR_A_D57 DDR_A_D56 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63
A
Compal Secret Data
Security Classification Issued Date
2
0.1U_0402_16V4Z
RP29 DDR_A_BS2 DDR_CKE0_DIMMA DDR_A_MA12 DDR_A_MA9
DDR_A_DM5
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1
DDR_A_DM0
R116 10K_0402_5% 2 1
DDR_A_DQS#2 DDR_A_DQS2
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
DDR_A_D5 DDR_A_D0
R115 10K_0402_5% 2 1
2
+
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
DDR_A_D16 DDR_A_D17
1 C150
C157
2
1
330U_D2E_2.5VM_R7
0.1U_0402_16V4Z
1
C149
2
0.1U_0402_16V4Z
2
1
C148
C156
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C155
C154
2
1
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
C153
2
2.2U_0805_16V4Z
C147
2.2U_0805_16V4Z
C152
2.2U_0805_16V4Z
2
1
203
+1.8V
VSS
DDR_A_D11 DDR_A_D10
204
DDR_A_DQS#1 DDR_A_DQS1
VSS
DDR_A_D8 DDR_A_D9
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
C151
DDR_A_D2 DDR_A_D3
Layout Note: Place near JP3
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
C146
DDR_A_DQS#0 DDR_A_DQS0
10 DDR_A_MA[0..14]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
0.1U_0402_16V4Z
DDR_A_D4 DDR_A_D1
10 DDR_A_DQS[0..7]
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2.2U_0805_16V4Z
10 DDR_A_DM[0..7]
D
V_DDR_MCH_REF 9,16
JDIMM1
10 DDR_A_D[0..63]
Title
Compal Electronics, Inc. DDRII-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
15
of
46
5
4
3
2
1
+1.8V
+1.8V
10 DDR_B_DQS#[0..7] V_DDR_MCH_REF
10 DDR_B_D[0..63]
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
DDR_B_D21 DDR_B_D20 DDR_B_DQS#2 DDR_B_DQS2
2
DDR_B_D19 DDR_B_D18 DDR_B_D28 DDR_B_D25 DDR_B_DM3
C
DDR_B_D30 DDR_B_D31
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
DDR_CKE2_DIMMB
9 DDR_CKE2_DIMMB
DDR_B_BS2
10 DDR_B_BS2
DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
+0.9V
1
2
1
2
1
2
1
2
1
2
1
2
1
DDR_B_CAS# DDR_CS3_DIMMB#
10 DDR_B_CAS# 9 DDR_CS3_DIMMB# 2 C196
C195
C194
C193
C192
C191
C190
C189
C188
C187
C186
C185
C184
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
DDR_B_MA10 DDR_B_BS0 DDR_B_WE#
10 DDR_B_BS0 10 DDR_B_WE#
M_ODT3
9 M_ODT3
DDR_B_D32 DDR_B_D37 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35
Layout Note: Place these resistor closely JP3,all trace length Max=1.5"
B
+0.9V +0.9V RP35 56_0404_4P2R_5% RP14 DDR_B_MA3 1 DDR_B_MA1 2
4 3
1 2 3 4
8 7 6 5
DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6
DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49
56_8P4R_0.05 56_0404_4P2R_5% RP16 DDR_B_BS0 1 DDR_B_MA10 2
4 3
56_0404_4P2R_5% RP24 DDR_CS3_DIMMB# 2 M_ODT3 1
3 4
RP36 1 2 3 4
8 7 6 5
DDR_B_MA4 DDR_B_MA2 DDR_B_BS1 DDR_B_MA0
DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D54 DDR_B_D55
56_8P4R_0.05 DDR_B_D60 DDR_B_D61
RP37 DDR_CKE3_DIMMB 1 R120
2 56_0402_5%
1 2 3 4
8 7 6 5
DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 DDR_B_MA13
DDR_B_DM7 DDR_B_D63 DDR_B_D58
56_8P4R_0.05
56_8P4R_0.05 RP39 1 2 3 4
8 7 6 5
DDR_B_MA8 DDR_B_MA5 DDR_B_WE# DDR_B_CAS#
1
1 C197
2
56_8P4R_0.05
2
FOX_AS0A426-N8RN-7F CONN@
2006/02/13
SO-DIMM B 2006/03/10
Deciphered Date
M_CLK_DDR2 M_CLK_DDR#2
M_CLK_DDR2 9 M_CLK_DDR#2 9
DDR_B_D14 DDR_B_D15
DDR_B_D16 DDR_B_D17 PM_EXTTS#1 9
DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D29 DDR_B_D24 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D26 DDR_B_D27
C
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB 9
DDR_B_MA14
0612 add
DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB#
DDR_B_BS1 10 DDR_B_RAS# 10 DDR_CS2_DIMMB# 9
M_ODT2 DDR_B_MA13
M_ODT2 9
DDR_B_D36 DDR_B_D33 DDR_B_DM4 DDR_B_D39 DDR_B_D38 DDR_B_D44 DDR_B_D45
B
DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 M_CLK_DDR3 M_CLK_DDR#3
M_CLK_DDR3 9 M_CLK_DDR#3 9
DDR_B_DM6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D59 DDR_B_D62 R118 1
2
3
2
+3VS
10K_0402_5%
Title
Date:
4
2
DDR_B_DM1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
2
1
D
Compal Secret Data
Security Classification Issued Date
C198
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
DDR_B_BS2 DDR_CKE2_DIMMB DDR_B_MA9 DDR_B_MA12
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
1
DDR_B_D12 DDR_B_D13
R119
A
8 7 6 5
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1
DDR_B_D6 DDR_B_D7
10K_0402_5%
1 2 3 4
CLK_SMBDATA CLK_SMBCLK
15,17,24 CLK_SMBDATA 15,17,24 CLK_SMBCLK +3VS
RP38
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
DDR_B_DM0
1
2
1
C181
C180
2
1
0.1U_0402_16V4Z
C179
2
1
0.1U_0402_16V4Z
C178
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C177
C183
2
1
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
C176
2
2.2U_0805_16V4Z
2
1
C175
C174
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
201
+1.8V
DDR_B_D5 DDR_B_D4
A
2
DDR_B_D10 DDR_B_D11
VSS
DDR_B_DQS#1 DDR_B_DQS1
202
DDR_B_D8 DDR_B_D9
VSS
DDR_B_D2 DDR_B_D3
Layout Note: Place near JP10
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
C182
DDR_B_DQS#0 DDR_B_DQS0
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
C173
DDR_B_D0 DDR_B_D1
10 DDR_B_MA[0..14]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
0.1U_0402_16V4Z
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2.2U_0805_16V4Z
10 DDR_B_DQS[0..7]
D
V_DDR_MCH_REF 9,15
JDIMM2
10 DDR_B_DM[0..7]
Compal Electronics, Inc. DDRII-SODIMM SLOT2 Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
16
of
46
5
CLKSEL0
CPU MHz
SRC MHz
PCI MHz
REF MHz
DOT_96 MHz
USB MHz
100
33.3
14.318
96.0
48.0
0
0
0
266
0
0
1
133
100
33.3
14.318
96.0
48.0
0
1
0
200
100
33.3
14.318
96.0
48.0
0
1
1
166
100
33.3
14.318
96.0
48.0
1
0
0
333
100
33.3
14.318
96.0
48.0
1
0
1
100
100
33.3
14.318
96.0
48.0
1
0
1
1
1
400
100
33.3
1
10U_0805_10V4Z
Routing the trace at least 10mil CLK_XTAL_OUT
1 2 R129 1K_0402_5%
CLK_XTAL_IN
1
1
C202 0.1U_0402_16V4Z
2
1
C203 0.1U_0402_16V4Z
2
1
C204 0.1U_0402_16V4Z
2
1
C205 0.1U_0402_16V4Z
2
C1496 47P_0402_50V8J
For WWAN
2
0.1U_0402_16V4Z 1 C206 C207
2 10U_0805_10V4Z
48.0
C213 18P_0402_50V8J
NB CPU
9 9 6 6
9 CLKREQ#_7 CLK_MCH_BCLK# CLK_MCH_BCLK CLK_CPU_BCLK# CLK_CPU_BCLK
1
D
10U_0805_10V4Z 0.1U_0402_16V4Z 1 1 1 C209 C210 C211
C208
1
47P_0402_50V8J 1 1 C212 C1506 C1507
2
2
1
1
2
2 0.1U_0402_16V4Z
2
2 0.1U_0402_16V4Z
2
2 2 0.1U_0402_16V4Z
C214 18P_0402_50V8J
2 47P_0402_50V8J
For WWAN
+1.05VS_CK505
R126
1
R_CLKREQ#_7
2 475_0402_1%
R_CLKREQ#_6
R133
1
2
CLK_MCH_3GPLL 9 CLK_MCH_3GPLL# 9 CLKREQ#_6 26 CLK_PCIE_MCARD2 26 CLK_PCIE_MCARD2# 26
475_0402_1%
+3VS_CK505
U3
2
1 1 1
2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
R_CKPWRGD FSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CLK_XTAL_OUT CLK_XTAL_IN
@ R143 1K_0402_5% R147
22 CLK_14M_ICH
1
2
@ R141 @ R142 R140
MCH_CLKSEL1 9
15,16,24 CLK_SMBDATA 15,16,24 CLK_SMBCLK R393 1
26 CLK_DEBUG_PORT_1 32 CLK_PCI_EC 20 CLK_PCI_ICH
2
1
R158
1
R161
1
2 33_0402_1% FSC REF1 CLK_SMBDATA T44 CLK_SMBCLK 2 39_0402_1% PCI2_1 PCI2_TME T83 2 33_0402_1% 27_SEL PCI_CLK3 2 33_0402_1% ITP_EN
73
@ R163 1K_0402_5%
1 2 R165 1K_0402_5%
MCH_CLKSEL2 9
R167 1 R1101 1
22 CLK_48M_ICH 27 CLK_48M_CR
CKPWRGD/PD# FS_B/TEST_MODE VSS_REF XTAL_OUT XTAL_IN VDD_REF REF_0/FS_C/TEST_ REF_1 SDA SCL NC VDD_PCI PCI_1 PCI_2 PCI_3 PCI_4/SEL_LCDCL PCIF_5/ITP_EN VSS_PCI thm_pad
+3VS_CK505
SI-1 Using USB_0 for CLK_48M_CR
2
1 7 CPU_BSEL2
2
Place close to U3
3G_PLL MiniCard_2(WLAN)
+1.05VS_CK505 C
PCI_STOP# CPU_STOP# VDD_SRC_IO SRC_10# SRC_10 CLKREQ_10# SRC_11 SRC_11# CLKREQ_11# SRC_9# SRC_9 CLKREQ_9# VSS_SRC CLKREQ_4# SRC_4# SRC_4 VDD_SRC_IO CLKREQ_3#
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
H_STP_PCI# H_STP_CPU#
H_STP_PCI# 22 H_STP_CPU# 22
R_CLKREQ#_10
R146
1
2 475_0402_1%
CLK_PCIE_MCARD0# 26 CLK_PCIE_MCARD0 26 CLKREQ#_10 26
MiniCard_0
R_CLKREQ#_9
R738
1
2 475_0402_1%
CLK_PCIE_LAN# 25 CLK_PCIE_LAN 25 CLKREQ#_9 25
LAN
R_CLKREQ#_4
R156
1
2 475_0402_1%
R_CLKREQ#_C
R162
1
2 475_0402_1%
CLKREQ#_4 26 CLK_PCIE_NCARD# 26 CLK_PCIE_NCARD 26
+1.05VS_CK505
NB (UMA)
SATA
CLK_PCIE_ICH# 22 CLK_PCIE_ICH 22
ICH
MCH_SSCDREFCLK# 9 MCH_SSCDREFCLK 9
NB_SSC (UMA)
2
9 CLK_MCH_DREFCLK 9 CLK_MCH_DREFCLK#
B
CLK_PCIE_SATA# 21 CLK_PCIE_SATA 21
+1.05VS_CK505 @ R174 0_0402_5%
New Card
CLKREQ#_C 22
SLG8SP553VTR_QFN72_10x10
FSA
2 22_0402_1% 2 22_0402_1%
1
FSC
0.1U_0402_16V4Z
+1.05VS_CK505
R122 1 2 0_0805_5%
+VCCP
R164 1 2 10K_0402_5% R171 1 2 0_0402_5%
1
C201
14.318MHZ_16PF_7A14300083
22,42 VGATE 42 CLK_ENABLE# 22 CK_PWRGD
@ R157 0_0402_5%
B
2
+VCCP
+3VS_CK505
1
7 CPU_BSEL1
0.1U_0402_16V4Z
+VCCP
MCH_CLKSEL0 9
1 2 R150 1K_0402_5%
R154 1 2 0_0402_5%
1
C200
+3VS_CK505 2
+VCCP
FSB
2
Y1
56_0402_5% CLRP1 NO SHORT PADS
2
1
C199
2
@ R139 1K_0402_5%
C
1
1
R128 1 2 2.2K_0402_5% R138 1 2 0_0402_5%
7 CPU_BSEL0
96.0
2
0_0805_5%
Reserved R123 1
FSA
14.318
+3VS_CK505 R121 1
1
1
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1
+3VS
VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO CLKREQ_7# SRC_8/CPU_ITP SRC_8#/CPU_ITP# VDD_SRC_IO SRC_7 SRC_7# VSS_SRC CLKREQ_6# SRC_6 SRC_6# VDD_SRC
FSA
CLKSEL1
2
VDD_48 USB_0/FS_A USB_1/CLKREQ_A# VSS_48 VDD_IO SRC_0/DOT_96 SRC_0#/DOT_96# VSS_IO VDD_PLL3 LCDCLK/27M LCDCLK#/27M_SS VSS_PLL3 VDD_PLL3_IO SRC_2 SRC_2# VSS_SRC SRC_3 SRC_3#
D
FSB
3
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
FSC
CLKSEL2
4
+3VS
R178
1
2
Q3B 3
CLK_SMBDATA
1
2N7002DW-7-F_SOT363-6 CLK_SMBCLK
4
2N7002DW-7-F_SOT363-6
@ R182 10K_0402_5%
2
1
CLK_48M_CR
2
1
CLK_48M_ICH
2
1
CLK_14M_ICH
2
1
CLK_PCI_ICH
2
1
CLK_PCI_EC
2
1
CLK_DEBUG_PORT_1 A
Install C217,C218,C219 for WWAN noise
PCI_CLK3 1
ITP_EN 1
SB, MINI PCI22,26 ICH_SMBCLK
@ R181 10K_0402_5%
@ C1482 5P_0402_50V8C @ C215 5P_0402_50V8C C216 12P_0402_50V8J @ C217 47P_0402_50V8J @ C218 47P_0402_50V8J @ C219 47P_0402_50V8J
2.2K_0402_5%
2
R180 10K_0402_5%
6
22,26 ICH_SMBDATA 5
+3VS
R179
2
2.2K_0402_5% Q3A
+3VS
A
EMI
+3VS
R183 10K_0402_5%
2007/08/28
Issued Date 2
Compal Secret Data
Security Classification
2006/03/10
Deciphered Date
Title
2
PCI_CLK3
0= SRC8/SRC8# 1= 0ITP/ITP# = Enable DOT96 & SRC1(UMA) 1 = Enable SRC0 & 27MHz(DIS)
1
ITP_EN
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. Clock Generator CK505 Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
17
of
46
B
C
D
E
BLUE GREEN RED
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
RED GREEN BLUE
+5VS
R186 2.2K_0402_5%
A
3
Y
4
VSYNC_G_A
D_VSYNC
2 0_0603_5%
D_DDCDATA
U5 SN74AHCT1G125GW_SOT353-5
1 @ C223 2
2
1 3
2
1
1 1 6
1 @ C224
5P_0402_50V8C
R187 2.2K_0402_5% 2 2
R185 2.2K_0402_5%
1 Q5A
5P_0402_50V8C
2N7002DW-7-F_SOT363-6 3
D_DDCCLK
2
R188 2.2K_0402_5% 3VDDCDA
3VDDCDA 11
5
2
R189 1
+CRTVDD
+3VS
1
D_HSYNC
2 0_0603_5%
5 1
3
CRT_VSYNC
G
11 CRT_VSYNC
R184 1
1
+3VS
2
A
1
2
+CRTVDD
2
CRT_HSYNC
Place close to JCRT1
16 17
SUYIN_070546FR015S263ZR CONN@
U4 SN74AHCT1G125GW_SOT353-5 HSYNC_G_A Y 4 P OE#
11 CRT_HSYNC
C222 0.1U_0402_16V4Z 1 2
+CRTVDD
G
2
P OE#
5 1
C221 0.1U_0402_16V4Z 1 2
2
2
+5VS
1
1
0.1U_0402_16V4Z C220 JCRT1
3
W=40mils
2
1.1A_6VDC_FUSE
@ D7 DAN217T146_SC59-3
1 RB491D_SC59-3
2
2
F1 1
@ D6
3
D4
@ D5
+CRTVDD
DAN217T146_SC59-3
+RCRT_VCC
2
+5VS
1
DAN217T146_SC59-3
A
3VDDCCL
4
3VDDCCL 11
Q5B 2N7002DW-7-F_SOT363-6
CRT Termination/EMI Filter 3
3
11 M_RED 11 M_GREEN
150_0402_1%
150_0402_1% R197 2 1
1 R195 2
BLUE
1
2
1
2
1
2
1
2
@ C225 @ C226 @ C227
1
2
1
2
10P_0402_50V8J
GREEN
L4 1 2 HLC0603CSCCR11JT_0603
10P_0402_50V8J
L3 1 2 HLC0603CSCCR11JT_0603
C_BLU
10P_0402_50V8J
C_GRN
22P_0402_50V8J
RED
22P_0402_50V8J
L2 1 2 HLC0603CSCCR11JT_0603
22P_0402_50V8J
150_0402_1% R196 2 1
11 M_BLUE
C_RED
C228 C229 C230
4
4
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Compal Electronics, Inc. CRT Connector Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet E
18
of
46
5
4
LVDS CONN & USB Camera + Dig Mic +LCDVDD
DMIC_DAT DMIC_CLK +3V_LOGO
R727 1 100_0805_5%
BKOFF# DDC2_CLK DDC2_DATA
2 2 @ R1237
DMIC_DAT 28 DMIC_CLK 28 +5VS INV_PWM 1 0_0402_5%
2 R1238
1
2
2
C232
D61 4
VIN
IO1
2
3
IO2 GND
1
2
USB20_N4
100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J
2 2 2N7002DW-7-F_SOT363-6 Q8A
S 2 G
1
100K_0402_5% C238 0.047U_0402_16V7K
INV_PWM 32 BKOFF# 32
Limited Current < 1A
Q8B 2N7002DW-7-F_SOT363-6
5
11 ENAVDD
1 0_0402_5%
NB_BKLT_CTRL 11
R201 100K_0402_5%
C
2 C434 680P_0402_50V7K
Avoid Panel display garbage after power on.
B+
Must close JLVDS1pin 24、26
+3VS
INVPWR_B+ @ L5
1
2
0_0805_5%
DDC2_CLK DDC2_DATA
R203 2.2K_0402_5%
@ C302 220P_0402_25V8J
1
R202 2.2K_0402_5%
EMI request
L6 1 2 FBMA-L11-201209-221LMA30T_0805
DMIC_DAT
2
2
DMIC_CLK
1
2 2 2 2 2 2
1 C234
EMI request.
PRTR5V0U2X_SOT143-4
@ C1399 1 @ C1400 1 @ C1401 1 @ C1402 1 @ C1504 1 @ C1505 1
2
2 R200 2
0.1U_0402_16V4Z
1
+5VALW
3
D
1
C233 4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.1U_0402_16V4Z
1 1
R199 1M_0402_5% 6 2
C231
DDC2_CLK 11 DDC2_DATA 11
ACES_88242-4001 CONN@
LVDS_ACLK+ LVDS_ACLKDDC2_CLK DDC2_DATA LVDS_BCLK+ LVDS_BCLK-
@ R245 10K_0402_5%
+USB_CAM
C
USB20_P4
R198 100_0805_5%
3
LVDS_B0+ LVDS_B0LVDS_B1+ LVDS_B1LVDS_B2+ LVDS_B2-
+LCDVDD
LVDS_A2- 11 BKOFF# LVDS_A2+ 11 LVDS_A1- 11 LVDS_A1+ 11 LVDS_A0- 11 LVDS_A0+ 11 LVDS_ACLK- 11 LVDS_ACLK+ 11
4
11 11 11 11 11 11
LVDS_B0+ LVDS_B0LVDS_B1+ LVDS_B1LVDS_B2+ LVDS_B2-
LVDS_A2LVDS_A2+ LVDS_A1LVDS_A1+ LVDS_A0LVDS_A0+ LVDS_ACLKLVDS_ACLK+
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
+3VS Q7 SI2301BDS-T1-E3_SOT23-3
1
LVDS_BCLK+ LVDS_BCLK-
11 LVDS_BCLK+ 11 LVDS_BCLK-
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND
1
1
+3VS
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GND
1
JLVDS1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41
+5VALW 1
+LCDVDD
USB20_P4 USB20_N4
22 USB20_P4 22 USB20_N4
D
2
2
2
1
1
INVPWR_B+
C237
680P_0402_50V7K
1 2
680P_0402_50V7K
C235 C236 D
2
1
+LCDVDD
680P_0402_50V7K
+3VS
3
1
1
2
2
@ C303 220P_0402_25V8J
EMI reserver B
B
USB Camera +5VS
+USB_CAM
OUT
R1091 215K_0603_1%
5
GND
1
1
3
SHDN
BYP
4
G916-390T1UF_SOT23-5
C1391
10U_0805_6.3V6M 2 R1093 100K_0402_1%
2
2
R440 0_0402_5% 1
C1392 10U_0805_6.3V6M
1
2
2
2
IN
1
U42 1
A
+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm +USB_CAM=1.25(1+R1091/R1093)
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. LCD CONN. Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
19
of
46
5
4
3
2
1
+3VS
PCI_TRDY#
2 8.2K_0402_5%
PCI_FRAME#
R277 1
2 8.2K_0402_5%
PCI_IRDY#
R278 1
2 8.2K_0402_5%
PCI_SERR#
R279 1
2 8.2K_0402_5%
PCI_PERR#
U12B D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3
+3VS
R281 1
2 8.2K_0402_5%
PCI_PIRQA#
R283 1
2 8.2K_0402_5%
PCI_PIRQC#
R284 1
2 8.2K_0402_5%
PCI_PIRQD#
R286 1
2 8.2K_0402_5%
PCI_PIRQF#
R288 2
1 8.2K_0402_5%
PCI_PIRQH#
R292 1
2 8.2K_0402_5%
PCI_REQ2#
R293 1
2 8.2K_0402_5%
PCI_REQ3#
+3VS R272 1
2 8.2K_0402_5%
PCI_DEVSEL#
R290 1
2 8.2K_0402_5%
PCI_REQ1#
R273 1
2 8.2K_0402_5%
PCI_STOP#
R276 1
2 8.2K_0402_5%
PCI_PLOCK#
C
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
RP28 1 2 3 4
8 7 6 5
PCI_PIRQE# PCI_PIRQB# PCI_PIRQG# PCI_REQ0#
J5 E1 J6 C4
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
PCI
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3#
D8 B4 D6 A5
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
D3 E3 R1 C6 E4 C2 J4 A4 F5 D7
PLTRST# PCICLK PME#
PCI_REQ0# PCI_GNT0# PCI_REQ1#
D
PCI_REQ2# PCI_REQ3# PCI_GNT3#
Place closely pin D4 CLK_PCI_ICH PCI_IRDY# PCI_RST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
C14 D4 R2
PLT_RST# CLK_PCI_ICH PCI_PME#
H4 K6 F2 G2
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PCI_RST# 32
@ R280 10_0402_5%
PCI_SERR# 32
1
2
PLT_RST# 9,25,26 CLK_PCI_ICH 17 PCI_PME# 32
@ C425 8.2P_0402_50V
C
Interrupt I/F PIRQA# PIRQB# PIRQC# PIRQD# ICH9-M ES_FCBGA676
F1 G4 B6 A7 F13 F12 E6 F6
1
2 8.2K_0402_5%
R275 1
2
D
R274 1
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
1 R291
2 0_0402_5%
ACCEL_INT 24
8.2K_0804_8P4R_5%
A16 swap override Strap B
PCI_GNT3# PCI_GNT3#
Low= A16 swap override Enble High= Default* @R294 1
Boot BIOS Strap PCI_GNT0#
2 1K_0402_5%
SPI_CS#1
B
Boot BIOS Location
0
1
SPI
1
0
PCI
1
1
LPC
* +3VALW
22 SPI_CS1#_R
SPI_CS1#_R
@ R295 1
PCI_GNT0#
@ R296 1
2 1K_0402_5% 2 1K_0402_5%
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. ICH9(1/4)-PCI/INT Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
20
of
46
5
4
3
2
ICH9M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
R300 1 R302
LAN100_SLP
ICH9M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05)
ICH_INTVRMEN ICH_SRTCRST#
D
C426 0.1U_0402_16V4Z
1
2
@ R303
ICH_LAN100_SLP
@ R304
E25 C13 F14 G13 D14 D13 D12 E13
+1.5VS
R312
28 HDA_BITCLK_CODEC
R207 9 HDA_BITCLK_NB 28 HDA_SYNC_CODEC
33_0402_5%
1
2
33_0402_5% 1 2 R316 33_0402_5% R208 R317
9 HDA_SYNC_NB 28,32 HDA_RST#_CODEC
1
33_0402_5% 33_0402_5%
R209
9 HDA_RST#_NB
R311 24.9_0402_1% 1 2 R259 HDABITCLK 1 2 0_0402_5% 2
1 1
33_0402_5%
2 2
1
2
28 HDA_SDIN0 9 HDA_SDIN2 28 HDA_SDOUT_CODEC 9 HDA_SDOUT_NB
R321 R204
33_0402_5% 33_0402_5%
1 1
2 2 PAD T55 PAD T56
P- HDD
SATA_RXN0_C SATA_RXP0_C SATA_TXN0 SATA_TXP0
0.01U_0402_16V7K C431 1 2 C433 1 2
SATA_TXN0 SATA_TXP0
Add 12p on HDA_SDOUT and HDA_SDOUT Add 12p on HDA_BITCLK_CODE and HDA_BITCLK_NB HDA_SDOUT_CODEC
C312 1
2
12P_0402_50V8J
HDA_SDOUT_NB
C66
1
2
12P_0402_50V8J
HDA_BITCLK_CODEC
C316 1
2
12P_0402_50V8J
HDA_BITCLK_NB
C67
2
12P_0402_50V8J
1
GLAN_CLK
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD_0 LAN_TXD_1 LAN_TXD_2 GPIO56 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC
AE7
HDA_RST#
HDA_SDIN0 HDA_SDIN2
AF4 AG4 AH3 AE5
HDA_SDOUT
AG5
SATA_TXN0_C SATA_TXP0_C
AG8
AH13 AJ13 AG14 AF14
@ R306 1 2 56_0402_5%
LPC_FRAME# 26,32
T54
1
AJ26
R_H_FERR#
R310
1
AD22
H_PWRGOOD
IGNNE#
AF25
H_IGNNE#
INIT# INTR RCIN#
AE22 AG25 L3
H_INIT# H_INTR KB_RST#
NMI SMI#
AF23 AF24
H_NMI H_SMI#
AH27
H_STPCLK#
AG26
THRMTRIP_ICH#
FERR#
TP12 SATA4RXN SATA4RXP SATA4TXN SATA4TXP
+VCCP
PAD
GATEA20 32 H_A20M# 6
R308 56_0402_5%
H_DPRSTP# 2 0_0402_5%
H_DPRSTP# 7,9,42 H_DPSLP# 7
H_FERR# 2 56_0402_5%
H_FERR# 6
H_PWRGOOD 7 H_IGNNE# 6
within 2" from R379
H_INIT# 6 H_INTR 6 KB_RST# 32
+VCCP C
H_NMI 6 H_SMI# 6
R315 56_0402_5%
H_STPCLK# 6 R319
2 54.9_0402_1%
1
H_THERMTRIP# 6,9
placed within 2" from ICH9M
AG27 AH11 AJ11 AG12 AF12
SATA_TXN4_C SATA_TXP4_C
0.01U_0402_16V7K 2 1 C428 2 1 C429
SATA_RXN4_C 24 SATA_RXP4_C 24 SATA_TXN4 24 SATA_TXP4 24
SATA_TXN4 SATA_TXP4
ODD
0.01U_0402_16V7K
SATALED# SATA5RXN SATA5RXP SATA5TXN SATA5TXP
SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP
LPC_FRAME#
R309
SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS
AH9 AJ9 AE10 AF10 AH18 AJ18 AJ7 AH7
SATA_TXN5_C SATA_TXP5_C
2 2
SATA_RXN5_C 30 SATA_RXP5_C 30 SATA_TXN5 30 SATA_TXP5 30
0.01U_0402_16V7K SATA_TXN5 1 C430 SATA_TXP5 1 C432 0.01U_0402_16V7K
CLK_PCIE_SATA# CLK_PCIE_SATA R322
e-SATA De-feature disable
CLK_PCIE_SATA# 17 CLK_PCIE_SATA 17
1 2 24.9_0402_1%
Within 500 mils
ICH9-M ES_FCBGA676
SI-1 Remove SSC
H_DPSLP#
J3 J1
H_DPRSTP_R# H_DPSLP#
CPUPWRGD
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34
K3
AJ25 AE23
STPCLK#
HDA_SDOUT
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
GATEA20 H_A20M#
THRMTRIP# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3
K5 K4 L6 K2
N7 AJ27
DPRSTP# DPSLP#
AF6 AH4
AJ16 AH16 AF17 AG17
LDRQ0# LDRQ1#/GPIO23 A20GATE A20M#
HDARST#
AG7 AE8
FWH4/LFRAME#
LAN_RSTSYNC
HDA_BITCLK HDA_SYNC
0.01U_0402_16V7K
B
B10 B28 B27
SATA_LED#
33 SATA_LED# 24 24 24 24
GLAN_COMP
@ R305 1 2 56_0402_5%
1
2
INTVRMEN LAN100_SLP
LPC
B22 A22
CPU
ICH_INTVRMEN LAN100_SLP
RTCRST# SRTCRST# INTRUDER#
RTC
1U_0603_10V4Z
A25 F20 C22
LAN / GLAN
C427
1
ICH_RTCRST# ICH_SRTCRST# SM_INTRUDER#
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
IHDA
CLRP2 SHORT PADS
2
1
+RTCVCC
H_DPRSTP# LPC_AD[0..3] 26,32
RTCX1 RTCX2
SATA
R307 1 2 20K_0402_5%
R301 1 2 10K_0402_5% +VCCP
U12A C23 C24
KB_RST#
D
Low = Internal VR Disabled High = Internal VR Enabled(Default)
ICH_RTCX1 ICH_RTCX2
GATEA20
R298 1 2 8.2K_0402_5%
2
1
+3VS
Low = Internal VR Disabled High = Internal VR Enabled(Default)
1
1 R299
ICH_INTVRMEN
SM_INTRUDER#
0_0402_5% 2 1
R297
2 1M_0402_5% 2 330K_0402_5% 2 330K_0402_5% 2 180K_0402_5%
0_0402_5% 2 1
1
2
+RTCVCC
C
1
B
Reserve cap on HDA_BITCLK for WWAN noise issue
Reserve SSC for EMI
BATT1
XOR CHAIN ENTRANCE STRAP:RSVD +3VS
@ +RTCVCC
@ R325 1 @ R326 1
BATT1.1
HDA_SDOUT_CODEC 2 1K_0402_5% ICH_RSVD 2 1K_0402_5%
ICH_RSVD 22
ICH_RTCX1
W=20mils
R329 1
W=20mils 2
D8 2
1
3 W=20mils
0_0402_5% R328 1 A
ICH_RSVD HDA_SDOUT_CODEC
0 0 1 1
1
ICH_RTCX2
2
10M_0402_5% C436 15P_0402_50V8J
0 1 0 1
1
1
2
2
2
4
2
3
32.768KHZ_12.5P_MC-146
2006/03/10
Deciphered Date
C435
PV for ESD
Title
JBATT1 1 2 3 4
0.1U_0402_16V4Z
1
1 2 GND GND ACES_85205-02001 CONN@
2
Compal Electronics, Inc. ICH9(2/4)_LAN,HD,IDE,LPC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
4
W=20mils 2
1K_0402_5%
2.2U_0603_6.3V4Z
Compal Secret Data 2007/08/28
Issued Date
R330 1
C438
15P_0402_50V8J
Security Classification
1
DAN202U_SC70
Place near ICH9
C437
Y2
5
CR2032 RTC BATTERY
+3VL
3
2
Wednesday, February 18, 2009
Sheet 1
21
of
46
A
R331 1 R332 1
+3VALW
+3VS
3
2
1
Place closely pin AF3 CLK_48M_ICH
2 2.2K_0402_5% 2 2.2K_0402_5%
R359 @ R361 R362
EC_SCI# CR_CPPE# CR_WAKE#
32 EC_LID_OUT# 17 H_STP_PCI# 17 H_STP_CPU#
R345
GPIO20 GPIO21
R353
1 2 100K_0402_5%
R372 R374 R375 R376 R377 R378 R379 R373 R380 B
R381
GPIO39
R225
32 EC_SCI# 32 EC_SMI#
@ R226
GPIO48 GPIO57
1
+3VS
GPIO49
R364 26 EXP_CPPE#
ICH_LOW_BAT# ICH_PCIE_WAKE# ICH_RI#
A14 E19
STP_PCI# STP_CPU#
PM_CLKRUN#
L4
@
OCP# AG19 CR_CPPE# AH21 EC_SCI#_SB 1 2 0_0402_5% AG21 EC_SMI# A21 EC_SCI#_GPIO12 1 2 0_0402_5% C12 C21 PAD T46 17/14 AE18 GPIO18 K1 GPIO20 AF8 CR_WAKE# AJ22 DIS/UMA A9 D19 PAD T47 CLKREQ#_C L1 17 CLKREQ#_C GPIO38 2 AE19 GPIO39 8.2K_0402_5% AG22 GPIO48 @ R739 1 2 AF21 GPIO49 0_0402_5% AH24 GPIO57 A8 R366 1 2 1K_0402_5% SB_SPKR M7 MCH_ICH_SYNC# AJ24 9 MCH_ICH_SYNC# ICH_RSVD B21 21 ICH_RSVD AH20 AJ20 AJ21
26 26 26 26
PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1
C445 1 C444 1
PCIE_RXN1 PCIE_RXP1 2 0.1U_0402_16V4Z PCIE_C_TXN1 2 0.1U_0402_16V4Z PCIE_C_TXP1
WLAN
26 26 26 26
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
C448 1 C449 1
PCIE_RXN3 PCIE_RXP3 2 0.1U_0402_16V4Z PCIE_C_TXN3 2 0.1U_0402_16V4Z PCIE_C_TXP3
LAN
25 25 25 25
GLAN_RXN GLAN_RXP GLAN_TXN GLAN_TXP
C452 1 C453 1
2 2
EC_SMI# GPIO14
2
Board ID New Card
1
26 26 26 26
PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4
C450 1 C451 1
PCIE_RXN4 PCIE_RXP4 2 0.1U_0402_16V4Z PCIE_C_TXN4 2 0.1U_0402_16V4Z PCIE_C_TXP4
SPI_CS1#_R
R748 10K_0402_5% R383 1
2 0_0402_5%
26 WXMIT_OFF#
+3VALW
USB_OC#0 USB_OC#1 USB_OC#2 WXMIT_OFF# USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11 USBRBIAS
1
R1183 R1184 R1185 R1186 WXMIT_OFF# USB_OC#5 R1187 USB_OC#10 R1188 USB_OC#11 R1189 R1190
DPRSLPVR/GPIO16 BATLOW# PWRBTN# LAN_RST# RSMRST#
SLP_M#
G20
PM_PWROK
M2
R348 1
B13
ICH_LOW_BAT#
R3
PWRBTN_OUT#
R346 1
4.7P_0402_50V8C
2
@ C441 4.7P_0402_50V8C
10K_0402_5% 2
DPRSLPVR 9,42
PWRBTN_OUT# 32
D20
R_EC_RSMRST# 38
D22
R_EC_RSMRST#
R5
CK_PWRGD
R6
M_PWROK
R354 1 R355 1
2 100_0402_5% 2 10K_0402_5%
EC_RSMRST# 32
CK_PWRGD 17 M_PWROK 9,32 +3VS
B16
F22 C19
CL_DATA0
CL_VREF0 CL_VREF1
C25 A19
CL_VREF0_ICH CL_VREF1_ICH
CL_RST0# CL_RST1#
F21 D18
CL_RST#
A16 C18 C11 C20
XMIT_OFF GPIO10 GPIO14 LAN_WOL_EN
MEM_LED/GPIO24 GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT WOL_EN/GPIO9
1
@ C440
D
2
PM_PWROK 9,32 2 0_0402_5%
CL_CLK0
CL_DATA0 CL_DATA1
1 2 1 SLP_S3# 29,32 SLP_S4# 32 SLP_S5# 32
F24 B19
CL_CLK0 CL_CLK1
10_0402_5%
T58 PAD
R360
CL_CLK0 9 CL_DATA0 9 C442
1
2 CL_RST# 9
1
2
3.24K_0402_1% R363 453_0402_1% NA lead free +3VALW
C
R367 XMIT_OFF 26
C443
1
R370 2
1
+3VALW
2
100K_0402_5%
1
2
3.24K_0402_1% R368 453_0402_1%
Within 500 mils
PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5
D23 D24 F23
SPI_CLK SPI_CS0# SPI_CS1#GPIO58/CLGPIO6
AG2 AG1
DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_CLKN DMI_CLKP
DMI_ZCOMP DMI_IRCOMP
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
SPI
SPI_MOSI SPI_MISO OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8#/GPIO44 OC9#/GPIO45 OC10#/GPIO46 OC11#/GPIO47
USB
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P
V27 V26 U29 U28
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
Y27 Y26 W29 W28
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
AB27 AB26 AA29 AA28
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
AD27 AD26 AC29 AC28
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
T26 T25
CLK_PCIE_ICH# CLK_PCIE_ICH
AF29 AF28
DMI_IRCOMP
AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2
DMI_RXN0 9 DMI_RXP0 9 DMI_TXN0 9 DMI_TXP0 9
PM_PWROK 2
DMI_RXN1 9 DMI_RXP1 9 DMI_TXN1 9 DMI_TXP1 9
D22 1
R_EC_RSMRST#
CH751H-40PT_SOD323-2
DMI_RXN2 9 DMI_RXP2 9 DMI_TXN2 9 DMI_TXP2 9 DMI_RXN3 9 DMI_RXP3 9 DMI_TXN3 9 DMI_TXP3 9
B
CLK_PCIE_ICH# 17 CLK_PCIE_ICH 17 R382 1
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9
24.9_0402_1% 2
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9
30 30 30 30 30 30 27 27 19 19 26 26 30 30 30 30 26 26 26 26
Within 500 mils +1.5VS
USB-0 Right side(with ESATA) USB-1 Left side USB-2 Left side USB-3 Cardreader USB-4 Camera USB-5 WLAN USB-6 Bluetooth USB-7 Finger Printer USB-8 MiniCard(WWAN/WiMAX) USB-9 Express card A
USBRBIAS USBRBIAS# ICH9-M ES_FCBGA676
R384 22.6_0402_1% 2
USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#0
S4_STATE#
CLPWROK
C29 C28 D27 D26
D25 E23
30 BT_OFF
1 2 110K_0402_5% 2 110K_0402_5% 2 110K_0402_5% 2 10K_0402_5% 1 2 110K_0402_5% 2 110K_0402_5% 2 110K_0402_5% 2 10K_0402_5% 1 2 10K_0402_5% 1 2 110K_0402_5% 2 110K_0402_5% 2 10K_0402_5%
J29 J28 K27 K26
GLAN_RXN G29 GLAN_RXP G28 0.1U_0402_16V4Z GLAN_TXN_C H27 0.1U_0402_16V4Z GLAN_TXP_C H26
17/14
R1179 R1180 R1181 R1182
N29 N28 P27 P26
E29 E28 F27 F26
@ R747 10K_0402_5%
C10
CK_PWRGD
SPKR MCH_SYNC# TP3 TP8 TP9 TP10
ME_EC_DATA1
EC_LID_OUT#
SLP_S3# SLP_S4# SLP_S5#
PWROK
TP11
L29 L28 M27 M26
GPIO10
C16 E16 G17
S4_STATE#/GPIO26
VRMPWRGD
GPIO1 GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5
SLP_S3# SLP_S4# SLP_S5#
@ R343
10_0402_5%
U12D
1
1
WAKE# SERIRQ THRM#
ME_EC_CLK1
R746 10K_0402_5%
A
CLKRUN#
ICH_SUSCLK
ICH9-M ES_FCBGA676
20 SPI_CS1#_R
USB_OC#6 USB_OC#1 USB_OC#2 USB_OC#4
D21 A20
PAD T59
2
2
DIS/UMA
SMBALERT#/GPIO11
H_STP_PCI# R_STP_CPU#
S4_STATE#
+3VS
2
WWAN
XDP_DBRESET#
@ R745 10K_0402_5% 1
R366 Low High -->No -->default boot
LINKALERT#
1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 1K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5%
+3VS
A17
6 OCP#
GPIO37
PMSYNC#/GPIO0
EC_LID_OUT#
VGATE
GPIO36
M6
ICH_PCIE_WAKE# E20 SIRQ M5 THERM_SCI# AJ23
17,42 VGATE
+3VS 28 SB_SPKR
R371
2 0_0402_5%
1
25,26 ICH_PCIE_WAKE# 32 SIRQ 32 THERM_SCI#
HDDHALT_LED#
+3VALW
R369
PM_BMBUSY#
9 PM_BMBUSY#
GPIO18
1 2 @ R365 10K_0402_5%
C
6 XDP_DBRESET# @ R340 10K_0402_5%
P1
@ R342
1
R358
@ R339 10K_0402_5%
SUSCLK
2
R357
SUS_STAT#/LPCPD# SYS_RESET#
CLK_14M_ICH 17 CLK_48M_ICH 17
1
R352
R4 G19
CLK_14M_ICH CLK_48M_ICH
2
R351
SUS_STAT# XDP_DBRESET#
H1 AF3
CLK14 CLK48
Place closely pin H1 CLK_14M_ICH
HDDHALT_LED# 33
0.1U_0402_16V4Z
R350
PM_BMBUSY#
T57
GPIO21 HDDHALT_LED# GPIO36 GPIO37
0.1U_0402_16V4Z
R349
PAD CLKREQ#_C
AH23 AF19 AE21 AD20
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37
Direct Media Interface
R356
clocks
SYS / GPIO
R344
RI#
Power MGT
R341
F19
MISC GPIO Controller Link
@ R338
ICH_RI#
SMB
PCI - Express
R337 D
+3VS
SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1
THERM_SCI# 1
@ R336
OCP#
1
R335
PM_CLKRUN#
2
R334
17,26 ICH_SMBCLK 17,26 ICH_SMBDATA
SIRQ
1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5%
2
R333
G16 A13 E17 C17 B18
SATA GPIO
U12C ICH_SMBCLK ICH_SMBDATA LINKALERT# ME_EC_CLK1 ME_EC_DATA1
1
4
2
5
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. ICH9(3/4)_DMI,USB,GPIO,PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
22
of
46
5
4
3
2
10U_0805_10V4Z C460
2
1
C456
2
1
2 2.2U_0603_6.3V4Z
2
10U_0805_10V4Z
1 ICH_V5REF_RUN
0.1U_0402_10V6K
1
2
C477
10U_0805_10V4Z
1U_0603_10V4Z
C476
C478 1U_0603_10V4Z
1
2
1
2
AC11 AD11 AE11 AF11 AG10 AG11 AH10 AJ10
VCC1_5_A[09] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16]
AC9
VCC1_5_A[17]
G10 G9
1
2
C483 0.1U_0402_16V4Z
C484 0.1U_0402_16V4Z
AJ5
2
VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2
VCCUSBPLL
AA7 AB6 AB7 AC6 AC7
VCC1_5_A[26] VCC1_5_A[27] VCC1_5_A[28] VCC1_5_A[29] VCC1_5_A[30]
A10 A11
VCCLAN1_05[1] VCCLAN1_05[2]
A12 B12
2
R390 1 +1.5VS
VCCLAN3_3[1] VCCLAN3_3[2] 23mA
CHB1608U301_0603 2
1
2
C487
2.2U_0603_6.3V4Z
1
10U_0805_10V4Z
0.1U_0402_16V4Z
C485
VCC1_5_A[23] VCC1_5_A[24] VCC1_5_A[25]
A27 4.7U_0805_10V4Z 2 D28 +1.5VS D29 CHB1608U301_0603 E26 1 C488 E27 1
VCCGLANPLL 80mA
R391 1
2
C489 0316 change design
+3VS 2
VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04]
R212 @ 0_0402_5%
0.1U_0402_16V4Z
AJ3 AC8 F17
T65 T66
AD8 VCCSUS1_5_ICH_1
A18 D16 D17 E22
VCCSUS3_3[05]
AF1
VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20]
T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7
2
(DMI)
0.1U_0402_16V4Z 1
AJ4
F18
2
C473
2
R740 2 180_0402_1%
1 1
+3VALW
+1.5VS C474
R741 150_0402_1%
2
2
+1.5VALW
T67
VCCSUS1_5_ICH_2
T68
0.1U_0402_16V4Z 1
2
VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] 1mA
A26
VCCCL1_05 VCCCL1_5
19/78/78mA
VCCGLAN3_3 ICH9-M ES_FCBGA676
GLAN POWER
A
VCC1_5_A[21] VCC1_5_A[22] 11mA 11mA
USB CORE
T69 T70
+3VS
1
VCCSUS1_5[2]
VCC1_5_A[20]
AC12 AC13 AC14
+1.5VS 2
VCCSUS1_5[1]
VCC1_5_A[18] VCC1_5_A[19]
AC21
1
2
2
+1.5VS
C475
212mA
2
1
1
+3VALW
1
2
1342mA
AC18 AC19
+1.5VS
1
2
1
1
0.1U_0402_16V4Z C480
1U_0603_10V4Z
VCCHDA
VCCSUSHDA VCCSUS1_05[1] VCCSUS1_05[2]
VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08]
ATX
C481 B
+3VS 0.1U_0402_16V4Z
C479
+1.5VS
B9 F9 G3 G6 J2 J7 K7
1
1
C468
2
AD19 AF20 AG24 AC20
VCCSATAPLL
AC16 AD15 AD16 AE15 AF15 AG15 AH15 AJ15
+1.5VS
ARX
2
1
+VCCP
C467
0316 change design
1
AJ19
2
0.1U_0402_16V4Z
+1.5VS
11mA 11mA
R389 1 2 CHB1608U301_0603
C464
C466
0.1U_0402_10V6K
+VCCP 1
0.1U_0402_16V4Z
C472
10U_0805_10V4Z
+3VS
AG29 AJ6 AC10
+1.5VS
C463
AB23 AC23
308mA VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14]
2
C471
2
20 mils
VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06]
C461
2
0.1U_0402_16V4Z
1
ICH_V5REF_SUS
VCC3_3[01] VCC3_3[02] VCC3_3[07]
1
C470
CH751H-40PT_SOD323-2
2mA
1
C469
10_0402_5%
48mA
V_CPU_IO[1] V_CPU_IO[2]
R385 1 2 CHB1608U301_0603
0.01U_0402_16V7K
0.1U_0402_16V4Z
C
D10
W23 Y23
VCC_DMI[2]
2
0.1U_0402_16V4Z
R388
R29
2
4.7U_0603_6.3V6M
+5VALW +3VALW
VCCDMIPLL
23mA VCC_DMI[1]
VCCPSUS
2
20 mils
C465
VCCPUSB
2
CH751H-40PT_SOD323-2
1
646mA
22U_0805_6.3VAM
D9
2mA
VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCC1_5_B[47] VCC1_5_B[48] VCC1_5_B[49] 47mA
VCCA3GP
R386 100_0402_5%
V5REF_SUS
AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29 F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23 W24 W25 K23 Y24 Y25
AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 C457 C455
2
+1.5VS_SB_B 1 1 + C459
V5REF
A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
1
AE1
VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26]
1634mA 2mA
1
ICH_V5REF_SUS
G3: 6uA
2
2
VCCRTC
CORE
1
2
A6
VCCP_CORE
1
A23
ICH_V5REF_RUN
PCI
C458 220U_D2_4VM
+3VS
1
+5VS
1
U12E
U12F
20 mils
40 mils
R387 1 2 CHB1608U301_0603
+1.5VS
D
2
+VCCP C454 0.1U_0402_16V4Z
C462 0.1U_0402_16V4Z
+RTCVCC
G22 G23
+3VALW
1
2
VCCCL1_05_ICH
C482 4.7U_0603_6.3V6M
T71
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106]
19/73/73mA VCCCL3_3[1] VCCCL3_3[2]
A24 B24
1 @ C486 1U_0603_10V4Z
+3VS
VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198]
VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]
H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25
D
C
B
A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
ICH9-M ES_FCBGA676
A
2
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. ICH9(4/4)_POWER&GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
23
of
46
24 23
GND GND
2
2
SATA_RXN0_C 21 SATA_RXP0_C 21
1
2
C493
1
2
+3VS
+3VS_ACL D23 2
1
CLK_SMBCLK +5VS
U29
VDDIO absolute man rating is VDD+0.1 1
+3VS_ACL_IO R568 0_0402_5% 1 2
2 3
SDA / SDI / SDO
GND
SDO
Reserved
Reserved
13
CLK_SMBDATA
12
R570 0_0402_5% 1 2
11
4
GND
GND
10
5
GND
INT 2
9
Vdd
INT 1
6
8
CLK_SMBDATA 15,16,17
ACCEL_INT 20
C
CS 2 R569
SATA_RXN4_C 21 SATA_RXP4_C 21
Near CONN side.
C512
1
2
C513
1
2
C514
1
2
C515
1
2
1 10K_0402_5%
10U_0805_10V4Z
SATA_TXP4 21 SATA_TXN4 21
10U_0805_10V4Z
1 C510 SATA_RXN4_C 1 C511 SATA_RXP4_C
1U_0603_10V4Z
SATA_TXP4 SATA_TXN4
0.1U_0402_16V4Z
Placea caps. near ODD CONN.
6 5 4 3 2 1
Vdd_IO
7 +5VS
0.01U_0402_16V7K SATA_RXN4 2 SATA_RXP4 2 0.01U_0402_16V7K
CLK_SMBCLK 15,16,17
0011101b
LIS302DLTR_LGA14_3x5
JODD
DP V5 V5 MD GND GND
D
Near CONN side.
CD-ROM Connector 13 12 11 10 9 8 7
2
+3VS
+3VS_ACL
GND A+ AGND BB+ GND
2
1
CH751H-40PT_SOD323-2
OCTEK_SAT-22EH1G_RV
C
1
+3VS_ACL_IO R564 0_0603_5% 1 2
C714
C492
C713
1
0.1U_0402_16V4Z
SATA_TXP0 21 SATA_TXN0 21
1 C494 SATA_RXN0_C 1 C495 SATA_RXP0_C
C491
+3VS_ACL
ACCELEROMETER (ST)
14
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
0.01U_0402_16V7K SATA_RXN0 2 SATA_RXP0 2 0.01U_0402_16V7K
1
1
SCL / SPC
V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12
SATA_TXP0 SATA_TXN0
10U_0805_10V4Z
D
1 2 3 4 5 6 7
C490
CONN@ JHDD GND A+ AGND BB+ GND
Pleace near HDD CONN (JP3)
+5VS
0.1U_0402_16V4Z
HDD Connector
2
10U_0805_6.3V6M
3
0.1U_0402_16V4Z
4
0.1U_0402_16V4Z
5
+5VS
SUYIN_127382FR013GX09ZR CONN@
B
B
PA@ ZZZ
PR@ ZZZ
PCB-MB
PCB-MB
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. HDD & CDROM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
24
of
46
5
4
3
LAN_DI LAN_CS
2
1 R695 2 R696
1
2 +3V_LAN 3.6K_0402_5% 1 1K_0402_1%
LAN Conn.
9/17 RT suggestion: R696 change to 1K ohm
Place Close to Chip
JRJ45 R697 300_0402_5% 2 1
U44 LAN_ACTIVITY# 20
22 GLAN_RXN
C241 2
1 0.1U_0402_16V7K PCIE_PTX_IRX_N2
21
22 GLAN_TXP
15
22 GLAN_TXN
16
17 CLK_PCIE_LAN 17 CLK_PCIE_LAN#
17 18
17 CLKREQ#_9
25
9,20,26 PLT_RST#
27
R688 1 22,26 ICH_PCIE_WAKE#
2 2.49K_0402_1%
HSOP HSON HSIP
LED0 HSIN
26 28
LAN_X1 LAN_X2
41 42
RTL8102EL
MDIP0 MDIN0 MDIP1 MDIN1 NC NC NC NC
REFCLK_P REFCLK_M CLKREQB PERSTB
46
ISOLATEB
LED3/EEDO LED2/EEDI/AUX LED1/EESK EECS
RSET
NC
LANWAKEB ISOLATEB CKXTAL1 CKXTAL2
1 R215 1K_0402_1% 2
C
7 14 31 47
ISOLATEB
22
GNDTX
LAN_ACTIVITY#
2 3 5 6 8 9 11 12
LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1-
1
T82 LANLED_ACT#
2
LANLED_LINK#
19 30 36 13 10
VCTRL12
2
1
+EVDD12 +LAN_VDD12
VDD33 VDD33
29 37
AVDD33 NC NC
1 40 43
SHLD1 PR4-
PR3PR3+
RJ45_MIDI0-
2 1
+3V_LAN
11
LANLED_LINK#
12
D
9
DETCET PIN2
10
PR2-
4
RJ45_MIDI0+
16
DETECT PIN1 PR4+
5
3
PR2+ PR1PR1+ SHLD1
15
Green LED+ Green LEDFOX_JM36113-P1122-7F CONN@
R698 300_0402_5%
LANGND 1
39 44 45
6
RJ45_MIDI1+
C269 0.1U_0402_16V4Z
1
LAN_SK_LAN_LINK#
Yellow LED-
7
@ D20 PACDN042_SOT23~D
2
Yellow LED+
14 8
C268 0.1U_0402_16V4Z RJ45_MIDI1-
4
VDDTX DVDD12 DVDD12 DVDD12 DVDD12
NC VCTRL12D
GND GND GND GND
38
48
NC NC NC
LAN_DO LAN_DI LAN_SK_LAN_LINK# LAN_CS
VCTRL12A
+3VS 23 24
33 34 35 32
2
1 0.1U_0402_16V7K PCIE_PTX_IRX_P2
3
C240 2
1
D
22 GLAN_RXP
+3V_LAN LANLED_ACT#
13
R1162 0_0603_5% 1 2 R1177 0_0603_5% +3V_LAN_IC 1 2 +3V_LAN
2
+LAN_VDD12
1
C271 0.1U_0402_16V4Z
2
C272 4.7U_0805_10V4Z
C
RTL8103EL-GR_LQFP48_7X7
R216 15K_0402_5%
U46
C247 1 +3VALW
C248 1
D
S
1
2
1 1 R218
32 LAN_POWER_OFF
2 10K_0402_5%
LAN_CT1 LAN_MDI1+ LAN_MDI1-
RD+ RDCT NC NC CT TD+ TD-
RX+ RXCT NC NC CT TX+ TX-
16 15 14 13 12 11 10 9
RJ45_MIDI0+ RJ45_MIDI0RJ45_CT0 RJ45_CT1 RJ45_MIDI1+ RJ45_MIDI1-
C257 1 C258 1
2 0.01U_0603_100V7-M RJ45_CT0_C 2 0.01U_0603_100V7-M RJ45_CT1_C
1 1
R693 75_0402_1% 2 2
RJ45_GND
R694 75_0402_1%
C259
1000P_1206_2KV7K
+3V_LAN
X'FORM_ HD-024A
1
2
G
2
2 0.01U_0402_16V7K
1 2 3 4 5 6 7 8
40 mils
3 @ C255
2 0.01U_0402_16V7K
LAN_MDI0+ LAN_MDI0LAN_CT0
Q19 SI2301BDS-T1-E3_SOT23-3
0.1U_0402_16V4Z
B
B
1
Close to Pin19
C252
2
1
Close to Pin45
+EVDD12
C253
2
1
C254
2
1
C261
2
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
C251
Close to Pin1,37,29 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
C250
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
C249
0.1U_0402_16V4Z
+LAN_VDD12
Close to Pin10,13,30,36
+3V_LAN
Close to Pin48 Y3
+LAN_VDD12
2
1
1
2
@ C265
@ 1 C262 2
C263
2
1
0.1U_0402_16V4Z
1
C264
LAN_X1 10U_0805_10V4Z
2
10U_0805_10V4Z
1
C267
0.1U_0402_16V4Z
A
2
1U_0402_6.3V4Z
C266
1U_0402_6.3V4Z
VCTRL12
2
1
LAN_X2
25MHz_20pF_6X25000017 1
C244
1
C245
27P_0402_50V8J 2 27P_0402_50V8J 2
A
9/17 RT suggestion: C267 change to 1uF
Compal Secret Data
Security Classification Issued Date
2007/08/28
2007/06/30
Deciphered Date
Title
Compal Electronics, Inc. RTL8102EL LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom Montevina UMA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Wednesday, February 18, 2009 Date: 5
4
3
2
Rev 0.1 Sheet 1
25
of
46
A
+3VALW
B
+3VALW
+3VS_WLAN R432
1
2
C568
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z 1 1
2 1 0_0805_5% 1
C566
1
1
C569
1
C570
C571
R431 2 1 0_0805_5% 1
C572 2 4.7U_0805_10V4Z
2
2
2
47P_0402_50V8J
2
2
2
2
Reserve for WWAN
ICH_PCIE_WAKE# CH_DATA CH_CLK CLKREQ#_6
30 CH_DATA 30 CH_CLK 17 CLKREQ#_6
CLK_PCIE_MCARD2# CLK_PCIE_MCARD2
17 CLK_PCIE_MCARD2# 17 CLK_PCIE_MCARD2
0.1U_0402_16V4Z
PLT_RST#
SI-1 Connect PLT_RST# to JP7.A17 17 CLK_DEBUG_PORT_1
SIM card Connector CONN@ JSIM 1 2 3 4 5 6
UIM_VPP UIM_RST UIM_CLK UIM_DATA UIM_PWR
1 2 3 4 5 G1 6 G2
R11 1
+3VS
2 0_0402_5% 2 0_0402_5%
PCIE_C_RXN3 PCIE_C_RXP3
PCIE_TXN3 PCIE_TXP3
22 PCIE_TXN3 22 PCIE_TXP3
10K_0402_5% CLKREQ#_6 2
R10 1
+3VS
2
7 8
R423 1 R425 1
22 PCIE_RXN3 22 PCIE_RXP3
UIM_CLK 1 C824 @ 18P_0402_50V8J
+3VS_WLAN
10K_0402_5% CLKREQ#_10 2
A1 A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 A39 A41 A43 A45 A47 A49 A51
WAKE# COEX1 COEX2 CLKREQ# GND REFCLKREFCLK+ GND Reserved Reserved GND PERn0 PERp0 GND GND PETn0 PETp0 GND GND +3.3Vaux +3.3Vaux GND Reserved Reserved Reserved Reserved
A53
GND
ACES_87212-06G0
UIM_PWR
+3VS_WWAN
17 CLK_PCIE_MCARD0# 17 CLK_PCIE_MCARD0
@ R400 1 2 0_0603_5%
2
0.01U_0402_16V7K 4.7U_0805_10V4Z
+3VS R418
S
3
+3VALW
1
2
2
2 32 WWAN_POWER_OFF
0.1U_0402_16V4Z
1 @ C1499
@ Q52
SI2301BDS-T1-E3_SOT23-3
2
PA@ R419 1 1 R421 PA@
22 PCIE_RXN1 22 PCIE_RXP1
1 2 0_1206_5%
D
1 PA@ C575
G
2
+3VS_WLAN
A6 A8 A10 A12 A14 A16
+1.5VS_WLAN
W_DISABLE# PERST# +3.3Vaux
A20 A22 A24
GND
GND
GND
XMIT_OFF# 2 PLT_RST# @ R424 1 R426 1
A28 A30 A32
+1.5V SMB_CLK SMB_DATA
GND
LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 1 D19 2 0_0805_5% 2 0_0805_5%
USB20_N5 22 USB20_P5 22
A42 A44 A46 A48
WL_LED# 33 +1.5VS_WLAN
+3.3Vaux
A52
+3VS_WLAN
GND
A54
GND
LED_WWAN# LED_WLAN# LED_WPAN# +1.5V
GND
0_0402_5% 2 PCIE_C_RXN1 2 PCIE_C_RXP1 0_0402_5% PCIE_TXN1 PCIE_TXP1
22 PCIE_TXN1 22 PCIE_TXP1
47P_0402_50V8J
Reserve for WWAN
+3VS_WWAN
B1 B3 B5 B7
WAKE# COEX1 COEX1 CLKREQ#
GND
B11 B13
REFCLKREFCLK+
B17 B19
Reserved Reserved
GND GND
B23 B25
PERn0 PERp0
B31 B33
PETn0 PETp0
B37 B39 B41 B43 B45 B47 B49 B51
B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 B38 B40 B42 B44 B46 B48 B50 B52
+3.3Vaux GND +1.5V UIM_PWR UIM_DATA UIM_CLK UIM_RESET UIM_VPP GND W_DISABLE# PERST# +3.3Vaux GND +1.5V SMB_CLK SMB_DATA GND USB_DUSB_D+ GND LED_WWAN# LED_WLAN# LED_WPAN# +1.5V GND +3.3Vaux
SI-1 For PR
UIM_PWR_R UIM_DATA_R UIM_CLK_R UIM_RST_R UIM_VPP_R UIM_PWR_R UIM_DATA_R UIM_CLK_R UIM_RST_R UIM_VPP_R
GND GND GND GND +3.3Vaux +3.3Vaux GND Reserved Reserved Reserved Reserved
+3VS_WWAN +1.5VS_WLAN UIM_PWR_R UIM_DATA_R UIM_CLK_R UIM_RST_R UIM_VPP_R PA@ D11 M_WXMIT_OFF# 2 PLT_RST# @ R420 1 R422 1 ICH_SMBCLK ICH_SMBDATA
1
XMIT_OFF 22
+3VALW +3VS_WLAN +1.5VS_WLAN
ICH_SMBCLK ICH_SMBDATA
A36 A38
USB_DUSB_D+
LPC_FRAME# 21,32 LPC_AD3 21,32 LPC_AD2 21,32 LPC_AD1 21,32 LPC_AD0 21,32
CH751H-40PT_SOD323-2
JMINIB ICH_PCIE_WAKE# CH_DATA CH_CLK CLKREQ#_10
17 CLKREQ#_10
1 PA@ C574
A2
+1.5V UIM_PWR UIM_DATA UIM_CLK UIM_RESET UIM_VPP
+3.3Vaux
QUASA_CA0416-092N21
@ R750 1 2 UIM_DATA 47K_0402_5%
+3VS_WWAN
1 PA@ C573
E
JMINIA
+1.5VS
@ C1498 47P_0402_50V8J
D
Mini Card Slot ---WLAN,WWAN
Reserve for WWAN
+1.5VS_WLAN 0.01U_0402_16V7K 4.7U_0805_10V4Z +3VS
1 @ C1497
C567
C
WL_LED# 1 PR@ R1225
WW_LED#_R 2 0_0402_5%
XMIT_OFF# 1 PR@ R1226
M_WXMIT_OFF# 2 0_0402_5%
R1227 R1228 R1229 R1230 R1231 R1232 R1233 R1234 R1235 R1236
1 1 1 1 1
2 2 2 2 2
1 1 1 1 1
2 2 2 2 2
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
PR@ PR@ PR@ PR@ PR@
UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP
PA@ PA@ PA@ PA@ PA@
2
CH751H-40PT_SOD323-2 1 WXMIT_OFF# 22 2 0_0805_5% +3VALW 2 0_0805_5% +3VS_WWAN +1.5VS_WLAN
USB20_N8 22 USB20_P8 22 WW_LED#_R
WW_LED# 33
+1.5VS_WLAN +3VS_WWAN
QUASA_CA0416-092N21
New Card
3
Express Card Power Switch
+1.5VS C576 1 2 0.1U_0402_16V4Z +3VS
C579 1
2 0.1U_0402_16V4Z
C580 1
2 0.1U_0402_16V4Z
2 4 17
+3VALW 9,20,25 PLT_RST# 32,35,40 SYSON 32,35,37,39 SUSP# +3VALW 22 EXP_CPPE#
PLT_RST#
6
SYSON
20
SUSP#
1
@ R439 1
22 USB20_N9 22 USB20_P9
U16 12 14
2 100K_0402_5%
10
EXP_CPPE#
9 18
1.5Vin 1.5Vin
1.5Vout 1.5Vout
3.3Vin 3.3Vin
3.3Vout 3.3Vout
AUX_IN SYSRST# SHDN#
AUX_OUT OC# PERST#
STBY#
NC
CPPE#
GND
11 13
+1.5VS_PEC
3 5
+3VS_PEC
15
+3V_PEC
22,25 ICH_PCIE_WAKE#
internal pull high to 3.3Vaux-in EC need setting at Hi-Z & output Low
2 0_0402_5% 2 0_0402_5%
1 1
USB9USB9+ EXP_CPPE# ICH_SMBCLK ICH_SMBDATA
+1.5VS_PEC +1.5VS_PEC
R438 1 2 0_0402_5%
+3V_PEC
PCIE_PME#_R PERST#
+3VS_PEC CLKREQ#_4 EXP_CPPE#
17 CLKREQ#_4
19 8
R436 R437
17,22 ICH_SMBCLK 17,22 ICH_SMBDATA
17 CLK_PCIE_NCARD# 17 CLK_PCIE_NCARD
PERST#
16
22 PCIE_RXN4 22 PCIE_RXP4
7
22 PCIE_TXN4 22 PCIE_TXP4
CPUSB#
Close to JEXP
RCLKEN ENE P2231NL E2 QFN 20P
4
Near to Express Card slot.
CONN@ JEXP
R12 +3VS
1
2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
+3VS_PEC
GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND
C577 0.1U_0402_16V4Z
3
1
1
2
2
C578 4.7U_0805_10V4Z
+1.5VS_PEC
C581 0.1U_0402_16V4Z
1
1
2
2
C582 4.7U_0805_10V4Z
+3V_PEC
GND GND SANTA_130801-5_RT
CLKREQ#_4
C583 0.1U_0402_16V4Z
1
1
2
2
C584 4.7U_0805_10V4Z
10K_0402_5%
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Compal Electronics, Inc. WLAN, WWAN, New Card Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet E
26
of
46
4
5
4
3
2
1
+3VS D
2
D
+VCC_4IN1
R1102 100K_0402_5% 0_0402_5% RST# 1
1
2
1
R1103 2
C1405
2
0.1U_0402_16V4Z 1 1 C1407 C1408
1
17 CLK_48M_CR 2
2
1 3 7 9 11 33
2
0.1U_0402_16V4Z
1 C1411
RST# MODE SEL
R1115 0_0402_5% 1 2
XTLI 2
2 @ C1415 6P_0402_50V8J
0.1U_0402_16V4Z
22 USB20_N3 22 USB20_P3 1
USB20_N3 USB20_P3 CR_LED#
8 44 45 47 48
3V3_IN RST# MODE_SEL XTLO XTLI
4 5 14
DM DP GPIO0
SI-1 Delete Crystall layout location
SI-1 Change LED type PA@ D54
1
2
2
1.2K_0402_5%
1
CR_LED#
HT-110TW_WHITE
6.19K_0402_1%
White
MODE SEL
R1111
1
C1409 1U_0603_10V4Z 1 2
2
RREF
12 32
DGND DGND
VREG MS_D4 NC
10 22 30
XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17 SD_DAT2/XD_RE#_SP16 SD_DAT3/XD_WE#_SP15 XD_RDY_SP14 SD_DAT4/XD_WP#/MS_D7_SP13 SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10 MS_INS#_SP9 SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6 XD_D5_SP5 XD_D4/SD_DAT1_SP4 SD_CD#_SP3 SD_WP_SP2 XD_CD#_SP1 EEDI
43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18
XTAL_CTR MS_D5
13 24
EEDO EECS EESK SD_CMD
15 16 17 36
2
D64 2
2
1 HT-110TW_WHITE PR@
@ C1412 47P_0402_50V8J
1
2
@ R1110 10K_0402_5%
6 46
1
+5VS
2 0_0402_5%
AV_PLL NC NC CARD_3V3 D3V3 D3V3
C
R1107
1 R1104
U47 C1406 1U_0603_16V6K
2
1
0.1U_0402_16V4Z C1404 1 2
+3VS
+3VS
C1410 4.7U_0603_6.3V6K
C1403 0.1U_0402_16V4Z
2
R1105 499K_0402_1%~D @ 1
1U_0402_6.3V6K
1
AGND AGND
Card Reader Connector CONN@ JREAD1
3
+VCC_4IN1 XD_CLE XDCE# XD_ALE XD_RE#_SDD2 XDWE#_SDD3 XDRDY XDWP#_SDD4 XDD0_SDD5 XDD1 XDD7_SDD6_MSD3 MSINS# XDD2_SDD7_MSD2 XDD6_SDD0_MSD0 XDD3_MSD1 XDD5_MSBS XDD4_SDD1 SDCD# SDWP XDCD# R1112 1
1
2 0_0402_5% 1 2 0_0402_5%
MSCLK R1106 SDCLK R1109
XD-VCC
XDD0_SDD5 XDD1 XDD2_SDD7_MSD2 XDD3_MSD1 XDD4_SDD1 XDD5_MSBS XDD6_SDD0_MSD0 XDD7_SDD6_MSD3
32 10 9 8 7 6 5 4
XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7
XDWE#_SDD3 XDWP#_SDD4 XD_ALE XDCD# XDRDY XD_RE#_SDD2 XDCE# XD_CLE
34 33 35 40 39 38 37 36
XD-WE XD-WP XD-ALE XD-CD XD-R/B XD-RE XD-CE XD-CLE
11 31
7IN1 GND 7IN1 GND
0_0402_5% 2 +3VS
41 42
7 IN 1 CONN
SD-VCC MS-VCC
21 28
SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-DAT4 SD-DAT5 SD-DAT6 SD-DAT7 SD-CMD SD-CD-SW
20 14 12 30 29 27 23 18 16 25 1
SDCLK XDD6_SDD0_MSD0 XDD4_SDD1 XD_RE#_SDD2 XDWE#_SDD3 XDWP#_SDD4 XDD0_SDD5 XDD7_SDD6_MSD3 XDD2_SDD7_MSD2 SDCMD SDCD#
SD-WP-SW
2
SDWP
MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-INS MS-BS
26 17 15 19 24 22 13
MSCLK XDD6_SDD0_MSD0 XDD3_MSD1 XDD2_SDD7_MSD2 XDD7_SDD6_MSD3 MSINS# XDD5_MSBS
+VCC_4IN1
C
7IN1 GND 7IN1 GND TAITW_R015-B10-LM
SDCMD
RTS5159E-GR_LQFP48_7X7
2
R1114 @ 10_0402_5%
1 10P_0402_50V8J @ C1413
2
B
2
R1113 @ 10_0402_5% B
1
SDCLK 1
MSCLK
1 10P_0402_50V8J @ C1414
2
A
A
Compal Secret Data
Security Classification Issued Date
2007/08/28
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. USB CardReader&CONN
Size Document Number Custom Date:
Rev 0.1
Montevina UMA
Wednesday, February 18, 2009 1
Sheet
27
of
46
B
C
CODEC POWER
1
300mA
R1118 R1122 0_0603_5%
1
2
U49
2
21 HDA_SDOUT_CODEC
0.01U_0402_16V7K
HDA_RST#_CODEC
5
HDA_SDOUT_CODEC
2
HDA_SYNC_CODEC
7
HDA_RST#_CODEC
21,32 HDA_RST#_CODEC
3
8
DVDD_CORE
HDA_BITCLK
HDA_SDO
R1132 1 1 R1178
19 DMIC_CLK 19 DMIC_DAT
22_0603_1% 2 2 0_0603_5%
30 29
EAPD_CODEC
32 EAPD_CODEC
10 23
PORT_A_L PORT_A_R
26 27
PORT_B_L PORT_B_R VREFOUT_B
13 14 20
MIC_EXTL MIC_EXTR VREFOUT_B
PORT_C_L PORT_C_R VREFOUT_C
15 16 21
MIC_INL MIC_INR VREFOUT_C
HDA_RST#
PORT_D_L PORT_D_R
24 25
DMIC_CLK DMIC0/GPIO1
PORT_E_L PORT_E_R
11 12
PC_BEEP/MONO SPDIF_OUT_0 SPDIF_OUT_1/GPIO7 EAPD/GPIO0/SPDIF_OUT 0 or 1
CAP2 VREFFILT
R1128 2 @ C1428 1
2
1
SENSEA 1 100K_0402_5% +VDDA_CODEC_R 1000P_0402_50V7K HP_IN_L HP_IN_R C1430 1 2 2.2U_0603_6.3V6K 1 2 2.2U_0603_6.3V6K
1
9
LINE_OUT_L LINE_OUT_R
MONO_INR 2 0.1U_0402_16V7K
1 C1434
1
2
HP Jack MIC_EXT_L 29 MIC_EXT_R 29
Jack MIC
MIC_IN_L 2 2.2U_0603_6.3V6K
1 C1432
MIC_IN_L 29
Internal SPKR.
MIC_IN_R 2 2.2U_0603_6.3V6K
1 C1433
R1133 47K_0402_5% 2 1
MONO_IN
MIC_IN_R 29
R1134 10K_0402_5% 2 1 +VDDA_CODEC
PV-1 For EMI
2
1
C1435
MIC_EXTR
2
1 C1459 0.1U_0402_16V7K
R1135
1
22 SB_SPKR
Q10A 2N7002DW-7-F_SOT363-6
D58 PSOT24C_SOT23-3
2
3
2
C1437
2
1
1
10U_0805_10V4Z
18 33
LINE_OUT_L 29 LINE_OUT_R 29
MIC_EXTL
22 19
92HD75B1X5NLGXYAX8 QFN 32P 1.5V CODEC
3
Q10B 5 4
C1478 1
1
HP_DET# 29 EXTMIC_DET# 29
2 1000P_0402_50V7K
Internal MIC
1U_0603_10V4Z
AVSS TPAD
C1429
HP_IN_L 29 HP_IN_R 29 MIC_EXT_L MIC_EXT_R
2 2.49K_0402_1% 2 39.2K_0402_1% 2 20K_0402_1%
1 1 1
10K_0402_5%
DVSS
R1124 R1125 R1126
C1431
C1436 4
MIC_IN_L
+VDDA_CODEC_R
0.1U_0402_16V7K
32 28 31
SENSE_A SENSE_B
HDA_SYNC
C1516 2
17
HDA_SDI
SI-1 For EMI request
1
AVDD
4.7K_0402_5%
2
HDA_BITCLK_CODEC 33_0402_5% R1130 1 2 HDA_SDIN0_CODEC
21 HDA_SYNC_CODEC
MIC_IN_R
3
21 HDA_SDIN0
4.7K_0402_5%
2 1000P_0402_50V7K
1
1
21 HDA_BITCLK_CODEC
R1120
4.7K_0402_5%
2
1U_0603_10V4Z R1121
2N7002DW-7-F_SOT363-6
6
DVDD_LV
C1419 1
6
1
+1.5VS
R1239 4.7K_0402_5%
1U_0603_10V4Z R1119
1U_0603_10V4Z
2
R1117 2 1 1K_0402_5%
C1423 2
0.1U_0402_16V7K
2
2
C1422 1
10U_0805_10V4Z
1
1U_0603_10V4Z
1
C1426
2
C1425
1
2
MIC_EXT_R
+VDDA_CODEC_R
VREFOUT_C
2
MIC_EXT_L C1424 0.1U_0402_16V7K
PV-1 ESD request
4.7K_0402_5%
1
+3VS
C1418 1
2
2
R1116 2 1 0_0402_5%
2
VREFOUT_B
1
+VDDA_CODEC
1
(4.75V(4.56~4.94V))
SI-1 Delete CODEC POWER IC
R1123 BLM18BD601SN1D_0603 2 1 +3VS_HDA
E
2
1
D
2
A
3
C1479 1
090212 For PC Beep Noise
2 1000P_0402_50V7K C1480
1
2 1000P_0402_50V7K C1481
1
2 1000P_0402_50V7K
R1174 1 R1175 1 R1176 1
2 0_0402_5%
2 0_1206_5%
2 0_1206_5%
GNDA 29
4
4
GND
GNDA
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Codec_IDT9275B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 0.1
Montevina UMA
Wednesday, February 18, 2009
Sheet E
28
of
46
A
B
C
D
E
JSPK1 SPKRSPKR+ SPKLSPKL+
AMP. FOR INTERNAL SPEAKER GAIN1
GAIN0
R1136 1 R1137 1 R1138 1 R1139 1
2 2 2 2
0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5%
Av(inv)
SPK_RSPK_R+ SPK_LSPK_L+
1 2 3 4 1
C1438
C1439
1
C1440
1
5 6
1
C1441
1
20
SPKR+
ROUT-
19
SPKR-
2
3 1
1 EC_MUTE# 32
1 2 100K_0402_5% 1 @ C1453
LOUT-
SPVDD
18
8
SPVDD
HPVDD
17
2
HP_OUTL
C1454
7
2
MV-1 For ESD request, close to JMIC2
0.1U_0402_16V4Z
+5VS
D57 PSOT24C_SOT23-3
1
16
1U_0603_10V4Z
2
1 2 C1458 1U_0603_10V4Z
INTMIC IN
28 MIC_IN_L 1
1
R1153 0_0805_5% 1
+3VS
1
22
3
21
ROUT+
HP_OUTR
SI-1 Add JSPK2 for PA
2 1U_0603_10V4Z
2
SPGND
SPGND
HPVSS
GND GND ACES_88231-02001
R1211 0_0402_5%
2
CONN@ JMIC2
2
HP_INR 26
SPKR_LIN-
15
1 2
2
5
14
1 2 3 4
1
4
2 1U_0603_10V4Z
CONN@ JSPK2 SPK_LSPK_L+
SLP_S3# 22,32
R1151
SPKL-
1U_0603_10V4Z
C1449
1
D56 PSOT24C_SOT23-3
HP_IN_L 28 HP_IN_R 28
23
HP_EN
1 C1461
2
330P_0402_50V7K
2
3 24
LOUT+
2
HP_IN_L HP_IN_R
C1455
BYPASS
6
2
GND1 GND2 E&T_3806-F04N-02R CONN@
U50 TPA6047A4RHBR QFN 32P
SPKR_LIN+
1
D55 PSOT24C_SOT23-3
@ R1147 1 2 100K_0402_5%
25 REG_EN
HP_INL 27 HP_INL
HP_INR
+VDDA_CODEC_IC
GAIN0
TML
GAIN1
2 2 2.2U_0805_10V6K 2.2U_0805_10V6K
SPKL+
10U_0805_10V4Z
1
1 1
SPKR_EN#
CPVSS
C1456
R1152 0_0805_5% 1
C1446 C1447
SPEAKER
9/20 SP02000CW00
10U_0805_10V4Z 2 1U_0603_10V4Z 2 0.1U_0402_16V7K 2
SPKR_RIN-
3
2 330P_0402_50V7K
330P_0402_50V7K
10U_0805_10V4Z
1
SPKR_RIN+
C1N
2
+5VS
2 1
0_0402_5% LINE_L_OUTR 1 0.47U_0402_6.3V6K
CPVDD
28 LINE_OUT_L
0_0402_5% LINE_R_OUTR 1 0.47U_0402_6.3V6K 1
9
C1451 2
0.47U_0402_6.3V6K R1148 LINE_C_OUTR 1 2 C1450 2 0.47U_0402_6.3V6K R1150 LINE_C_OUTL 1 2 C1452 2
C1457
C1448 2
28 LINE_OUT_R 2
R1144 1 2 0_0603_5%
28
GAIN1
0_0402_5% 2 GAIN1 0_0402_5% 2 GAIN0
33
1
31
1 R1145
32
@ R1143
C1443 1 C1444 1 C1445 1
C1442 1U_0603_10V4Z
29
2 100K_0402_5%
21.6dB
2
Close to Pin29
2
SGND
1 R1142
1
GAIN0
1
2 100K_0402_5%
C1P
1
1 @ R1141
REG_OUT
V 15.6dB
0
TPA6047 LDO OUTPUT 4.7V +VDDA_CODEC
R1140 0_0805_5% 2 1
10
1
+5VS +5VS
13
12dB
12
1
30
0
2 330P_0402_50V7K
VDD
10dB
CPGND
0
11
0
1 2 3 4
1 2
28 MIC_IN_R
3 4
1 2 GND GND ACES_88231-02001
HP_OUTL HP_OUTR
3
3
SI-1 Add Audio board connector
Audio connector JAUDIO 28 MIC_EXT_R 28 MIC_EXT_L
HP_OUTL HP_OUTR
SI-1 Change IR1 to SCR00000E00 +5VL
1 2 3 4 5 6 7 8 9 10
MIC_EXT_R MIC_EXT_L
28 EXTMIC_DET# 28 HP_DET#
EXTMIC_DET# HP_DET#
1
Consumer IR
1 2 3 4 5 6 7 8 9 10
R1158 100_0805_5%
11 12
IR1 1
2
4
2 32 CIR_IN
CIR_IN
3 4
C1466
Vout VCC
4
GND GND IRM-V536/TR1_3P
Compal Secret Data
Security Classification
4.7U_0805_10V4Z
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
AMP & Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
GND1 GND2 ACES_87213-1000G CONN@
B
C
D
Rev 0.1
Montevina UMA
Wednesday, February 18, 2009
Sheet E
29
of
46
5
4
3
Right side USB Power Switch
2
1
Right side ESATA/USB combination Connector
+5VALW
USB_VCCC USB_VCCC
U41
C1381
TPS2061IDGNR_MSOP8 2
4.7U_0805_10V4Z
1 + 2
JESAT C1383 1000P_0402_50V7K
USB_EN#
1
W=100mils
8 7 6 5
OUT OUT OUT OC#
C1382 0.1U_0402_16V4Z
D
GND IN IN EN#
C1380 150U_B_6.3VM_R40M
1 2 3 4
1
2
R1080 1 R1081 1
22 USB20_N0 22 USB20_P0
1
2
1
2 10K_0402_5%
1 0.01U_0402_16V7K SATA_RXN5 1 0.01U_0402_16V7K SATA_RXP5
C1385 2 C1384 2
+5VALW
D45
USB20_P0_R
3
GND GND GND GND TYCO_1759576-1 CONN@
@
4
D
GND A+ ESATA AGND BB+ GND
12 13 14 15
+5VALW
USB
VBUS DD+ GND
5 6 7 8 9 10 11
SATA_TXP5 SATA_TXN5
21 SATA_TXP5 21 SATA_TXN5 21 SATA_RXN5_C 21 SATA_RXP5_C
R1083
1 2 3 4
USB20_N0_R USB20_P0_R
2 0_0402_5% 2 0_0402_5%
@
VIN
IO1
IO2 GND
2
USB20_N0_R
D46
1
+5VALW SATA_TXN5
PRTR5V0U2X_SOT143-4
4
VIN
IO1
2
3
IO2 GND
1
SATA_TXP5
PRTR5V0U2X_SOT143-4
C
C
Finger printer
BT Connector JBT 10
+3VS
2
9
R1084 R1085
@ R1086 1 @ R1087 1
1 0_0402_5% 1 0_0402_5%
2 2
USB20_P6 22 USB20_N6 22 BT_LED 33 CH_DATA 26 CH_CLK 26
1K_0402_5% 1K_0402_5%
2 2
@
0.1U_0402_16V4Z D30 4
+5VALW
IO1
IO2 GND
2
USB20_P7_R
D47 VIN
3
+3VS
IO1
IO2 GND
2
USB20_P6_R
1
PRTR5V0U2X_SOT143-4 R235 1
+3VALW
2 +3VAUX_BT
0_0603_5%
P-TWO_161011-04021
Q105 @ 1
1
B
2 0_0603_5%
PRTR5V0U2X_SOT143-4
3
2
1
R1090 100K_0402_5%
2
2
C1386 @ 1U_0603_10V4Z
0.1U_0402_16V4Z
1
G
1
2
SI2301BDS-T1-E3_SOT23-3
R236 D
3
VIN
USB20_N6_R
1 2 3 4 GND GND
S
USB20_N7_R
1 2 3 4 5 6
4
+5VALW
1
1
2 0_0402_5% USB20_N7_R 2 0_0402_5% USB20_P7_R
R634 1 R635 1
22 USB20_N7 22 USB20_P7
+3VS_FP
2
+3VAUX_BT USB20_P6_R USB20_N6_R
CONN@ JFPR
1
B
8 7 6 5 4 3 2 1
ACES_87213-0800G CONN@
R628 0_0805_5%
C756
GND 8 7 6 5 4 3 2 GND 1
C1387
1
2
0.01U_0402_16V7K
USB cable connector for Right side
22 BT_OFF
R1092 1
2 10K_0402_5%
C1388
1
C1389
2 4.7U_0805_10V4Z
C1390 1 2 0.1U_0402_16V4Z
JUSB +5VALW 32 USB_EN# 22 USB20_N2 22 USB20_P2 22 USB20_N1 22 USB20_P1
USB_EN#
1 2 3 4 5 6 7 8 9 10
11 12
A
1 2 3 4 5 6 7 8 9 10
GND1 GND2
A
ACES_87213-1000G CONN@
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. USB, BT, eSATA Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
30
of
46
5
4
3
2
1
SPI ROM
D
D
+3VL U27 20mils C712 0.1U_0402_16V4Z
1
32 SPI_CLK 32 FWR#
1 R553 1 R554 1 R556
VCC
3
2 32 FSEL#
8
SPI_FSEL# 2 10_0402_5% SPI_CLK_R 2 10_0402_5% SPI_FWR# 2 10_0402_5%
VSS
4
W
7
HOLD
1
S
6
C
5
D
Q
2
SPI_SO 1 R555
FRD# 2 0_0402_5%
FRD# 32
WIESON G6179 8P SPI
R230 SPI_FSEL# 2
1
33_0402_5% R231 SPI_CLK_R 2
SPI_FWR#
1
R232 2
1
C308 2
1
22P_0402_50V8J
1
33_0402_5%
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH WIESO_G6179-100000_8P
22P_0402_50V8J
33_0402_5%
C
C307 2
C309 2
1
C
22P_0402_50V8J
EMI request
B
B
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. BIOS ROM Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
31
of
46
+1.5VS
C301
+3VL_EC +3VS
C715
C716
C717
C718
+3VL
C719
2 2 1000P_0402_50V7K
2
+3VL_EC R572 1
+EC_AVCC
2 0_0805_5%
1
2 33_0402_5%
15P_0402_50V8J 17 CLK_PCI_EC
20 PCI_RST#
2 47K_0402_5%
R578
1 0.1U_0402_16V4Z
2
2 C721
22 EC_SCI# 1
1
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
JOPEN
+3VALW
+3VL
+3VS
1 1
R713 100K_0402_5%
@ R124 10K_0402_5%
R583 10K_0402_5%
R721 10K_0402_5%
2
2
2
2
AD
PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D
LID_SW#
TP_BTN#
R191 10K_0402_5%
33,36 33,36 6 6
2 @ R589 1 0_0402_5%
PS2 Interface
SPI Flash ROM
SLP_S3# SLP_S5# EC_SMI# 2 LID_SW# 0_0402_5% ESB_CLK_R ESB_DAT_R EC_PME# @ R591 2 0_0603_5% 1 9 TSATN# FAN_SPEED 6 FAN_SPEED WWAN_POWER_OFF 26 WWAN_POWER_OFF UTX LAN_POWER_OFF_R R5931 2 +3VL ON/OFFBTN 4.7K_0402_5% 33 ON/OFFBTN
1
33 NUM_LED#
1 C324 0.1U_0402_16V4Z
2
C723 15P_0402_50V8J 1 2
C325 0.1U_0402_16V4Z
2
NC
OSC
122 123
PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
OSC
1
CRY1
2
+EC_AVCC
@ C794 1
2 100P_0402_50V8J
INV_PWM 19
KSO14
@ C795 1
2 100P_0402_50V8J
DIM_LED 35 ACOFF 37
KSO13
@ C796 1
BATT_TEMP BATT_OVP ADP_I ADP_ID TP_BTN#
2 100P_0402_50V8J
KSO12
@ C797 1
2 100P_0402_50V8J
KSO3
@ C798 1
2 100P_0402_50V8J
KSO6
@ C799 1
2 100P_0402_50V8J
KSO8
@ C800 1
68 70 71 72
FAN_SET VCTRL IREF AC_SET
2 100P_0402_50V8J
KSO7
@ C801 1
2 100P_0402_50V8J
KSO4
@ C802 1
2 100P_0402_50V8J
KSO2
@ C803 1
83 84 85 86 87 88
EC_MUTE# USB_EN# I2C_INT
2 100P_0402_50V8J
KSI0
@ C804 1
2 100P_0402_50V8J
KSO1
@ C805 1
2 100P_0402_50V8J
KSO5
@ C806 1
2 100P_0402_50V8J
KSI3
@ C807 1
2 100P_0402_50V8J
KSI2
@ C808 1
2 100P_0402_50V8J
KSO0
@ C809 1
2 100P_0402_50V8J
KSI5
@ C810 1
2 100P_0402_50V8J
KSI4
@ C811 1
2 100P_0402_50V8J
KSO9
@ C812 1
2 100P_0402_50V8J
KSI6
@ C813 1
2 100P_0402_50V8J
KSI7
@ C814 1
2 100P_0402_50V8J
KSI1
@ C815 1
2 100P_0402_50V8J
1
0.01U_0402_16V7K ECAGND 2
BATT_TEMP 36 BATT_OVP 36 ADP_I 37 ADP_ID 36 TP_BTN# 33
FAN_SET 6 VCTRL 37 IREF 37 AC_SET 37 EC_MUTE# 29 USB_EN# 30 I2C_INT 33
R579 1 R580 1
2 10K_0402_5% 2 10K_0402_5%
TP_CLK TP_DATA
TP_CLK 33 TP_DATA 33 R582
97 98 99 109
2 0_0402_5%
1
AC_LED# 36
119 120 126 128
R227 R228 R229
1 1 1
2 2 2
GPI
L30 0_0603_5%
73 74 89 90 91 92 93 95 121 127
2 10K_0402_5%
1
CIR_IN VCC1_PWRGD FSTCHG STD_ADP CAPS_LED# BAT_LED# ON/OFFBTN_LED# SYSON VR_ON AC_IN
2
110 112 114 115 116 117 118
V18R
124
KB926QFD2_LQFP128_14X14
SLP_S4# ENBKL EAPD_CODEC THERM_SCI# SUSP# PWRBTN_OUT# NMI_DBG#
FRD# 31 FWR# 31 SPI_CLK 31 FSEL# 31
SPI_CLK 1
2
BKOFF# 19 M_PWROK 9,22 TP_LED# 33
R254 1
2
NMI_DBG#
CONN.( TYPE "D" KB) CONN@ JKB
SLP_S4# 22 ENBKL 11 EAPD_CODEC 28 THERM_SCI# 22 SUSP# 26,35,37,39 PWRBTN_OUT# 22
C724 4.7U_0603_6.3V6K
14" INT_KBD
PM_PWROK 9,22
100_0402_5%
KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1
+3VL ADP_ID
1
For C Revision
C327 22P_0402_50V8J
1 10K_0402_5% EC_RSMRST# 22 EC_LID_OUT# 22 EC_ON 38 WL_BLUE_LED# 33
+3VL
2
PV-1 For WWAN noise
+5VL
CIR_IN 29 T84 FSTCHG 37 STD_ADP 37 CAPS_LED# 33 BAT_LED# 33 ON/OFFBTN_LED# 33 SYSON 26,35,40 VR_ON 42
R586 EC_RSMRST# 100 101 R588 1 2 EC_ON 0_0402_5% 102 WL_BLUE_LED# 103 PM_PWROK_R 104 BKOFF# 105 M_PWROK 106 TP_LED# 107 108
PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7
FRD# FWR# SPI_CLK FSEL#
33_0402_5% 47_0402_5% 33_0402_5%
2
D16 1
CH751H-40PT_SOD323-2
R714 10K_0402_5% D14 1
+3VL
2 PCI_SERR#
PCI_SERR# 20
CH751H-40PT_SOD323-2
R715 150K_0402_5%
1 2
0_0805_5% R443 1
2
1 C726
LAN_POWER_OFF_R
2 0.1U_0402_16V4Z
L31 1
AC_IN
2 0_0603_5%
2
D13 1
ACIN
0_0402_5% +3VL
+3VL
1
2
1
1
R1099 4.7K_0402_5% 1
R1100 4.7K_0402_5% 33 ESB_CLK 33 ESB_DAT
C791
2 R731 R732
1 1
2 0_0402_5% 2 0_0402_5%
@ C315 10P_0402_25V8K ESB_CLK_R ESB_DAT_R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
ACIN 37
CH751H-40PT_SOD323-2
2
25 LAN_POWER_OFF
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11
1
EC DEBUG port @ R233 2
CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59
+3VL_EC
C725 15P_0402_50V8J
UTX
SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS#
XCLK1 XCLK0
@ R595 20M_0402_5%
4
32.768KHZ_12.5PF_9H03200413 1
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
2
NC
NUM_LED#
CRY2
Y5 3
EMI request
SM Bus
GND GND GND GND GND
PCI_RST#
SLP_S3# SLP_S5# EC_SMI# LID_SW#
63 64 65 66 75 76
DIM_LED ACOFF
R720
GPIO
SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47
2 100P_0402_50V8J
KSO11
SPI Device Interface
1
EC_PME#
77 78 79 80
PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0
EC_PME# 22,29 22 22 33
R190 1 OPP@
33 WL_BLUE_BTN
2
2
SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2
SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2
INV_PWM
+5V_TP
11 24 35 94 113
20 PCI_PME#
DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F
DA Output KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49
21 23 26 27
C720
BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43
1
+3VALW
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82
@ C793 1
AVCC
PWM Output
J1
1
R581 8.2K_0402_5% 2
1
R213 8.2K_0402_5%
R403 1
1
PCI_RST#
1
SUSP#
2
SYSON
HDA_RST#_EC
12 13 37 20 2 0_0402_5% 38
INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13
MISC
2 100P_0402_50V8J
KSO10
2
+3VL
CLK_PCI_EC PCI_RST# ECRST#
GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC &
@ C792 1
1
@ R576 2
1 2 3 4 5 7 8 10
1
@ C722 1
21 GATEA20 21 KB_RST# 22 SIRQ 21,26 LPC_FRAME# 21,26 LPC_AD3 21,26 LPC_AD2 21,26 LPC_AD1 21,26 LPC_AD0
GATEA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
KSO15
2
4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
AGND
2 2 2 2
69
1 1 1 1
For EMI
HDA_RST#_EC
1
Q21 MMBT3904_NL_SOT23-3
ECAGND
R573 R577 R574 R575
VCC VCC VCC VCC VCC VCC
SMB_EC_DA1 SMB_EC_CK1 SMB_EC_DA2 SMB_EC_CK2
3
21,28 HDA_RST#_CODEC
67
9 22 33 96 111 125
U30
1
EC recommend
R251 10K_0402_5%
C
+3VS
2
100P_0402_50V8J
1
R250 56_0402_5%
E
+3VL
BATT_OVP
1
HDA level shift
1
B
2 2 0.1U_0402_16V4Z
1000P_0402_50V7K
2
1
0.1U_0402_16V4Z 1
2 2
0.1U_0402_16V4Z 1 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 G1 G2
ACES_85202-24051
SI-1 Reverse KB connector
2 100P_0402_50V8J
Vendor Recommend
Compal Secret Data
Security Classification Issued Date
2007/08/28
Deciphered Date
2006/07/26
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Compal Electronics, Inc. EC KB926/KB Conn. Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet
32
of
46
B
C
D
E
Power Button
MV-1 For ESD request, close to JTPSW
for debug only
SI-1 Delete SW2
TP_LED# TP_BTN#
3
2
3
+5VS 2
D65 SM05_SOT23
System LED Conn
8 7 6 5 4 3 2 1
+5VALW +5VS
White AMBER
+3VS 32 BAT_LED# 21 SATA_LED# 22 HDDHALT_LED#
ON/OFFBTN_LED#
Keyboard backlight Conn
Caps-Lock Conn
CONN@ JLED 10
8 GND 7 6 5 4 3 2 1 GND
+5VS
CONN@ JCAP 1 2 3 4 GND GND
9
ACES_87213-0800G
+5VS_LED
1 2 3 4 5 6
2
0_0805_5%
CAPS_LED# 32
T/P Board (Inculde T/P_ON/OFF)
CONN@ JKBL
R205 1
1 2 3 4 5 6
CONN@ JTPSW
1 2 3 4 GND GND
1 2 3 4 GND GND
P-TWO_161011-04021
P-TWO_161011-04021
1 2 3 4 5 6
+5VS
TP_LED# TP_BTN#
TP_LED# 32 TP_BTN# 32
P-TWO_161011-04021
T/P Board Conn +3VL
+5VALW
ENE@ R56 1 R149 1 ENE@ main@1 R169
32 ON/OFFBTN_LED# 32 ESB_CLK 32 ESB_DAT 32 I2C_INT +5VALW 32 LID_SW# 32 ON/OFFBTN
OPP@ OPP@
R151 R1191
2
+5V_TP
C313
D67 SM05_SOT23 JCSB CONN@
1 2 3 4 5 6 7 8 9 10 11 12
ESB_CLK_CAP ESB_DAT_CAP
2 FBMA-11-100505-801T 0402 2 FBMA-11-100505-801T 0402
Close to JP59 2 1.8K_0402_5%
2
3
1 2 3 4 5 6 7 8 9 10 GND GND
1 2 3 4 5 6
TP_CLK TP_DATA
TP_CLK 32 TP_DATA 32
P-TWO_161011-04021 @ C730 100P_0402_50V8J
1
1
2
2
@ C731 100P_0402_50V8J
MV-1 For ESD request, close to JTP 3
Mini card LED
P-TWO_161021-10021
2 0_0402_5% C1518 1
C729 0.1U_0402_16V4Z
2
1 2 3 4 GND GND
2
4.7U_0603_6.3V6K
+5VS
+3VS
0.1U_0402_16V4Z 2
R193 10K_0402_5% @ D60
1
R1192 1 OPP@
CONN@ JTP 3
2 0_0402_5% 2 0_0402_5%
1 2 R238 1K_0402_1%
32 NUM_LED#
1
2
1
2 0_0402_5% 2 0_0402_5%
1 1
2 0_0603_5%
1
WL_BLUE_LED#
R691 1
SM05_SOT23
2
32 WL_BLUE_BTN
+5V_TP R53 0_0805_5% OPP@
1
Cypress@ R729 1 R730 1 Cypress@
32,36 SMB_EC_CK1 32,36 SMB_EC_DA1
R51 0_0805_5% Main@ 2
SWITCH BOARD.
+5V_TP
1
1
+5VALW
ENE@ C326 33P_0402_50V8K ESB_CLK_CAP 2 1
2
D28 SM05_SOT23
1
SI-1 Change Cap board power rail to +3VL
TP_DATA TP_CLK 3
2
3
1
1
1
1
D66 SM05_SOT23
2
A
MV-1 For ESD request, close to JCSB 1
D
3
WL_BLUE_LED# 32 Q11 2N7002_SOT23-3
S
2 G
1
30 BT_LED
2
R716 100K_0402_5%
D24 26 WL_LED#
2
26 WW_LED#
3
WL_BLUE_LED#
1
PSOT24C_SOT23-3 4
4
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Compal Electronics, Inc. KBD, ON/OFF, SW, CIR Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet E
33
of
46
4
3
R648 2
+3VS_LS
0_0603_5% 2
37
39
40
41
42
43
44
45
46
38 IN_D1-
IN_D1+
VCC3V
IN_D2-
IN_D2+
GND
IN_D3-
IN_D3+
VCC3V
GND DDC_EN
32
HDMI_DETECT
29
HDMIDAT
SCL_SOURCE
SCL_SINK
28
HDMICLK
R1205 2 2 2 2
1 1 1 1
0_0402_5% 0_0402_5% 4.7K_0402_5% 0_0402_5%
+3VS_LS +3VS_LS
+3VS_LS
@ R1247 2
27 26
+3VS_LS
25
2 R655
4.7K_0402_5% 1 +3VS_LS
1 2 R1249 0_0402_5% 1 0_0402_5%
GND
HDMI_DETECT
24
OUT_D123
OUT_D1+ 22
VCC3V 21
OUT_D220
OUT_D2+ 19
GND
OE*
D
R654 10K_0402_5%
D
S
Q108
2 G C
2N7002_SOT23-3
S IC STHDLS101TQTR QFN 48P HDMI SHIFTER
1
18
2 0_0402_5%
OUT_D3-
thm_pad
17
GND
VCC3V OUT_D3+
VCC3V
VCC3V
12
GND
2
31 30
ANALOG2
2
R1203
R1245 @ R1246 R651 @ R652
SDA_SINK
4.7K_0402_5% 2
1 R1252
+3VS_LS
33
HPD_SINK
16
C
VCC3V
GND
15
@ R1251 1
1
SDA_SOURCE
49 +3VS_LS
1
2
PC1
OUT_D4-
2
2
0_0402_5%
HPD_SOURCE
11
2.2U_0603_6.3V4Z
0_0402_5%
34
ANALOG1(REXT)
13
1 @C1517
0_0402_5% 2 4.7K_0402_5% 2
35
8
10 R1248 1 @ R1250 1
+3VS_LS
1 4.7K_0402_5% +3VS_LS
7
9
9 HDMICLK_NB 2 0_0402_5%
47
C321 GND
2
2
1
1
5
@ R1202 36
1
1
2
FUCNTION2
1 4.7K_0402_5% +3VS_LS
1
4
PC0
2
FUNCTION3
FUNCTION4
FUNCTION1
OUT_D4+
TMDS_B_HPD
VCC3V
3
6
9 HDMIDAT_NB
GND
14
2
R653 3.9K_0402_1% 2 1
GND
@ R1241
3
2
2 4.7K_0402_5%
2 0_0402_5%
1 R1206
48 IN_D4+
2
1
+3VS_LS
2 1 R1204
2 1 @ R1244
R1242 1 2 0_0402_5%
IN_D4-
1
U43
1
10U_0805_6.3V6M
1
+3VS
0.1U_0402_10V6K C318
TMDS_B_DATA0 11 TMDS_B_DATA0# 11
1 @ R1201 4.7K_0402_5%
@ R1243 4.7K_0402_5%
1
1
11 TMDS_B_CLK# 11 TMDS_B_CLK
@ R1240 4.7K_0402_5%
R650 2.2K_0402_5% 2
TMDS_B_DATA1 11 TMDS_B_DATA1# 11
+3VS_LS +3VS_LS
+3VS_LS
R649 2.2K_0402_5%
+3VS_LS
11 TMDS_B_DATA2# 11 TMDS_B_DATA2
+3VS_LS
EQUALIZATION SETTING: [PC1,PC0]=00,8dB [PC1,PC0]=01,4dB (Recommanded) [PC1,PC0]=10,12dB [PC1,PC0]=11,0dB
1
D
1
0.1U_0402_10V6K C319
+3VS_LS
2
0.01U_0402_16V7K C320
5
HDMI_TX_0-
R1207 20K_0402_5%
@C769
@ R656
2
HDMICLK+
2
0.5P_0402_50V8B
+3VS_LS
1
HDMI_TX_2-
0.5P_0402_50V8B
HDMI_CLK-
WCM-2012-900T_0805 HDMI_CLK+ 3
L39 HDMI_TX_0-
1
1
2
2
HDMI_TX_0+
4
4
3
WCM-2012-900T_0805 HDMI_TX0+ 3
1 @ R1215
2 0_0402_5%
@ R1216 1
0_0402_5% 2
HDMI_TX0-
HDMI_TX_1+
4
A
2
1
2
4
3
1 @ R1217
2 0_0402_5%
@ R1218 1
0_0402_5% 2
HDMI_TX_2-
1 4
1
HDMI_TX1-
WCM-2012-900T_0805 HDMI_TX1+ 3
2 0_0402_5%
RB411D T146 _SOT23-3 D31
X 4.7K ohm
+5VS_HDMI 1
R1244
X
X
R653 R1206
X
3.9K ohm 499 ohm 499 ohm 0 ohm X 0 ohm
X
X
X
2.2uF
0 ohm
X
X
4.7K ohm
R1251
X
X
4.7K ohm
R1252 R1247
0 ohm X
0 ohm X
R1249
0 ohm
0 ohm
R1245
0 ohm
0 ohm
R1246 R1203
C773 R1207 R1208
X
HDMI_DETECT
X
R665 1 2 1K_0402_1%
L40 1
C774 330P_0402_50V7K 2
0 ohm X
X
X
4.7K ohm
X
0 ohm
X 4.7K ohm
X
2
C314 @ 2200P_0402_25V7K
18 16 15 19
HDMI_CLKHDMI_CLK+ HDMI_TX0HDMI_TX0+ HDMI_TX1HDMI_TX1+ HDMI_TX2HDMI_TX2+
12 10 9 7 6 4 3 1
+5V SDA SCL HP_DET CKCK+ D0D0+ D1D1+ D2D2+
CEC Reserved
GND GND GND GND GND GND GND GND DDC/CEC_GND
13 14 2 5 8 11 20 21 22 23 17
A
X X
X
0.1uF
1uF
1uF
Security Classification
V
X
X
Issued Date
X
1 0.1U_0402_16V4Z C773
SUYIN_100042MR019S153ZL CONN@
X
V
HDMIDAT HDMICLK 2
FBML10160808121LMT_0603 1
D32 SKS10-04AT_TSMA
4.7K ohm
X
2
B
JHDMI1
X
R1250
R1202
1 @ R1219
4.7K ohm
4.7K ohm
R1205
3
4.7K ohm X
HDMI_TX2-
4
0 ohm X
WCM-2012-900T_0805 HDMI_TX2+ 3
2
X
2 2200P_0402_25V7K
X
R1241 2
0 ohm
C273
R1243
R1248
L42
HDMI_TX_2+
X
@ 1
R1204 4.7K ohm
C1517
L41 1
X
+5VS
1
0_0402_5% 2
X
HDMI Connector
1
@ R1214 1
R1242 R1201
Parade 8171
R50 3.9K_0402_1%
2 0_0402_5%
Parade 8101T
2
3
1 @ R1213
R1240
ST
R49 3.9K_0402_1% 2 1
2
4
HDMI_TX_1-
HDMI_TX_1+ 0.5P_0402_50V8B
2
4
@C772
2
2 HDMICLK+ B
@ R659 1 2 68_0402_5%
2 68_0402_5%
0_0402_5% 2
2
HDMI_TX_0+ 0.5P_0402_50V8B
SI-1 Use ST only
L38 1
+3VS_LS
@ R658 1
To option use ST or Parade
1
@C770
2 68_0402_5%
HDMI_TX_1@C771 HDMI_TX_2+
R1208 7.5K_0402_1%
HDMICLK-
1
1 TMDS_B_HPD 0_0402_5%
@ R1212 1
@ R657
2 68_0402_5%
1
11 TMDS_B_HPD#
HDMICLK-
R9
TMDS_B_HPD#
1
4.7K ohm
X
Compal Secret Data 2007/08/28
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. HDMI LS & Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Sheet
Wednesday, February 18, 2009 1
34
of
46
6
+1.8V to +1.8VS Transfer
SI7326DN-T1-E3_PAK1212-8
+1.8V
2
C1513
1
2
2
SUSP# 26,32,37,39
+1.8V
+0.9V
H3 HOLEA
H4 HOLEA
H5 HOLEA
H6 HOLEA
H7 HOLEA
H8 HOLEA
H9 HOLEA
1
H2 HOLEA
1
SUSP#
1 +VCCP
+1.5VS
2
1
C1515
1
5
H1 HOLEA
+3VS
1
C1514
Q13B
Discharge circuit +5VS
C
0.1U_0402_16V4Z
1
1
2
C1512 SUSP 41
1
SYSON
1
26,32,40 SYSON
SUSP
1
Q13A
100K_0402_5%
1
SYSON#
1
100K_0402_5% 41 SYSON#
0.1U_0402_16V4Z
R640
0.1U_0402_16V4Z
1 R639
6
2
SI-1 For EMI DDR issue SI-R 2 caps and change to GND
+3VL
0.1U_0402_16V4Z
1
2
2 RUNON
@ C768
10U_0805_10V4Z
1
4
@ C767
0.1U_0402_16V4Z
2
10U_0805_10V4Z
1
+3VL
1 2 3
5
@ C766
1
+1.8VS
U34 @
C
0.01U_0402_16V7K
1
+1.8V
Q35 2N7002_SOT23-3
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6 4 3 2
2
S
C765
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2 C65 4700P_0402_25V7K
D
DIM_LED# D
2 G
2
Q34B
1
1
Q34A
2
2
1 4
SUSP
5
DIM_LED
32 DIM_LED
470_0402_5% SUSP
R224 470_0402_5%
C294 0.1U_0402_16V4Z
2
1
R638
1
RUNON
2
1
1
RUNON_3VS
2
1
R637 10K_0402_5% 2
10U_0805_10V4Z
1
C764
3
2
3 10U_0805_10V4Z
1 330K_0402_5%
+5VS_LED
Q15
SI2301BDS-T1-E3_SOT23-3
0.1U_0402_16V4Z
2
R636
2
1
10U_0805_10V4Z
2
C762
3
2
2
1
C761 4
R223 330K_0402_5%
10U_0805_10V4Z
1
1
+5VS
D
C760
SI7326DN-T1-E3_PAK1212-8 +3VS +3VALW U33 1 2 5 3 1 1 C759 C763
G
D
B+
0.1U_0402_16V4Z
+5VALW B+
1
DIM LED
+3VALW to +3VS Transfer
+5VS
SI7326DN-T1-E3_PAK1212-8 U32 1 2 5 3
2
S
+5VALW to +5VS Transfer
3
2
4
4
5
+1.8VS H13 HOLEA
1
1
H12 HOLEA
1
1
H11 HOLEA
2
470_0402_5%
SUSP
1
5
1
1 2 3 Q12B SUSP
@ R647
470_0402_5%
D
3
2
4
2 6 Q12A SYSON#
2N7002DW-7-F_SOT363-6
5
H10 HOLEA
R646
2N7002DW-7-F_SOT363-6
1
1 2 Q9B SUSP
470_0402_5%
1
2
3
2 6 Q9A SUSP
R643
470_0402_5%
4
4
5
1
2 3 Q6B SUSP
R645
470_0402_5% 2N7002DW-7-F_SOT363-6
2 6 1
2
2N7002DW-7-F_SOT363-6
Q6A SUSP
R644
470_0402_5%
2N7002DW-7-F_SOT363-6
R642
470_0402_5%
2N7002DW-7-F_SOT363-6
R641
1
1
B
1
B
S
@ Q44
1
FM1 1
FM2 1
FM3
FM4 1
2 G 2N7002_SOT23-3
T21 T33 T45 T52 T60 T62 T64 T73 T75
T32 T34 T51 T53 T61 T63 T72 T74 T76
For ICT
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. DC/DC Interface Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
35
of
46
A
B
C
D
+3VALW 3
PQ3 TP0610K-T1-E3_SOT23-3 +3VL
BATT
1 PR9 2 100K_0402_5%
connect to KBC pin97
PL1 HCB2012KF-121T50_0805 2 PL2 HCB2012KF-121T50_0805 1 2
1
PJSOT24C_SOT23-3 2
1
0.01U_0402_25V7K PC6
1 PC3 1000P_0402_50V7K
2
PD1
2 1 PC2 100P_0402_50V8J
3
2
ACES_87302-0441
105K_0402_1% PR6 1 2
8 2
1
2
ADPIN
+
1
0 -
PU1A LM358ADT_SO8
PR5 10K_0402_5% 2 1
P
3
BATT_OVP 32
G
2
2
VIN
RLZ3.6B_LL34
1 2 PR3 10K_0402_5%
1
4
ADP_SIGNAL
PC5 1000P_0402_50V7K 2 1
6 5 4 3 2 1
@1000P_0402_50V7K
PC4 100P_0402_50V8J 2 1
GND GND 4 3 2 1
2
PR2 10K_0402_5%
+5VALW
499K_0402_1% PR4 1 2
PD4
1
JDC1
PC12
1
PR8 2K_0402_5%
1
1
2 1
ADP_ID 32
1
2
1
0.01U_0402_25V7K PC1
340K_0402_1% PR1 1 2
AC_LED# 32
2
2
VMB
1
PD2
3
PC8 1000P_0402_50V7K
PC9 0.01U_0402_50V4Z
CPU
2
3 1
PJSOT24C_SOT23-3
3
1
1
1
2 PJSOT24C_SOT23-3
PH1 10K_TH11-3H103FT_0603_1%
PR14 100_0402_5%
1 1 PC10 0.22U_0603_10V7K
-
8 6
2 PR11 150K_0402_1%
PR12 2.49K_0402_1%
PR15 150K_0402_1%
1
2
2
+3VL
2
PR16 6.49K_0402_1% 1 2
+
1
S
P
1
+5VALW
D
3
SMB_EC_CK1 32,33
37
5
0 G
SMB_EC_CK1 BAT_ID
EN0 38
PR10 200K_0402_1% 1 2
4
SMB_EC_DA1 32,33
1
SMB_EC_DA1
7
PQ1 SSM3K7002FU_SC70-3
2 G
PU1B LM358ADT_SO8
PC11 1000P_0402_50V7K
2
2
2
2
PR13 100_0402_5%
1
3
PR7 604K_0402_1% 1 2
+5VS
1
PD3 SUYIN_200045MR006G101ZR
PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C
1
1
EC_SMD EC_SMC
2
1 2 3 4 5 6 7 8
2
1 2 3 4 5 6 GND GND
BATT
PL3 HCB2012KF-121T50_0805 2 PL4 HCB2012KF-121T50_0805 1 2
JBATT
PR17 1K_0402_5%
2
BATT_TEMP 32
4
4
Compal Secret Data
Security Classification Issued Date
2007/05/29
Deciphered Date
2008/05/29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title
Compal Electronics, Inc. DC Connector/CPU_OTP
Size
Document Number
Rev 0.1
Montevina Consumer Discrete Date:
W ednesday, February 18, 2009 D
Sheet
36
of
46
A
B
C
P4
D
B+
BATT P2 PQ102 AO4433 1P SO8
PR102
4
1 1 5 6 7 8
3
3 2 1
2 21
2
2
1 2
BQ24740VREF 1
20
19
18
47K_0402_5% PR119 BAT_ID 36
2
2 G
1
PR121 200K_0402_1%
1
IREF 32
1
PR120 2 1 133K_0402_1%
PR122 681K_0402_1% 1 2
2
PC124 0.1U_0603_25V7K
3
BATT
S
2
17
PQ111 SSM3K7002FU_SC70-3
1
PC118 0.1U_0402_10V7K
1
PC121 100P_0402_50V8J 2 1
2
1 2
PC105 4.7U_0805_25V6-K
1
1
DPMDET
CELLS
SRP
SRN
BAT
SRSET
IADAPT
PC135 @470P_0603_50V8J
1U_0603_10V6K PR117 100K_0402_5% 1 2
2
1VIN_1
1
PQ110
PC119
PR124 1K_0402_5% 1 2
VIN 1 2
PU102B
PACIN
1
7
O
LM393DG_SO8
1
G
8 P
-
1
PR133 10K_0603_0.1%
3
PR134 10K_0402_5% 2
2
PD103 RLZ4.3B_LL34
S FSTCHG# 1
PQ113 SSM3K7002FU_SC70-3 3
STD_ADP 32
PR136 60.4K_0402_1% 1 2 VIN_1
D
2 G
32 FSTCHG
1.24VREF
PC126 0.047U_0402_16V7K
+
2
PQ112 SSM3K7002FU_SC70-3
6
ACIN 32
PR127 10K_0402_1%
2
1 PU102A LM393DG_SO8
D
2 G 3
1
5
1
PR132 100K_0402_5% 2 1
CHGEN#
PR130 2.15K_0402_1% 1 2
2
+3VL
4
PR128 10K_0402_5% 2 1
1 2
PR126 100K_0402_1%
8
PC125 0.1U_0603_25V7K
PR129 10K_0402_1% 2 1
2
1
+3VL
P 4
4 S TR AO4468 1N SO8
22
IADAPT
15
2 PC120 0.22U_0603_10V7K 2 1
2
PC123 0.1U_0402_10V7K
2
PR135 10K_0603_0.1%
G
1
O -
PR141 @4.7_1206_5%
1 1SS355_SOD323-2
VIN
1 2
+
23
DL_CHG
2
+3VL
PR131 133K_0402_1%
2
REGN
D
PR123 1M_0402_5% 1 2
PR125 47_1206_5%
3
LX_CHG
24
PC128 4.7U_0805_25V6-K
PGND
VIN
VIN
25
PR112 0.015_1206_1% 1 2
PC116 4.7U_0805_25V6-K
LODRV
ISYNSET
PR118 10K_0402_5% 1 2
PD104 1SS355_SOD323-2
PL102 10U_LF919AS-100M-P3_4.5A_20% 1 2
2 2
EXTPWR
PR116 15K_0402_1%
2
2
PR115 100K_0402_1%
Charge Detector
BATT
0.1U_0402_10V7K
1
REGN
PQ106 DTC115EUA_SC70-3
4
2
PH
VADJ
32
1
VDAC
1
1
14
32 ADP_I
3
26
1
12 13
2
PR114 @0_0402_5% 1 2
PC117 1U_0603_10V6K
2
HIDRV
2
PD102 VADJ
PR113 143K_0402_1%
16
1
32 VCTRL
PU101 BQ24740RHDR_QFN28_5X5
VREF
AO4466_SO8 PC111 1
+3VL 11
SSM3K7002FU_SC70-3
2 1SS355_SOD323-2
10
27
PC114 4.7U_0805_25V6-K
28
ACOFF
PQ108
1
BTST
PC110 1U_0805_25V6K 1 2 PR142 0_0402_5% BST_CHG1 2 PR139 0_0402_5% DH_CHG 1 2
5 6 7 8
CHGEN
PVCC
AGND
2
29
2
1
2 ACN
TP
IADSLP
BQ24740VREF
1
PR108 10_1206_5% 1 2
1
1
S
1U_0603_6.3V6M
PQ109
2 G
PD101 ACOFF#
D
3
PACIN
PR111 3K_0402_1% 1 2
2
ACOFF#
3 2 1
PC112 1 2
PACIN_1 38
VIN
CHG_B+
PC113 4.7U_0805_25V6-K 2 1
9
PC104 4.7U_0805_25V6-K
2 ACN
1 2
ACP 3
5
6
4 LPMD
ACDET
LPREF 8
PR103 47K_0402_5% 1 2
PR105 10K_0402_5%
1
SUSP#
8 7 6 5
CHG_B+
CHGEN# 7
26,32,35,39
PR110 0_0402_5% 1 2
0.012_2512_1%
2
1 2 3
PL101 HCB2012KF-121T50_0805 2
PC102 1U_0603_6.3V6M
PC108 0.1U_0603_25V7K
1 2
PR140 100K_0402_5%
1
1
ACDET ACSET
2
1
PC107 @0.01U_0402_16V7K
1 PR109 150K_0402_5%
3
2 S
PR104 0_0402_5% 2
ACSET
1
PQ105 DTC115EUA_SC70-3
3 1
D
1
2 PR106 200K_0402_5%
PQ104 DTA144EUA_SC70-3
4
2 1
1
3
1 2
1
2
2
3
PQ107 SSM3K7002FU_SC70-3 2 G
8 7 6 5
32 AC_SET PC106 0.47U_0603_16V7K 2 Structure> 1
B
C
D
E
1
1
Compal confidential
2
2
Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M core logic 3
3
2009-02-16 REV:1.0 4
4
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cover Sheet Rev 0.1
Montevina UMA
Date:
A
B
C
D
Wednesday, February 18, 2009
Sheet E
1
of
46
A
B
C
Compal confidential
D
E
Montevina Consumer UMA CK505
Mobile Penryn
Thermal Sensor EMC1402
1
72QFN
Clock Generator SLG8SP553V
uFCPGA-478 CPU
P06
1
P17
P6, 7, 8
Fan conn
P06
H_A#(3..35)
FSB
H_D#(0..63)
LVDS Panel Interface CRT
DDR2 800MHz 1.8V P19
Intel Cantiga MCH
HDMI
DDR2 SO-DIMM X2 BANK 0, 1, 2, 3
USB conn x1
P35
BT Conn
USB2.0 X12
PCI-E BUS*4
WLAN
Mini-Card WWAN
P26
P26
P19
Azalia
Intel ICH9-M Mini-Card
2
P30
C-Link USB Camera
P25
P30
P9,10, 11, 12, 13, 14
DMI X4
RTL8103EL (10/100M)
P15, 16
Dual Channel
FCBGA 1329 GM47
P18
Support V1.3 2
667/800/1066 MHz 1.05V
P30
SATA Slave
mBGA-676 New Card
Finger print
SATA Master-1
CardReader
SATA Slave
P20,21,22,23
P26
5 in1 Slot P27
Audio CKT
P27
AMP & Audio Jack
Codec_IDT92HD75B
TPA6047
P28
RJ45/11 CONN
LPC BUS
P25
3
P29
MDC
3
P28
SATA HDD Connector
P24
ENE KB926 P32
RTC CKT. P21
P30
P32
P33
P33
e-SATA Connector
Int.KBD
Touch Pad CONN.
LED
SATA ODD ConnectorP24
SPI
USB Board Conn USB port x2
SPI ROM SST25VF080P31
ACCELEROMETER-1 P24 ST
P30
4
4
K/B backlight Conn
Capsense switch Conn
P33
P33
Compal Secret Data
Security Classification
DC/DC Interface CKT.
2006/02/13
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P36
Block Diagram Rev 0.1
Montevina UMA
Date:
A
B
C
D
Wednesday, February 18, 2009
Sheet E
2
of
46
A
Voltage Rails
Symbol Note : O MEANS ON
X MEANS OFF
USB assignment:
: means Digital Ground : means Analog Ground
power plane +5VALW
+B
+1.5V
+5VS +3VS +1.5VS +0.75V +VCCP +CPU_CORE +2.5VS +1.8V
+3VALW
State
S0
O
O
O
O
S1
O
O
O
O
S3
O
O
O
X
S5 S4/AC
O
O
X
X
S5 S4/ Battery only
O
X
X
X
X
X
X
X
S5 S4/AC & Battery don't exist 1
@ : means just reserve , no build 45@ : means need be mounted when 45 level assy or rework stage. DEBUG@ : means just reserve for debug. BATT @ : means need be mounted when 45 level assy or rework stage. CONN@ : means ME part ESATA @ : means just reserve for ESATA GS @ : means just reserve for G sensor FP @ : means just reserve for Finger Print Multi @ : means just reserve for Multi Bay NewC@ : means just reserve for New card Main@ : means just reserve for Main stream OPP@ : means just reserve for OPP 2MiniC@ : means just reserve for 2nd Mini card slot PA @ : means just reserve for PA PR @ : means just reserve for PR
SMBUS Control Table SOURCE INVERTER BATT SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMB_CK_CLK1 SMB_CK_DAT1 LCD_CLK LCD_DAT
KB926 KB926 ICH9 Cantiga
USB-0 Right side(with eSATA) USB-1 Left side USB-2 Left side USB-3 Cardreader USB-4 Camera USB-5 WLAN USB-6 Bluetooth USB-7 Finger Printer USB-8 MiniCard(WWAN/TV) USB-9 Express card USB-10 X USB-11 X
X X X X
V X X X
SERIAL Thermal EEPROM Sensor
V X X X
X V X X
SODIMM CLK CHIP
X X V X
X X V X
MINI CARD
X X V X
LCD
X X X V
Cap sensor board
NEW CARD
V X X X
X X V X
PCIe-1 PCIe-2 PCIe-3 PCIe-4 PCIe-5 PCIe-6
WWAN X WLAN GLAN (Realtek) X New Card
I2C / SMBUS ADDRESSING DEVICE
HEX ADDRESS
DDR SO-DIMM 0 DDR SO-DIMM 1 CLOCK GENERATOR (EXT.)
A0 A4 D2
10100000 10100100 11010010
X X V X
Compal Secret Data 2007/08/28
Deciphered Date
2006/03/10
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Notes List Rev 0.1
Montevina UMA
Date:
A
1
G sensor
Security Classification Issued Date
PCIe assignment:
Wednesday, February 18, 2009
Sheet
3
of
46
5
4
3
2
1
60mA
50mA
25mA 1A D
+V_BATTERY
10mA 177mA
INVPWR_B+
ICH9
1.7A
+3VALW
278mA
LAN
VIN 2A
1A
LVDS CON 300mA
AC
5.89A
3.39A
B++
+3VS
1.5A
657mA
C
0.3A
0.58A
+1.5VS
+5VALW
2.2A 1.56A
1.3A
ICH_VCC1_5 ICH9
1A
ICH9
1A
35mA
+5VS
B+ 7A
10mA
1.8A
700mA B
3.7A
3.7 X 3=11.1V
1.9A
B+++
12.11A
DDR2
+1.8V 50mA
800Mhz
4.7A
New card ICH9 +LCDVDD
LVDS CON
1.05V_B+
10mA
+VCC_CORE
1.26A
+VCCP
34A/1.025V
+3VS_CK505 C
Mini card (WLAN) Mini card (TV tu/WWAN/Robeson)
+VDDA IDT 9275B +5VAMP ODD SATA
B
PC Camera(4.75V)
+0.9V
2.3A
CPU_B+
SPI ROM
4G x2
1.17A
2A
+3VALW_EC
MCH 50mA
BATT
+3VS_DVDD ALC268
RT5158 250mA
DC
Finger printer
D
20mA
0.3A
+3VAUX_BT
ICH9 MCH CPU
CPU
A
A
Compal Secret Data
Security Classification Issued Date
2007/08/28
Deciphered Date
2006/03/10
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Power delevry Size C Date:
5
4
3
2
Compal Electronics, Inc. Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009 1
Sheet
4
of
46
A
1
1
Compal Secret Data
Security Classification 2007/08/28
Issued Date
Deciphered Date
2006/03/10
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Notes List Rev 0.1
Montevina UMA
Date:
A
Wednesday, February 18, 2009
Sheet
5
of
46
5
4
3
2
1
ITP-XDP Connector +VCCP
XDP_TDI
R2
1
2
54.9_0402_1%
XDP_TMS
R3
1
2
54.9_0402_1%
XDP_TDO
R4
1
2
54.9_0402_1%
XDP_TRST#
R7
1
2
54.9_0402_1%
XDP_TCK
R8
1
2
54.9_0402_1%
D
9 H_A#[3..16]
JCPU1A
9 H_ADSTB#1
H_STPCLK# H_INTR H_NMI H_SMI#
H_A20M# H_FERR# H_IGNNE#
A6 A5 C4
H_STPCLK# H_INTR H_NMI H_SMI#
D5 C6 B4 A3
A20M# FERR# IGNNE#
B
RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]
H_BR0#
D20 B3
H_IERR# H_INIT#
LOCK#
H4
H_LOCK#
RESET# RS[0]# RS[1]# RS[2]# TRDY#
C1 F3 F4 G3 G2
H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY#
G6 E4
H_HIT# H_HITM#
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#
BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
THERMAL PROCHOT# THERMDA THERMDC THERMTRIP#
STPCLK# LINT0 LINT1 SMI#
M4 N5 T2 V3 B2 D2 D22 D3 F6
F1
IERR# INIT#
HIT# HITM#
A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
ICH
21 H_A20M# 21 H_FERR# 21 H_IGNNE#
H_DEFER# H_DRDY# H_DBSY#
BR0#
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
H5 F21 E1
DEFER# DRDY# DBSY#
ADDR GROUP_1
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1
C
H_ADS# H_BNR# H_BPRI#
D21 A24 B25 C7
A22 A21
This shall place near CPU
H_DEFER# 9 H_DRDY# 9 H_DBSY# 9 H_BR0# 9 T1 H_INIT# 21
Place TP with a GND 0.1" away
H_LOCK# 9 H_RESET# 9 H_RS#0 9 H_RS#1 9 H_RS#2 9 H_TRDY# 9 H_HIT# 9 H_HITM# 9
H_PROCHOT#
H CLK BCLK[0] BCLK[1]
H_ADS# 9 H_BNR# 9 H_BPRI# 9
H_THERMDA_R H_THERMDC_R H_THERMTRIP#
CLK_CPU_BCLK CLK_CPU_BCLK#
C
+3VS
0.1U_0402_16V4Z
K3 H2 K2 J3 L1
H1 E2 G5
ADS# BNR# BPRI#
CONTROL
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
XDP/ITP SIGNALS
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
XDP_DBRESET# 22
R13 R14 R15
1 1 1
2 56_0402_1% 2 0_0402_5% 2 0_0402_5%
+VCCP H_THERMDA H_THERMDC C3 1
H_THERMTRIP# 9,21
+3VS
CLK_CPU_BCLK 17 CLK_CPU_BCLK# 17
1 C2 U1
2 1 H_THERMDA
2
H_THERMDC 2 2200P_0402_50V7K THERM#
3
R16 1 2 10K_0402_5%
4
VDD
SMCLK
DP
SMDATA
DN
ALERT#
THERM#
GND
8
SMB_EC_CK2
7
SMB_EC_DA2
6
R6 1
SMB_EC_CK2 32 SMB_EC_DA2 32 2 10K_0402_5%
+3VS
5
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
RESERVED
9 H_REQ#0 9 H_REQ#1 9 H_REQ#2 9 H_REQ#3 9 H_REQ#4 9 H_A#[17..35]
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0
ADDR GROUP_0
9 H_ADSTB#0
21 21 21 21
D
B
Fan Control circuit SI-1 Change to voltage control circuit
Penryn +5VS +VCCP +3VS
FAN_SPEED
E
C
OCP# 3 1 @ Q1 MMBT3904_NL_SOT23-3
2.2U_0603_6.3V4Z
1
2
B
32 FAN_SPEED H_PROCHOT#
1
OCP# 22
C1510 1000P_0402_50V7K
2
U51
1
R1209 10K_0402_5%
2 2
1
C4 @ R17 56_0402_5%
1
9 8 7 6 5
Thermal Pad VEN GND VIN GND VO GND VSET GND
C5 0.1U_0402_16V4Z
2
1 2 3 4
+5VS_FAN 1
G996RD1U_TDFN8_3X3
2
CONN@ JFAN1
C1509
1 2 3
2.2U_0603_6.3V4Z
ACES_85204-03001
FAN_SPEED
+5VS
1 2 3
G1 G2
4 5
D63 2
3 2 1
32 FAN_SET
+VCCP A
Vcc Line to be protected GND
A
2
DLPT05-7-F_SOT23-3
1
R18 56_0402_5%
Compal Secret Data
Security Classification
H_IERR#
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. Penryn(1/3)-AGTL+/ITP-XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
6
of
46
4
3
2
1
+VCC_CORE
2 1K_0402_5% 2 1K_0402_5% T2 T3 T4 T5 T6 17 CPU_BSEL0 17 CPU_BSEL1 17 CPU_BSEL2
+V_CPU_GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]
MISC
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3
COMP[0] COMP[1] COMP[2] COMP[3]
R26 U26 AA1 Y1
COMP0 COMP1 COMP2 COMP3
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
E5 B5 D24 D6 D7 AE6
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI#
DATA GRP 2
Penryn
* Route the TEST3 and TEST5 signals through a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
166
0
1
1
200
0
1
0
266
0
0
0
H_DPRSTP# 9,21,42 H_DPSLP# 21 H_DPWR# 9 H_PWRGOOD 21 H_CPUSLP# 9 H_PSI# 42
R23
R24
R25
R26
Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
D
+VCCP R19
G21 +VCCPA +VCCPB V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
1 1
2 2
0_0402_5% 0_0402_5%
C
R20 1 + C6 330U_D2E_2.5VM_R7 2
B26 C26
VCCA[01] VCCA[02]
+1.5VS
AD6 AF5 AE5 AF4 AE3 AF3 AE2
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
AF7
VCCSENSE
AE7
VSSSENSE
42 42 42 42 42 42 42
1 C7 2
1 C8 2
Near pin B26
VCCSENSE 42 VSSSENSE 42
B
Penryn .
Length match within 25 mils. The trace width/space/other is 20/7/25. +VCCP 1
B
H_DSTBN#3 9 H_DSTBP#3 9 H_DINV#3 9
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
0.01U_0402_16V7K
1 1
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#
H_DSTBN#2 9 H_DSTBP#2 9 H_DINV#2 9 H_D#[48..63] 9
27.4_0402_1% 2 1
@ R21 @ R22
D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]#
JCPU1C
54.9_0402_1% 2 1
9 H_DSTBN#1 9 H_DSTBP#1 9 H_DINV#1
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
DATA GRP 1
C
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2
27.4_0402_1% 2 1
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16..31]
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
DATA GRP 3
9 9 9 9
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#
DATA GRP 0
D
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
+VCC_CORE
H_D#[32..47] 9
JCPU1B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0
54.9_0402_1% 2 1
9 H_D#[0..15]
10U_0805_6.3V6M
5
2
+V_CPU_GTLREF
+VCC_CORE
1
R27 1K_0402_1%
R28
1
2 100_0402_1%
VCCSENSE
R30
1
2 100_0402_1%
VSSSENSE
2
R29 2K_0402_1%
Close to CPU pin within 500mils.
Close to CPU pin AD26 within 500mils.
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
A
Compal Electronics, Inc. Penryn(2/3)-AGTL+/ITP-XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
7
of
46
5
4
3
2
1
+VCC_CORE
1
Place these capacitors on L8 (North side,Secondary Layer)
2
1
C9 10U_0805_6.3V6M
2
1
C10 10U_0805_6.3V6M
2
1
C11 10U_0805_6.3V6M
2
1
C12 10U_0805_6.3V6M
2
1
C13 10U_0805_6.3V6M
2
C14 10U_0805_6.3V6M
1
2
1
C15 10U_0805_6.3V6M
2
C16 10U_0805_6.3V6M
D
D
+VCC_CORE JCPU1D
B
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
Place these capacitors on L8 (North side,Secondary Layer)
1
2
1
C17 10U_0805_6.3V6M
2
1
C18 10U_0805_6.3V6M
2
1
C19 10U_0805_6.3V6M
2
1
C20 10U_0805_6.3V6M
2
1
C21 10U_0805_6.3V6M
2
C22 10U_0805_6.3V6M
1
2
1
C23 10U_0805_6.3V6M
2
C24 10U_0805_6.3V6M
+VCC_CORE
Place these capacitors on L8 (North side,Secondary Layer)
1
2
1
C25 10U_0805_6.3V6M
2
1
C26 10U_0805_6.3V6M
2
1
C27 10U_0805_6.3V6M
2
1
C28 10U_0805_6.3V6M
2
1
C29 10U_0805_6.3V6M
2
C30 10U_0805_6.3V6M
1
2
1
C31 10U_0805_6.3V6M
2
C32 10U_0805_6.3V6M
+VCC_CORE
Place these capacitors on L8 (North side,Secondary Layer)
1
2
1
C33 10U_0805_6.3V6M
2
1
C34 10U_0805_6.3V6M
2
1
C35 10U_0805_6.3V6M
2
1
C36 10U_0805_6.3V6M
2
1
C37 10U_0805_6.3V6M
2
C38 10U_0805_6.3V6M
1
2
1
C39 10U_0805_6.3V6M
2
C40 10U_0805_6.3V6M C
Mid Frequence Decoupling
ESR 1980uF
Near CPU CORE regulator
1 C41
+ 2
@ C42
1 + 2
1 +
C43
2
1 +
C44
2
330U_D2_2VY_R7M
+VCC_CORE
330U_D2_2VY_R7M
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
330U_D2_2VY_R7M
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
330U_D2_2VY_R7M
C
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
B
+VCCP
1
2
C45 0.1U_0402_10V6K
Inside CPU center cavity in 2 rows 1
2
1
C46 0.1U_0402_10V6K
2
1
C47 0.1U_0402_10V6K
2
1
C48 0.1U_0402_10V6K
2
1
C49 0.1U_0402_10V6K
2
C50 0.1U_0402_10V6K
Penryn .
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. Penryn(3/3)-AGTL+/ITP-XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
8
of
46
4
3
B15 K13 F13 B13 B14
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_CPURST# H_CPUSLP#
B6 F12 C8
H_RS#0 H_RS#1 H_RS#2
H_RS#_0 H_RS#_1 H_RS#_2
2 1 2
1
2 10K_0402_5%
CLKREQ#_7
R40
1
2 10K_0402_5%
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
7 7 7 7
C54
H_RS#0 6 H_RS#1 6 H_RS#2 6
2
PLT_RST#
within 100 mils from NB
0.1U_0402_16V4Z
R41 R42
22 PM_BMBUSY# 7,21,42 H_DPRSTP# 15 PM_EXTTS#0 16 PM_EXTTS#1 22,32 PM_PWROK 1 2 1 2 100_0402_5% 0_0402_5%
PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_PWROK THERMTRIP# DPRSLPVR
1 @ C55 2
1
+1.8V
R55
C59
2 1
1
2
R48 10K_0402_1%
C57 2
221_0603_1% 2 1
+H_SWNG
1
V_DDR_MCH_REF 0.1U_0402_16V4Z
R54
CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
R45 10K_0402_1%
15,16 V_DDR_MCH_REF
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
BA17 AY16 AV16 AR13
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
BD17 AY17 BF15 AY13
M_ODT0 M_ODT1 M_ODT2 M_ODT3
BG22 BH21
SMRCOMP SMRCOMP#
BF28 BH28
SMRCOMP_VOH SMRCOMP_VOL
AV42 AR36 BF17 BC36
V_DDR_MCH_REF SM_PWROK SM_REXT TP_SM_DRAMRST#
B38 A38 E41 F41
CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK#
F43 E43
CLK_MCH_3GPLL CLK_MCH_3GPLL#
AE41 AE37 AE47 AH39
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
AE40 AE38 AE48 AH40
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
AE35 AE43 AE46 AH42
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
AD35 AE44 AF46 AH43
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST#
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
11 CFG5 11 CFG6 11 CFG7 11 CFG8 11 CFG9 11 CFG10 11 CFG11 11 CFG12 11 CFG13 11 CFG14 11 CFG15 11 CFG16 11 CFG17 11 CFG18 11 CFG19 11 CFG20
6 6 6 6 6
R47
BC28 AY28 AY36 BB36
PEG_CLK PEG_CLK#
2
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
R29 B7 N33 P32 AT40 AT11 T20 R32
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
15 15 16 16
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
15 15 16 16
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
15 15 16 16
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
15 15 16 16
M_ODT0 M_ODT1 M_ODT2 M_ODT3 R34 R35
D
15 15 16 16
+1.8V
1 1
2 80.6_0402_1% 2 80.6_0402_1%
1 1
2 0_0402_5% 2 499_0402_1%
Follow Design Guide For Cantiga: 80.6ohm
R36 R37 T29
CLK_MCH_DREFCLK 17 CLK_MCH_DREFCLK# 17 MCH_SSCDREFCLK 17 MCH_SSCDREFCLK# 17 CLK_MCH_3GPLL 17 CLK_MCH_3GPLL# 17 C
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
T85 T86 7 7 7 7
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1
CLK
R39
17 MCH_CLKSEL0 17 MCH_CLKSEL1 17 MCH_CLKSEL2
+V_DDR_MCH_REF generated by DC-DC
0.1U_0402_16V4Z
C58
100_0402_1% 2 1
0.1U_0402_16V4Z
24.9_0402_1% 2 1
1K_0402_1% 1 2 2K_0402_1% 2 1
PM_EXTTS#1
7 7 7 7
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
2 10K_0402_5%
AR24 AR21 AU24 AV20
SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
DMI
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
1
NC
H_RCOMP
RESERVED RESERVED RESERVED RESERVED
PM
+H_VREF
R52
0.01U_0402_25V7K
2.2U_0603_6.3V4Z C53 H_ADS# 6 H_ADSTB#0 6 H_ADSTB#1 6 H_BNR# 6 H_BPRI# 6 H_BR0# 6 H_DEFER# 6 H_DBSY# 6 CLK_MCH_BCLK 17 CLK_MCH_BCLK# 17 H_DPWR# 7 H_DRDY# 6 H_HIT# 6 H_HITM# 6 H_LOCK# 6 H_TRDY# 6
+VCCP
R46
T25 T26 T27 T28
BG23 BF23 BH18 BF18
R38
Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20. +VCCP
RESERVED
+3VS
20,25,26 PLT_RST# 6,21 H_THERMTRIP# 22,42 DPRSLPVR
Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20
AY21
PM_EXTTS#0
H_AVREF H_DVREF
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
1
2
CANTIGA ES_FCBGA1329
Layout note:
A
2
T24 R33 1K_0402_1%
SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
GFX_VR_EN
B33 B32 G33 F33 E33
T30 T31
C34
T35
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
22 22 22 22
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
22 22 22 22
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
22 22 22 22
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
22 22 22 22
B
+VCCP 1
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
1
RESERVED RESERVED RESERVED
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
AH37 AH36 AN36 AJ35 AH34
CL_CLK0 CL_DATA0 M_PWROK CL_RST# +CL_VREF
0621 add CLK and DAT for DVI DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN#
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
N28 M28 G36 E36 K36 H36 B12
T36 T37
HDMICLK_NB HDMIDAT_NB CLKREQ#_7 MCH_ICH_SYNC# TSATN#
R43 1K_0402_1%
CL_CLK0 22 CL_DATA0 22 M_PWROK 22,32 CL_RST# 22
B28 B30 B29 HDA_SDIN2_NB C29 A28
C56 0.1U_0402_16V4Z HDMICLK_NB 34 HDMIDAT_NB 34 CLKREQ#_7 17 MCH_ICH_SYNC#
1 R737
2
H_SWING H_RCOMP
SMRCOMP_VOL
1
T22 T23
B31 B2 M1
DDR CLK/ CONTROL/COMPENSATION
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
1
L9 M8 AA6 AE5
20% of 1.8V VCC_SM
1
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
R32 3.01K_0402_1%
2
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
C52
L10 M7 AA5 AE6
2.2U_0603_6.3V4Z C51
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
80% of 1.8V VCC_SM
AP24 AT21 AV24 AU20
1
A11 B11
J8 L3 Y13 Y1
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
B
+H_VREF
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
2
SMRCOMP_VOH
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1
1
22
2 56_0402_5% +VCCP TSATN# 32
HDA_BITCLK_NB 21 R210 HDA_RST#_NB 21 1 HDA_SDOUT_NB 21 HDA_SYNC_NB 21
R44 499_0402_1%
2
2
C12 E11
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
2
R31 1K_0402_1%
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
GRAPHICS VID
H_RESET# H_CPUSLP#
6 H_RESET# 7 H_CPUSLP#
H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
1
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24
ME
C5 E3
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
1
+1.8V
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20
CFG
+H_SWNG H_RCOMP
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
1
MISC
C
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
HOST
D
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6
RSVD
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
0.01U_0402_25V7K
U2A
7 H_D#[0..63]
2
U2B
H_A#[3..35] 6
HDA
5
*R44*Follow Intel feedback
2
HDA_SDIN2 21
33_0402_5%
0830 Add pull-up and pull-down resistor.
CANTIGA ES_FCBGA1329
Compal Secret Data
Security Classification
Near B3 pin
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. Cantiga(1/6)-AGTL/DMI/DDR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
9
of
46
A
5
4
3
2
1
D
D
16 DDR_B_D[0..63]
B
BB20 BD20 AY20
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
SA_RAS# SA_CAS# SA_WE#
DDR_A_RAS# 15 DDR_A_CAS# 15 DDR_A_WE# 15
A
DDR_A_DM[0..7] SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_A_BS0 15 DDR_A_BS1 15 DDR_A_BS2 15
15
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
15
15
DDR_A_MA[0..14] 15
CANTIGA ES_FCBGA1329
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE#
B
DDR_A_BS0 DDR_A_BS1 DDR_A_BS2
MEMORY
BD21 BG18 AT25
SA_BS_0 SA_BS_1 SA_BS_2
MEMORY
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SYSTEM
C
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
DDR
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
U2E
SYSTEM
U2D
DDR
15 DDR_A_D[0..63]
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
BC16 BB17 BB33
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
AU17 BG16 BF14
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
DDR_B_BS0 16 DDR_B_BS1 16 DDR_B_BS2 16 DDR_B_RAS# 16 DDR_B_CAS# 16 DDR_B_WE# 16
DDR_B_DM[0..7] 16
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
16
16
C
DDR_B_MA[0..14] 16
B
CANTIGA ES_FCBGA1329
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. Cantiga(2/6)-DDR2 A/B CH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
10
of
46
5
4
2
1
Strap Pin Table
ENBKL
2 10K_0402_5%
ENAVDD R60 1
H47 E46 G40 A40
LVDS_A0+ LVDS_A1+ LVDS_A2+ LVDS_A3+
H48 D45 F40 B40
LVDS_B0LVDS_B1LVDS_B2LVDS_B3-
A41 H38 G37 J37
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3
LVDS_B0+ LVDS_B1+ LVDS_B2+ LVDS_B3+ TV_COMPS TV_LUMA TV_CRMA
B42 G38 F37 K37
LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
1 R66
R67
E28 G28 J28 G29
18 3VDDCCL 18 3VDDCDA 18 CRT_HSYNC
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3
TVA_DAC TVB_DAC TVC_DAC TV_RTN
2
HSYNC
2
VSYNC
H32 J32 J29 E29 L29
TV_DCONSEL_0 TV_DCONSEL_1
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
CRT_BLUE
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
1
18 CRT_VSYNC
3VDDCCL 3VDDCDA CRT_HSYNC R68 1 30.1_0402_1% CRT_VSYNC R69 1 30.1_0402_1%
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
VGA
2
C31 E32
150_0402_1%
150_0402_1%
R65
150_0402_1%
Follow Intel DG & Checklist
H24
2.2K_0402_5% 0_0402_5%
2 2
1
1 1
1
18 M_BLUE 18 M_GREEN 18 M_RED
@ R64 R406 M_BLUE M_GREEN M_RED
2
2 +3VS
R63
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3
TV
R62
75_0402_1%
R61
75_0402_1%
75_0402_1%
Follow Intel DG & Checklist
C
F25 H25 K25
1
T41 T48 T49 T50
LVDS_A0LVDS_A1LVDS_A2LVDS_A3-
L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
2
T40
LVDS_ACLKLVDS_ACLK+ LVDS_BCLKLVDS_BCLK+
1
T39
L_CTRL_DATA L_DDC_CLK L_DDC_DATA
PEG_COMPI PEG_COMPO
LVDS
T38
M33 K33 J33 M29 C44 B43 E37 E38 C41 C40 B37 A37
2 4.75K_0402_1%
2
19 ENAVDD
Follow Intel DG & Checklist
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK
R70 1.02K_0402_1%
T37 T36
CFG[2:0] FSB Freq select
PEGCOMP trace width and spacing is 20/25 mils.
H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40
000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved Reserved CFG[4:3] 0 = DMI x 12 = DMI x CFG5 (DMI select) * Interface is 40 = The iTPM Host CFG6 enable 1 = The iTPM Host Interface is disable 0 =(TLS)chiper suite with no CFG7 (Intel Management confidentiality =(TLS)chiper suite with Engine Crypto strap) 1confidentiality Reserved CFG8
+VCC_PEG
R57 1 2 49.9_0402_1%
TMDS_B_HPD#
CFG9 (PCIE Graphics Lane Reversal)
TMDS_B_HPD# 34
TMDS_BDATA2# TMDS_BDATA1# TMDS_BDATA0# TMDS_BCLK#
J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
TMDS_BDATA2 TMDS_BDATA1 TMDS_BDATA0 TMDS_BCLK
C274 C275 C276 C277
1 1 1 1
2 2 2 2
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
TMDS_B_DATA2# 34 TMDS_B_DATA1# 34 TMDS_B_DATA0# 34 TMDS_B_CLK# 34
CFG[13:12] (XOR/ALLZ) CFG[15:14]
CFG16 (FSB Dynamic ODT) 01 == Disabled
Enabled Reserved
CFG[18:17] 1 1 1 1
2 2 2 2
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
*
CFG20 (PCIE/SDVO concurrent)
C
*
(Lane number in Operation 1 = Order) Reverse Lane
TMDS_B_DATA2 34 TMDS_B_DATA1 34 TMDS_B_DATA0 34 TMDS_B_CLK 34
*
*
CFG19 (DMI Lane Reversal) 0 = Normal C278 C279 C280 C281
*
0 = Reverse Lane,15->0, 114->1 = Normal Operation,Lane Number in order 0= Enable 1 = Disable * Reserved 00 = Reserved 01 = XOR Mode 10 = All Z Mode Enabled 11 = Normal (Default) Enabled * Operation Reserved
CFG10 (PCIE Lookback CFG11 enable)
J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46
D
0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.
*
+3VS
1
R59 1 DDC2_CLK DDC2_DATA
19 DDC2_CLK 19 DDC2_DATA
D
2 10K_0402_5%
GRAPHICS
19 NB_BKLT_CTRL 32 ENBKL +3VS
100K_0402_5%
L32 G32 M32
PCI-EXPRESS
NB_BKLT_CTRL ENBKL R58 1
1
2
2
1
3
U2C
R148
+3VS
@ R71 4.02K_0402_1%
CANTIGA ES_FCBGA1329 B
2
B
9 CFG16
2
CFG5
1
9 CFG5
9 CFG19
@ R74 2.21K_0402_1%
1 2 4.02K_0402_1%
@ R73
1 2 4.02K_0402_1%
@R75
1 2 4.02K_0402_1%
2
9 CFG20
@ R72
For 3G WWAN
LVDS_ACLK+
19 LVDS_ACLK+
LVDS_ACLKLVDS_A0+
19 LVDS_ACLK19 LVDS_A0+ 19 LVDS_A019 LVDS_A1+ 19 LVDS_A119 LVDS_A2+
2 1
LVDS_A0LVDS_A1+
2 1
LVDS_A1LVDS_A2+
2 1
LVDS_A2-
19 LVDS_A2-
1
2
@ C60 0.1U_0402_10V6K @ C61 0.1U_0402_10V6K @ C62 0.1U_0402_10V6K @ C63 0.1U_0402_10V6K
For 3G WWAN
19 LVDS_BCLK+ 19 LVDS_BCLK19 LVDS_B0+ 19 LVDS_B019 LVDS_B1+ 19 LVDS_B119 LVDS_B2+ 19 LVDS_B2-
9 CFG11 LVDS_BCLK+ LVDS_BCLKLVDS_B0+
1
2 1
LVDS_B0LVDS_B1+
2 1
LVDS_B1LVDS_B2+
2 1
LVDS_B2-
2
9 CFG12
@ C1500 0.1U_0402_10V6K
9 CFG13
@ C1501 0.1U_0402_10V6K
9 CFG6 9 CFG7
@ C1502 0.1U_0402_10V6K
9 CFG8
@ C1503 0.1U_0402_10V6K
9 CFG9
A
9 CFG10
1 2 2.21K_0402_1%
2007/08/28
2006/03/10
Deciphered Date
9 CFG14
@ R81
1 2 2.21K_0402_1%
@R83
1 2 2.21K_0402_1%
@R84
1 2 2.21K_0402_1%
9 CFG17
@R86
1 2 2.21K_0402_1%
9 CFG18
Compal Secret Data
Security Classification Issued Date
@R79
Title
9 CFG15
@R76
1 2 2.21K_0402_1%
@ R77
1 2 2.21K_0402_1%
@ R78
1 2 2.21K_0402_1%
@R80
1 2 2.21K_0402_1%
@R82
1 2 2.21K_0402_1%
@R85
1 2 2.21K_0402_1%
@R87
1 2 2.21K_0402_1%
Compal Electronics, Inc. Cantiga(3/6)-VGA/LVDS/TV
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
A
2
Wednesday, February 18, 2009
Sheet 1
11
of
46
5
4
+3VS_DAC_BG
C82
C81
VTT
C80
CRT PLL A LVDS A PEG A SM
AXF SM CK
A CK
0.1U_0402_16V4Z
VCCD_LVDS VCCD_LVDS
60.31mA
PEG DMI
K47
+1.8V_TXLVDS
2
2
+ C100
2
10U_0805_10V4Z
+1.05VS_PEGPLL
VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG
V48 U48 V47 U47 U46
+VCC_PEG
VCC_DMI VCC_DMI VCC_DMI VCC_DMI
AH48 AF48 AH47 AG47
+1.05VS_DMI
1
2
1
2
1
1
2 2
+VCCP_D
VTTLF VTTLF VTTLF
A8 L1 AB2
D3 2
+VCCP
R105 1 2 10_0402_5%
1
2
1
2
0.47U_0603_10V7K C112
1
1
2
2006/03/10
Deciphered Date
Title
R108 1 2 0_0603_5%
1
+1.8V
C116
2007/08/28
+1.8V
2
Compal Secret Data
Security Classification Issued Date
1
+1.8V_TXLVDS
1000P_0402_50V7K
2
2
R107 1 2 0_0603_5% C114
1
C113
2
C120
1
R112 1 2 100_0603_1%
1
40 mils 1U_0603_10V4Z
10U_0805_10V4Z
+1.5VS
0.1U_0402_16V4Z
2
C119
1
0.022U_0402_16V7K
C118
2
R111 1 2 BLM18PG181SN1D_0603
+3VS_HV
+3VS
+3VS
0.1U_0402_16V4Z
C117
1
0.022U_0402_16V7K
A
R106 1 2 0_0402_5%
CH751H-40PT_SOD323-2 0.47U_0603_10V7K C111
+1.5VS_QDAC
+VCCP R104 1 2 0_0603_5%
B
+1.8V_LVDS
+3VS_TVDAC
1
2
+1.05VS_DMI
+VCCP L1 1 2 BLM18PG121SN1D_0603
+3VS_HV
C35 B35 A35
0.47U_0603_10V7K C110
CANTIGA ES_FCBGA1329
+1.8V_SM_CK
1
456mA
VTTLF
50mA
LVDS
VCCD_PEG_PLL
VCC_HV VCC_HV VCC_HV
HV
TV HDA
157.2mA
BF21 BH20 BG20 BF20
1
R102 1 2 0_0805_5%
1
118.8mA
1732mA
48.363mA
C99
VCC_TX_LVDS
D TV/CRT
VCCD_HPLL
+V1.05VS_AXF
10U_0805_10V4Z
+1.8V_LVDS
M38 L37
VCCD_QDAC
B22 B21 A21
124mA
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
105.3mA
58.67mA
+VCCP
0.1U_0402_16V4Z C109
AA47
VCCD_TVDAC
2
C101
+1.05VS_PEGPLL
50mA
VCC_AXF VCC_AXF VCC_AXF
+VCCP R101 1 2 MBK2012121YZF_0805
C108
AF1
C85
+1.05VS_MPLL
10U_0805_10V4Z
L28
+1.5VS_QDAC +1.05VS_HPLL
VCC_HDA
2
1
+VCC_PEG
TVA 24.15mA TVB 39.48mA TVX 24.15mA VCCA_TV_DAC VCCA_TV_DAC
1
R99 1 2 0_0805_5%
C
C107
M25
VCCA_SM_CK VCCA_SM_CK 26mA VCCA_SM_CK VCCA_SM_CK 26mA VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF
1
2
C106
A32
1
2
0.1U_0402_16V4Z
+1.5VS
C79
POWER
0.1U_0402_16V4Z
+3VS_TVDAC
B24 A24
+1.5VS_TVDAC B
720mA
+1.5VS
220U_D2_4VM
2
2
+1.5VS_TVDAC
+VCCP R98 1 2 MBK2012121YZF_0805
C98
C105
2
1
0.1U_0402_16V4Z
C104
2
1
1U_0603_10V4Z
2
1
10U_0805_10V4Z
1U_0603_10V4Z
1
C103
C102
VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM
+1.05VS_HPLL
321.35mA AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23
+1.05VS_A_SM_CK
R103 1 2 0_0603_5%
VCCA_PEG_PLL
C97
2 1U_0603_10V4Z
1
0.1U_0402_16V4Z
2
2
R95 1 2 0_0805_5%
0.1U_0402_16V4Z
4.7U_0805_10V4Z
1U_0603_10V4Z
2
1
2
1
C93
2
1
C96
1
C92
220U_D2_4VM
1
@
10U_0805_10V4Z
C95
C94
+
10U_0805_10V4Z
1
2
C91
+1.05VS_A_SM R100 1 2 0_0805_5%
2
1
C90
+VCCP
AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
2
+1.8V
0.022U_0402_16V7K
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
AA48
+1.05VS_PEGPLL
C89
1
VCCA_PEG_BG
50mA 1
2
10U_0805_10V4Z
AD48
+1.5VS_PEG_BG
VSSA_LVDS
1
C78
R97 1 2 0_0603_5%
VCCA_LVDS
414uA
2
+VCCP R94 1 2 10U_FLC-453232-100K_0.25A_10%
C84
+1.5VS
J47
2
10U_0805_10V4Z
+3VS
C88
+VCCP R93 1 2 0_0603_5%
+1.8V_SM_CK +1.05VS_DPLLB
C83
1
1000P_0402_50V7K 2
2
1
10U_0805_10V4Z
+1.8V_TXLVDS
@ R96 1 2 0_0603_5%
C
139.2mA
VCCA_MPLL
13.2mA J48
1
10U_0805_10V4Z
AE1
VCCA_HPLL
1
2
10U_0805_10V4Z
+1.05VS_MPLL
24mA
C74
2
64.8mA
C87
VCCA_DPLLB
AD1
0.1U_0402_16V4Z
L48
+1.05VS_HPLL
1
1 2 R90 10U_FLC-453232-100K_0.25A_10%
D
C86
+1.05VS_DPLLB
64.8mA
2
1
2
0.1U_0402_16V4Z
VCCA_DPLLA
2
1
2.2U_0805_16V4Z
F47
+1.05VS_DPLLA
0.1U_0402_16V4Z
C76
0.022U_0402_16V7K
C75
2
R91 1 2 BLM18PG181SN1D_0603
+
4.7U_0805_10V4Z
VCCA_DAC_BG VSSA_DAC_BG
1
C72
A25 B25
+3VS_DAC_BG
U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
0.47U_0603_10V7K
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
VCCA_CRT_DAC VCCA_CRT_DAC
+3VS
1
+VCCP +V1.05VS_AXF
C71
+3VS_DAC_CRT
+3VS_DAC_CRT
1
+1.05VS_DPLLA
C73
852mA 73mA B27 A26
2.68mA D
+VCCP
1
U2H 4.7U_0805_10V4Z
2
2
220U_D2_4VM
2
1
R88 2 BLM18PG181SN1D_0603
10U_0805_10V4Z
1
C70 0.1U_0402_16V4Z
C69
2
0.022U_0402_16V7K
C68
1
1
3
**RED Mark: Means UMA & dis@ Power select** ~It check by INTEL Graphics Disable Guidelines~
+3VS
2 A
Compal Electronics, Inc. Cantiga(4/6)-PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
12
of
46
5
4
3
2
1
+VCCP
U2G
1
BA36 BB24 BD16 BB21 AW16 AW13 AT13
VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC
1U_0603_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
1 GM47@ C134 + C1508 2
2
330U_D2E_2.5VM_R7
1
1 C138
2
2
2
10U_0805_10V4Z
1 @ C1491 2
1 @ C1494 2
22P_0402_25V8K
2
1 C137
2
22P_0402_25V8K
22P_0402_25V8K
1 @ C1493
1 C136
22P_0402_25V8K
2
+ C135
22P_0402_25V8K
1 @ C1490
1
1 @ C1492 2
1 @ C1495 2
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
Reserve for WWAN
1
4.7U_0603_6.3V6M 1
C127
2
2
0.22U_0402_10V4Z
C
2
1
2
Compal Secret Data 2007/08/28
2006/03/10
Deciphered Date
Title
1
2
1
2
1U_0603_10V4Z
1
1U_0603_10V4Z
2
C145
1
0.47U_0402_6.3V6K
2
C144
1
C143
2
0.22U_0603_10V7K
1
0.22U_0603_10V7K
AV44 VCCSM_LF1 BA37 VCCSM_LF2 AM40 VCCSM_LF3 AV21 VCCSM_LF4 AY5 VCCSM_LF5 AM10 VCCSM_LF6 BB13 VCCSM_LF7
C142
VCC_AXG_SENSE VSS_AXG_SENSE
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
CANTIGA ES_FCBGA1329
Issued Date
C129 D
2
A
Security Classification
1
C128
C141
AJ14 AH14
0.1U_0402_16V4Z
C140 0.1U_0402_16V4Z
PAD T42 PAD T43
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
C139 0.1U_0402_16V4Z
CANTIGA ES_FCBGA1329
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
B
VCC GFX
+VCCP
SI-1 Add C for GM47
Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14
VCC GFX NCTF
6326.84mA
22P_0402_25V8K
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
330U_D2E_2.5VM_R7
B
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
VCC SM LF
2
2
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29
VCC SM
2
1
+VCCP
POWER
VCC
2
1
0317 change value
VCC NCTF
T32
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
+
VCC CORE
AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23
1
C123
2
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
10U_0805_10V4Z C122
2
1
C125
C
2
1
0.1U_0402_16V4Z C133
2
1
0.22U_0402_10V4Z C132
2
1
0.22U_0402_10V4Z C124
+
10U_0805_10V4Z C131
220U_D2_4VM
1
AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33
10U_0805_10V4Z C126
D
+1.8V 0.01U_0402_16V7K C130
+VCCP
Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA
330U_D2E_2.5VM_R7
U2F
POWER
3000mA
Compal Electronics, Inc. Cantiga(5/6)-PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
A
2
Wednesday, February 18, 2009
Sheet 1
13
of
46
5
4
3
2
1
U2J
C
B
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6
BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13
CANTIGA ES_FCBGA1329
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS NCTF
D
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS SCB
AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36
BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17
NC
U2I
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4
D
BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1
C
U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17
B
BH48 BH1 A48 C1 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48
CANTIGA ES_FCBGA1329
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. Cantiga(6/6)-PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
14
of
46
5
4
3
2
1
+1.8V
+1.8V V_DDR_MCH_REF
10 DDR_A_DQS#[0..7]
2
DDR_A_D18 DDR_A_D19 DDR_A_D29 DDR_A_D24 DDR_A_DM3 DDR_A_D26 DDR_A_D27
C
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
9 DDR_CKE0_DIMMA 10 DDR_A_BS2
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
2
1
2
10 DDR_A_BS0 10 DDR_A_WE# 1
10 DDR_A_CAS# 9 DDR_CS1_DIMMA#
DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# M_ODT1
9 M_ODT1 2
DDR_A_D37 DDR_A_D36
C170
C169
C168
C167
C166
C165
C164
C163
C162
C161
C160
C159
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
C158
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8
+0.9V
1
DDR_CKE0_DIMMA
DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D39 DDR_A_D38 DDR_A_D45 DDR_A_D44
B
Layout Note: Place these resistor closely JP3,all trace length Max=1.5"
+0.9V RP30
1 2 3 4
8 7 6 5
1 2 3 4
8 7 6 5
56_8P4R_0.05
56_8P4R_0.05
RP31
RP32
DDR_A_MA8 DDR_A_MA5 DDR_A_MA1 DDR_A_MA3
1 2 3 4
8 7 6 5
1 2 3 4
DDR_A_MA14 DDR_CKE1_DIMMA DDR_A_MA6 DDR_A_MA7
DDR_A_D47 DDR_A_D46 DDR_A_D49 DDR_A_D48
DDR_A_DQS#6 DDR_A_DQS6 8 7 6 5
DDR_A_MA2 DDR_A_MA4 DDR_A_BS1 DDR_A_MA0
DDR_A_D54 DDR_A_D50
56_8P4R_0.05
56_8P4R_0.05
DDR_A_D61 DDR_A_D60
RP33
RP34
DDR_A_DM7
DDR_A_BS0 DDR_A_MA10 DDR_A_CAS# DDR_A_WE#
1 2 3 4
8 7 6 5
56_8P4R_0.05
1 2 3 4
8 7 6 5
DDR_A_MA13 M_ODT0 DDR_CS0_DIMMA# DDR_A_RAS#
DDR_A_D59 DDR_A_D58 16,17,24 CLK_SMBDATA 16,17,24 CLK_SMBCLK +3VS
56_8P4R_0.05
A
56_0404_4P2R_5% RP11 DDR_CS1_DIMMA# 2 M_ODT1 1
3 4
DDR_A_MA11
2
1
2.2U_0603_6.3V4Z
+0.9V
CLK_SMBDATA CLK_SMBCLK
1
1 C171 C172
2
R117 56_0402_5%
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
FOX_ASOA426-M4R-TR CONN@
SO-DIMM A
DDR_A_D6 DDR_A_D7
2006/02/13
2006/03/10
Deciphered Date
1
2
1
2
D
DDR_A_D13 DDR_A_D12 DDR_A_DM1 M_CLK_DDR0 M_CLK_DDR#0
M_CLK_DDR0 9 M_CLK_DDR#0 9
DDR_A_D15 DDR_A_D14
DDR_A_D20 DDR_A_D21 PM_EXTTS#0 9
DDR_A_DM2 DDR_A_D23 DDR_A_D22 DDR_A_D28 DDR_A_D25 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D31 DDR_A_D30 DDR_CKE1_DIMMA
C
DDR_CKE1_DIMMA 9
DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 DDR_A_MA13
DDR_A_BS1 10 DDR_A_RAS# 10 DDR_CS0_DIMMA# 9 M_ODT0 9
DDR_A_D32 DDR_A_D33 DDR_A_DM4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 B
DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D43 DDR_A_D42 DDR_A_D52 DDR_A_D53 M_CLK_DDR1 M_CLK_DDR#1
M_CLK_DDR1 9 M_CLK_DDR#1 9
DDR_A_DM6 DDR_A_D51 DDR_A_D55 DDR_A_D57 DDR_A_D56 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63
A
Compal Secret Data
Security Classification Issued Date
2
0.1U_0402_16V4Z
RP29 DDR_A_BS2 DDR_CKE0_DIMMA DDR_A_MA12 DDR_A_MA9
DDR_A_DM5
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1
DDR_A_DM0
R116 10K_0402_5% 2 1
DDR_A_DQS#2 DDR_A_DQS2
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
DDR_A_D5 DDR_A_D0
R115 10K_0402_5% 2 1
2
+
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
DDR_A_D16 DDR_A_D17
1 C150
C157
2
1
330U_D2E_2.5VM_R7
0.1U_0402_16V4Z
1
C149
2
0.1U_0402_16V4Z
2
1
C148
C156
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C155
C154
2
1
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
C153
2
2.2U_0805_16V4Z
C147
2.2U_0805_16V4Z
C152
2.2U_0805_16V4Z
2
1
203
+1.8V
VSS
DDR_A_D11 DDR_A_D10
204
DDR_A_DQS#1 DDR_A_DQS1
VSS
DDR_A_D8 DDR_A_D9
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
C151
DDR_A_D2 DDR_A_D3
Layout Note: Place near JP3
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
C146
DDR_A_DQS#0 DDR_A_DQS0
10 DDR_A_MA[0..14]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
0.1U_0402_16V4Z
DDR_A_D4 DDR_A_D1
10 DDR_A_DQS[0..7]
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2.2U_0805_16V4Z
10 DDR_A_DM[0..7]
D
V_DDR_MCH_REF 9,16
JDIMM1
10 DDR_A_D[0..63]
Title
Compal Electronics, Inc. DDRII-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
15
of
46
5
4
3
2
1
+1.8V
+1.8V
10 DDR_B_DQS#[0..7] V_DDR_MCH_REF
10 DDR_B_D[0..63]
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
DDR_B_D21 DDR_B_D20 DDR_B_DQS#2 DDR_B_DQS2
2
DDR_B_D19 DDR_B_D18 DDR_B_D28 DDR_B_D25 DDR_B_DM3
C
DDR_B_D30 DDR_B_D31
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
DDR_CKE2_DIMMB
9 DDR_CKE2_DIMMB
DDR_B_BS2
10 DDR_B_BS2
DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
+0.9V
1
2
1
2
1
2
1
2
1
2
1
2
1
DDR_B_CAS# DDR_CS3_DIMMB#
10 DDR_B_CAS# 9 DDR_CS3_DIMMB# 2 C196
C195
C194
C193
C192
C191
C190
C189
C188
C187
C186
C185
C184
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
DDR_B_MA10 DDR_B_BS0 DDR_B_WE#
10 DDR_B_BS0 10 DDR_B_WE#
M_ODT3
9 M_ODT3
DDR_B_D32 DDR_B_D37 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35
Layout Note: Place these resistor closely JP3,all trace length Max=1.5"
B
+0.9V +0.9V RP35 56_0404_4P2R_5% RP14 DDR_B_MA3 1 DDR_B_MA1 2
4 3
1 2 3 4
8 7 6 5
DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6
DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49
56_8P4R_0.05 56_0404_4P2R_5% RP16 DDR_B_BS0 1 DDR_B_MA10 2
4 3
56_0404_4P2R_5% RP24 DDR_CS3_DIMMB# 2 M_ODT3 1
3 4
RP36 1 2 3 4
8 7 6 5
DDR_B_MA4 DDR_B_MA2 DDR_B_BS1 DDR_B_MA0
DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D54 DDR_B_D55
56_8P4R_0.05 DDR_B_D60 DDR_B_D61
RP37 DDR_CKE3_DIMMB 1 R120
2 56_0402_5%
1 2 3 4
8 7 6 5
DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 DDR_B_MA13
DDR_B_DM7 DDR_B_D63 DDR_B_D58
56_8P4R_0.05
56_8P4R_0.05 RP39 1 2 3 4
8 7 6 5
DDR_B_MA8 DDR_B_MA5 DDR_B_WE# DDR_B_CAS#
1
1 C197
2
56_8P4R_0.05
2
FOX_AS0A426-N8RN-7F CONN@
2006/02/13
SO-DIMM B 2006/03/10
Deciphered Date
M_CLK_DDR2 M_CLK_DDR#2
M_CLK_DDR2 9 M_CLK_DDR#2 9
DDR_B_D14 DDR_B_D15
DDR_B_D16 DDR_B_D17 PM_EXTTS#1 9
DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D29 DDR_B_D24 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D26 DDR_B_D27
C
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB 9
DDR_B_MA14
0612 add
DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB#
DDR_B_BS1 10 DDR_B_RAS# 10 DDR_CS2_DIMMB# 9
M_ODT2 DDR_B_MA13
M_ODT2 9
DDR_B_D36 DDR_B_D33 DDR_B_DM4 DDR_B_D39 DDR_B_D38 DDR_B_D44 DDR_B_D45
B
DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 M_CLK_DDR3 M_CLK_DDR#3
M_CLK_DDR3 9 M_CLK_DDR#3 9
DDR_B_DM6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D59 DDR_B_D62 R118 1
2
3
2
+3VS
10K_0402_5%
Title
Date:
4
2
DDR_B_DM1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
2
1
D
Compal Secret Data
Security Classification Issued Date
C198
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
DDR_B_BS2 DDR_CKE2_DIMMB DDR_B_MA9 DDR_B_MA12
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
1
DDR_B_D12 DDR_B_D13
R119
A
8 7 6 5
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1
DDR_B_D6 DDR_B_D7
10K_0402_5%
1 2 3 4
CLK_SMBDATA CLK_SMBCLK
15,17,24 CLK_SMBDATA 15,17,24 CLK_SMBCLK +3VS
RP38
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
DDR_B_DM0
1
2
1
C181
C180
2
1
0.1U_0402_16V4Z
C179
2
1
0.1U_0402_16V4Z
C178
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C177
C183
2
1
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
C176
2
2.2U_0805_16V4Z
2
1
C175
C174
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
201
+1.8V
DDR_B_D5 DDR_B_D4
A
2
DDR_B_D10 DDR_B_D11
VSS
DDR_B_DQS#1 DDR_B_DQS1
202
DDR_B_D8 DDR_B_D9
VSS
DDR_B_D2 DDR_B_D3
Layout Note: Place near JP10
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
C182
DDR_B_DQS#0 DDR_B_DQS0
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
C173
DDR_B_D0 DDR_B_D1
10 DDR_B_MA[0..14]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
0.1U_0402_16V4Z
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2.2U_0805_16V4Z
10 DDR_B_DQS[0..7]
D
V_DDR_MCH_REF 9,15
JDIMM2
10 DDR_B_DM[0..7]
Compal Electronics, Inc. DDRII-SODIMM SLOT2 Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
16
of
46
5
CLKSEL0
CPU MHz
SRC MHz
PCI MHz
REF MHz
DOT_96 MHz
USB MHz
100
33.3
14.318
96.0
48.0
0
0
0
266
0
0
1
133
100
33.3
14.318
96.0
48.0
0
1
0
200
100
33.3
14.318
96.0
48.0
0
1
1
166
100
33.3
14.318
96.0
48.0
1
0
0
333
100
33.3
14.318
96.0
48.0
1
0
1
100
100
33.3
14.318
96.0
48.0
1
0
1
1
1
400
100
33.3
1
10U_0805_10V4Z
Routing the trace at least 10mil CLK_XTAL_OUT
1 2 R129 1K_0402_5%
CLK_XTAL_IN
1
1
C202 0.1U_0402_16V4Z
2
1
C203 0.1U_0402_16V4Z
2
1
C204 0.1U_0402_16V4Z
2
1
C205 0.1U_0402_16V4Z
2
C1496 47P_0402_50V8J
For WWAN
2
0.1U_0402_16V4Z 1 C206 C207
2 10U_0805_10V4Z
48.0
C213 18P_0402_50V8J
NB CPU
9 9 6 6
9 CLKREQ#_7 CLK_MCH_BCLK# CLK_MCH_BCLK CLK_CPU_BCLK# CLK_CPU_BCLK
1
D
10U_0805_10V4Z 0.1U_0402_16V4Z 1 1 1 C209 C210 C211
C208
1
47P_0402_50V8J 1 1 C212 C1506 C1507
2
2
1
1
2
2 0.1U_0402_16V4Z
2
2 0.1U_0402_16V4Z
2
2 2 0.1U_0402_16V4Z
C214 18P_0402_50V8J
2 47P_0402_50V8J
For WWAN
+1.05VS_CK505
R126
1
R_CLKREQ#_7
2 475_0402_1%
R_CLKREQ#_6
R133
1
2
CLK_MCH_3GPLL 9 CLK_MCH_3GPLL# 9 CLKREQ#_6 26 CLK_PCIE_MCARD2 26 CLK_PCIE_MCARD2# 26
475_0402_1%
+3VS_CK505
U3
2
1 1 1
2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
R_CKPWRGD FSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CLK_XTAL_OUT CLK_XTAL_IN
@ R143 1K_0402_5% R147
22 CLK_14M_ICH
1
2
@ R141 @ R142 R140
MCH_CLKSEL1 9
15,16,24 CLK_SMBDATA 15,16,24 CLK_SMBCLK R393 1
26 CLK_DEBUG_PORT_1 32 CLK_PCI_EC 20 CLK_PCI_ICH
2
1
R158
1
R161
1
2 33_0402_1% FSC REF1 CLK_SMBDATA T44 CLK_SMBCLK 2 39_0402_1% PCI2_1 PCI2_TME T83 2 33_0402_1% 27_SEL PCI_CLK3 2 33_0402_1% ITP_EN
73
@ R163 1K_0402_5%
1 2 R165 1K_0402_5%
MCH_CLKSEL2 9
R167 1 R1101 1
22 CLK_48M_ICH 27 CLK_48M_CR
CKPWRGD/PD# FS_B/TEST_MODE VSS_REF XTAL_OUT XTAL_IN VDD_REF REF_0/FS_C/TEST_ REF_1 SDA SCL NC VDD_PCI PCI_1 PCI_2 PCI_3 PCI_4/SEL_LCDCL PCIF_5/ITP_EN VSS_PCI thm_pad
+3VS_CK505
SI-1 Using USB_0 for CLK_48M_CR
2
1 7 CPU_BSEL2
2
Place close to U3
3G_PLL MiniCard_2(WLAN)
+1.05VS_CK505 C
PCI_STOP# CPU_STOP# VDD_SRC_IO SRC_10# SRC_10 CLKREQ_10# SRC_11 SRC_11# CLKREQ_11# SRC_9# SRC_9 CLKREQ_9# VSS_SRC CLKREQ_4# SRC_4# SRC_4 VDD_SRC_IO CLKREQ_3#
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
H_STP_PCI# H_STP_CPU#
H_STP_PCI# 22 H_STP_CPU# 22
R_CLKREQ#_10
R146
1
2 475_0402_1%
CLK_PCIE_MCARD0# 26 CLK_PCIE_MCARD0 26 CLKREQ#_10 26
MiniCard_0
R_CLKREQ#_9
R738
1
2 475_0402_1%
CLK_PCIE_LAN# 25 CLK_PCIE_LAN 25 CLKREQ#_9 25
LAN
R_CLKREQ#_4
R156
1
2 475_0402_1%
R_CLKREQ#_C
R162
1
2 475_0402_1%
CLKREQ#_4 26 CLK_PCIE_NCARD# 26 CLK_PCIE_NCARD 26
+1.05VS_CK505
NB (UMA)
SATA
CLK_PCIE_ICH# 22 CLK_PCIE_ICH 22
ICH
MCH_SSCDREFCLK# 9 MCH_SSCDREFCLK 9
NB_SSC (UMA)
2
9 CLK_MCH_DREFCLK 9 CLK_MCH_DREFCLK#
B
CLK_PCIE_SATA# 21 CLK_PCIE_SATA 21
+1.05VS_CK505 @ R174 0_0402_5%
New Card
CLKREQ#_C 22
SLG8SP553VTR_QFN72_10x10
FSA
2 22_0402_1% 2 22_0402_1%
1
FSC
0.1U_0402_16V4Z
+1.05VS_CK505
R122 1 2 0_0805_5%
+VCCP
R164 1 2 10K_0402_5% R171 1 2 0_0402_5%
1
C201
14.318MHZ_16PF_7A14300083
22,42 VGATE 42 CLK_ENABLE# 22 CK_PWRGD
@ R157 0_0402_5%
B
2
+VCCP
+3VS_CK505
1
7 CPU_BSEL1
0.1U_0402_16V4Z
+VCCP
MCH_CLKSEL0 9
1 2 R150 1K_0402_5%
R154 1 2 0_0402_5%
1
C200
+3VS_CK505 2
+VCCP
FSB
2
Y1
56_0402_5% CLRP1 NO SHORT PADS
2
1
C199
2
@ R139 1K_0402_5%
C
1
1
R128 1 2 2.2K_0402_5% R138 1 2 0_0402_5%
7 CPU_BSEL0
96.0
2
0_0805_5%
Reserved R123 1
FSA
14.318
+3VS_CK505 R121 1
1
1
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1
+3VS
VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO CLKREQ_7# SRC_8/CPU_ITP SRC_8#/CPU_ITP# VDD_SRC_IO SRC_7 SRC_7# VSS_SRC CLKREQ_6# SRC_6 SRC_6# VDD_SRC
FSA
CLKSEL1
2
VDD_48 USB_0/FS_A USB_1/CLKREQ_A# VSS_48 VDD_IO SRC_0/DOT_96 SRC_0#/DOT_96# VSS_IO VDD_PLL3 LCDCLK/27M LCDCLK#/27M_SS VSS_PLL3 VDD_PLL3_IO SRC_2 SRC_2# VSS_SRC SRC_3 SRC_3#
D
FSB
3
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
FSC
CLKSEL2
4
+3VS
R178
1
2
Q3B 3
CLK_SMBDATA
1
2N7002DW-7-F_SOT363-6 CLK_SMBCLK
4
2N7002DW-7-F_SOT363-6
@ R182 10K_0402_5%
2
1
CLK_48M_CR
2
1
CLK_48M_ICH
2
1
CLK_14M_ICH
2
1
CLK_PCI_ICH
2
1
CLK_PCI_EC
2
1
CLK_DEBUG_PORT_1 A
Install C217,C218,C219 for WWAN noise
PCI_CLK3 1
ITP_EN 1
SB, MINI PCI22,26 ICH_SMBCLK
@ R181 10K_0402_5%
@ C1482 5P_0402_50V8C @ C215 5P_0402_50V8C C216 12P_0402_50V8J @ C217 47P_0402_50V8J @ C218 47P_0402_50V8J @ C219 47P_0402_50V8J
2.2K_0402_5%
2
R180 10K_0402_5%
6
22,26 ICH_SMBDATA 5
+3VS
R179
2
2.2K_0402_5% Q3A
+3VS
A
EMI
+3VS
R183 10K_0402_5%
2007/08/28
Issued Date 2
Compal Secret Data
Security Classification
2006/03/10
Deciphered Date
Title
2
PCI_CLK3
0= SRC8/SRC8# 1= 0ITP/ITP# = Enable DOT96 & SRC1(UMA) 1 = Enable SRC0 & 27MHz(DIS)
1
ITP_EN
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. Clock Generator CK505 Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
17
of
46
B
C
D
E
BLUE GREEN RED
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
RED GREEN BLUE
+5VS
R186 2.2K_0402_5%
A
3
Y
4
VSYNC_G_A
D_VSYNC
2 0_0603_5%
D_DDCDATA
U5 SN74AHCT1G125GW_SOT353-5
1 @ C223 2
2
1 3
2
1
1 1 6
1 @ C224
5P_0402_50V8C
R187 2.2K_0402_5% 2 2
R185 2.2K_0402_5%
1 Q5A
5P_0402_50V8C
2N7002DW-7-F_SOT363-6 3
D_DDCCLK
2
R188 2.2K_0402_5% 3VDDCDA
3VDDCDA 11
5
2
R189 1
+CRTVDD
+3VS
1
D_HSYNC
2 0_0603_5%
5 1
3
CRT_VSYNC
G
11 CRT_VSYNC
R184 1
1
+3VS
2
A
1
2
+CRTVDD
2
CRT_HSYNC
Place close to JCRT1
16 17
SUYIN_070546FR015S263ZR CONN@
U4 SN74AHCT1G125GW_SOT353-5 HSYNC_G_A Y 4 P OE#
11 CRT_HSYNC
C222 0.1U_0402_16V4Z 1 2
+CRTVDD
G
2
P OE#
5 1
C221 0.1U_0402_16V4Z 1 2
2
2
+5VS
1
1
0.1U_0402_16V4Z C220 JCRT1
3
W=40mils
2
1.1A_6VDC_FUSE
@ D7 DAN217T146_SC59-3
1 RB491D_SC59-3
2
2
F1 1
@ D6
3
D4
@ D5
+CRTVDD
DAN217T146_SC59-3
+RCRT_VCC
2
+5VS
1
DAN217T146_SC59-3
A
3VDDCCL
4
3VDDCCL 11
Q5B 2N7002DW-7-F_SOT363-6
CRT Termination/EMI Filter 3
3
11 M_RED 11 M_GREEN
150_0402_1%
150_0402_1% R197 2 1
1 R195 2
BLUE
1
2
1
2
1
2
1
2
@ C225 @ C226 @ C227
1
2
1
2
10P_0402_50V8J
GREEN
L4 1 2 HLC0603CSCCR11JT_0603
10P_0402_50V8J
L3 1 2 HLC0603CSCCR11JT_0603
C_BLU
10P_0402_50V8J
C_GRN
22P_0402_50V8J
RED
22P_0402_50V8J
L2 1 2 HLC0603CSCCR11JT_0603
22P_0402_50V8J
150_0402_1% R196 2 1
11 M_BLUE
C_RED
C228 C229 C230
4
4
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Compal Electronics, Inc. CRT Connector Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet E
18
of
46
5
4
LVDS CONN & USB Camera + Dig Mic +LCDVDD
DMIC_DAT DMIC_CLK +3V_LOGO
R727 1 100_0805_5%
BKOFF# DDC2_CLK DDC2_DATA
2 2 @ R1237
DMIC_DAT 28 DMIC_CLK 28 +5VS INV_PWM 1 0_0402_5%
2 R1238
1
2
2
C232
D61 4
VIN
IO1
2
3
IO2 GND
1
2
USB20_N4
100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J
2 2 2N7002DW-7-F_SOT363-6 Q8A
S 2 G
1
100K_0402_5% C238 0.047U_0402_16V7K
INV_PWM 32 BKOFF# 32
Limited Current < 1A
Q8B 2N7002DW-7-F_SOT363-6
5
11 ENAVDD
1 0_0402_5%
NB_BKLT_CTRL 11
R201 100K_0402_5%
C
2 C434 680P_0402_50V7K
Avoid Panel display garbage after power on.
B+
Must close JLVDS1pin 24、26
+3VS
INVPWR_B+ @ L5
1
2
0_0805_5%
DDC2_CLK DDC2_DATA
R203 2.2K_0402_5%
@ C302 220P_0402_25V8J
1
R202 2.2K_0402_5%
EMI request
L6 1 2 FBMA-L11-201209-221LMA30T_0805
DMIC_DAT
2
2
DMIC_CLK
1
2 2 2 2 2 2
1 C234
EMI request.
PRTR5V0U2X_SOT143-4
@ C1399 1 @ C1400 1 @ C1401 1 @ C1402 1 @ C1504 1 @ C1505 1
2
2 R200 2
0.1U_0402_16V4Z
1
+5VALW
3
D
1
C233 4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.1U_0402_16V4Z
1 1
R199 1M_0402_5% 6 2
C231
DDC2_CLK 11 DDC2_DATA 11
ACES_88242-4001 CONN@
LVDS_ACLK+ LVDS_ACLKDDC2_CLK DDC2_DATA LVDS_BCLK+ LVDS_BCLK-
@ R245 10K_0402_5%
+USB_CAM
C
USB20_P4
R198 100_0805_5%
3
LVDS_B0+ LVDS_B0LVDS_B1+ LVDS_B1LVDS_B2+ LVDS_B2-
+LCDVDD
LVDS_A2- 11 BKOFF# LVDS_A2+ 11 LVDS_A1- 11 LVDS_A1+ 11 LVDS_A0- 11 LVDS_A0+ 11 LVDS_ACLK- 11 LVDS_ACLK+ 11
4
11 11 11 11 11 11
LVDS_B0+ LVDS_B0LVDS_B1+ LVDS_B1LVDS_B2+ LVDS_B2-
LVDS_A2LVDS_A2+ LVDS_A1LVDS_A1+ LVDS_A0LVDS_A0+ LVDS_ACLKLVDS_ACLK+
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
+3VS Q7 SI2301BDS-T1-E3_SOT23-3
1
LVDS_BCLK+ LVDS_BCLK-
11 LVDS_BCLK+ 11 LVDS_BCLK-
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND
1
1
+3VS
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GND
1
JLVDS1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41
+5VALW 1
+LCDVDD
USB20_P4 USB20_N4
22 USB20_P4 22 USB20_N4
D
2
2
2
1
1
INVPWR_B+
C237
680P_0402_50V7K
1 2
680P_0402_50V7K
C235 C236 D
2
1
+LCDVDD
680P_0402_50V7K
+3VS
3
1
1
2
2
@ C303 220P_0402_25V8J
EMI reserver B
B
USB Camera +5VS
+USB_CAM
OUT
R1091 215K_0603_1%
5
GND
1
1
3
SHDN
BYP
4
G916-390T1UF_SOT23-5
C1391
10U_0805_6.3V6M 2 R1093 100K_0402_1%
2
2
R440 0_0402_5% 1
C1392 10U_0805_6.3V6M
1
2
2
2
IN
1
U42 1
A
+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm +USB_CAM=1.25(1+R1091/R1093)
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. LCD CONN. Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
19
of
46
5
4
3
2
1
+3VS
PCI_TRDY#
2 8.2K_0402_5%
PCI_FRAME#
R277 1
2 8.2K_0402_5%
PCI_IRDY#
R278 1
2 8.2K_0402_5%
PCI_SERR#
R279 1
2 8.2K_0402_5%
PCI_PERR#
U12B D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3
+3VS
R281 1
2 8.2K_0402_5%
PCI_PIRQA#
R283 1
2 8.2K_0402_5%
PCI_PIRQC#
R284 1
2 8.2K_0402_5%
PCI_PIRQD#
R286 1
2 8.2K_0402_5%
PCI_PIRQF#
R288 2
1 8.2K_0402_5%
PCI_PIRQH#
R292 1
2 8.2K_0402_5%
PCI_REQ2#
R293 1
2 8.2K_0402_5%
PCI_REQ3#
+3VS R272 1
2 8.2K_0402_5%
PCI_DEVSEL#
R290 1
2 8.2K_0402_5%
PCI_REQ1#
R273 1
2 8.2K_0402_5%
PCI_STOP#
R276 1
2 8.2K_0402_5%
PCI_PLOCK#
C
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
RP28 1 2 3 4
8 7 6 5
PCI_PIRQE# PCI_PIRQB# PCI_PIRQG# PCI_REQ0#
J5 E1 J6 C4
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
PCI
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3#
D8 B4 D6 A5
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
D3 E3 R1 C6 E4 C2 J4 A4 F5 D7
PLTRST# PCICLK PME#
PCI_REQ0# PCI_GNT0# PCI_REQ1#
D
PCI_REQ2# PCI_REQ3# PCI_GNT3#
Place closely pin D4 CLK_PCI_ICH PCI_IRDY# PCI_RST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
C14 D4 R2
PLT_RST# CLK_PCI_ICH PCI_PME#
H4 K6 F2 G2
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PCI_RST# 32
@ R280 10_0402_5%
PCI_SERR# 32
1
2
PLT_RST# 9,25,26 CLK_PCI_ICH 17 PCI_PME# 32
@ C425 8.2P_0402_50V
C
Interrupt I/F PIRQA# PIRQB# PIRQC# PIRQD# ICH9-M ES_FCBGA676
F1 G4 B6 A7 F13 F12 E6 F6
1
2 8.2K_0402_5%
R275 1
2
D
R274 1
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
1 R291
2 0_0402_5%
ACCEL_INT 24
8.2K_0804_8P4R_5%
A16 swap override Strap B
PCI_GNT3# PCI_GNT3#
Low= A16 swap override Enble High= Default* @R294 1
Boot BIOS Strap PCI_GNT0#
2 1K_0402_5%
SPI_CS#1
B
Boot BIOS Location
0
1
SPI
1
0
PCI
1
1
LPC
* +3VALW
22 SPI_CS1#_R
SPI_CS1#_R
@ R295 1
PCI_GNT0#
@ R296 1
2 1K_0402_5% 2 1K_0402_5%
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. ICH9(1/4)-PCI/INT Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
20
of
46
5
4
3
2
ICH9M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
R300 1 R302
LAN100_SLP
ICH9M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05)
ICH_INTVRMEN ICH_SRTCRST#
D
C426 0.1U_0402_16V4Z
1
2
@ R303
ICH_LAN100_SLP
@ R304
E25 C13 F14 G13 D14 D13 D12 E13
+1.5VS
R312
28 HDA_BITCLK_CODEC
R207 9 HDA_BITCLK_NB 28 HDA_SYNC_CODEC
33_0402_5%
1
2
33_0402_5% 1 2 R316 33_0402_5% R208 R317
9 HDA_SYNC_NB 28,32 HDA_RST#_CODEC
1
33_0402_5% 33_0402_5%
R209
9 HDA_RST#_NB
R311 24.9_0402_1% 1 2 R259 HDABITCLK 1 2 0_0402_5% 2
1 1
33_0402_5%
2 2
1
2
28 HDA_SDIN0 9 HDA_SDIN2 28 HDA_SDOUT_CODEC 9 HDA_SDOUT_NB
R321 R204
33_0402_5% 33_0402_5%
1 1
2 2 PAD T55 PAD T56
P- HDD
SATA_RXN0_C SATA_RXP0_C SATA_TXN0 SATA_TXP0
0.01U_0402_16V7K C431 1 2 C433 1 2
SATA_TXN0 SATA_TXP0
Add 12p on HDA_SDOUT and HDA_SDOUT Add 12p on HDA_BITCLK_CODE and HDA_BITCLK_NB HDA_SDOUT_CODEC
C312 1
2
12P_0402_50V8J
HDA_SDOUT_NB
C66
1
2
12P_0402_50V8J
HDA_BITCLK_CODEC
C316 1
2
12P_0402_50V8J
HDA_BITCLK_NB
C67
2
12P_0402_50V8J
1
GLAN_CLK
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD_0 LAN_TXD_1 LAN_TXD_2 GPIO56 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC
AE7
HDA_RST#
HDA_SDIN0 HDA_SDIN2
AF4 AG4 AH3 AE5
HDA_SDOUT
AG5
SATA_TXN0_C SATA_TXP0_C
AG8
AH13 AJ13 AG14 AF14
@ R306 1 2 56_0402_5%
LPC_FRAME# 26,32
T54
1
AJ26
R_H_FERR#
R310
1
AD22
H_PWRGOOD
IGNNE#
AF25
H_IGNNE#
INIT# INTR RCIN#
AE22 AG25 L3
H_INIT# H_INTR KB_RST#
NMI SMI#
AF23 AF24
H_NMI H_SMI#
AH27
H_STPCLK#
AG26
THRMTRIP_ICH#
FERR#
TP12 SATA4RXN SATA4RXP SATA4TXN SATA4TXP
+VCCP
PAD
GATEA20 32 H_A20M# 6
R308 56_0402_5%
H_DPRSTP# 2 0_0402_5%
H_DPRSTP# 7,9,42 H_DPSLP# 7
H_FERR# 2 56_0402_5%
H_FERR# 6
H_PWRGOOD 7 H_IGNNE# 6
within 2" from R379
H_INIT# 6 H_INTR 6 KB_RST# 32
+VCCP C
H_NMI 6 H_SMI# 6
R315 56_0402_5%
H_STPCLK# 6 R319
2 54.9_0402_1%
1
H_THERMTRIP# 6,9
placed within 2" from ICH9M
AG27 AH11 AJ11 AG12 AF12
SATA_TXN4_C SATA_TXP4_C
0.01U_0402_16V7K 2 1 C428 2 1 C429
SATA_RXN4_C 24 SATA_RXP4_C 24 SATA_TXN4 24 SATA_TXP4 24
SATA_TXN4 SATA_TXP4
ODD
0.01U_0402_16V7K
SATALED# SATA5RXN SATA5RXP SATA5TXN SATA5TXP
SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP
LPC_FRAME#
R309
SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS
AH9 AJ9 AE10 AF10 AH18 AJ18 AJ7 AH7
SATA_TXN5_C SATA_TXP5_C
2 2
SATA_RXN5_C 30 SATA_RXP5_C 30 SATA_TXN5 30 SATA_TXP5 30
0.01U_0402_16V7K SATA_TXN5 1 C430 SATA_TXP5 1 C432 0.01U_0402_16V7K
CLK_PCIE_SATA# CLK_PCIE_SATA R322
e-SATA De-feature disable
CLK_PCIE_SATA# 17 CLK_PCIE_SATA 17
1 2 24.9_0402_1%
Within 500 mils
ICH9-M ES_FCBGA676
SI-1 Remove SSC
H_DPSLP#
J3 J1
H_DPRSTP_R# H_DPSLP#
CPUPWRGD
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34
K3
AJ25 AE23
STPCLK#
HDA_SDOUT
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
GATEA20 H_A20M#
THRMTRIP# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3
K5 K4 L6 K2
N7 AJ27
DPRSTP# DPSLP#
AF6 AH4
AJ16 AH16 AF17 AG17
LDRQ0# LDRQ1#/GPIO23 A20GATE A20M#
HDARST#
AG7 AE8
FWH4/LFRAME#
LAN_RSTSYNC
HDA_BITCLK HDA_SYNC
0.01U_0402_16V7K
B
B10 B28 B27
SATA_LED#
33 SATA_LED# 24 24 24 24
GLAN_COMP
@ R305 1 2 56_0402_5%
1
2
INTVRMEN LAN100_SLP
LPC
B22 A22
CPU
ICH_INTVRMEN LAN100_SLP
RTCRST# SRTCRST# INTRUDER#
RTC
1U_0603_10V4Z
A25 F20 C22
LAN / GLAN
C427
1
ICH_RTCRST# ICH_SRTCRST# SM_INTRUDER#
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
IHDA
CLRP2 SHORT PADS
2
1
+RTCVCC
H_DPRSTP# LPC_AD[0..3] 26,32
RTCX1 RTCX2
SATA
R307 1 2 20K_0402_5%
R301 1 2 10K_0402_5% +VCCP
U12A C23 C24
KB_RST#
D
Low = Internal VR Disabled High = Internal VR Enabled(Default)
ICH_RTCX1 ICH_RTCX2
GATEA20
R298 1 2 8.2K_0402_5%
2
1
+3VS
Low = Internal VR Disabled High = Internal VR Enabled(Default)
1
1 R299
ICH_INTVRMEN
SM_INTRUDER#
0_0402_5% 2 1
R297
2 1M_0402_5% 2 330K_0402_5% 2 330K_0402_5% 2 180K_0402_5%
0_0402_5% 2 1
1
2
+RTCVCC
C
1
B
Reserve cap on HDA_BITCLK for WWAN noise issue
Reserve SSC for EMI
BATT1
XOR CHAIN ENTRANCE STRAP:RSVD +3VS
@ +RTCVCC
@ R325 1 @ R326 1
BATT1.1
HDA_SDOUT_CODEC 2 1K_0402_5% ICH_RSVD 2 1K_0402_5%
ICH_RSVD 22
ICH_RTCX1
W=20mils
R329 1
W=20mils 2
D8 2
1
3 W=20mils
0_0402_5% R328 1 A
ICH_RSVD HDA_SDOUT_CODEC
0 0 1 1
1
ICH_RTCX2
2
10M_0402_5% C436 15P_0402_50V8J
0 1 0 1
1
1
2
2
2
4
2
3
32.768KHZ_12.5P_MC-146
2006/03/10
Deciphered Date
C435
PV for ESD
Title
JBATT1 1 2 3 4
0.1U_0402_16V4Z
1
1 2 GND GND ACES_85205-02001 CONN@
2
Compal Electronics, Inc. ICH9(2/4)_LAN,HD,IDE,LPC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
4
W=20mils 2
1K_0402_5%
2.2U_0603_6.3V4Z
Compal Secret Data 2007/08/28
Issued Date
R330 1
C438
15P_0402_50V8J
Security Classification
1
DAN202U_SC70
Place near ICH9
C437
Y2
5
CR2032 RTC BATTERY
+3VL
3
2
Wednesday, February 18, 2009
Sheet 1
21
of
46
A
R331 1 R332 1
+3VALW
+3VS
3
2
1
Place closely pin AF3 CLK_48M_ICH
2 2.2K_0402_5% 2 2.2K_0402_5%
R359 @ R361 R362
EC_SCI# CR_CPPE# CR_WAKE#
32 EC_LID_OUT# 17 H_STP_PCI# 17 H_STP_CPU#
R345
GPIO20 GPIO21
R353
1 2 100K_0402_5%
R372 R374 R375 R376 R377 R378 R379 R373 R380 B
R381
GPIO39
R225
32 EC_SCI# 32 EC_SMI#
@ R226
GPIO48 GPIO57
1
+3VS
GPIO49
R364 26 EXP_CPPE#
ICH_LOW_BAT# ICH_PCIE_WAKE# ICH_RI#
A14 E19
STP_PCI# STP_CPU#
PM_CLKRUN#
L4
@
OCP# AG19 CR_CPPE# AH21 EC_SCI#_SB 1 2 0_0402_5% AG21 EC_SMI# A21 EC_SCI#_GPIO12 1 2 0_0402_5% C12 C21 PAD T46 17/14 AE18 GPIO18 K1 GPIO20 AF8 CR_WAKE# AJ22 DIS/UMA A9 D19 PAD T47 CLKREQ#_C L1 17 CLKREQ#_C GPIO38 2 AE19 GPIO39 8.2K_0402_5% AG22 GPIO48 @ R739 1 2 AF21 GPIO49 0_0402_5% AH24 GPIO57 A8 R366 1 2 1K_0402_5% SB_SPKR M7 MCH_ICH_SYNC# AJ24 9 MCH_ICH_SYNC# ICH_RSVD B21 21 ICH_RSVD AH20 AJ20 AJ21
26 26 26 26
PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1
C445 1 C444 1
PCIE_RXN1 PCIE_RXP1 2 0.1U_0402_16V4Z PCIE_C_TXN1 2 0.1U_0402_16V4Z PCIE_C_TXP1
WLAN
26 26 26 26
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
C448 1 C449 1
PCIE_RXN3 PCIE_RXP3 2 0.1U_0402_16V4Z PCIE_C_TXN3 2 0.1U_0402_16V4Z PCIE_C_TXP3
LAN
25 25 25 25
GLAN_RXN GLAN_RXP GLAN_TXN GLAN_TXP
C452 1 C453 1
2 2
EC_SMI# GPIO14
2
Board ID New Card
1
26 26 26 26
PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4
C450 1 C451 1
PCIE_RXN4 PCIE_RXP4 2 0.1U_0402_16V4Z PCIE_C_TXN4 2 0.1U_0402_16V4Z PCIE_C_TXP4
SPI_CS1#_R
R748 10K_0402_5% R383 1
2 0_0402_5%
26 WXMIT_OFF#
+3VALW
USB_OC#0 USB_OC#1 USB_OC#2 WXMIT_OFF# USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11 USBRBIAS
1
R1183 R1184 R1185 R1186 WXMIT_OFF# USB_OC#5 R1187 USB_OC#10 R1188 USB_OC#11 R1189 R1190
DPRSLPVR/GPIO16 BATLOW# PWRBTN# LAN_RST# RSMRST#
SLP_M#
G20
PM_PWROK
M2
R348 1
B13
ICH_LOW_BAT#
R3
PWRBTN_OUT#
R346 1
4.7P_0402_50V8C
2
@ C441 4.7P_0402_50V8C
10K_0402_5% 2
DPRSLPVR 9,42
PWRBTN_OUT# 32
D20
R_EC_RSMRST# 38
D22
R_EC_RSMRST#
R5
CK_PWRGD
R6
M_PWROK
R354 1 R355 1
2 100_0402_5% 2 10K_0402_5%
EC_RSMRST# 32
CK_PWRGD 17 M_PWROK 9,32 +3VS
B16
F22 C19
CL_DATA0
CL_VREF0 CL_VREF1
C25 A19
CL_VREF0_ICH CL_VREF1_ICH
CL_RST0# CL_RST1#
F21 D18
CL_RST#
A16 C18 C11 C20
XMIT_OFF GPIO10 GPIO14 LAN_WOL_EN
MEM_LED/GPIO24 GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT WOL_EN/GPIO9
1
@ C440
D
2
PM_PWROK 9,32 2 0_0402_5%
CL_CLK0
CL_DATA0 CL_DATA1
1 2 1 SLP_S3# 29,32 SLP_S4# 32 SLP_S5# 32
F24 B19
CL_CLK0 CL_CLK1
10_0402_5%
T58 PAD
R360
CL_CLK0 9 CL_DATA0 9 C442
1
2 CL_RST# 9
1
2
3.24K_0402_1% R363 453_0402_1% NA lead free +3VALW
C
R367 XMIT_OFF 26
C443
1
R370 2
1
+3VALW
2
100K_0402_5%
1
2
3.24K_0402_1% R368 453_0402_1%
Within 500 mils
PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5
D23 D24 F23
SPI_CLK SPI_CS0# SPI_CS1#GPIO58/CLGPIO6
AG2 AG1
DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_CLKN DMI_CLKP
DMI_ZCOMP DMI_IRCOMP
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
SPI
SPI_MOSI SPI_MISO OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8#/GPIO44 OC9#/GPIO45 OC10#/GPIO46 OC11#/GPIO47
USB
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P
V27 V26 U29 U28
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
Y27 Y26 W29 W28
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
AB27 AB26 AA29 AA28
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
AD27 AD26 AC29 AC28
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
T26 T25
CLK_PCIE_ICH# CLK_PCIE_ICH
AF29 AF28
DMI_IRCOMP
AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2
DMI_RXN0 9 DMI_RXP0 9 DMI_TXN0 9 DMI_TXP0 9
PM_PWROK 2
DMI_RXN1 9 DMI_RXP1 9 DMI_TXN1 9 DMI_TXP1 9
D22 1
R_EC_RSMRST#
CH751H-40PT_SOD323-2
DMI_RXN2 9 DMI_RXP2 9 DMI_TXN2 9 DMI_TXP2 9 DMI_RXN3 9 DMI_RXP3 9 DMI_TXN3 9 DMI_TXP3 9
B
CLK_PCIE_ICH# 17 CLK_PCIE_ICH 17 R382 1
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9
24.9_0402_1% 2
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9
30 30 30 30 30 30 27 27 19 19 26 26 30 30 30 30 26 26 26 26
Within 500 mils +1.5VS
USB-0 Right side(with ESATA) USB-1 Left side USB-2 Left side USB-3 Cardreader USB-4 Camera USB-5 WLAN USB-6 Bluetooth USB-7 Finger Printer USB-8 MiniCard(WWAN/WiMAX) USB-9 Express card A
USBRBIAS USBRBIAS# ICH9-M ES_FCBGA676
R384 22.6_0402_1% 2
USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#0
S4_STATE#
CLPWROK
C29 C28 D27 D26
D25 E23
30 BT_OFF
1 2 110K_0402_5% 2 110K_0402_5% 2 110K_0402_5% 2 10K_0402_5% 1 2 110K_0402_5% 2 110K_0402_5% 2 110K_0402_5% 2 10K_0402_5% 1 2 10K_0402_5% 1 2 110K_0402_5% 2 110K_0402_5% 2 10K_0402_5%
J29 J28 K27 K26
GLAN_RXN G29 GLAN_RXP G28 0.1U_0402_16V4Z GLAN_TXN_C H27 0.1U_0402_16V4Z GLAN_TXP_C H26
17/14
R1179 R1180 R1181 R1182
N29 N28 P27 P26
E29 E28 F27 F26
@ R747 10K_0402_5%
C10
CK_PWRGD
SPKR MCH_SYNC# TP3 TP8 TP9 TP10
ME_EC_DATA1
EC_LID_OUT#
SLP_S3# SLP_S4# SLP_S5#
PWROK
TP11
L29 L28 M27 M26
GPIO10
C16 E16 G17
S4_STATE#/GPIO26
VRMPWRGD
GPIO1 GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5
SLP_S3# SLP_S4# SLP_S5#
@ R343
10_0402_5%
U12D
1
1
WAKE# SERIRQ THRM#
ME_EC_CLK1
R746 10K_0402_5%
A
CLKRUN#
ICH_SUSCLK
ICH9-M ES_FCBGA676
20 SPI_CS1#_R
USB_OC#6 USB_OC#1 USB_OC#2 USB_OC#4
D21 A20
PAD T59
2
2
DIS/UMA
SMBALERT#/GPIO11
H_STP_PCI# R_STP_CPU#
S4_STATE#
+3VS
2
WWAN
XDP_DBRESET#
@ R745 10K_0402_5% 1
R366 Low High -->No -->default boot
LINKALERT#
1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 1K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5%
+3VS
A17
6 OCP#
GPIO37
PMSYNC#/GPIO0
EC_LID_OUT#
VGATE
GPIO36
M6
ICH_PCIE_WAKE# E20 SIRQ M5 THERM_SCI# AJ23
17,42 VGATE
+3VS 28 SB_SPKR
R371
2 0_0402_5%
1
25,26 ICH_PCIE_WAKE# 32 SIRQ 32 THERM_SCI#
HDDHALT_LED#
+3VALW
R369
PM_BMBUSY#
9 PM_BMBUSY#
GPIO18
1 2 @ R365 10K_0402_5%
C
6 XDP_DBRESET# @ R340 10K_0402_5%
P1
@ R342
1
R358
@ R339 10K_0402_5%
SUSCLK
2
R357
SUS_STAT#/LPCPD# SYS_RESET#
CLK_14M_ICH 17 CLK_48M_ICH 17
1
R352
R4 G19
CLK_14M_ICH CLK_48M_ICH
2
R351
SUS_STAT# XDP_DBRESET#
H1 AF3
CLK14 CLK48
Place closely pin H1 CLK_14M_ICH
HDDHALT_LED# 33
0.1U_0402_16V4Z
R350
PM_BMBUSY#
T57
GPIO21 HDDHALT_LED# GPIO36 GPIO37
0.1U_0402_16V4Z
R349
PAD CLKREQ#_C
AH23 AF19 AE21 AD20
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37
Direct Media Interface
R356
clocks
SYS / GPIO
R344
RI#
Power MGT
R341
F19
MISC GPIO Controller Link
@ R338
ICH_RI#
SMB
PCI - Express
R337 D
+3VS
SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1
THERM_SCI# 1
@ R336
OCP#
1
R335
PM_CLKRUN#
2
R334
17,26 ICH_SMBCLK 17,26 ICH_SMBDATA
SIRQ
1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5%
2
R333
G16 A13 E17 C17 B18
SATA GPIO
U12C ICH_SMBCLK ICH_SMBDATA LINKALERT# ME_EC_CLK1 ME_EC_DATA1
1
4
2
5
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. ICH9(3/4)_DMI,USB,GPIO,PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
22
of
46
5
4
3
2
10U_0805_10V4Z C460
2
1
C456
2
1
2 2.2U_0603_6.3V4Z
2
10U_0805_10V4Z
1 ICH_V5REF_RUN
0.1U_0402_10V6K
1
2
C477
10U_0805_10V4Z
1U_0603_10V4Z
C476
C478 1U_0603_10V4Z
1
2
1
2
AC11 AD11 AE11 AF11 AG10 AG11 AH10 AJ10
VCC1_5_A[09] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16]
AC9
VCC1_5_A[17]
G10 G9
1
2
C483 0.1U_0402_16V4Z
C484 0.1U_0402_16V4Z
AJ5
2
VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2
VCCUSBPLL
AA7 AB6 AB7 AC6 AC7
VCC1_5_A[26] VCC1_5_A[27] VCC1_5_A[28] VCC1_5_A[29] VCC1_5_A[30]
A10 A11
VCCLAN1_05[1] VCCLAN1_05[2]
A12 B12
2
R390 1 +1.5VS
VCCLAN3_3[1] VCCLAN3_3[2] 23mA
CHB1608U301_0603 2
1
2
C487
2.2U_0603_6.3V4Z
1
10U_0805_10V4Z
0.1U_0402_16V4Z
C485
VCC1_5_A[23] VCC1_5_A[24] VCC1_5_A[25]
A27 4.7U_0805_10V4Z 2 D28 +1.5VS D29 CHB1608U301_0603 E26 1 C488 E27 1
VCCGLANPLL 80mA
R391 1
2
C489 0316 change design
+3VS 2
VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04]
R212 @ 0_0402_5%
0.1U_0402_16V4Z
AJ3 AC8 F17
T65 T66
AD8 VCCSUS1_5_ICH_1
A18 D16 D17 E22
VCCSUS3_3[05]
AF1
VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20]
T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7
2
(DMI)
0.1U_0402_16V4Z 1
AJ4
F18
2
C473
2
R740 2 180_0402_1%
1 1
+3VALW
+1.5VS C474
R741 150_0402_1%
2
2
+1.5VALW
T67
VCCSUS1_5_ICH_2
T68
0.1U_0402_16V4Z 1
2
VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] 1mA
A26
VCCCL1_05 VCCCL1_5
19/78/78mA
VCCGLAN3_3 ICH9-M ES_FCBGA676
GLAN POWER
A
VCC1_5_A[21] VCC1_5_A[22] 11mA 11mA
USB CORE
T69 T70
+3VS
1
VCCSUS1_5[2]
VCC1_5_A[20]
AC12 AC13 AC14
+1.5VS 2
VCCSUS1_5[1]
VCC1_5_A[18] VCC1_5_A[19]
AC21
1
2
2
+1.5VS
C475
212mA
2
1
1
+3VALW
1
2
1342mA
AC18 AC19
+1.5VS
1
2
1
1
0.1U_0402_16V4Z C480
1U_0603_10V4Z
VCCHDA
VCCSUSHDA VCCSUS1_05[1] VCCSUS1_05[2]
VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08]
ATX
C481 B
+3VS 0.1U_0402_16V4Z
C479
+1.5VS
B9 F9 G3 G6 J2 J7 K7
1
1
C468
2
AD19 AF20 AG24 AC20
VCCSATAPLL
AC16 AD15 AD16 AE15 AF15 AG15 AH15 AJ15
+1.5VS
ARX
2
1
+VCCP
C467
0316 change design
1
AJ19
2
0.1U_0402_16V4Z
+1.5VS
11mA 11mA
R389 1 2 CHB1608U301_0603
C464
C466
0.1U_0402_10V6K
+VCCP 1
0.1U_0402_16V4Z
C472
10U_0805_10V4Z
+3VS
AG29 AJ6 AC10
+1.5VS
C463
AB23 AC23
308mA VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14]
2
C471
2
20 mils
VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06]
C461
2
0.1U_0402_16V4Z
1
ICH_V5REF_SUS
VCC3_3[01] VCC3_3[02] VCC3_3[07]
1
C470
CH751H-40PT_SOD323-2
2mA
1
C469
10_0402_5%
48mA
V_CPU_IO[1] V_CPU_IO[2]
R385 1 2 CHB1608U301_0603
0.01U_0402_16V7K
0.1U_0402_16V4Z
C
D10
W23 Y23
VCC_DMI[2]
2
0.1U_0402_16V4Z
R388
R29
2
4.7U_0603_6.3V6M
+5VALW +3VALW
VCCDMIPLL
23mA VCC_DMI[1]
VCCPSUS
2
20 mils
C465
VCCPUSB
2
CH751H-40PT_SOD323-2
1
646mA
22U_0805_6.3VAM
D9
2mA
VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCC1_5_B[47] VCC1_5_B[48] VCC1_5_B[49] 47mA
VCCA3GP
R386 100_0402_5%
V5REF_SUS
AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29 F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23 W24 W25 K23 Y24 Y25
AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 C457 C455
2
+1.5VS_SB_B 1 1 + C459
V5REF
A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
1
AE1
VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26]
1634mA 2mA
1
ICH_V5REF_SUS
G3: 6uA
2
2
VCCRTC
CORE
1
2
A6
VCCP_CORE
1
A23
ICH_V5REF_RUN
PCI
C458 220U_D2_4VM
+3VS
1
+5VS
1
U12E
U12F
20 mils
40 mils
R387 1 2 CHB1608U301_0603
+1.5VS
D
2
+VCCP C454 0.1U_0402_16V4Z
C462 0.1U_0402_16V4Z
+RTCVCC
G22 G23
+3VALW
1
2
VCCCL1_05_ICH
C482 4.7U_0603_6.3V6M
T71
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106]
19/73/73mA VCCCL3_3[1] VCCCL3_3[2]
A24 B24
1 @ C486 1U_0603_10V4Z
+3VS
VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198]
VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]
H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25
D
C
B
A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
ICH9-M ES_FCBGA676
A
2
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. ICH9(4/4)_POWER&GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
23
of
46
24 23
GND GND
2
2
SATA_RXN0_C 21 SATA_RXP0_C 21
1
2
C493
1
2
+3VS
+3VS_ACL D23 2
1
CLK_SMBCLK +5VS
U29
VDDIO absolute man rating is VDD+0.1 1
+3VS_ACL_IO R568 0_0402_5% 1 2
2 3
SDA / SDI / SDO
GND
SDO
Reserved
Reserved
13
CLK_SMBDATA
12
R570 0_0402_5% 1 2
11
4
GND
GND
10
5
GND
INT 2
9
Vdd
INT 1
6
8
CLK_SMBDATA 15,16,17
ACCEL_INT 20
C
CS 2 R569
SATA_RXN4_C 21 SATA_RXP4_C 21
Near CONN side.
C512
1
2
C513
1
2
C514
1
2
C515
1
2
1 10K_0402_5%
10U_0805_10V4Z
SATA_TXP4 21 SATA_TXN4 21
10U_0805_10V4Z
1 C510 SATA_RXN4_C 1 C511 SATA_RXP4_C
1U_0603_10V4Z
SATA_TXP4 SATA_TXN4
0.1U_0402_16V4Z
Placea caps. near ODD CONN.
6 5 4 3 2 1
Vdd_IO
7 +5VS
0.01U_0402_16V7K SATA_RXN4 2 SATA_RXP4 2 0.01U_0402_16V7K
CLK_SMBCLK 15,16,17
0011101b
LIS302DLTR_LGA14_3x5
JODD
DP V5 V5 MD GND GND
D
Near CONN side.
CD-ROM Connector 13 12 11 10 9 8 7
2
+3VS
+3VS_ACL
GND A+ AGND BB+ GND
2
1
CH751H-40PT_SOD323-2
OCTEK_SAT-22EH1G_RV
C
1
+3VS_ACL_IO R564 0_0603_5% 1 2
C714
C492
C713
1
0.1U_0402_16V4Z
SATA_TXP0 21 SATA_TXN0 21
1 C494 SATA_RXN0_C 1 C495 SATA_RXP0_C
C491
+3VS_ACL
ACCELEROMETER (ST)
14
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
0.01U_0402_16V7K SATA_RXN0 2 SATA_RXP0 2 0.01U_0402_16V7K
1
1
SCL / SPC
V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12
SATA_TXP0 SATA_TXN0
10U_0805_10V4Z
D
1 2 3 4 5 6 7
C490
CONN@ JHDD GND A+ AGND BB+ GND
Pleace near HDD CONN (JP3)
+5VS
0.1U_0402_16V4Z
HDD Connector
2
10U_0805_6.3V6M
3
0.1U_0402_16V4Z
4
0.1U_0402_16V4Z
5
+5VS
SUYIN_127382FR013GX09ZR CONN@
B
B
PA@ ZZZ
PR@ ZZZ
PCB-MB
PCB-MB
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. HDD & CDROM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Wednesday, February 18, 2009
Sheet 1
24
of
46
5
4
3
LAN_DI LAN_CS
2
1 R695 2 R696
1
2 +3V_LAN 3.6K_0402_5% 1 1K_0402_1%
LAN Conn.
9/17 RT suggestion: R696 change to 1K ohm
Place Close to Chip
JRJ45 R697 300_0402_5% 2 1
U44 LAN_ACTIVITY# 20
22 GLAN_RXN
C241 2
1 0.1U_0402_16V7K PCIE_PTX_IRX_N2
21
22 GLAN_TXP
15
22 GLAN_TXN
16
17 CLK_PCIE_LAN 17 CLK_PCIE_LAN#
17 18
17 CLKREQ#_9
25
9,20,26 PLT_RST#
27
R688 1 22,26 ICH_PCIE_WAKE#
2 2.49K_0402_1%
HSOP HSON HSIP
LED0 HSIN
26 28
LAN_X1 LAN_X2
41 42
RTL8102EL
MDIP0 MDIN0 MDIP1 MDIN1 NC NC NC NC
REFCLK_P REFCLK_M CLKREQB PERSTB
46
ISOLATEB
LED3/EEDO LED2/EEDI/AUX LED1/EESK EECS
RSET
NC
LANWAKEB ISOLATEB CKXTAL1 CKXTAL2
1 R215 1K_0402_1% 2
C
7 14 31 47
ISOLATEB
22
GNDTX
LAN_ACTIVITY#
2 3 5 6 8 9 11 12
LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1-
1
T82 LANLED_ACT#
2
LANLED_LINK#
19 30 36 13 10
VCTRL12
2
1
+EVDD12 +LAN_VDD12
VDD33 VDD33
29 37
AVDD33 NC NC
1 40 43
SHLD1 PR4-
PR3PR3+
RJ45_MIDI0-
2 1
+3V_LAN
11
LANLED_LINK#
12
D
9
DETCET PIN2
10
PR2-
4
RJ45_MIDI0+
16
DETECT PIN1 PR4+
5
3
PR2+ PR1PR1+ SHLD1
15
Green LED+ Green LEDFOX_JM36113-P1122-7F CONN@
R698 300_0402_5%
LANGND 1
39 44 45
6
RJ45_MIDI1+
C269 0.1U_0402_16V4Z
1
LAN_SK_LAN_LINK#
Yellow LED-
7
@ D20 PACDN042_SOT23~D
2
Yellow LED+
14 8
C268 0.1U_0402_16V4Z RJ45_MIDI1-
4
VDDTX DVDD12 DVDD12 DVDD12 DVDD12
NC VCTRL12D
GND GND GND GND
38
48
NC NC NC
LAN_DO LAN_DI LAN_SK_LAN_LINK# LAN_CS
VCTRL12A
+3VS 23 24
33 34 35 32
2
1 0.1U_0402_16V7K PCIE_PTX_IRX_P2
3
C240 2
1
D
22 GLAN_RXP
+3V_LAN LANLED_ACT#
13
R1162 0_0603_5% 1 2 R1177 0_0603_5% +3V_LAN_IC 1 2 +3V_LAN
2
+LAN_VDD12
1
C271 0.1U_0402_16V4Z
2
C272 4.7U_0805_10V4Z
C
RTL8103EL-GR_LQFP48_7X7
R216 15K_0402_5%
U46
C247 1 +3VALW
C248 1
D
S
1
2
1 1 R218
32 LAN_POWER_OFF
2 10K_0402_5%
LAN_CT1 LAN_MDI1+ LAN_MDI1-
RD+ RDCT NC NC CT TD+ TD-
RX+ RXCT NC NC CT TX+ TX-
16 15 14 13 12 11 10 9
RJ45_MIDI0+ RJ45_MIDI0RJ45_CT0 RJ45_CT1 RJ45_MIDI1+ RJ45_MIDI1-
C257 1 C258 1
2 0.01U_0603_100V7-M RJ45_CT0_C 2 0.01U_0603_100V7-M RJ45_CT1_C
1 1
R693 75_0402_1% 2 2
RJ45_GND
R694 75_0402_1%
C259
1000P_1206_2KV7K
+3V_LAN
X'FORM_ HD-024A
1
2
G
2
2 0.01U_0402_16V7K
1 2 3 4 5 6 7 8
40 mils
3 @ C255
2 0.01U_0402_16V7K
LAN_MDI0+ LAN_MDI0LAN_CT0
Q19 SI2301BDS-T1-E3_SOT23-3
0.1U_0402_16V4Z
B
B
1
Close to Pin19
C252
2
1
Close to Pin45
+EVDD12
C253
2
1
C254
2
1
C261
2
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
C251
Close to Pin1,37,29 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
C250
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
C249
0.1U_0402_16V4Z
+LAN_VDD12
Close to Pin10,13,30,36
+3V_LAN
Close to Pin48 Y3
+LAN_VDD12
2
1
1
2
@ C265
@ 1 C262 2
C263
2
1
0.1U_0402_16V4Z
1
C264
LAN_X1 10U_0805_10V4Z
2
10U_0805_10V4Z
1
C267
0.1U_0402_16V4Z
A
2
1U_0402_6.3V4Z
C266
1U_0402_6.3V4Z
VCTRL12
2
1
LAN_X2
25MHz_20pF_6X25000017 1
C244
1
C245
27P_0402_50V8J 2 27P_0402_50V8J 2
A
9/17 RT suggestion: C267 change to 1uF
Compal Secret Data
Security Classification Issued Date
2007/08/28
2007/06/30
Deciphered Date
Title
Compal Electronics, Inc. RTL8102EL LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom Montevina UMA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Wednesday, February 18, 2009 Date: 5
4
3
2
Rev 0.1 Sheet 1
25
of
46
A
+3VALW
B
+3VALW
+3VS_WLAN R432
1
2
C568
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z 1 1
2 1 0_0805_5% 1
C566
1
1
C569
1
C570
C571
R431 2 1 0_0805_5% 1
C572 2 4.7U_0805_10V4Z
2
2
2
47P_0402_50V8J
2
2
2
2
Reserve for WWAN
ICH_PCIE_WAKE# CH_DATA CH_CLK CLKREQ#_6
30 CH_DATA 30 CH_CLK 17 CLKREQ#_6
CLK_PCIE_MCARD2# CLK_PCIE_MCARD2
17 CLK_PCIE_MCARD2# 17 CLK_PCIE_MCARD2
0.1U_0402_16V4Z
PLT_RST#
SI-1 Connect PLT_RST# to JP7.A17 17 CLK_DEBUG_PORT_1
SIM card Connector CONN@ JSIM 1 2 3 4 5 6
UIM_VPP UIM_RST UIM_CLK UIM_DATA UIM_PWR
1 2 3 4 5 G1 6 G2
R11 1
+3VS
2 0_0402_5% 2 0_0402_5%
PCIE_C_RXN3 PCIE_C_RXP3
PCIE_TXN3 PCIE_TXP3
22 PCIE_TXN3 22 PCIE_TXP3
10K_0402_5% CLKREQ#_6 2
R10 1
+3VS
2
7 8
R423 1 R425 1
22 PCIE_RXN3 22 PCIE_RXP3
UIM_CLK 1 C824 @ 18P_0402_50V8J
+3VS_WLAN
10K_0402_5% CLKREQ#_10 2
A1 A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 A39 A41 A43 A45 A47 A49 A51
WAKE# COEX1 COEX2 CLKREQ# GND REFCLKREFCLK+ GND Reserved Reserved GND PERn0 PERp0 GND GND PETn0 PETp0 GND GND +3.3Vaux +3.3Vaux GND Reserved Reserved Reserved Reserved
A53
GND
ACES_87212-06G0
UIM_PWR
+3VS_WWAN
17 CLK_PCIE_MCARD0# 17 CLK_PCIE_MCARD0
@ R400 1 2 0_0603_5%
2
0.01U_0402_16V7K 4.7U_0805_10V4Z
+3VS R418
S
3
+3VALW
1
2
2
2 32 WWAN_POWER_OFF
0.1U_0402_16V4Z
1 @ C1499
@ Q52
SI2301BDS-T1-E3_SOT23-3
2
PA@ R419 1 1 R421 PA@
22 PCIE_RXN1 22 PCIE_RXP1
1 2 0_1206_5%
D
1 PA@ C575
G
2
+3VS_WLAN
A6 A8 A10 A12 A14 A16
+1.5VS_WLAN
W_DISABLE# PERST# +3.3Vaux
A20 A22 A24
GND
GND
GND
XMIT_OFF# 2 PLT_RST# @ R424 1 R426 1
A28 A30 A32
+1.5V SMB_CLK SMB_DATA
GND
LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 1 D19 2 0_0805_5% 2 0_0805_5%
USB20_N5 22 USB20_P5 22
A42 A44 A46 A48
WL_LED# 33 +1.5VS_WLAN
+3.3Vaux
A52
+3VS_WLAN
GND
A54
GND
LED_WWAN# LED_WLAN# LED_WPAN# +1.5V
GND
0_0402_5% 2 PCIE_C_RXN1 2 PCIE_C_RXP1 0_0402_5% PCIE_TXN1 PCIE_TXP1
22 PCIE_TXN1 22 PCIE_TXP1
47P_0402_50V8J
Reserve for WWAN
+3VS_WWAN
B1 B3 B5 B7
WAKE# COEX1 COEX1 CLKREQ#
GND
B11 B13
REFCLKREFCLK+
B17 B19
Reserved Reserved
GND GND
B23 B25
PERn0 PERp0
B31 B33
PETn0 PETp0
B37 B39 B41 B43 B45 B47 B49 B51
B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 B38 B40 B42 B44 B46 B48 B50 B52
+3.3Vaux GND +1.5V UIM_PWR UIM_DATA UIM_CLK UIM_RESET UIM_VPP GND W_DISABLE# PERST# +3.3Vaux GND +1.5V SMB_CLK SMB_DATA GND USB_DUSB_D+ GND LED_WWAN# LED_WLAN# LED_WPAN# +1.5V GND +3.3Vaux
SI-1 For PR
UIM_PWR_R UIM_DATA_R UIM_CLK_R UIM_RST_R UIM_VPP_R UIM_PWR_R UIM_DATA_R UIM_CLK_R UIM_RST_R UIM_VPP_R
GND GND GND GND +3.3Vaux +3.3Vaux GND Reserved Reserved Reserved Reserved
+3VS_WWAN +1.5VS_WLAN UIM_PWR_R UIM_DATA_R UIM_CLK_R UIM_RST_R UIM_VPP_R PA@ D11 M_WXMIT_OFF# 2 PLT_RST# @ R420 1 R422 1 ICH_SMBCLK ICH_SMBDATA
1
XMIT_OFF 22
+3VALW +3VS_WLAN +1.5VS_WLAN
ICH_SMBCLK ICH_SMBDATA
A36 A38
USB_DUSB_D+
LPC_FRAME# 21,32 LPC_AD3 21,32 LPC_AD2 21,32 LPC_AD1 21,32 LPC_AD0 21,32
CH751H-40PT_SOD323-2
JMINIB ICH_PCIE_WAKE# CH_DATA CH_CLK CLKREQ#_10
17 CLKREQ#_10
1 PA@ C574
A2
+1.5V UIM_PWR UIM_DATA UIM_CLK UIM_RESET UIM_VPP
+3.3Vaux
QUASA_CA0416-092N21
@ R750 1 2 UIM_DATA 47K_0402_5%
+3VS_WWAN
1 PA@ C573
E
JMINIA
+1.5VS
@ C1498 47P_0402_50V8J
D
Mini Card Slot ---WLAN,WWAN
Reserve for WWAN
+1.5VS_WLAN 0.01U_0402_16V7K 4.7U_0805_10V4Z +3VS
1 @ C1497
C567
C
WL_LED# 1 PR@ R1225
WW_LED#_R 2 0_0402_5%
XMIT_OFF# 1 PR@ R1226
M_WXMIT_OFF# 2 0_0402_5%
R1227 R1228 R1229 R1230 R1231 R1232 R1233 R1234 R1235 R1236
1 1 1 1 1
2 2 2 2 2
1 1 1 1 1
2 2 2 2 2
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
PR@ PR@ PR@ PR@ PR@
UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP
PA@ PA@ PA@ PA@ PA@
2
CH751H-40PT_SOD323-2 1 WXMIT_OFF# 22 2 0_0805_5% +3VALW 2 0_0805_5% +3VS_WWAN +1.5VS_WLAN
USB20_N8 22 USB20_P8 22 WW_LED#_R
WW_LED# 33
+1.5VS_WLAN +3VS_WWAN
QUASA_CA0416-092N21
New Card
3
Express Card Power Switch
+1.5VS C576 1 2 0.1U_0402_16V4Z +3VS
C579 1
2 0.1U_0402_16V4Z
C580 1
2 0.1U_0402_16V4Z
2 4 17
+3VALW 9,20,25 PLT_RST# 32,35,40 SYSON 32,35,37,39 SUSP# +3VALW 22 EXP_CPPE#
PLT_RST#
6
SYSON
20
SUSP#
1
@ R439 1
22 USB20_N9 22 USB20_P9
U16 12 14
2 100K_0402_5%
10
EXP_CPPE#
9 18
1.5Vin 1.5Vin
1.5Vout 1.5Vout
3.3Vin 3.3Vin
3.3Vout 3.3Vout
AUX_IN SYSRST# SHDN#
AUX_OUT OC# PERST#
STBY#
NC
CPPE#
GND
11 13
+1.5VS_PEC
3 5
+3VS_PEC
15
+3V_PEC
22,25 ICH_PCIE_WAKE#
internal pull high to 3.3Vaux-in EC need setting at Hi-Z & output Low
2 0_0402_5% 2 0_0402_5%
1 1
USB9USB9+ EXP_CPPE# ICH_SMBCLK ICH_SMBDATA
+1.5VS_PEC +1.5VS_PEC
R438 1 2 0_0402_5%
+3V_PEC
PCIE_PME#_R PERST#
+3VS_PEC CLKREQ#_4 EXP_CPPE#
17 CLKREQ#_4
19 8
R436 R437
17,22 ICH_SMBCLK 17,22 ICH_SMBDATA
17 CLK_PCIE_NCARD# 17 CLK_PCIE_NCARD
PERST#
16
22 PCIE_RXN4 22 PCIE_RXP4
7
22 PCIE_TXN4 22 PCIE_TXP4
CPUSB#
Close to JEXP
RCLKEN ENE P2231NL E2 QFN 20P
4
Near to Express Card slot.
CONN@ JEXP
R12 +3VS
1
2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
+3VS_PEC
GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND
C577 0.1U_0402_16V4Z
3
1
1
2
2
C578 4.7U_0805_10V4Z
+1.5VS_PEC
C581 0.1U_0402_16V4Z
1
1
2
2
C582 4.7U_0805_10V4Z
+3V_PEC
GND GND SANTA_130801-5_RT
CLKREQ#_4
C583 0.1U_0402_16V4Z
1
1
2
2
C584 4.7U_0805_10V4Z
10K_0402_5%
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Compal Electronics, Inc. WLAN, WWAN, New Card Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet E
26
of
46
4
5
4
3
2
1
+3VS D
2
D
+VCC_4IN1
R1102 100K_0402_5% 0_0402_5% RST# 1
1
2
1
R1103 2
C1405
2
0.1U_0402_16V4Z 1 1 C1407 C1408
1
17 CLK_48M_CR 2
2
1 3 7 9 11 33
2
0.1U_0402_16V4Z
1 C1411
RST# MODE SEL
R1115 0_0402_5% 1 2
XTLI 2
2 @ C1415 6P_0402_50V8J
0.1U_0402_16V4Z
22 USB20_N3 22 USB20_P3 1
USB20_N3 USB20_P3 CR_LED#
8 44 45 47 48
3V3_IN RST# MODE_SEL XTLO XTLI
4 5 14
DM DP GPIO0
SI-1 Delete Crystall layout location
SI-1 Change LED type PA@ D54
1
2
2
1.2K_0402_5%
1
CR_LED#
HT-110TW_WHITE
6.19K_0402_1%
White
MODE SEL
R1111
1
C1409 1U_0603_10V4Z 1 2
2
RREF
12 32
DGND DGND
VREG MS_D4 NC
10 22 30
XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17 SD_DAT2/XD_RE#_SP16 SD_DAT3/XD_WE#_SP15 XD_RDY_SP14 SD_DAT4/XD_WP#/MS_D7_SP13 SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10 MS_INS#_SP9 SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6 XD_D5_SP5 XD_D4/SD_DAT1_SP4 SD_CD#_SP3 SD_WP_SP2 XD_CD#_SP1 EEDI
43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18
XTAL_CTR MS_D5
13 24
EEDO EECS EESK SD_CMD
15 16 17 36
2
D64 2
2
1 HT-110TW_WHITE PR@
@ C1412 47P_0402_50V8J
1
2
@ R1110 10K_0402_5%
6 46
1
+5VS
2 0_0402_5%
AV_PLL NC NC CARD_3V3 D3V3 D3V3
C
R1107
1 R1104
U47 C1406 1U_0603_16V6K
2
1
0.1U_0402_16V4Z C1404 1 2
+3VS
+3VS
C1410 4.7U_0603_6.3V6K
C1403 0.1U_0402_16V4Z
2
R1105 499K_0402_1%~D @ 1
1U_0402_6.3V6K
1
AGND AGND
Card Reader Connector CONN@ JREAD1
3
+VCC_4IN1 XD_CLE XDCE# XD_ALE XD_RE#_SDD2 XDWE#_SDD3 XDRDY XDWP#_SDD4 XDD0_SDD5 XDD1 XDD7_SDD6_MSD3 MSINS# XDD2_SDD7_MSD2 XDD6_SDD0_MSD0 XDD3_MSD1 XDD5_MSBS XDD4_SDD1 SDCD# SDWP XDCD# R1112 1
1
2 0_0402_5% 1 2 0_0402_5%
MSCLK R1106 SDCLK R1109
XD-VCC
XDD0_SDD5 XDD1 XDD2_SDD7_MSD2 XDD3_MSD1 XDD4_SDD1 XDD5_MSBS XDD6_SDD0_MSD0 XDD7_SDD6_MSD3
32 10 9 8 7 6 5 4
XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7
XDWE#_SDD3 XDWP#_SDD4 XD_ALE XDCD# XDRDY XD_RE#_SDD2 XDCE# XD_CLE
34 33 35 40 39 38 37 36
XD-WE XD-WP XD-ALE XD-CD XD-R/B XD-RE XD-CE XD-CLE
11 31
7IN1 GND 7IN1 GND
0_0402_5% 2 +3VS
41 42
7 IN 1 CONN
SD-VCC MS-VCC
21 28
SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-DAT4 SD-DAT5 SD-DAT6 SD-DAT7 SD-CMD SD-CD-SW
20 14 12 30 29 27 23 18 16 25 1
SDCLK XDD6_SDD0_MSD0 XDD4_SDD1 XD_RE#_SDD2 XDWE#_SDD3 XDWP#_SDD4 XDD0_SDD5 XDD7_SDD6_MSD3 XDD2_SDD7_MSD2 SDCMD SDCD#
SD-WP-SW
2
SDWP
MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-INS MS-BS
26 17 15 19 24 22 13
MSCLK XDD6_SDD0_MSD0 XDD3_MSD1 XDD2_SDD7_MSD2 XDD7_SDD6_MSD3 MSINS# XDD5_MSBS
+VCC_4IN1
C
7IN1 GND 7IN1 GND TAITW_R015-B10-LM
SDCMD
RTS5159E-GR_LQFP48_7X7
2
R1114 @ 10_0402_5%
1 10P_0402_50V8J @ C1413
2
B
2
R1113 @ 10_0402_5% B
1
SDCLK 1
MSCLK
1 10P_0402_50V8J @ C1414
2
A
A
Compal Secret Data
Security Classification Issued Date
2007/08/28
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. USB CardReader&CONN
Size Document Number Custom Date:
Rev 0.1
Montevina UMA
Wednesday, February 18, 2009 1
Sheet
27
of
46
B
C
CODEC POWER
1
300mA
R1118 R1122 0_0603_5%
1
2
U49
2
21 HDA_SDOUT_CODEC
0.01U_0402_16V7K
HDA_RST#_CODEC
5
HDA_SDOUT_CODEC
2
HDA_SYNC_CODEC
7
HDA_RST#_CODEC
21,32 HDA_RST#_CODEC
3
8
DVDD_CORE
HDA_BITCLK
HDA_SDO
R1132 1 1 R1178
19 DMIC_CLK 19 DMIC_DAT
22_0603_1% 2 2 0_0603_5%
30 29
EAPD_CODEC
32 EAPD_CODEC
10 23
PORT_A_L PORT_A_R
26 27
PORT_B_L PORT_B_R VREFOUT_B
13 14 20
MIC_EXTL MIC_EXTR VREFOUT_B
PORT_C_L PORT_C_R VREFOUT_C
15 16 21
MIC_INL MIC_INR VREFOUT_C
HDA_RST#
PORT_D_L PORT_D_R
24 25
DMIC_CLK DMIC0/GPIO1
PORT_E_L PORT_E_R
11 12
PC_BEEP/MONO SPDIF_OUT_0 SPDIF_OUT_1/GPIO7 EAPD/GPIO0/SPDIF_OUT 0 or 1
CAP2 VREFFILT
R1128 2 @ C1428 1
2
1
SENSEA 1 100K_0402_5% +VDDA_CODEC_R 1000P_0402_50V7K HP_IN_L HP_IN_R C1430 1 2 2.2U_0603_6.3V6K 1 2 2.2U_0603_6.3V6K
1
9
LINE_OUT_L LINE_OUT_R
MONO_INR 2 0.1U_0402_16V7K
1 C1434
1
2
HP Jack MIC_EXT_L 29 MIC_EXT_R 29
Jack MIC
MIC_IN_L 2 2.2U_0603_6.3V6K
1 C1432
MIC_IN_L 29
Internal SPKR.
MIC_IN_R 2 2.2U_0603_6.3V6K
1 C1433
R1133 47K_0402_5% 2 1
MONO_IN
MIC_IN_R 29
R1134 10K_0402_5% 2 1 +VDDA_CODEC
PV-1 For EMI
2
1
C1435
MIC_EXTR
2
1 C1459 0.1U_0402_16V7K
R1135
1
22 SB_SPKR
Q10A 2N7002DW-7-F_SOT363-6
D58 PSOT24C_SOT23-3
2
3
2
C1437
2
1
1
10U_0805_10V4Z
18 33
LINE_OUT_L 29 LINE_OUT_R 29
MIC_EXTL
22 19
92HD75B1X5NLGXYAX8 QFN 32P 1.5V CODEC
3
Q10B 5 4
C1478 1
1
HP_DET# 29 EXTMIC_DET# 29
2 1000P_0402_50V7K
Internal MIC
1U_0603_10V4Z
AVSS TPAD
C1429
HP_IN_L 29 HP_IN_R 29 MIC_EXT_L MIC_EXT_R
2 2.49K_0402_1% 2 39.2K_0402_1% 2 20K_0402_1%
1 1 1
10K_0402_5%
DVSS
R1124 R1125 R1126
C1431
C1436 4
MIC_IN_L
+VDDA_CODEC_R
0.1U_0402_16V7K
32 28 31
SENSE_A SENSE_B
HDA_SYNC
C1516 2
17
HDA_SDI
SI-1 For EMI request
1
AVDD
4.7K_0402_5%
2
HDA_BITCLK_CODEC 33_0402_5% R1130 1 2 HDA_SDIN0_CODEC
21 HDA_SYNC_CODEC
MIC_IN_R
3
21 HDA_SDIN0
4.7K_0402_5%
2 1000P_0402_50V7K
1
1
21 HDA_BITCLK_CODEC
R1120
4.7K_0402_5%
2
1U_0603_10V4Z R1121
2N7002DW-7-F_SOT363-6
6
DVDD_LV
C1419 1
6
1
+1.5VS
R1239 4.7K_0402_5%
1U_0603_10V4Z R1119
1U_0603_10V4Z
2
R1117 2 1 1K_0402_5%
C1423 2
0.1U_0402_16V7K
2
2
C1422 1
10U_0805_10V4Z
1
1U_0603_10V4Z
1
C1426
2
C1425
1
2
MIC_EXT_R
+VDDA_CODEC_R
VREFOUT_C
2
MIC_EXT_L C1424 0.1U_0402_16V7K
PV-1 ESD request
4.7K_0402_5%
1
+3VS
C1418 1
2
2
R1116 2 1 0_0402_5%
2
VREFOUT_B
1
+VDDA_CODEC
1
(4.75V(4.56~4.94V))
SI-1 Delete CODEC POWER IC
R1123 BLM18BD601SN1D_0603 2 1 +3VS_HDA
E
2
1
D
2
A
3
C1479 1
090212 For PC Beep Noise
2 1000P_0402_50V7K C1480
1
2 1000P_0402_50V7K C1481
1
2 1000P_0402_50V7K
R1174 1 R1175 1 R1176 1
2 0_0402_5%
2 0_1206_5%
2 0_1206_5%
GNDA 29
4
4
GND
GNDA
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Codec_IDT9275B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 0.1
Montevina UMA
Wednesday, February 18, 2009
Sheet E
28
of
46
A
B
C
D
E
JSPK1 SPKRSPKR+ SPKLSPKL+
AMP. FOR INTERNAL SPEAKER GAIN1
GAIN0
R1136 1 R1137 1 R1138 1 R1139 1
2 2 2 2
0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5%
Av(inv)
SPK_RSPK_R+ SPK_LSPK_L+
1 2 3 4 1
C1438
C1439
1
C1440
1
5 6
1
C1441
1
20
SPKR+
ROUT-
19
SPKR-
2
3 1
1 EC_MUTE# 32
1 2 100K_0402_5% 1 @ C1453
LOUT-
SPVDD
18
8
SPVDD
HPVDD
17
2
HP_OUTL
C1454
7
2
MV-1 For ESD request, close to JMIC2
0.1U_0402_16V4Z
+5VS
D57 PSOT24C_SOT23-3
1
16
1U_0603_10V4Z
2
1 2 C1458 1U_0603_10V4Z
INTMIC IN
28 MIC_IN_L 1
1
R1153 0_0805_5% 1
+3VS
1
22
3
21
ROUT+
HP_OUTR
SI-1 Add JSPK2 for PA
2 1U_0603_10V4Z
2
SPGND
SPGND
HPVSS
GND GND ACES_88231-02001
R1211 0_0402_5%
2
CONN@ JMIC2
2
HP_INR 26
SPKR_LIN-
15
1 2
2
5
14
1 2 3 4
1
4
2 1U_0603_10V4Z
CONN@ JSPK2 SPK_LSPK_L+
SLP_S3# 22,32
R1151
SPKL-
1U_0603_10V4Z
C1449
1
D56 PSOT24C_SOT23-3
HP_IN_L 28 HP_IN_R 28
23
HP_EN
1 C1461
2
330P_0402_50V7K
2
3 24
LOUT+
2
HP_IN_L HP_IN_R
C1455
BYPASS
6
2
GND1 GND2 E&T_3806-F04N-02R CONN@
U50 TPA6047A4RHBR QFN 32P
SPKR_LIN+
1
D55 PSOT24C_SOT23-3
@ R1147 1 2 100K_0402_5%
25 REG_EN
HP_INL 27 HP_INL
HP_INR
+VDDA_CODEC_IC
GAIN0
TML
GAIN1
2 2 2.2U_0805_10V6K 2.2U_0805_10V6K
SPKL+
10U_0805_10V4Z
1
1 1
SPKR_EN#
CPVSS
C1456
R1152 0_0805_5% 1
C1446 C1447
SPEAKER
9/20 SP02000CW00
10U_0805_10V4Z 2 1U_0603_10V4Z 2 0.1U_0402_16V7K 2
SPKR_RIN-
3
2 330P_0402_50V7K
330P_0402_50V7K
10U_0805_10V4Z
1
SPKR_RIN+
C1N
2
+5VS
2 1
0_0402_5% LINE_L_OUTR 1 0.47U_0402_6.3V6K
CPVDD
28 LINE_OUT_L
0_0402_5% LINE_R_OUTR 1 0.47U_0402_6.3V6K 1
9
C1451 2
0.47U_0402_6.3V6K R1148 LINE_C_OUTR 1 2 C1450 2 0.47U_0402_6.3V6K R1150 LINE_C_OUTL 1 2 C1452 2
C1457
C1448 2
28 LINE_OUT_R 2
R1144 1 2 0_0603_5%
28
GAIN1
0_0402_5% 2 GAIN1 0_0402_5% 2 GAIN0
33
1
31
1 R1145
32
@ R1143
C1443 1 C1444 1 C1445 1
C1442 1U_0603_10V4Z
29
2 100K_0402_5%
21.6dB
2
Close to Pin29
2
SGND
1 R1142
1
GAIN0
1
2 100K_0402_5%
C1P
1
1 @ R1141
REG_OUT
V 15.6dB
0
TPA6047 LDO OUTPUT 4.7V +VDDA_CODEC
R1140 0_0805_5% 2 1
10
1
+5VS +5VS
13
12dB
12
1
30
0
2 330P_0402_50V7K
VDD
10dB
CPGND
0
11
0
1 2 3 4
1 2
28 MIC_IN_R
3 4
1 2 GND GND ACES_88231-02001
HP_OUTL HP_OUTR
3
3
SI-1 Add Audio board connector
Audio connector JAUDIO 28 MIC_EXT_R 28 MIC_EXT_L
HP_OUTL HP_OUTR
SI-1 Change IR1 to SCR00000E00 +5VL
1 2 3 4 5 6 7 8 9 10
MIC_EXT_R MIC_EXT_L
28 EXTMIC_DET# 28 HP_DET#
EXTMIC_DET# HP_DET#
1
Consumer IR
1 2 3 4 5 6 7 8 9 10
R1158 100_0805_5%
11 12
IR1 1
2
4
2 32 CIR_IN
CIR_IN
3 4
C1466
Vout VCC
4
GND GND IRM-V536/TR1_3P
Compal Secret Data
Security Classification
4.7U_0805_10V4Z
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
AMP & Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
GND1 GND2 ACES_87213-1000G CONN@
B
C
D
Rev 0.1
Montevina UMA
Wednesday, February 18, 2009
Sheet E
29
of
46
5
4
3
Right side USB Power Switch
2
1
Right side ESATA/USB combination Connector
+5VALW
USB_VCCC USB_VCCC
U41
C1381
TPS2061IDGNR_MSOP8 2
4.7U_0805_10V4Z
1 + 2
JESAT C1383 1000P_0402_50V7K
USB_EN#
1
W=100mils
8 7 6 5
OUT OUT OUT OC#
C1382 0.1U_0402_16V4Z
D
GND IN IN EN#
C1380 150U_B_6.3VM_R40M
1 2 3 4
1
2
R1080 1 R1081 1
22 USB20_N0 22 USB20_P0
1
2
1
2 10K_0402_5%
1 0.01U_0402_16V7K SATA_RXN5 1 0.01U_0402_16V7K SATA_RXP5
C1385 2 C1384 2
+5VALW
D45
USB20_P0_R
3
GND GND GND GND TYCO_1759576-1 CONN@
@
4
D
GND A+ ESATA AGND BB+ GND
12 13 14 15
+5VALW
USB
VBUS DD+ GND
5 6 7 8 9 10 11
SATA_TXP5 SATA_TXN5
21 SATA_TXP5 21 SATA_TXN5 21 SATA_RXN5_C 21 SATA_RXP5_C
R1083
1 2 3 4
USB20_N0_R USB20_P0_R
2 0_0402_5% 2 0_0402_5%
@
VIN
IO1
IO2 GND
2
USB20_N0_R
D46
1
+5VALW SATA_TXN5
PRTR5V0U2X_SOT143-4
4
VIN
IO1
2
3
IO2 GND
1
SATA_TXP5
PRTR5V0U2X_SOT143-4
C
C
Finger printer
BT Connector JBT 10
+3VS
2
9
R1084 R1085
@ R1086 1 @ R1087 1
1 0_0402_5% 1 0_0402_5%
2 2
USB20_P6 22 USB20_N6 22 BT_LED 33 CH_DATA 26 CH_CLK 26
1K_0402_5% 1K_0402_5%
2 2
@
0.1U_0402_16V4Z D30 4
+5VALW
IO1
IO2 GND
2
USB20_P7_R
D47 VIN
3
+3VS
IO1
IO2 GND
2
USB20_P6_R
1
PRTR5V0U2X_SOT143-4 R235 1
+3VALW
2 +3VAUX_BT
0_0603_5%
P-TWO_161011-04021
Q105 @ 1
1
B
2 0_0603_5%
PRTR5V0U2X_SOT143-4
3
2
1
R1090 100K_0402_5%
2
2
C1386 @ 1U_0603_10V4Z
0.1U_0402_16V4Z
1
G
1
2
SI2301BDS-T1-E3_SOT23-3
R236 D
3
VIN
USB20_N6_R
1 2 3 4 GND GND
S
USB20_N7_R
1 2 3 4 5 6
4
+5VALW
1
1
2 0_0402_5% USB20_N7_R 2 0_0402_5% USB20_P7_R
R634 1 R635 1
22 USB20_N7 22 USB20_P7
+3VS_FP
2
+3VAUX_BT USB20_P6_R USB20_N6_R
CONN@ JFPR
1
B
8 7 6 5 4 3 2 1
ACES_87213-0800G CONN@
R628 0_0805_5%
C756
GND 8 7 6 5 4 3 2 GND 1
C1387
1
2
0.01U_0402_16V7K
USB cable connector for Right side
22 BT_OFF
R1092 1
2 10K_0402_5%
C1388
1
C1389
2 4.7U_0805_10V4Z
C1390 1 2 0.1U_0402_16V4Z
JUSB +5VALW 32 USB_EN# 22 USB20_N2 22 USB20_P2 22 USB20_N1 22 USB20_P1
USB_EN#
1 2 3 4 5 6 7 8 9 10
11 12
A
1 2 3 4 5 6 7 8 9 10
GND1 GND2
A
ACES_87213-1000G CONN@
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. USB, BT, eSATA Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
30
of
46
5
4
3
2
1
SPI ROM
D
D
+3VL U27 20mils C712 0.1U_0402_16V4Z
1
32 SPI_CLK 32 FWR#
1 R553 1 R554 1 R556
VCC
3
2 32 FSEL#
8
SPI_FSEL# 2 10_0402_5% SPI_CLK_R 2 10_0402_5% SPI_FWR# 2 10_0402_5%
VSS
4
W
7
HOLD
1
S
6
C
5
D
Q
2
SPI_SO 1 R555
FRD# 2 0_0402_5%
FRD# 32
WIESON G6179 8P SPI
R230 SPI_FSEL# 2
1
33_0402_5% R231 SPI_CLK_R 2
SPI_FWR#
1
R232 2
1
C308 2
1
22P_0402_50V8J
1
33_0402_5%
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH WIESO_G6179-100000_8P
22P_0402_50V8J
33_0402_5%
C
C307 2
C309 2
1
C
22P_0402_50V8J
EMI request
B
B
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. BIOS ROM Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
31
of
46
+1.5VS
C301
+3VL_EC +3VS
C715
C716
C717
C718
+3VL
C719
2 2 1000P_0402_50V7K
2
+3VL_EC R572 1
+EC_AVCC
2 0_0805_5%
1
2 33_0402_5%
15P_0402_50V8J 17 CLK_PCI_EC
20 PCI_RST#
2 47K_0402_5%
R578
1 0.1U_0402_16V4Z
2
2 C721
22 EC_SCI# 1
1
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
JOPEN
+3VALW
+3VL
+3VS
1 1
R713 100K_0402_5%
@ R124 10K_0402_5%
R583 10K_0402_5%
R721 10K_0402_5%
2
2
2
2
AD
PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D
LID_SW#
TP_BTN#
R191 10K_0402_5%
33,36 33,36 6 6
2 @ R589 1 0_0402_5%
PS2 Interface
SPI Flash ROM
SLP_S3# SLP_S5# EC_SMI# 2 LID_SW# 0_0402_5% ESB_CLK_R ESB_DAT_R EC_PME# @ R591 2 0_0603_5% 1 9 TSATN# FAN_SPEED 6 FAN_SPEED WWAN_POWER_OFF 26 WWAN_POWER_OFF UTX LAN_POWER_OFF_R R5931 2 +3VL ON/OFFBTN 4.7K_0402_5% 33 ON/OFFBTN
1
33 NUM_LED#
1 C324 0.1U_0402_16V4Z
2
C723 15P_0402_50V8J 1 2
C325 0.1U_0402_16V4Z
2
NC
OSC
122 123
PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
OSC
1
CRY1
2
+EC_AVCC
@ C794 1
2 100P_0402_50V8J
INV_PWM 19
KSO14
@ C795 1
2 100P_0402_50V8J
DIM_LED 35 ACOFF 37
KSO13
@ C796 1
BATT_TEMP BATT_OVP ADP_I ADP_ID TP_BTN#
2 100P_0402_50V8J
KSO12
@ C797 1
2 100P_0402_50V8J
KSO3
@ C798 1
2 100P_0402_50V8J
KSO6
@ C799 1
2 100P_0402_50V8J
KSO8
@ C800 1
68 70 71 72
FAN_SET VCTRL IREF AC_SET
2 100P_0402_50V8J
KSO7
@ C801 1
2 100P_0402_50V8J
KSO4
@ C802 1
2 100P_0402_50V8J
KSO2
@ C803 1
83 84 85 86 87 88
EC_MUTE# USB_EN# I2C_INT
2 100P_0402_50V8J
KSI0
@ C804 1
2 100P_0402_50V8J
KSO1
@ C805 1
2 100P_0402_50V8J
KSO5
@ C806 1
2 100P_0402_50V8J
KSI3
@ C807 1
2 100P_0402_50V8J
KSI2
@ C808 1
2 100P_0402_50V8J
KSO0
@ C809 1
2 100P_0402_50V8J
KSI5
@ C810 1
2 100P_0402_50V8J
KSI4
@ C811 1
2 100P_0402_50V8J
KSO9
@ C812 1
2 100P_0402_50V8J
KSI6
@ C813 1
2 100P_0402_50V8J
KSI7
@ C814 1
2 100P_0402_50V8J
KSI1
@ C815 1
2 100P_0402_50V8J
1
0.01U_0402_16V7K ECAGND 2
BATT_TEMP 36 BATT_OVP 36 ADP_I 37 ADP_ID 36 TP_BTN# 33
FAN_SET 6 VCTRL 37 IREF 37 AC_SET 37 EC_MUTE# 29 USB_EN# 30 I2C_INT 33
R579 1 R580 1
2 10K_0402_5% 2 10K_0402_5%
TP_CLK TP_DATA
TP_CLK 33 TP_DATA 33 R582
97 98 99 109
2 0_0402_5%
1
AC_LED# 36
119 120 126 128
R227 R228 R229
1 1 1
2 2 2
GPI
L30 0_0603_5%
73 74 89 90 91 92 93 95 121 127
2 10K_0402_5%
1
CIR_IN VCC1_PWRGD FSTCHG STD_ADP CAPS_LED# BAT_LED# ON/OFFBTN_LED# SYSON VR_ON AC_IN
2
110 112 114 115 116 117 118
V18R
124
KB926QFD2_LQFP128_14X14
SLP_S4# ENBKL EAPD_CODEC THERM_SCI# SUSP# PWRBTN_OUT# NMI_DBG#
FRD# 31 FWR# 31 SPI_CLK 31 FSEL# 31
SPI_CLK 1
2
BKOFF# 19 M_PWROK 9,22 TP_LED# 33
R254 1
2
NMI_DBG#
CONN.( TYPE "D" KB) CONN@ JKB
SLP_S4# 22 ENBKL 11 EAPD_CODEC 28 THERM_SCI# 22 SUSP# 26,35,37,39 PWRBTN_OUT# 22
C724 4.7U_0603_6.3V6K
14" INT_KBD
PM_PWROK 9,22
100_0402_5%
KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1
+3VL ADP_ID
1
For C Revision
C327 22P_0402_50V8J
1 10K_0402_5% EC_RSMRST# 22 EC_LID_OUT# 22 EC_ON 38 WL_BLUE_LED# 33
+3VL
2
PV-1 For WWAN noise
+5VL
CIR_IN 29 T84 FSTCHG 37 STD_ADP 37 CAPS_LED# 33 BAT_LED# 33 ON/OFFBTN_LED# 33 SYSON 26,35,40 VR_ON 42
R586 EC_RSMRST# 100 101 R588 1 2 EC_ON 0_0402_5% 102 WL_BLUE_LED# 103 PM_PWROK_R 104 BKOFF# 105 M_PWROK 106 TP_LED# 107 108
PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7
FRD# FWR# SPI_CLK FSEL#
33_0402_5% 47_0402_5% 33_0402_5%
2
D16 1
CH751H-40PT_SOD323-2
R714 10K_0402_5% D14 1
+3VL
2 PCI_SERR#
PCI_SERR# 20
CH751H-40PT_SOD323-2
R715 150K_0402_5%
1 2
0_0805_5% R443 1
2
1 C726
LAN_POWER_OFF_R
2 0.1U_0402_16V4Z
L31 1
AC_IN
2 0_0603_5%
2
D13 1
ACIN
0_0402_5% +3VL
+3VL
1
2
1
1
R1099 4.7K_0402_5% 1
R1100 4.7K_0402_5% 33 ESB_CLK 33 ESB_DAT
C791
2 R731 R732
1 1
2 0_0402_5% 2 0_0402_5%
@ C315 10P_0402_25V8K ESB_CLK_R ESB_DAT_R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
ACIN 37
CH751H-40PT_SOD323-2
2
25 LAN_POWER_OFF
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11
1
EC DEBUG port @ R233 2
CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59
+3VL_EC
C725 15P_0402_50V8J
UTX
SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS#
XCLK1 XCLK0
@ R595 20M_0402_5%
4
32.768KHZ_12.5PF_9H03200413 1
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
2
NC
NUM_LED#
CRY2
Y5 3
EMI request
SM Bus
GND GND GND GND GND
PCI_RST#
SLP_S3# SLP_S5# EC_SMI# LID_SW#
63 64 65 66 75 76
DIM_LED ACOFF
R720
GPIO
SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47
2 100P_0402_50V8J
KSO11
SPI Device Interface
1
EC_PME#
77 78 79 80
PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0
EC_PME# 22,29 22 22 33
R190 1 OPP@
33 WL_BLUE_BTN
2
2
SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2
SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2
INV_PWM
+5V_TP
11 24 35 94 113
20 PCI_PME#
DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F
DA Output KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49
21 23 26 27
C720
BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43
1
+3VALW
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82
@ C793 1
AVCC
PWM Output
J1
1
R581 8.2K_0402_5% 2
1
R213 8.2K_0402_5%
R403 1
1
PCI_RST#
1
SUSP#
2
SYSON
HDA_RST#_EC
12 13 37 20 2 0_0402_5% 38
INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13
MISC
2 100P_0402_50V8J
KSO10
2
+3VL
CLK_PCI_EC PCI_RST# ECRST#
GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC &
@ C792 1
1
@ R576 2
1 2 3 4 5 7 8 10
1
@ C722 1
21 GATEA20 21 KB_RST# 22 SIRQ 21,26 LPC_FRAME# 21,26 LPC_AD3 21,26 LPC_AD2 21,26 LPC_AD1 21,26 LPC_AD0
GATEA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
KSO15
2
4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
AGND
2 2 2 2
69
1 1 1 1
For EMI
HDA_RST#_EC
1
Q21 MMBT3904_NL_SOT23-3
ECAGND
R573 R577 R574 R575
VCC VCC VCC VCC VCC VCC
SMB_EC_DA1 SMB_EC_CK1 SMB_EC_DA2 SMB_EC_CK2
3
21,28 HDA_RST#_CODEC
67
9 22 33 96 111 125
U30
1
EC recommend
R251 10K_0402_5%
C
+3VS
2
100P_0402_50V8J
1
R250 56_0402_5%
E
+3VL
BATT_OVP
1
HDA level shift
1
B
2 2 0.1U_0402_16V4Z
1000P_0402_50V7K
2
1
0.1U_0402_16V4Z 1
2 2
0.1U_0402_16V4Z 1 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 G1 G2
ACES_85202-24051
SI-1 Reverse KB connector
2 100P_0402_50V8J
Vendor Recommend
Compal Secret Data
Security Classification Issued Date
2007/08/28
Deciphered Date
2006/07/26
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Compal Electronics, Inc. EC KB926/KB Conn. Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet
32
of
46
B
C
D
E
Power Button
MV-1 For ESD request, close to JTPSW
for debug only
SI-1 Delete SW2
TP_LED# TP_BTN#
3
2
3
+5VS 2
D65 SM05_SOT23
System LED Conn
8 7 6 5 4 3 2 1
+5VALW +5VS
White AMBER
+3VS 32 BAT_LED# 21 SATA_LED# 22 HDDHALT_LED#
ON/OFFBTN_LED#
Keyboard backlight Conn
Caps-Lock Conn
CONN@ JLED 10
8 GND 7 6 5 4 3 2 1 GND
+5VS
CONN@ JCAP 1 2 3 4 GND GND
9
ACES_87213-0800G
+5VS_LED
1 2 3 4 5 6
2
0_0805_5%
CAPS_LED# 32
T/P Board (Inculde T/P_ON/OFF)
CONN@ JKBL
R205 1
1 2 3 4 5 6
CONN@ JTPSW
1 2 3 4 GND GND
1 2 3 4 GND GND
P-TWO_161011-04021
P-TWO_161011-04021
1 2 3 4 5 6
+5VS
TP_LED# TP_BTN#
TP_LED# 32 TP_BTN# 32
P-TWO_161011-04021
T/P Board Conn +3VL
+5VALW
ENE@ R56 1 R149 1 ENE@ main@1 R169
32 ON/OFFBTN_LED# 32 ESB_CLK 32 ESB_DAT 32 I2C_INT +5VALW 32 LID_SW# 32 ON/OFFBTN
OPP@ OPP@
R151 R1191
2
+5V_TP
C313
D67 SM05_SOT23 JCSB CONN@
1 2 3 4 5 6 7 8 9 10 11 12
ESB_CLK_CAP ESB_DAT_CAP
2 FBMA-11-100505-801T 0402 2 FBMA-11-100505-801T 0402
Close to JP59 2 1.8K_0402_5%
2
3
1 2 3 4 5 6 7 8 9 10 GND GND
1 2 3 4 5 6
TP_CLK TP_DATA
TP_CLK 32 TP_DATA 32
P-TWO_161011-04021 @ C730 100P_0402_50V8J
1
1
2
2
@ C731 100P_0402_50V8J
MV-1 For ESD request, close to JTP 3
Mini card LED
P-TWO_161021-10021
2 0_0402_5% C1518 1
C729 0.1U_0402_16V4Z
2
1 2 3 4 GND GND
2
4.7U_0603_6.3V6K
+5VS
+3VS
0.1U_0402_16V4Z 2
R193 10K_0402_5% @ D60
1
R1192 1 OPP@
CONN@ JTP 3
2 0_0402_5% 2 0_0402_5%
1 2 R238 1K_0402_1%
32 NUM_LED#
1
2
1
2 0_0402_5% 2 0_0402_5%
1 1
2 0_0603_5%
1
WL_BLUE_LED#
R691 1
SM05_SOT23
2
32 WL_BLUE_BTN
+5V_TP R53 0_0805_5% OPP@
1
Cypress@ R729 1 R730 1 Cypress@
32,36 SMB_EC_CK1 32,36 SMB_EC_DA1
R51 0_0805_5% Main@ 2
SWITCH BOARD.
+5V_TP
1
1
+5VALW
ENE@ C326 33P_0402_50V8K ESB_CLK_CAP 2 1
2
D28 SM05_SOT23
1
SI-1 Change Cap board power rail to +3VL
TP_DATA TP_CLK 3
2
3
1
1
1
1
D66 SM05_SOT23
2
A
MV-1 For ESD request, close to JCSB 1
D
3
WL_BLUE_LED# 32 Q11 2N7002_SOT23-3
S
2 G
1
30 BT_LED
2
R716 100K_0402_5%
D24 26 WL_LED#
2
26 WW_LED#
3
WL_BLUE_LED#
1
PSOT24C_SOT23-3 4
4
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Compal Electronics, Inc. KBD, ON/OFF, SW, CIR Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet E
33
of
46
4
3
R648 2
+3VS_LS
0_0603_5% 2
37
39
40
41
42
43
44
45
46
38 IN_D1-
IN_D1+
VCC3V
IN_D2-
IN_D2+
GND
IN_D3-
IN_D3+
VCC3V
GND DDC_EN
32
HDMI_DETECT
29
HDMIDAT
SCL_SOURCE
SCL_SINK
28
HDMICLK
R1205 2 2 2 2
1 1 1 1
0_0402_5% 0_0402_5% 4.7K_0402_5% 0_0402_5%
+3VS_LS +3VS_LS
+3VS_LS
@ R1247 2
27 26
+3VS_LS
25
2 R655
4.7K_0402_5% 1 +3VS_LS
1 2 R1249 0_0402_5% 1 0_0402_5%
GND
HDMI_DETECT
24
OUT_D123
OUT_D1+ 22
VCC3V 21
OUT_D220
OUT_D2+ 19
GND
OE*
D
R654 10K_0402_5%
D
S
Q108
2 G C
2N7002_SOT23-3
S IC STHDLS101TQTR QFN 48P HDMI SHIFTER
1
18
2 0_0402_5%
OUT_D3-
thm_pad
17
GND
VCC3V OUT_D3+
VCC3V
VCC3V
12
GND
2
31 30
ANALOG2
2
R1203
R1245 @ R1246 R651 @ R652
SDA_SINK
4.7K_0402_5% 2
1 R1252
+3VS_LS
33
HPD_SINK
16
C
VCC3V
GND
15
@ R1251 1
1
SDA_SOURCE
49 +3VS_LS
1
2
PC1
OUT_D4-
2
2
0_0402_5%
HPD_SOURCE
11
2.2U_0603_6.3V4Z
0_0402_5%
34
ANALOG1(REXT)
13
1 @C1517
0_0402_5% 2 4.7K_0402_5% 2
35
8
10 R1248 1 @ R1250 1
+3VS_LS
1 4.7K_0402_5% +3VS_LS
7
9
9 HDMICLK_NB 2 0_0402_5%
47
C321 GND
2
2
1
1
5
@ R1202 36
1
1
2
FUCNTION2
1 4.7K_0402_5% +3VS_LS
1
4
PC0
2
FUNCTION3
FUNCTION4
FUNCTION1
OUT_D4+
TMDS_B_HPD
VCC3V
3
6
9 HDMIDAT_NB
GND
14
2
R653 3.9K_0402_1% 2 1
GND
@ R1241
3
2
2 4.7K_0402_5%
2 0_0402_5%
1 R1206
48 IN_D4+
2
1
+3VS_LS
2 1 R1204
2 1 @ R1244
R1242 1 2 0_0402_5%
IN_D4-
1
U43
1
10U_0805_6.3V6M
1
+3VS
0.1U_0402_10V6K C318
TMDS_B_DATA0 11 TMDS_B_DATA0# 11
1 @ R1201 4.7K_0402_5%
@ R1243 4.7K_0402_5%
1
1
11 TMDS_B_CLK# 11 TMDS_B_CLK
@ R1240 4.7K_0402_5%
R650 2.2K_0402_5% 2
TMDS_B_DATA1 11 TMDS_B_DATA1# 11
+3VS_LS +3VS_LS
+3VS_LS
R649 2.2K_0402_5%
+3VS_LS
11 TMDS_B_DATA2# 11 TMDS_B_DATA2
+3VS_LS
EQUALIZATION SETTING: [PC1,PC0]=00,8dB [PC1,PC0]=01,4dB (Recommanded) [PC1,PC0]=10,12dB [PC1,PC0]=11,0dB
1
D
1
0.1U_0402_10V6K C319
+3VS_LS
2
0.01U_0402_16V7K C320
5
HDMI_TX_0-
R1207 20K_0402_5%
@C769
@ R656
2
HDMICLK+
2
0.5P_0402_50V8B
+3VS_LS
1
HDMI_TX_2-
0.5P_0402_50V8B
HDMI_CLK-
WCM-2012-900T_0805 HDMI_CLK+ 3
L39 HDMI_TX_0-
1
1
2
2
HDMI_TX_0+
4
4
3
WCM-2012-900T_0805 HDMI_TX0+ 3
1 @ R1215
2 0_0402_5%
@ R1216 1
0_0402_5% 2
HDMI_TX0-
HDMI_TX_1+
4
A
2
1
2
4
3
1 @ R1217
2 0_0402_5%
@ R1218 1
0_0402_5% 2
HDMI_TX_2-
1 4
1
HDMI_TX1-
WCM-2012-900T_0805 HDMI_TX1+ 3
2 0_0402_5%
RB411D T146 _SOT23-3 D31
X 4.7K ohm
+5VS_HDMI 1
R1244
X
X
R653 R1206
X
3.9K ohm 499 ohm 499 ohm 0 ohm X 0 ohm
X
X
X
2.2uF
0 ohm
X
X
4.7K ohm
R1251
X
X
4.7K ohm
R1252 R1247
0 ohm X
0 ohm X
R1249
0 ohm
0 ohm
R1245
0 ohm
0 ohm
R1246 R1203
C773 R1207 R1208
X
HDMI_DETECT
X
R665 1 2 1K_0402_1%
L40 1
C774 330P_0402_50V7K 2
0 ohm X
X
X
4.7K ohm
X
0 ohm
X 4.7K ohm
X
2
C314 @ 2200P_0402_25V7K
18 16 15 19
HDMI_CLKHDMI_CLK+ HDMI_TX0HDMI_TX0+ HDMI_TX1HDMI_TX1+ HDMI_TX2HDMI_TX2+
12 10 9 7 6 4 3 1
+5V SDA SCL HP_DET CKCK+ D0D0+ D1D1+ D2D2+
CEC Reserved
GND GND GND GND GND GND GND GND DDC/CEC_GND
13 14 2 5 8 11 20 21 22 23 17
A
X X
X
0.1uF
1uF
1uF
Security Classification
V
X
X
Issued Date
X
1 0.1U_0402_16V4Z C773
SUYIN_100042MR019S153ZL CONN@
X
V
HDMIDAT HDMICLK 2
FBML10160808121LMT_0603 1
D32 SKS10-04AT_TSMA
4.7K ohm
X
2
B
JHDMI1
X
R1250
R1202
1 @ R1219
4.7K ohm
4.7K ohm
R1205
3
4.7K ohm X
HDMI_TX2-
4
0 ohm X
WCM-2012-900T_0805 HDMI_TX2+ 3
2
X
2 2200P_0402_25V7K
X
R1241 2
0 ohm
C273
R1243
R1248
L42
HDMI_TX_2+
X
@ 1
R1204 4.7K ohm
C1517
L41 1
X
+5VS
1
0_0402_5% 2
X
HDMI Connector
1
@ R1214 1
R1242 R1201
Parade 8171
R50 3.9K_0402_1%
2 0_0402_5%
Parade 8101T
2
3
1 @ R1213
R1240
ST
R49 3.9K_0402_1% 2 1
2
4
HDMI_TX_1-
HDMI_TX_1+ 0.5P_0402_50V8B
2
4
@C772
2
2 HDMICLK+ B
@ R659 1 2 68_0402_5%
2 68_0402_5%
0_0402_5% 2
2
HDMI_TX_0+ 0.5P_0402_50V8B
SI-1 Use ST only
L38 1
+3VS_LS
@ R658 1
To option use ST or Parade
1
@C770
2 68_0402_5%
HDMI_TX_1@C771 HDMI_TX_2+
R1208 7.5K_0402_1%
HDMICLK-
1
1 TMDS_B_HPD 0_0402_5%
@ R1212 1
@ R657
2 68_0402_5%
1
11 TMDS_B_HPD#
HDMICLK-
R9
TMDS_B_HPD#
1
4.7K ohm
X
Compal Secret Data 2007/08/28
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc. HDMI LS & Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
Montevina UMA
Date:
5
4
3
2
Sheet
Wednesday, February 18, 2009 1
34
of
46
6
+1.8V to +1.8VS Transfer
SI7326DN-T1-E3_PAK1212-8
+1.8V
2
C1513
1
2
2
SUSP# 26,32,37,39
+1.8V
+0.9V
H3 HOLEA
H4 HOLEA
H5 HOLEA
H6 HOLEA
H7 HOLEA
H8 HOLEA
H9 HOLEA
1
H2 HOLEA
1
SUSP#
1 +VCCP
+1.5VS
2
1
C1515
1
5
H1 HOLEA
+3VS
1
C1514
Q13B
Discharge circuit +5VS
C
0.1U_0402_16V4Z
1
1
2
C1512 SUSP 41
1
SYSON
1
26,32,40 SYSON
SUSP
1
Q13A
100K_0402_5%
1
SYSON#
1
100K_0402_5% 41 SYSON#
0.1U_0402_16V4Z
R640
0.1U_0402_16V4Z
1 R639
6
2
SI-1 For EMI DDR issue SI-R 2 caps and change to GND
+3VL
0.1U_0402_16V4Z
1
2
2 RUNON
@ C768
10U_0805_10V4Z
1
4
@ C767
0.1U_0402_16V4Z
2
10U_0805_10V4Z
1
+3VL
1 2 3
5
@ C766
1
+1.8VS
U34 @
C
0.01U_0402_16V7K
1
+1.8V
Q35 2N7002_SOT23-3
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6 4 3 2
2
S
C765
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2 C65 4700P_0402_25V7K
D
DIM_LED# D
2 G
2
Q34B
1
1
Q34A
2
2
1 4
SUSP
5
DIM_LED
32 DIM_LED
470_0402_5% SUSP
R224 470_0402_5%
C294 0.1U_0402_16V4Z
2
1
R638
1
RUNON
2
1
1
RUNON_3VS
2
1
R637 10K_0402_5% 2
10U_0805_10V4Z
1
C764
3
2
3 10U_0805_10V4Z
1 330K_0402_5%
+5VS_LED
Q15
SI2301BDS-T1-E3_SOT23-3
0.1U_0402_16V4Z
2
R636
2
1
10U_0805_10V4Z
2
C762
3
2
2
1
C761 4
R223 330K_0402_5%
10U_0805_10V4Z
1
1
+5VS
D
C760
SI7326DN-T1-E3_PAK1212-8 +3VS +3VALW U33 1 2 5 3 1 1 C759 C763
G
D
B+
0.1U_0402_16V4Z
+5VALW B+
1
DIM LED
+3VALW to +3VS Transfer
+5VS
SI7326DN-T1-E3_PAK1212-8 U32 1 2 5 3
2
S
+5VALW to +5VS Transfer
3
2
4
4
5
+1.8VS H13 HOLEA
1
1
H12 HOLEA
1
1
H11 HOLEA
2
470_0402_5%
SUSP
1
5
1
1 2 3 Q12B SUSP
@ R647
470_0402_5%
D
3
2
4
2 6 Q12A SYSON#
2N7002DW-7-F_SOT363-6
5
H10 HOLEA
R646
2N7002DW-7-F_SOT363-6
1
1 2 Q9B SUSP
470_0402_5%
1
2
3
2 6 Q9A SUSP
R643
470_0402_5%
4
4
5
1
2 3 Q6B SUSP
R645
470_0402_5% 2N7002DW-7-F_SOT363-6
2 6 1
2
2N7002DW-7-F_SOT363-6
Q6A SUSP
R644
470_0402_5%
2N7002DW-7-F_SOT363-6
R642
470_0402_5%
2N7002DW-7-F_SOT363-6
R641
1
1
B
1
B
S
@ Q44
1
FM1 1
FM2 1
FM3
FM4 1
2 G 2N7002_SOT23-3
T21 T33 T45 T52 T60 T62 T64 T73 T75
T32 T34 T51 T53 T61 T63 T72 T74 T76
For ICT
A
A
Compal Secret Data
Security Classification 2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. DC/DC Interface Document Number
Rev 0.1
Montevina UMA Wednesday, February 18, 2009
Sheet 1
35
of
46
A
B
C
D
+3VALW 3
PQ3 TP0610K-T1-E3_SOT23-3 +3VL
BATT
1 PR9 2 100K_0402_5%
connect to KBC pin97
PL1 HCB2012KF-121T50_0805 2 PL2 HCB2012KF-121T50_0805 1 2
1
PJSOT24C_SOT23-3 2
1
0.01U_0402_25V7K PC6
1 PC3 1000P_0402_50V7K
2
PD1
2 1 PC2 100P_0402_50V8J
3
2
ACES_87302-0441
105K_0402_1% PR6 1 2
8 2
1
2
ADPIN
+
1
0 -
PU1A LM358ADT_SO8
PR5 10K_0402_5% 2 1
P
3
BATT_OVP 32
G
2
2
VIN
RLZ3.6B_LL34
1 2 PR3 10K_0402_5%
1
4
ADP_SIGNAL
PC5 1000P_0402_50V7K 2 1
6 5 4 3 2 1
@1000P_0402_50V7K
PC4 100P_0402_50V8J 2 1
GND GND 4 3 2 1
2
PR2 10K_0402_5%
+5VALW
499K_0402_1% PR4 1 2
PD4
1
JDC1
PC12
1
PR8 2K_0402_5%
1
1
2 1
ADP_ID 32
1
2
1
0.01U_0402_25V7K PC1
340K_0402_1% PR1 1 2
AC_LED# 32
2
2
VMB
1
PD2
3
PC8 1000P_0402_50V7K
PC9 0.01U_0402_50V4Z
CPU
2
3 1
PJSOT24C_SOT23-3
3
1
1
1
2 PJSOT24C_SOT23-3
PH1 10K_TH11-3H103FT_0603_1%
PR14 100_0402_5%
1 1 PC10 0.22U_0603_10V7K
-
8 6
2 PR11 150K_0402_1%
PR12 2.49K_0402_1%
PR15 150K_0402_1%
1
2
2
+3VL
2
PR16 6.49K_0402_1% 1 2
+
1
S
P
1
+5VALW
D
3
SMB_EC_CK1 32,33
37
5
0 G
SMB_EC_CK1 BAT_ID
EN0 38
PR10 200K_0402_1% 1 2
4
SMB_EC_DA1 32,33
1
SMB_EC_DA1
7
PQ1 SSM3K7002FU_SC70-3
2 G
PU1B LM358ADT_SO8
PC11 1000P_0402_50V7K
2
2
2
2
PR13 100_0402_5%
1
3
PR7 604K_0402_1% 1 2
+5VS
1
PD3 SUYIN_200045MR006G101ZR
PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C
1
1
EC_SMD EC_SMC
2
1 2 3 4 5 6 7 8
2
1 2 3 4 5 6 GND GND
BATT
PL3 HCB2012KF-121T50_0805 2 PL4 HCB2012KF-121T50_0805 1 2
JBATT
PR17 1K_0402_5%
2
BATT_TEMP 32
4
4
Compal Secret Data
Security Classification Issued Date
2007/05/29
Deciphered Date
2008/05/29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title
Compal Electronics, Inc. DC Connector/CPU_OTP
Size
Document Number
Rev 0.1
Montevina Consumer Discrete Date:
W ednesday, February 18, 2009 D
Sheet
36
of
46
A
B
C
P4
D
B+
BATT P2 PQ102 AO4433 1P SO8
PR102
4
1 1 5 6 7 8
3
3 2 1
2 21
2
2
1 2
BQ24740VREF 1
20
19
18
47K_0402_5% PR119 BAT_ID 36
2
2 G
1
PR121 200K_0402_1%
1
IREF 32
1
PR120 2 1 133K_0402_1%
PR122 681K_0402_1% 1 2
2
PC124 0.1U_0603_25V7K
3
BATT
S
2
17
PQ111 SSM3K7002FU_SC70-3
1
PC118 0.1U_0402_10V7K
1
PC121 100P_0402_50V8J 2 1
2
1 2
PC105 4.7U_0805_25V6-K
1
1
DPMDET
CELLS
SRP
SRN
BAT
SRSET
IADAPT
PC135 @470P_0603_50V8J
1U_0603_10V6K PR117 100K_0402_5% 1 2
2
1VIN_1
1
PQ110
PC119
PR124 1K_0402_5% 1 2
VIN 1 2
PU102B
PACIN
1
7
O
LM393DG_SO8
1
G
8 P
-
1
PR133 10K_0603_0.1%
3
PR134 10K_0402_5% 2
2
PD103 RLZ4.3B_LL34
S FSTCHG# 1
PQ113 SSM3K7002FU_SC70-3 3
STD_ADP 32
PR136 60.4K_0402_1% 1 2 VIN_1
D
2 G
32 FSTCHG
1.24VREF
PC126 0.047U_0402_16V7K
+
2
PQ112 SSM3K7002FU_SC70-3
6
ACIN 32
PR127 10K_0402_1%
2
1 PU102A LM393DG_SO8
D
2 G 3
1
5
1
PR132 100K_0402_5% 2 1
CHGEN#
PR130 2.15K_0402_1% 1 2
2
+3VL
4
PR128 10K_0402_5% 2 1
1 2
PR126 100K_0402_1%
8
PC125 0.1U_0603_25V7K
PR129 10K_0402_1% 2 1
2
1
+3VL
P 4
4 S TR AO4468 1N SO8
22
IADAPT
15
2 PC120 0.22U_0603_10V7K 2 1
2
PC123 0.1U_0402_10V7K
2
PR135 10K_0603_0.1%
G
1
O -
PR141 @4.7_1206_5%
1 1SS355_SOD323-2
VIN
1 2
+
23
DL_CHG
2
+3VL
PR131 133K_0402_1%
2
REGN
D
PR123 1M_0402_5% 1 2
PR125 47_1206_5%
3
LX_CHG
24
PC128 4.7U_0805_25V6-K
PGND
VIN
VIN
25
PR112 0.015_1206_1% 1 2
PC116 4.7U_0805_25V6-K
LODRV
ISYNSET
PR118 10K_0402_5% 1 2
PD104 1SS355_SOD323-2
PL102 10U_LF919AS-100M-P3_4.5A_20% 1 2
2 2
EXTPWR
PR116 15K_0402_1%
2
2
PR115 100K_0402_1%
Charge Detector
BATT
0.1U_0402_10V7K
1
REGN
PQ106 DTC115EUA_SC70-3
4
2
PH
VADJ
32
1
VDAC
1
1
14
32 ADP_I
3
26
1
12 13
2
PR114 @0_0402_5% 1 2
PC117 1U_0603_10V6K
2
HIDRV
2
PD102 VADJ
PR113 143K_0402_1%
16
1
32 VCTRL
PU101 BQ24740RHDR_QFN28_5X5
VREF
AO4466_SO8 PC111 1
+3VL 11
SSM3K7002FU_SC70-3
2 1SS355_SOD323-2
10
27
PC114 4.7U_0805_25V6-K
28
ACOFF
PQ108
1
BTST
PC110 1U_0805_25V6K 1 2 PR142 0_0402_5% BST_CHG1 2 PR139 0_0402_5% DH_CHG 1 2
5 6 7 8
CHGEN
PVCC
AGND
2
29
2
1
2 ACN
TP
IADSLP
BQ24740VREF
1
PR108 10_1206_5% 1 2
1
1
S
1U_0603_6.3V6M
PQ109
2 G
PD101 ACOFF#
D
3
PACIN
PR111 3K_0402_1% 1 2
2
ACOFF#
3 2 1
PC112 1 2
PACIN_1 38
VIN
CHG_B+
PC113 4.7U_0805_25V6-K 2 1
9
PC104 4.7U_0805_25V6-K
2 ACN
1 2
ACP 3
5
6
4 LPMD
ACDET
LPREF 8
PR103 47K_0402_5% 1 2
PR105 10K_0402_5%
1
SUSP#
8 7 6 5
CHG_B+
CHGEN# 7
26,32,35,39
PR110 0_0402_5% 1 2
0.012_2512_1%
2
1 2 3
PL101 HCB2012KF-121T50_0805 2
PC102 1U_0603_6.3V6M
PC108 0.1U_0603_25V7K
1 2
PR140 100K_0402_5%
1
1
ACDET ACSET
2
1
PC107 @0.01U_0402_16V7K
1 PR109 150K_0402_5%
3
2 S
PR104 0_0402_5% 2
ACSET
1
PQ105 DTC115EUA_SC70-3
3 1
D
1
2 PR106 200K_0402_5%
PQ104 DTA144EUA_SC70-3
4
2 1
1
3
1 2
1
2
2
3
PQ107 SSM3K7002FU_SC70-3 2 G
8 7 6 5
32 AC_SET PC106 0.47U_0603_16V7K 2 Structure> 1
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