ECS 761GX-M754 - REV 1.0

SAVE OFFLINE

1

A

2

3

4

5

6

761GX-M754

8

P1.COVER SHEET P2.BLOCK 03.ClawHammer_1_HyperTransport 04.ClawHammer_2_DDR 05.ClawHammer_3_Misc 06.ClawHammer_4_Power 07.DDR DIMM 08.Termination Resistors 09.761GX-1 LDT, PCI Express 10.761GX-2 MuTIOL & Others 11.761GX-3 Power and Ground 12.761GX-4 Power, Decoupling 13.PCI Express_X16 14.VGA Connector 15.Clock Generator 16.964-1 PCI/IDE/HyperZip 17.964-2 LPC/MII/CPU/GPIO 18.964-3 USB/SATA 19.964-4 Power 20.PCI 1 21.PCI 2 & PCI3 22.IDE 23.Super I/O (ITE8712) 24.HM/FAN 25.COM1/COM2/LPT 26.KB/MS/ROM/FDC 27.ATX/Panel/RTC 28.USB 29.RT8800 (CPU VCORE ) 30.VCC2.5VDUAL&DDR_VTT 31.IVDD/VDDQ 32.Dual/PWR_Detect 33.Audio Codec 34.Audio Interface 35.LANPHY(RTL8201BL/CL)

REV:1.0 REV:B--->1.0

7

PCB: 15-K97-011000 BOM: 89-200-K97100

B

C

A

B

C

Signature Date D

Designer Layout Check Approval 1

D

Eli Yang

10/04/2005

Ruru

Elitegroup Computer Systems

Jacy Wu

761GX-M754

Title Size Custom

Evan

Document Number

Date: 2

3

4

5

6

7

Rev 1.0

Cover Sheet

Tuesday, October 04, 2005

Sheet

1

of 8

35

1

2

3

4

5

6

7

8

System Block Diagram A

A

DDR SDRAM CPU TEMPERATURE MONITOR

Temperature monitor

AMD-ATHLON64-754

F75383S DIMM 1

LINK0

16*16

IN

DIMM 2

SSTL-2 Termination

OUT

PCI-E X16

VGA CONN

SIS761GX B

B

MuTIOL 1GMHz LAN RTL8201CL

PCI SLOT 3

PCI SLOT 2

AC'97 Audio Codec ALC655/AD1888

PCI SLOT 1

SiS964 PS/2 IDE 1

IDE 2

KEYBOARD /MOUSE

USB 0

USB 2

USB 4

USB 6

USB 1

USB 3

USB 5

USB 7

SATA1 C

C

LPC Bus

SATA2

LPC ROM

Optional

CPU FAN

SYS FAN

VOLTAGE MONITOR

FAN CONTROL

LPC Super I/O SYSTEM TEMPERATURE MONITOR

ITE8712F/J

PCB size:244*204 mm PARALLEL

22U/25DE

5*7 mm

100U/16DE

6.3*11 mm

220U/10DE

6.3*11 mm

470U/16DE

8*11 mm

1000U/10DE

8*14 mm

1200U/16DE

10*25 mm

1800U/63DE

8*20 mm

3300U/25DE

10*25 mm

FLOPPY

D

2

D

COM1/2

D

D

D

3

C

1 23 1

3

G

S

G

G

S

S

B

E

E BC

Elitegroup Computer Systems

2

1

761GX-M754

Title

TO-263

TO-263

TO-252

SOT-23

SOT-23

SOT-23

T0-92

T0-92

B55QS03

2SK3296

20N03 TM3055TL-S 45N03

2N7002 SI2303S SI2301S

2N3904 2N3906 MMBT2907A

BAT54C BAT54S

LM431 78L05-D

2N2222A 2N2097A

Size Custom

Document Number

1

2

3

4

5

6

Rev 1.0

BLOCK SCH.

Date:

Tuesday, October 04, 2005 7

Sheet

2

of 8

35

8

7

6

5

4

VLDT-

3

2

1

VLDT CPUA

VDD_HT0A_RUN

D L0_CADIN_L0 L0_CADIN_H0 L0_CADIN_L1 L0_CADIN_H1 L0_CADIN_L2 L0_CADIN_H2 L0_CADIN_L3 L0_CADIN_H3 L0_CADIN_L4 L0_CADIN_H4 L0_CADIN_L5 L0_CADIN_H5 L0_CADIN_L6 L0_CADIN_H6 L0_CADIN_L7 L0_CADIN_H7 L0_CADIN_L8 L0_CADIN_H8 L0_CADIN_L9 L0_CADIN_H9 L0_CADIN_L10 L0_CADIN_H10 L0_CADIN_L11 L0_CADIN_H11 L0_CADIN_L12 L0_CADIN_H12 L0_CADIN_L13 L0_CADIN_H13 L0_CADIN_L14 L0_CADIN_H14 L0_CADIN_L15 L0_CADIN_H15

C

L0_CTLIN_L1 L0_CTLIN_H1

B27 B29 C26 C28 D25 D27 D29 AD28 AD27 AC29 AD29 AB28 AB27 AA29 AB29 W29 Y29 V28 V27 U29 V29 T28 T27 AC25 AD25 AC26 AC27 AA25 AB25 AA26 AA27 W26 W27 U25 V25 U26 U27 R25 T25

VLDT0_A0 VLDT0_A1 VLDT0_A2 VLDT0_A3 VLDT0_A4 VLDT0_A5 VLDT0_A6 L0_CADIN_L0 L0_CADIN_H0 L0_CADIN_L1 L0_CADIN_H1 L0_CADIN_L2 L0_CADIN_H2 L0_CADIN_L3 L0_CADIN_H3 L0_CADIN_L4 L0_CADIN_H4 L0_CADIN_L5 L0_CADIN_H5 L0_CADIN_L6 L0_CADIN_H6 L0_CADIN_L7 L0_CADIN_H7 L0_CADIN_L8 L0_CADIN_H8 L0_CADIN_L9 L0_CADIN_H9 L0_CADIN_L10 L0_CADIN_H10 L0_CADIN_L11 L0_CADIN_H11 L0_CADIN_L12 L0_CADIN_H12 L0_CADIN_L13 L0_CADIN_H13 L0_CADIN_L14 L0_CADIN_H14 L0_CADIN_L15 L0_CADIN_H15

L0_CLKIN_L0 L0_CLKIN_H0 L0_CLKIN_L1 L0_CLKIN_H1

Y28 Y27 W25 Y25

L0_CLKIN_L0 L0_CLKIN_H0 L0_CLKIN_L1 L0_CLKIN_H1

L0_CTLIN_L0 L0_CTLIN_H0 ER94 49.9-1 ER95 49.9-1

R29 T29 R26 R27

L0_CTLIN_L0 L0_CTLIN_H0 L0_CTLIN_L1 L0_CTLIN_H1

VLDT0_B0 VLDT0_B1 VLDT0_B2 VLDT0_B3 VLDT0_B4 VLDT0_B5 VLDT0_B6

AF25 AE28 AF29 AG26 AG28 AH27 AH29

VDD_HT0B_RUN_CLAW

D

L0_CADOUT_L0 L0_CADOUT_H0 L0_CADOUT_L1 L0_CADOUT_H1 L0_CADOUT_L2 L0_CADOUT_H2 L0_CADOUT_L3 L0_CADOUT_H3 L0_CADOUT_L4 L0_CADOUT_H4 L0_CADOUT_L5 L0_CADOUT_H5 L0_CADOUT_L6 L0_CADOUT_H6 L0_CADOUT_L7 L0_CADOUT_H7 L0_CADOUT_L8 L0_CADOUT_H8 L0_CADOUT_L9 L0_CADOUT_H9 L0_CADOUT_L10 L0_CADOUT_H10 L0_CADOUT_L11 L0_CADOUT_H11 L0_CADOUT_L12 L0_CADOUT_H12 L0_CADOUT_L13 L0_CADOUT_H13 L0_CADOUT_L14 L0_CADOUT_H14 L0_CADOUT_L15 L0_CADOUT_H15

F29 E29 F27 F28 H29 G29 H27 H28 K27 K28 M29 L29 M27 M28 P29 N29 E27 E26 F25 E25 G27 G26 H25 G25 K25 J25 L27 L26 M25 L25 N27 N26

L0_CADOUT_L0 L0_CADOUT_H0 L0_CADOUT_L1 L0_CADOUT_H1 L0_CADOUT_L2 L0_CADOUT_H2 L0_CADOUT_L3 L0_CADOUT_H3 L0_CADOUT_L4 L0_CADOUT_H4 L0_CADOUT_L5 L0_CADOUT_H5 L0_CADOUT_L6 L0_CADOUT_H6 L0_CADOUT_L7 L0_CADOUT_H7 L0_CADOUT_L8 L0_CADOUT_H8 L0_CADOUT_L9 L0_CADOUT_H9 L0_CADOUT_L10 L0_CADOUT_H10 L0_CADOUT_L11 L0_CADOUT_H11 L0_CADOUT_L12 L0_CADOUT_H12 L0_CADOUT_L13 L0_CADOUT_H13 L0_CADOUT_L14 L0_CADOUT_H14 L0_CADOUT_L15 L0_CADOUT_H15

L0_CLKOUT_L0 L0_CLKOUT_H0 L0_CLKOUT_L1 HyperTransport L0_CLKOUT_H1 Link0 L0_CTLOUT_L0 L0_CTLOUT_H0 L0_CTLOUT_L1 L0_CTLOUT_H1

K29 J29 J27 J26

L0_CLKOUT_L0 L0_CLKOUT_H0 L0_CLKOUT_L1 L0_CLKOUT_H1

P27 P28 P25 N25

L0_CTLOUT_L0 L0_CTLOUT_H0

9 9 9 9 9 9

L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 L0_CTLIN_H0 L0_CTLIN_L0

9 9 9 9 9 9

L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CTLOUT_H0 L0_CTLOUT_L0

L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 L0_CTLIN_H0 L0_CTLIN_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CTLOUT_H0 L0_CTLOUT_L0

L0_CADIN_L[0..15]

9 L0_CADIN_L[0..15]

L0_CADIN_H[0..15]

9 L0_CADIN_H[0..15]

L0_CADOUT_H[0..15]

9 L0_CADOUT_H[0..15]

L0_CADOUT_L[0..15]

9 L0_CADOUT_L[0..15]

C

VLDT Power Decoupling

ZIF-754P-DRA

Rout with 250 mil trace or a plane

VLDT

In CPU pins rout >100 mil

Put near the VLDT0-A VLDT

BC213

VLDT

BC214

BC215

BC216

B

MC21 10u-10V-08

2

.22u-25VY .22u-25VY .22u-25VY .22u-25VY

1

B

MC22 4.7u-16V-08

Put near the VLDT0-B

BC217

BC218

BC219

VLDT-

BC220 MC23

1

VLDT-

10u-10V-08

2

.22u-25VY.22u-25VY.22u-25VY.22u-25VY

MC24 4.7u-16V-08

A

A

Elitegroup Computer Systems 761GX-M754

Title Size B Date:

Document Number

Rev 1.0

CPU1/HYPER_TRANSPORT Tuesday, October 04, 2005

Sheet

3

of

35

7,8 7,8

MEMCKEA MEMCKEB

MAB[0..13] MEMCHECK[7..0]

7,8 7,8

MEMCKEA MEMCKEB

7,8

7MEMRASA_L

MEMRASA_L MEMCASA_L MEMWEA_L

MEMCASA_L MEMWEA_L MEMBANKA1 MEMBANKA0

6

5

4

MEMBANKA1 MEMBANKA0

MEMDATA0 MEMDATA4 MEMDATA5 MEMDATA1 MEMDATA3 MEMDATA2 MEMDATA6 MEMDATA7 MEMDATA8 MEMDATA12 MEMDATA9 MEMDATA13 MEMDATA14 MEMDATA15 MEMDATA10 MEMDATA11 MEMDATA20 MEMDATA16 MEMDATA17 MEMDATA21 MEMDATA18 MEMDATA22 MEMDATA19 MEMDATA23 MEMDATA24 MEMDATA28 MEMDATA25 MEMDATA29 MEMDATA26 MEMDATA30 MEMDATA27 MEMDATA31 MEMDATA32 MEMDATA36 MEMDATA33 MEMDATA37 MEMDATA34 MEMDATA38 MEMDATA39 MEMDATA35 MEMDATA40 MEMDATA44 MEMDATA45 MEMDATA41 MEMDATA42 MEMDATA43 MEMDATA46 MEMDATA47 MEMDATA54 MEMDATA50 MEMDATA55 MEMDATA51 MEMDATA48 MEMDATA49 MEMDATA52 MEMDATA53 MEMDATA60 MEMDATA56 MEMDATA61 MEMDATA57 MEMDATA62 MEMDATA58 MEMDATA63 MEMDATA59

Routing in the top layer

MAA[0..13]

MAA[0..13]

3

7,8 MEMDATA[63..0]

MEMDATA[63:0] with 5/15 MEMDQS[8:0] with 5/20

A

M3 T4 U5 W5 Y4 AB3 AA5 AD4 AC5 AD5 M4 AF4 AF6 E9 D12 E14

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13

MEMRASA_L MEMCASA_L MEMWEA_L

H5 D4 G5

MEMRASA_L MEMCASA_L MEMWEA_L

MEMBANKA0 MEMBANKA1

H3 K3

MEMBANKA0 MEMBANKA1

MEMRASB_L MEMCASB_L MEMWEB_L

H4 F5 F4

MEMRASB_L MEMCASB_L MEMWEB_L

MEMBANKB0 MEMBANKB1

J5 L5

MEMBANKB0 MEMBANKB1

AE8 AE7

MEMCKEA MEMCKEB

MEMCKEA MEMCKEB MEMZN MEMZP MEMVREF1

D14 C14 AG12

VTT_SENSE

AE13

MEMRESET_L

AG10

7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8

DDRVREF with 40~50 mil, 25 mil clearance or shielded by GND

VCC2.5V_DUAL

ER96

BC221

75-1

.1u-25VY

ER97

BC222

75-1

.1u-25VY 1000P

DDRVREF_CPU BC223

VCC2.5V_DUAL EMI

C349

C350

39P-O

39P-O

1

7,8

MEMCKEA

7,8

MEMCKEB

MEMCKEA MEMCKEB

7,8 7,8 7,8 7,8

MEMRASA_L MEMRASB_L MEMWEA_L MEMWEB_L

7,8

MEMCASB_L

7,8

MEMCASA_L

7,8 7,8 7,8 7,8

MEMBANKB1 MEMBANKA1 MEMBANKA0 MEMBANKB0

MEMRASA_L MEMRASB_L MEMWEA_L MEMWEB_L

MEMZN,MEMZP with 5/10, 125 mil

B

BC242 1000P-O

BC243 100P-O

BC244 1000P-O

BC245 1000P

Size B Date:

Document Number

Rev 1.0

CPU2/DDR Tuesday, October 04, 2005

Sheet

4

of

35

8

7

6

5

4

Max current 105 mA

VCC2.5V

3

Width:50mil and Long:500~750mil

2

1

1 2 MLB-160808-0120A-N2 L59 1 2 MLB-160808-0120A-N2

R788 680

Width:50mil and Long:500mil VDDA1 C351

MC30 4.7u-16V-08

9 32 9

3300P VLDT ER101 ER100

D

LDTREST_ PWRGD_CPU LDTSTOP_L

LDTREST_ PWRGD_CPU LDTSTOP_L

L0_REF1 L0_REF0

1000P

1000P

COREFB_H COREFB_L

Rout with 10/5/10 29 COREFB_H 29 COREFB_L or differential pairs 5/5/5/5/5

BC246 3900P

VDDA1 VDDA2

AF20 AE18 AJ27

RESET_L PWROK LDTSTOP_L

AF27 AE26

L0_REF1 L0_REF0

A23 A24 B23

COREFB_H COREFB_L CORE_SENSE

AE12 AF12 AE11

VDDIOFB_H VDDIOFB_L VDDIO_SENSE

AJ21 AH21

CLKIN_H CLKIN_L

C16 AG15

VTT_A5 VTT_B5

AH17

DBRDY

Rout 5/5/5 mil, Long: