INTELBRAS N6000W - COMPAL LA-3821P JFT00 - REV 0.3
43 Pages • 26,622 Words • PDF • 1.1 MB
Uploaded at 2021-09-24 06:02
This document was submitted by our user and they confirm that they have the consent to share it. Assuming that you are writer or own the copyright of this document, report to us by using this DMCA report button.
A
B
C
D
E
1
1
Compal confidential
2
2
Schematics Document Mobile Merom uFCPGA with Satna Rosa Platform 3
3
2007-07-24 REV:0.3
4
Compal Secret Data 2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. Cover Sheet
Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
4
Sheet
E
1
of
43
A
B
Compal confidential File Name : LA-3821P ZZZ1
C
D
E
Supra 1.0 (Merom +Crestline+ICH8) 12"
PCB 1
1
Mobile Yonah/Merom uFCPGA-478 CPU Socket P
Fan Control page 4
Thermal Sensor ADM1032AR
page 4,5,6
Clock Generator ICS9LPRS355
page 4
page 15
FSB H_A#(3..31)
LVDS Conn
H_D#(0..63)
533/667/800MHz
LED
USB2.0
page 7,8,9,10,11,12
page 28 USB2.0
2
RTC CKT.
USB2.0
page 19
DDR2-SO-DIMM X2 BANK 0, 1, 2, 3
page 13,14
Dual Channel
NB Crestline
page 17
DDR2 -400/533/667
DMI USB2.0
Bluetooth Ver:2.0 page 29 Conn FingerPrinter page 29 Conn PC Camera page 29 Conn Card Reader RTS5158 page 26 USB Conn X 3
2
RJ11CONN page 26
page 29
MDC V1.5
PCI-E BUS
page 26 AC-LINK/Azalia
SB ICH8 Marvall Giga LAN 8055 page 26
AMON Agere CSP1040 page
Audio Realtek ALC268
page 24
Mini-Card WLAN
3
page 22
Mini-Card Robeson page 22
New card
page 18,19,20,21
AMP & Audio Jack TPA6017A2 page 26
SATA
SATA HDD Connector page 23
28
3
page 22 PATA Master
IDE ODD Connector
RJ45CONN
page 22
page 27
LPC BUS
ENE KB926
Power On/Off CKT.
page 30
page 28
4
SPI
page 29
Int.KBD
Touch Pad CONN.
DC/DC Interface CKT.
SPI ROM 25LF080A
page 28
4
page 30
page 31
2006/02/13
Issued Date
Page 32,33,34,35,36,37,38
A
Compal Secret Data
Security Classification
Power Circuit DC/DC
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
C
D
Title
Compal Electronics, Inc. Block Diagram
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet E
2
of
43
5
4
3
2
1
Voltage Rails +5VS +3VS
power plane +B D
+5VALW +3VALW
+1.5VS +1.25VS
+1.8V
+0.9V
State
D
+VCCP +CPU_CORE
S0
O
O
O
O
S1
O
O
O
O
O
O
O
X
S3 S5 S4/AC
O
O
X
X
S5 S4/ Battery only
O
X
X
X
S5 S4/AC & Battery don't exist
X
X
X
X
Symbol Note : : means Digital Ground
: means Analog Ground @ : means just reserve , no build DEBUG@ : means just reserve for debug.
C
C
SMBUS Control Table
B
I2C / SMBUS ADDRESSING
SOURCE
DEVICE
HEX
ADDRESS
DDR SO-DIMM 0
A0
10100000
DDR SO-DIMM 1
A4
10100100
CL OCK GENERATOR (EXT.)
D2
11010010
INVERTER
BATT
SODIMM
CLK CHIP
MINI CARD
LCD
X X
V X
V X
X V
X X
X X
X X
X X
ICH8
X
X
X
X
V
V
V
X
Crestline
X
X
X
X
X
X
X
V
SMB_EC_CK1 SMB_EC_DA1
KB925
SMB_EC_CK2 SMB_EC_DA2
KB925
SMB_CK_CLK1 SMB_CK_DAT1 LCD_CLK LCD_DAT
BOM: 43XXXXXX
om l.c Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Notes List
Size
Document Number
LA-3821P Date:
nf @ ho tm
ai
PJP?
R ev 0.3
ai
Jump-Short:
A
Tuesday, July 31, 2007
he x
A
B
THERMAL SERIAL SENSOR EEPROM (CPU) ADM1032
Sheet
1
3
of
43
5
4
3
2
1
D
D
7/23
+VCCP
H_STPCLK# H_INTR H_NMI H_SMI#
H_STPCLK# H_INTR H_NMI H_SMI#
D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6
B
A20M# FERR# IGNNE#
G6 E4
H_HIT# H_HITM#
BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
H_BR0# H_INIT#
R10 56_0402_5% 2 1
7
+VCCP
19 C2
H_LOCK# 7
PROCHOT# THERMDA THERMDC THERMTRIP#
D21 A24 B25
54.9_0402_1%
2
54.9_0402_1%
XDP_TRST#
R7
1
2
51_0402_1%
XDP_TCK
R8
1
2
1
54.9_0402_1%
0.1U_0402_16V4Z 2
H_RESET# 7 H_RS#0 7 H_RS#1 7 H_RS#2 7 H_TRDY# 7 H_HIT# 7 H_HITM# 7
EMI request 4/18
C
Thermal Sensor ADM1032ARMZ +3VS XDP_TCK XDP_TDI 0.1U_0402_16V4Z XDP_DBRESET# 20
U1 1
+VCCP
H_THERMDA_R1 R14 H_THERMDC_R1 R15
2 0_0402_5% 2 0_0402_5%
H_THERMDA H_THERMDC
1
2
H_THERMTRIP# 7,19 1
+3VS CLK_CPU_BCLK CLK_CPU_BCLK#
THERM#
4
SDATA
D-
ALERT#
THERM#
GND
8
SMB_EC_CK2
7
SMB_EC_DA2
6 5
ADM1032ARMZ-2REEL_MSOP8
2
Address:100_1100
SMB_EC_DA2 SMB_EC_CK2
30,32 SMB_EC_DA2 30,32 SMB_EC_CK2
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
B
For Merom, R14 and R15 are 0ohm For Penryn, R14 and R15 are 100ohm.
+5VS
Voltage Fan Control circuit +5VS 1
2 1
+VCC_FAN
E
1
C
20 2
A
C13
EN_FAN
1000P_0402_50V7K
32
1 2 3 4
VEN VIN VO VSET
GND GND GND GND
8 7 6 5
G993P1UF_SOP8
D2
1
2
C5
1
C6
2
+VCC_FAN FAN_SPEED
1 2 3 4 5
1 2 3 GND GND
ACES_85205-03001
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
JP3
U24
1
FAN_SPEED
2 4.7U_0805_10V4Z
B
2 2
32 FAN_SPEED
D1 1SS355_SOD323-2
C12
+3VS
@ 56_0402_5%
5
SCLK
D+
CLK_CPU_BCLK 15 CLK_CPU_BCLK# 15
R17 10K_0402_5%
OCP#
3
10K_0402_5% A22 A21
SP07000FP00 S SOCKET TYCO 2-1871873-2 478P H3 CPU SP07000FD00 S SOCKET FOXCONN PZ4782A-274M-41 478P H3
3 1 OCP# @ Q2 MMBT3904_SOT23
H_THERMDC
VDD
R16
R18
H_PROCHOT#
2
C4
Merom Ball-out Rev 1a CONN@ +VCCP
H_THERMDA
2200P_0402_50V7K
H CLK BCLK[0] BCLK[1]
1
H_PROCHOT#
2 1 68_0402_5%
H_THERMTRIP#
C7
2
C3 XDP_TMS XDP_TRST# XDP_DBRESET# H_PROCHOT#
THERMAL
2
1
H_DEFER# 7 H_DRDY# 7 H_DBSY# 7
R13
STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]
RESET# RS[0]# RS[1]# RS[2]# TRDY#
H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY#
1
R3
1000P_0402_50V7K
A6 A5 C4
H_LOCK#
C1 F3 F4 G3 G2
R2
XDP_TMS
4.7U_0805_10V4Z
19 19 19 19
H_A20M# H_FERR# H_IGNNE#
H_IERR# H_INIT#
XDP_TDI
1
H_A20M# H_FERR# H_IGNNE#
H_BR0#
D20 B3
H_ADS# 7 H_BNR# 7 H_BPRI# 7
2
19 19 19
F1
H4
HIT# HITM#
A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
H5 F21 E1
H_DEFER# H_DRD Y# H_DBSY#
LOCK#
ICH
H_ADSTB#1
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#
ADDR GROUP 1
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1
C
7
K3 H2 K2 J3 L1
BR0# IERR# INIT#
H_ADS# H_BNR# H_BPRI#
1
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
DEFER# DRDY# DBSY#
H1 E2 G5
2
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17..35]
ADS# BNR# BPRI#
CONTROL
7 7 7 7 7 7
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
XDP/ITP SIGNALS
H_ADSTB#0
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
ADDR GROUP 0
7
JP2A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0
BAS16_SOT23-3
H_A#[3..16]
RESERVED
7
3
2
Title
Compal Electronics, Inc. Merom(1/3)-AGTL+/XDP
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet 1
4
of
43
4
3
2
1
+VCC_CORE
R21 R22
AD26 C23 D25 C24 AF26 AF1 A26
C8
H_DSTBN#1 H_DSTBP#1 H_DINV#1 2 @ 1K_0402_5% 2 @ 1K_0402_5%
1 1 1
15 15 15
2
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
B22 B23 C21
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3
COMP[0] COMP[1] COMP[2] COMP[3]
R26 U26 AA1 Y1
COMP0 COMP1 COMP2 COMP3
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
E5 B5 D24 D6 D7 AE6
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI#
MISC
BSEL[0] BSEL[1] BSEL[2]
Merom Ball-out Rev 1a CONN@
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
B
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
166
0
1
1
200
0
1
0
H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7
H_DPRSTP# 7,19,39 H_DPSLP# 19 H_DPWR# 7 H_PWRGOOD 19 H_CPUSLP# 7 H_PSI# 39
Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
D
+VCCP R19 2 2 R20
0_0402_5% 1 1 0_0402_5% 1 + 2
330U_D2E_2.5VM_R7
B26 C26
VCCA[01] VCCA[02]
AD6 AF5 AE5 AF4 AE3 AF3 AE2
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
VCCSENSE
AF7
VCCSENSE
VSSSENSE
AE7
VSSSENSE
Merom Ball-out Rev 1a CONN@
C
C7
39 39 39 39 39 39 39
1
2
VCCSENSE 39
1
2
+1.5VS
0.01U_0402_16V7K
7 7 7
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
C9
V_CPU_GTLREF TEST1 TEST2 TEST3 T1 TEST4 @ 0.1U_0402_16V4Z TEST5 T2 TEST6 T3
C
D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#
H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7 H_D#[48..63] 7
R26 27.4_0402_1% 2 1
D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
JP2C
R25 54.9_0402_1% 2 1
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2
DATA GRP 2
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16..31]
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
R24 27.4_0402_1% 2 1
7 7 7 7
DATA GRP 1
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#
DATA GRP 0
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
D
+VCC_CORE
H_D#[32..47] 7
JP2B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0
R23 54.9_0402_1% 2 1
H_D#[0..15]
DATA GRP 3
7
10U_0805_6.3V6M C10
5
Near pin B26
VSSSENSE 39 B
.
Length match within 25 mils. The trace width/space/other is 20/7/25.
1
+VCCP
R28 1K_0402_1% 2
+VCC_CORE R29 100_0402_1% 2
VCCSENSE
R31 100_0402_1% 1 2
VSSSENSE
1
1
V_CPU_GTLREF
2
R30 2K_0402_1%
Close to CPU pin AD26 within 500mils.
Close to CPU pin within 500mils. A
Compal Secret Data 2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Merom(2/3)-AGTL+/PWR
Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
A
Sheet
1
5
of
43
5
4
3
2
1
D
D
JP2D
C
B
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
Near CPU CORE regulator
Proadlizer
+VCC_CORE
+VCC_CORE
1 2 C43 @ 330U_D2E_2.5VM_R7
1
1
+
+
2
2
07/23
C
+ C44 @ 330U_D2E_2.5VM_R7
C11 1200P_PFAF250E128MNTTE_2.5VM
3 4
EMI solution
B
Place these inside socket cavity on L8 (North side Secondary) +VCCP
Merom Ball-out Rev 1a .
1
2
1
C48 0.1U_0402_16V4Z
2
C49 0.1U_0402_16V4Z
1
2
C50 0.1U_0402_16V4Z
1
2
1
C51 0.1U_0402_16V4Z
2
1
C52 0.1U_0402_16V4Z
2
C53 0.1U_0402_16V4Z
A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Merom(3/3)-GND&Bypass
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet 1
6
of
43
5 5 5 5
H_RS#0 H_RS#1 H_RS#2
4 4 4
BL15 BK14
SM_RCOMP_VOH SM_RCOMP_VOL
BK31 BL31
SMRCOMP_VOH SMRCOMP_VOL
SM_VREF_0 SM_VREF_1
AR49 AW4
1
10K_0402_5%
1
MUXING DDR
2 1 2
C57
2
CLK
PM_EXTTS#1
R39 CLKREQ#_B
2
T4 T5 T6 T7 T8 T9 T10 T11 T12
C FG5 C FG6 C FG7 C FG8 C FG9 CFG10 CFG11 CFG12 CFG13
T13
CFG16
T14 T15 T16
CFG18 CFG19 CFG20
20 PM_BMBUSY# 5,19,39 H_DPRSTP# 13 PM_EXTTS#0 14 PM_EXTTS#1 20,32 PM_PWROK 18,22,23,24 PLT_RST# 4,19 H_THERMTRIP# 20,39 DPRSLPVR
P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35
PM_BMBUSY# G41 H_DPRSTP# L39 PM_EXTTS#0 L36 PM_EXTTS#1 J36 PM_PWROK AW49 PLT_RST# AV20 H_THERMTRIP# N20 DPRSLPVR G36
BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2
1
+1.8V
2
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16
R35
+1.8V 20_0402_1% 1 1 20_0402_1%
2 2
R36
V_DDR_MCH_REF
CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK#
K44 K45
CLK_MCH_3GPLL CLK_MCH_3GPLL#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
AN47 AJ38 AN42 AN46
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
AM47 AJ39 AN41 AN45
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
AJ46 AJ41 AM40 AM44
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
AJ47 AJ42 AM39 AM43
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN
CLK_MCH_DREFCLK 15 CLK_MCH_DREFCLK# 15 MCH_SSCDREFCLK 15 MCH_SSCDREFCLK# 15 CLK_MCH_3GPLL 15 CLK_MCH_3GPLL# 15
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
20 20 20 20
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
20 20 20 20
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
20 20 20 20
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
20 20 20 20
T17 T18 T19 T20 T21
E35 A39 C38 B39 E36
B
+1.25VM_AXD
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
CL_CLK0 CL_DATA0 M_PWROK CL_RST# CL_VREF
AM49 AK50 AT43 AN49 AM50
CL_CLK0 20 CL_DATA0 20 M_PWROK 20,32 CL_RST# 20 CL_VREF 0.1U_0402_16V4Z 1
SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2
2
H35 K36 G39 G40
CLKREQ#_B M CH_ICH_SYNC#
R48
CLKREQ#_B 15 MCH_ICH_SYNC# 20
R49 0_0402_5%
A
ai
l.c
2
2
1K_0402_1%
A37 R32
CRESTLINE_1p0
@ R47 1K_0402_1%
R42
R43 392_0402_1%
C58
20K_0402_5% 2
13 13 14 14
C
10K_0402_5%
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
13 13 14 14
M_ODT0 M_ODT1 M_ODT2 M_ODT3
B42 C42 H48 H47
PEG_CLK PEG_CLK#
1
1
V_DDR_MCH_REF C59 0.1U_0402_16V4Z
0.1U_0402_16V4Z C61
1 R46
221_0603_1%
2 1 R52 2
100_0402_1%
R51 24.9_0402_1% 2 1
C60
1 R45
1K_0402_1%
2 1 R50 2
2K_0402_1%
13,14,37 V_DDR_MCH_REF
2
SM_RCOMP SM_RCOMP#
SMRCOMP SMRCOMP#
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
NC
5
C56
R38
@ R44 1K_0402_1%
1
M_ODT0 M_ODT1 M_ODT2 M_ODT3
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
D
om
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.
H_SWNG
BH18 BJ15 BJ14 BE16
SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3
13 13 14 14
1
5 5 5 5
4 4 4 4 4
1
10K_0402_5%
15 MCH_CLKSEL0 15 MCH_CLKSEL1 15 MCH_CLKSEL2
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
2
PM
within 100 mils from NB
1K_0402_1%
R37 PM_EXTTS#0
5 5 5 5
+VCCP
2
2
R34
RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45
SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3
DMI
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
+VCCP
1
2
1
+3VS
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
H_RCOMP
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
1 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 15 CLK_MCH_BCLK# 15 H_DPWR# 5 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4
CRESTLINE_1p0
0.1U_0402_16V4Z H_VREF
H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34
13 DDR_A_MA14 14 DDR_B_MA14
layout note:
A
1
0.01U_0402_16V7K
SMRCOMP_VOL
H_AVREF H_DVREF
Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20
BG20 BK16 BG16 BE13
R33 3.01K_0402_1% NA lead free
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
2
H_RS#0 H_RS#1 H_RS#2
1
E12 D7 D8
2
H_RS#_0 H_RS#_1 H_RS#_2
C55
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
2.2U_0805_16V4Z C54
M14 E13 A11 H13 B12
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
13 13 14 14
1
H_VREF
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
BE29 AY32 BD39 BG37
SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
2
H_SWING H_RCOMP
B
B9 A9
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Near B3 pin 4
3
2
Title
nf @ ho tm
H_CPURST# H_CPUSLP#
L7 K2 AC2 AJ10
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
AW30 BA23 AW25 AW23
13 13 14 14
Compal Electronics, Inc.
CRESTLINE(1/6)-AGTL+/DMI/DDR2 Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
B6 E5
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
Tuesday, July 31, 2007
he x
H_RESET# H_CPUSLP#
M7 K3 AD2 AH11
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
1K_0402_1%
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
1
H_SCOMP H_SCOMP#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
SMRCOMP_VOH
R32
AV29 BB23 BA25 AV23
2
W1 W2
K5 L2 AD13 AE13
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
1
+1.8V
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4
1
B3 C2
H_SCOMP H_SCOMP#
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRD Y# H_HIT# H_HITM# H_LOCK# H_TRDY#
1
2
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14
GRAPHICS VID
R41 54.9_0402_1% 2 1 H_RESET# H_CPUSLP#
H_SWNG H_RCOMP
G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
2
P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20
CFG
R40 54.9_0402_1% 2 1
+VCCP
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
ME
C
J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
1
For Crestline: 20ohm For Calero: 80.6ohm
RSVD
D
E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13
2.2U_0805_16V4Z
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
2
U3B
0.01U_0402_16V7K
U3A
H_D#[0..63]
4 5
3
H_A#[3..35] 4
HOST
5
4
MISC
5
Sheet
1
7
of
43
5
4
3
2
1
D
D
14 DDR_B_D[0..63]
B
DDR_A_BS0 DDR_A_BS1 DDR_A_BS2
SA_CAS#
BL17
DDR_A_CAS#
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13
BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13
SA_RAS# SA_RCVEN#
BE18 AY20
DDR_A_RAS# SA_RCVEN#
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
SA_WE#
BA19
DDR_A_WE#
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_A_BS0 13 DDR_A_BS1 13 DDR_A_BS2 13 DDR_A_CAS# 13 DDR_A_DM[0..7] 13
DDR_A_DQS[0..7] 13
DDR_A_DQS#[0..7] 13
DDR_A_MA[0..13] 13
DDR_A_RAS# 13 T23 DDR_A_WE# 13
AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2
CRESTLINE_1p0
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
B
BB19 BK19 BF29
MEMORY
SA_BS_0 SA_BS_1 SA_BS_2
U3E
SYSTEM
MEMORY
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SYSTEM
C
AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11
DDR
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
A
U3D
DDR
13 DDR_A_D[0..63]
SB_BS_0 SB_BS_1 SB_BS_2
AY17 BG18 BG36
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
SB_CAS#
BE17
DDR_B_CAS#
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_RAS# SB_RCVEN# SB_WE#
AV16 AY18
DDR_B_RAS# SB_RCVEN#
BC17
DDR_B_WE#
DDR_B_BS0 14 DDR_B_BS1 14 DDR_B_BS2 14 DDR_B_CAS# 14 DDR_B_DM[0..7] 14
DDR_B_DQS[0..7] 14
DDR_B_DQS#[0..7] 14
C
DDR_B_MA[0..13] 14
DDR_B_RAS# 14 T22 DDR_B_WE# 14
B
CRESTLINE_1p0
A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. CRESTLINE((2/6)-DDR2 A/B CH
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet 1
8
of
43
5
4
3
2
1
Strap Pin Table 010 = FSB 800MHz CFG[2:0] FSB Freq select
011 = FSB 667MHz Others = Reserved
17,32
For Crestline:2.4kohm For Calero: 1.5Kohm
BKLT_CTRL
T49 ENABLT R54 1 R55 1 LCD_CLK LCD_DATA ENAVDD
ENABLT +3VS
17 LCD_CLK 17 LCD_DATA 17 ENAVDD
1 2.4K_0402_1%
17 17
LVDSACLVDSAC+
17 17 17
LVDSA0LVDSA1LVDSA2-
17 17 17
LVDSA0+ LVDSA1+ LVDSA2+
J40 H39 E39 E40 C37 D35 K40 L41 L43 N41 N40 D46 C45 D44 E42
LVDSACLVDSAC+
LVDSA0LVDSA1LVDSA2-
G51 E51 F49
LVDSA0+ LVDSA1+ LVDSA2+
G50 E50 F48 G44 B47 B45
C
E44 A47 A45
5/03
1 1 1
150_0402_5% E27 150_0402_5% G27 150_0402_5% K27 F27 J27 L27
R57
+3VS
CRT_B
16
CRT_G
16
CRT_R
16 16 16
3VDDCCL 3VDDCDA CRT_HSYNC
16
CRT_VSYNC
CRT_B
H32 G32 K29 J29 F29 E29
CRT_G CRT_R
3VDDCCL 3VDDCDA CR T_HSYNC
K33 G35 F33 C32 E33
CRT_VSYNC
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2
TVA_DAC TVB_DAC TVC_DAC TVA_RTN TVB_RTN TVC_RTN TV_DCONSEL_0 TV_DCONSEL_1
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
1
16
M35 P33
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2
2
1.3K_0402_1%
R58
VGA
B
2.2K_0402_5% 1 2
LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
PEG_COMPI PEG_COMPO
TV
R247 2 R355 2 R358 2
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN
LVDS
2 R56
2 10K_0402_5% 2 10K_0402_5%
0 = DMI x 2
CFG5 (DMI select)
U3C
GRAPHICS
0312_Add test point.
PCI-EXPRESS
D
N43 M43
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
PEGCOMP
R53 24.9_0402_1% 1 2
D
1 = DMI x 4
*
+VCCP
CFG6
PEGCOMP trace width and spacing is 20/25 mils.
Reserved 0 = Reserved
CFG7 (CPU Strap)
1 = Mobile CPU CFG8 (Low power PCIE) CFG9
*
0 = Normal mode 1 = Low Power mode
*
0 = Reverse Lane
(PCIE Graphics Lane Reversal) CFG[11:10]
1 = Normal Operation
*
Reserved 00 01 10 11
CFG[13:12] (XOR/ALLZ)
CFG[15:14]
= Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation (Default)
* C
Reserved
CFG16 (FSB Dynamic ODT)
0 = Disabled 1 = Enabled
CFG[18:17]
*
Reserved 0 = No SDVO Device Present
SDVO_CTRLDATA
1 = SDVO Device Present
CFG19 (DMI Lane Reversal)
0 = Normal Operation (Lane number in Order)
*
*
1 = Reverse Lane CFG20 (PCIE/SDVO concurrent)
0 = Only PCIE or SDVO is operational.
*
1 = PCIE/SDVO are operating simu.
CFG[17:3] have internal pull up CFG[19:18] have internal pull down
B
CRESTLINE_1p0
For Crestline:1.3kohm For Calero: 255ohm
A
Compal Secret Data 2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc.
CRESTLINE((3/6)-VGA/LVDS/TV Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
A
Sheet
1
9
of
43
5
4
VCC SYNC
+3VS
2
2
2 1U_0603_10V4Z
N28
+1.5VS_QDAC
250mA 100mA
VCC_TX_LVDS
A PEG
C70
+3VS_HV
VCC_HV_1 VCC_HV_2
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
VCC_RXR_DMI_1 VCC_RXR_DMI_2
AD51 1200mA W50 W51 V49 V50
1450mA +VCC_PEG
AH50 250mA AH51
1
2
+
2
@
1
2
2
2
2 1 MBK2012121YZF_0805
+1.25VS
10U_FLC-453232-100K_0.25A_10% C95 0.1U_0402_16V4Z
1
1
2
2
+VCCP
+1.25VM_MPLL
+VCC_PEG
20mils
R74
1 +
2
1
2
2
2 1 MBK2012121YZF_0805
10U_0805_10V4Z
2
1
C103
2
1
+1.25VS
R73
2 1 0_0805_5%
1
C96 10U_0805_10V4Z
0.1U_0402_16V4Z
A7 F2 AH1
CRESTLINE_1p0
1
C92
1
+1.25VS
R71
R 70
1
C102 220U_6.3V_M
VTTLF1 VTTLF2 VTTLF3
100mA
C40 B40
0.47U_0603_10V7K C108
C110
2
+1.25VM_HPLL
+1.8V_TXLVDS
0.47U_0603_10V7K C107
+3VS BLM18PG181SN1D_0603 2 1 R 75
VCCD_LVDS_1 VCCD_LVDS_2
2
C
+1.25VS_DPLLA
A43
0.1U_0402_16V4Z
C109 0.022U_0402_16V7K
2
VCCD_PEG_PLL
J41 H42
2
1
+1.8V_SM_CK
0.47U_0603_10V7K C106
150mA
1
VCCD_HPLL
U48
+1.8V_LVDS
1
VCCD_QDAC
AN2
+1.25VS_PEGPLL
+3VS_TVDACC
VCCD_CRT VCCD_TVDAC
1
+1.5VS R68 1 2 0_0805_5%
120mA
100mA
D TV/CRT
75mA 50mAM32 25mAL29 5mA
2
+1.5VS_TVDAC
2
10U_0805_10V4Z
40mA
+3VS_TVDACC
VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2
2
1
C94
40mA
+3VS_TVDACB
+1.25VM_HPLL
VCCA_SM_CK_1 VCCA_SM_CK_2
C25 B25 C27 B27 B28 A28
BK24 BK23 BJ24 BJ23
1
C93
40mA +3VS_TVDACA
+1.5VS_TVDAC_R
4/20
BC29 BB29
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
C101
2
2 1 0_0603_5%
Reserv resister
B
VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2
+1.25VS_DMI
0.1U_0402_16V4Z
C100
2
1
0.1U_0402_16V4Z
C99
2
1
1U_0603_10V4Z
1
R450 +1.5VS_TVDAC
AT22 AT21 AT19 AT18 AT17 AR17 AR16
C 91
100mA 10U_0805_10V4Z
2
C98
C97
1
1U_0603_10V4Z
2 1 0_0603_5%
1
VTTLF
10U_0805_10V4Z 4.7U_0805_10V4Z 2 2 +1.25VM_A_SM_CK
1
+1.25VS L1 BLM18PG121SN1D_0603 2 1
150U_B_6.3VM_R40M
R72
C90
LVDS
220U_6.3V_M
C 89
SM CK
1
+1.25VS_PEGPLL
100mA
AJ50
1
+1.25VS
+V1.25VS_AXF
VCC_DMI
HV
1 2 0_0805_5%
POWER
B23 B21 A21
R65 1 2 0_0805_5%
0.1U_0402_16V4Z
1 C88 +
350mA VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
+1.8V
2
C86
+1.25VS
2
2
1
C87 0.022U_0402_16V7K
C
VCC_AXD_NCTF
2
1
C85
950mA
VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5
1
R64 0_0603_5%
C84
+1.25VM_A_SM R69
VCCA_PEG_PLL
AW18 AV19 AU19 AU18 AU17
AR29
R66 1 2 0_0805_5%
1
2
10U_0805_10V4Z
2
U51
AT23 AU28 AU24 AT29 AT25 AT30
0.1U_0402_16V4Z
+1.25VS_PEGPLL 20 mils
VSSA_PEG_BG
1
10U_0805_10V4Z
C83
K49
1
200mA VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6
C82
0.1U_0402_16V4Z
VCCA_PEG_BG
2
2
C81
K50
2
+1.8V_SM_CK
+1.25VS
1
+1.25VM_AXD
1U_0603_10V4Z
5mA
AXD
+3VS_PEG_BG R67 2 1 0_0603_5%
+3VS
AXF
VSSA_LVDS
2
C75
VTT PLL
VCCA_LVDS
B41
PEG
A41
1
C80
DMI
1000P_0402_50V7K
A LVDS
+1.8V_TXLVDS
A SM
10mA
2
C74
VCCA_MPLL
C73
CRT
VCCA_HPLL
AM2
150mA
R62 0_0603_5%
C78
AL2
+1.25VM_MPLL
1
0.1U_0402_16V4Z
+1.25VM_HPLL
2
C77
2
1
C76
VCCA_DPLLB
50mA
+1.25VS_DMI
1
10U_0805_10V4Z
VCCA_DPLLA
H49
80mA
10U_0805_10V4Z
B49
+1.25VS_DPLLB
2
1
2
D
0.1U_0402_16V4Z C79
+1.25VS_DPLLA
2
2.2U_0805_16V4Z
VSSA_DAC_BG
2 2
4.7U_0805_10V4Z
B32
1
+
0.47U_0603_10V7K
2
VCCA_DAC_BG
80mA
0.1U_0402_16V4Z
1 C72
C71 0.022U_0402_16V7K
1
A30
+3VS_DAC_BG
+3VS BLM18PG181SN1D_0603 2 1 R 63
1
1
1
C68
+3VS_DAC_CRT
C 69
10U_FLC-453232-100K_0.25A_10%
1
C67
VCCA_CRT_DAC_1 VCCA_CRT_DAC_2
1
+1.25VS
C66
+3VS_DAC_CRT
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1
C65
7/25
A33 B33
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22
4.7U_0805_10V4Z
C64
80mA
330U_D2E_2.5VM_R7
VCCSYNC
2
1U_0603_10V4Z
U 3H
J32
+1.25VS
+V1.25VS_AXF
R61
1
10U_0805_10V4Z
2
+1.25VS_DPLLB
5mA D
1
+VCCP
850mA
10U_0805_10V4Z
2
1 C62
0.1U_0402_16V4Z
2
2
R 59 2 1 0_0603_5%
A CK
1
3
10mA 0.1U_0402_16V4Z
1
1U_0603_10V4Z
2
0.1U_0402_16V4Z
C63 0.022U_0402_16V7K
1
+3VS BLM18PG181SN1D_0603 2 1 R 60 C508
TV
+3VS_DAC_BG
C104 0.1U_0402_16V4Z
1
1
2
2
C105 10U_0805_10V4Z
B
+VCCP_D
D3
+VCCP
2
R 76 2 1 10_0402_5% CH751H-40PT_SOD323-2
1
R77 2 1 0_0402_5%
+3VS_HV
+3VS +1.5VS_QDAC +3VS_TVDACA
2 1 100_0603_1% 1 C112
2
1
2
0.1U_0402_16V4Z
2
+1.5VS R78
C111 0.022U_0402_16V7K
C114
2
1
0.1U_0402_16V4Z
C113 0.022U_0402_16V7K
1
+3VS BLM18PG181SN1D_0603 2 1 R 79
+1.8V_TXLVDS R 80
2 1 0_0603_5% C115 1000P_0402_50V7K
1
1
2
2
+1.8V
C116 10U_0805_10V4Z
0208_Change C117 value from 220uF to 10uF. +1.8V_LVDS A
+3VS_TVDACB
2 1 0_0603_5% 1
2
C118 1U_0603_10V4Z
2
A
R 82 C117 10U_0805_10V4Z
C120
2
1
0.1U_0402_16V4Z
C119 0.022U_0402_16V7K
1
+3VS BLM18PG181SN1D_0603 2 1 R 81
+1.8V
1
2
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. CRESTLINE(4/6)-PWR
Size Document Number C ustom LA-38 21P D ate:
Rev 0.3
T u es d ay , J u l y 3 1 , 2 0 07
Sheet 1
10
of
43
5
4
3
2
1
+VCCP +VCCP
U3G
VCC_AXG=7700mA
VCC=1260mA
U3F
2
2
1
VCC AXM VCC AXM NCTF
VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19
A3 B2 C1 BL1 BL51 A51
VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7
AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
+VCCP
VCC_AXG=7700mA +VCCP 0.1U_0402_16V4Z
10U_0805_10V4Z 1 C136
1
C135
+
C137
1
1 C138
1U_0603_10V4Z
2
2
2
330U_D2E_2.5VM_R7
1 C139
2 10U_0805_10V4Z
CRESTLINE_1p0
2
0.1U_0402_16V4Z 1 C121
1
2
2
C122
1
C123 D
2 4.7U_0805_10V4Z
0.22U_0603_10V7K
C
B
1
1
2
1
2
1
2
1
2
A
om
2
C151 1U_0603_10V4Z
2
C150 1U_0603_10V4Z
A
1
C149 0.47U_0603_10V7K
2
C148 0.22U_0603_10V7K
AW45VCCSM_LF1 BC39 VCCSM_LF2 BE39 VCCSM_LF3 BD17 VCCSM_LF4 BD4 VCCSM_LF5 AW8 VCCSM_LF6 AT6 VCCSM_LF7 1
C147 0.22U_0603_10V7K
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
C146 0.1U_0402_16V4Z
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83
C145 0.1U_0402_16V4Z
R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14
VCC GFX NCTF
2
1
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36
VCC SM
1
C132
+
0.01U_0402_16V7K C131
AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33
1 C129 330U_4V_M
10U_0805_10V4Z C130
2
C144 0.1U_0402_16V4Z
2
1
2
C134
2
1
C143 0.1U_0402_16V4Z
Compal Secret Data 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc.
CRESTLINE((5/6)-PWR/GND Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
Security Classification
nf @ ho tm
ai
l.c
CRESTLINE_1p0
Tuesday, July 31, 2007
he x
2
1
C142 0.1U_0402_16V4Z
1
C141 0.22U_0402_10V4Z
2
C140 0.22U_0402_10V4Z
1
2
10U_0805_10V4Z C133
10U_0805_10V4Z
B
1
+1.8V
VCC_AXM=970mA
VCC_AXM=970mA
VCC_13
POWER
POWER VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6
R30
AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30
3720mA
2
+VCCP
1
R83 1 2 0_0603_5%
10U_0805_10V4Z
C
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
VCC GFX
2
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
VSS SCB
2
1
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50
VCC NCTF
2
1
C128
2
1
0.1U_0402_16V4Z C127
2
1
0.22U_0603_10V7K C126
C124
0.22U_0402_10V4Z C125
+
10U_0805_10V4Z
220U_D2_2.5VM
1
AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37
VSS NCTF
VCC=1260mA
VCC CORE
+VCCP D
VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12
VCC SM LF
AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32
Sheet
1
11
of
43
5
4
3
2
1
U3I A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16
D
C
B
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99
VSS
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
U3J C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39
VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243
K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3
VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286
VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305
W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28
VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
D
C
VSS
B
CRESTLINE_1p0
CRESTLINE_1p0 A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. CRESTLINE((6/6)-PWR/GND
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet 1
12
of
43
5
4
3
2
1
+1.8V
+1.8V V_DDR_MCH_REF
8 DDR_A_DQS#[0..7]
DDR_A_D2 DDR_A_D3
D
DDR_A_D8 DDR_A_D14
Layout Note: Place near JP34
DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D9 DDR_A_D15
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
V_DDR_MCH_REF 7,14,37
DDR_A_D6 DDR_A_D0 DDR_A_DM0 DDR_A_D5 DDR_A_D7
1
2
1
C153
DDR_A_DQS#0 DDR_A_DQS0
7,8 DDR_A_MA[0..14]
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
0.1U_0402_16V4Z
DDR_A_D4 DDR_A_D1
8 DDR_A_DQS[0..7]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
C152
8 DDR_A_DM[0..7]
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2.2U_0805_16V4Z
JP4
8 DDR_A_D[0..63]
2
D
DDR_A_D13 DDR_A_D12 DDR_A_DM1 M_CLK_DDR0 M_CLK_DDR#0
M_CLK_DDR0 7 M_CLK_DDR#0 7
DDR_A_D11 DDR_A_D10
+1.8V
DDR_A_DM3 DDR_A_D26 DDR_A_D27 DDR_CKE0_DIMMA
8
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
8 8
+0.9V
DDR_A_MA10 DDR_A_BS0 DDR_A_WE#
DDR_A_BS0 DDR_A_WE#
DDR_A_CAS# DDR_CS1_DIMMA#
8 DDR_A_CAS# 7 DDR_CS1_DIMMA#
2
1
2
M_ODT1
M_ODT1
1
DDR_A_D37 DDR_A_D36
2
DDR_A_DQS#4 DDR_A_DQS4
C176
C175
C174
C173
C172
C171
C170
C169
C168
C167
C166
C165
C164
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
7
DDR_A_D35 DDR_A_D32 DDR_A_D40 DDR_A_D44
B
DDR_A_DM5 DDR_A_D41 DDR_A_D46 DDR_A_D49 DDR_A_D48 +0.9V
1 2 RP3
4 3
4 3
56_0404_4P2R_5% RP4 1 4 4 2 3 3
56_0404_4P2R_5% 1 DDR_A_MA7 2 DDR_A_MA6
56_0404_4P2R_5% RP6 DDR_A_RAS# 1 4 4 DDR_CS0_DIMMA# 2 3 3
56_0404_4P2R_5% 1 DDR_A_MA12 2 DDR_A_MA9
DDR_A_MA8 DDR_A_MA5 RP5
RP7 DDR_A_MA1 DDR_A_BS0
1 2
56_0404_4P2R_5% RP8 4 4 3 3
1 2
56_0404_4P2R_5% RP10 56_0404_4P2R_5% 4 4 1 DDR_A_MA0 3 3 2 DDR_A_BS1
RP9 DDR_A_WE# DDR_A_CAS# A
Layout Note: Place t hes e resistor closely JP34,all trace length Max=1.5"
56_0404_4P2R_5% 1 DDR_CKE0_DIMMA 2 DDR_A_BS2
DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D54 DDR_A_D50 DDR_A_D61 DDR_A_D60 DDR_A_DM7 DDR_A_D59 DDR_A_D58
56_0404_4P2R_5% 1 DDR_A_MA4 2 DDR_A_MA2
+3VS
RP11 56_0404_4P2R_5% RP12 56_0404_4P2R_5% DDR_CS1_DIMMA# 2 3 4 1 M_ODT0 M_ODT1 1 4 3 2 DDR_A_MA13 56_0404_4P2R_5% RP13 56_0404_4P2R_5% 4 1 DDR_CKE1_DIMMA 1 2 3 2 DDR_A_MA14
DDR_A_MA11 R86
CLK_SMBDATA CLK_SMBCLK
14,15 CLK_SMBDATA 14,15 CLK_SMBCLK
1
C178
2
2006/02/13
Issued Date
2
FOX_ASOA426-M4R-TR CONN@
SO-DIMM A
DDR_A_D31 DDR_A_D30 DDR_CKE1_DIMMA
DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 DDR_A_MA13
4
3
DDR_A_BS1 8 DDR_A_RAS# 8 DDR_CS0_DIMMA# 7 M_ODT0
7
DDR_A_D39 DDR_A_D38 DDR_A_DM4 DDR_A_D34 DDR_A_D33 DDR_A_D45 DDR_A_D43 B
DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D47 DDR_A_D42 DDR_A_D52 DDR_A_D53 M_CLK_DDR1 M_CLK_DDR#1
M_CLK_DDR1 7 M_CLK_DDR#1 7
DDR_A_DM6 DDR_A_D51 DDR_A_D55 DDR_A_D57 DDR_A_D56 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63
A
SP07F001720 S SOCKET FOXCONN AS0A426-N4RN-7F DR2R H4 FOX_AS0A426-M4R-TR_200P
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
C
DDR_CKE1_DIMMA 7
DDR_A_MA14
Compal Secret Data
Security Classification
56_0402_5%
1
C177
0.1U_0402_16V4Z
DDR_A_MA3 DDR_A_MA10
RP2
2.2U_0805_16V4Z
RP1
DDR_A_DQS#3 DDR_A_DQS3
ai
7 DDR_CKE0_DIMMA
DDR_A_D28 DDR_A_D25
2
Title
nf @ ho tm
C
DDR_A_D23 DDR_A_D22
om
DDR_A_D29 DDR_A_D24
PM_EXTTS#0 7
DDR_A_DM2
l.c
DDR_A_D18 DDR_A_D19
DDR_A_D20 DDR_A_D21
Compal Electronics, Inc. DDRII-SODIMM SLOT1
Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
C154 330U_4V_M 2
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204
Tuesday, July 31, 2007
he x
+
2
DDR_A_DQS#2 DDR_A_DQS2
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND
R85 10K_0402_5% 2 1
2
1
C163
C162
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C161
0.1U_0402_16V4Z
2
1
C160
C159
2
1
0.1U_0402_16V4Z
C158
2
1
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
C157
2
2.2U_0805_16V4Z
2
1
C156
2.2U_0805_16V4Z
C155
2.2U_0805_16V4Z
1
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
R84 10K_0402_5% 2 1
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203
DDR_A_D16 DDR_A_D17 1
Sheet
1
13
of
43
5
4
3
2
1
+1.8V
8 DDR_B_DQS#[0..7]
+1.8V
8 DDR_B_D[0..63]
V_DDR_MCH_REF
8 DDR_B_DM[0..7]
DDR_B_D10 DDR_B_D11
+1.8V
2
DDR_B_D17 DDR_B_D20
1
C189
C188
2
1
0.1U_0402_16V4Z
C187
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
1
C186
0.1U_0402_16V4Z
2
1
C185
C184
2
1
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
C183
2
2.2U_0805_16V4Z
C182
C181
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2
1
DDR_B_DQS#2 DDR_B_DQS2
2
DDR_B_D18 DDR_B_D19 DDR_B_D28 DDR_B_D25 DDR_B_DM3 DDR_B_D30 DDR_B_D31
C
DDR_CKE2_DIMMB
7 DDR_CKE2_DIMMB
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
8
DDR_B_BS2
DDR_B_BS2
DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
+0.9V
2
1
2
DDR_B_MA10 DDR_B_BS0 DDR_B_WE#
DDR_B_BS0 DDR_B_WE#
DDR_B_CAS# DDR_CS3_DIMMB#
8 DDR_B_CAS# 7 DDR_CS3_DIMMB# 1
7
M_ODT3
M_ODT3
DDR_B_D32 DDR_B_D33
2 C202
C201
C200
C199
C198
C197
C196
C195
C194
C193
C192
C191
C190
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
8 8
DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35
B
DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43
RP14 1 2
DDR_B_BS0 DDR_B_MA10
RP16 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_B_MA14 1 4 4 1 DDR_B_MA11 2 3 3 2
DDR_B_MA0 DDR_B_BS1
RP18 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DDR_B_MA5 1 4 4 1 DDR_B_MA8 2 3 3 2
4 3
4 3
RP15 56_0404_4P2R_5% DDR_B_MA9 1 DDR_B_MA12 2
Layout Note: Place t hes e resistor closely JP10,all trace length Max=1.5"
DDR_B_D51 DDR_B_D50 DDR_B_D56 DDR_B_D61 DDR_B_DM7 DDR_B_D59 DDR_B_D58
RP20 56_0404_4P2R_5% RP21 56_0404_4P2R_5% DDR_B_RAS# DDR_B_MA7 1 4 4 1 DDR_CS2_DIMMB# 2 DDR_B_MA6 3 3 2
56_0402_5%
2.2U_0805_16V4Z
1 2
C204 C203
2
2006/02/13
Issued Date
2
M_CLK_DDR3 M_CLK_DDR#3
DDR_B_D21 DDR_B_D16
4
3
PM_EXTTS#1 7
DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D26 DDR_B_D24 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D29 DDR_B_D27
C
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB 7
DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB#
DDR_B_BS1 8 DDR_B_RAS# 8 DDR_CS2_DIMMB# 7
M_ODT2 DDR_B_MA13
M_ODT2
DDR_B_DM4 DDR_B_D39 DDR_B_D38 DDR_B_D44 DDR_B_D45
B
DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 M_CLK_DDR2 M_CLK_DDR#2
M_CLK_DDR2 7 M_CLK_DDR#2 7
DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63
FOX_AS0A426-N8RN-7F CONN@
SO-DIMM B
SP07000BZ00 S SOCKET FOXCON AS0A426-N8RN-7F H8 DDR2R FOX_AS0A426-N8RN-7F_200P
2006/03/10
Deciphered Date
2
7
DDR_B_D36 DDR_B_D37
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
M_CLK_DDR3 7 M_CLK_DDR#3 7
DDR_B_D14 DDR_B_D15
R87 1
2
+3VS
10K_0402_5%
Compal Secret Data
Security Classification
56_0404_4P2R_5%
1
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 GND
DDR_B_DM1
R88
DDR_CKE3_DIMMB R89
DDR_B_BS2 DDR_CKE2_DIMMB
1
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
2
D
10K_0402_5%
RP22 56_0404_4P2R_5% RP23 56_0404_4P2R_5% DDR_B_MA4 1 4 4 1 DDR_B_MA2 2 3 3 2 RP24 56_0404_4P2R_5% RP25 56_0404_4P2R_5% DDR_CS3_DIMMB# 2 M_ODT2 3 4 1 M_ODT3 DDR_B_MA13 1 4 3 2 56_0404_4P2R_5% RP26 4 1 2 3
CLK_SMBDATA CLK_SMBCLK
13,15 CLK_SMBDATA 13,15 CLK_SMBCLK +3VS
DDR_B_CAS# DDR_B_WE# A
DDR_B_DQS#6 DDR_B_DQS6
0.1U_0402_16V4Z
+0.9V
DDR_B_MA1 DDR_B_MA3
DDR_B_D48 DDR_B_D49
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201
2
1
DDR_B_D12 DDR_B_D13
1
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D6 DDR_B_D7
1
A
2
DDR_B_D8 DDR_B_D9
DDR_B_DM0
C180
DDR_B_D2 DDR_B_D3
Layout Note: Place near JP10
DDR_B_D5 DDR_B_D4
C179
DDR_B_DQS#0 DDR_B_DQS0 D
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
0.1U_0402_16V4Z
DDR_B_D0 DDR_B_D1
7,8 DDR_B_MA[0..14]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
2.2U_0805_16V4Z
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
8 DDR_B_DQS[0..7]
1
V_DDR_MCH_REF 7,13,37
JP5
Title
Compal Electronics, Inc. DDRII-SODIMM SLOT2
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet 1
14
of
43
4
CPU MHz
SRC MHz
PCI MHz
0
1
133
100
33.3
0
1
0
200
100
33.3
0
1
1
166
100
33.3
1
+3VS
2 1
FBMA-L11-201209-221LMA30T_0805
1
C205 10U_0805_10V4Z
2
2
1
C206 0.1U_0402_16V4Z
1 C207 680P_0402_50V7K
2
2
1
C208 0.1U_0402_16V4Z
+1.25VS
1 C209 680P_0402_50V7K
2
1
C210
C211 R91
2
0.1U_0402_16V4Z
2
2.2K_0402_5%
Place close to U4
FSB Frequency Selet:
1
20,22,23 ICH_SMBDATA
R1074
R1086
R1098
1
FBMA-L11-201209-221LMA30T_0805
Stuff
R1086
R1139
R1135
No Stuff
R1083
R1107
R1128
R1113
R1098
R1135
R1139
R1113 R1074
R1128 R1139
R1083
R1086
R1098
R1074
R1107
R1113
C212
2 10U_0805_10V4Z
R1135
D
R1128
R94
1 2
CPU_BSEL0
2 1
2
CLRP2 NO SHORT PADS
VDD_PCI VDD48 VDDPLL3 VDDREF
39 55
VDDSRC VDDCPU
12 20 26
VDD96_IO VDDPLL3_IO VDDSRC_IO
36 49
CLRP4,CLRP5 for 667/800 FSB select SHORT CLRP5, NO SHORT CLRP4 -- CPU option SHORT CLRP4, NO SHORT CLRP5 -- FSB 667
0301_Change R105 from 22 ohm to 0 ohm. 0312_Change R106, 107, 109 from 22 to 33 ohm.
R103
475_0402_1%1
2 R104
475_0402_1%1
2 R105
PCI_CLK1
3
22_0402_5% 1 22_0402_5% 1 0_0402_5% 1
2 R106 2 R354 2 R107
PCI2_TME
4
32 CLK_PCI_EC
33_0402_5% 1
2 R108
27_SEL
18 CLK_PCI_ICH
33_0402_5% 1
20 CLKSATAREQ#
@ 1K_0402_5%
CLKREQ#_B
2
7
2
22 CLK_DEBUG_PORT_0 Remove PCI LAN,Change to Debug clock31 CLK_DEBUG_PORT_1 +VCCP 32 CLK_DEBUG_PORT_2
R110
1
CPU_BSEL1
1
2
1 2 R114 0_0402_5%
2
MCH_CLKSEL1 7
Routing the trace at least 10mil
R113 1K_0402_5%
PCI3
ITP_EN
2 R109
5 6 7
PCI1/CR#_B
C224 18P_0402_50V8J @ R117
B
14.31818MHZ_16P CLK_XTAL_OUT
1
59
2
1
2
33_0402_1% 1
2
R119
33_0402_1% 1
2
R123
2
20 CLK_14M_ICH R124
33_0402_1% 1
2 @ R125
5
CPU_BSEL2
1 2 R130 0_0402_5%
10
FSB
57
FSC
62
1
2
2
23
1= Enable SRC0 & 27MHz For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed
29 58
R_CLK_PCIE_NCARD# R_CLK_PCIE_NCARD
33 32
R335
SRC9 SRC9#
30 R_CLK_PCIE_LAN 31 R_CLK_PCIE_LAN#
X1 X2
USB_48MHZ/FSLA
44 43
R111 1 1 R112
R_MINI_ROB_CLKREQ# R_CLKREQ#_G
R146 10K_0402_5% @
R440 1 1 R439 1 R334 1
CLK_SMBCLK
2
0_0402_5% 0_0402_5%
2 2
475_0402_1% R115 2 1 2 1 R333 475_0402_1%
1
2
C222
2
C223
2
C376
2
C
New card WLAN clock REQ
NCARD_CLKREQ# 23
CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24 +3VS
R332 10K_0402_5%
1
R116 10K_0402_5% 2 +3VS
R121 1 1 R122
2 2
0_0402_5% 0_0402_5%
24 25
R _PCIE_ICH R_PCIE_ICH#
R126 1 1 R127
2 2
0_0402_5% 0_0402_5%
21 22
R_PCIE_SATA R_PCIE_SATA#
R131 1 1 R132
2 2
0_0402_5% 0_0402_5%
17 18
SSCDREFCLK R134 SSCDREFCLK# R135
1 1
2 2
0_0402_5% 0_0402_5%
13 14
R_MCH_DREFCLK R_MCH_DREFCLK#
R136 1 1 R137
2 2
0_0402_5% 0_0402_5%
56
1 @ R141
2
ICS9LPRS355_TSSOP64
1 @ R142 1 R143
2
0_0402_5% 0_0402_5%
MINI_ROB_CLKREQ# 22 MINI_CLKREQ# 22
Mini card Robeson clock REQ Mini card WLAN clock REQ B
CLK_PCIE_MCARD 22 CLK_PCIE_MCARD# 22
CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7
CLK_PCIE_ICH 20 CLK_PCIE_ICH# 20
CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19
MCH_SSCDREFCLK 7 MCH_SSCDREFCLK# 7
GND GND SRC0/DOT96 SRC0/DOT96#
GNDCPU
CLK_MCH_DREFCLK 7 CLK_MCH_DREFCLK# 7
GNDSRC GNDSRC CK_PWRGD/PD# GNDREF
VGATE
0_0402_5%
CLK_ENABLE 32
0_0402_5%
CK_PWRGD 20
2
2006/02/13
3
20,39
Compal Secret Data
Security Classification Issued Date
0_0402_5%
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
2
C221
CLK_PCIE_NCARD# 23 CLK_PCIE_NCARD 23
2
R_MCH_3GPLL R_MCH_3GPLL#
SRC1/SE1/27MHz_NonSS SRC1#/SE2/27MHz_SS
C220
1 CLK_48M_ICH @ 5P_0402_50V8C 1 CLK_14M_ICH @ 4.7P_0402_50V8C 1 CLK_PCI_ICH @ 4.7P_0402_50V8C 1 CLK_PCI_EC @ 4.7P_0402_50V8C 1 CLK_DEBUG_PORT_0 @ 4.7P_0402_50V8C 1 CLK_DEBUG_PORT_1 @ 5P_0402_50V8C 1 CLK_DEBUG_PORT_2 @ 5P_0402_50V8C
+3VS
10K_0402_5%
27 28
REF0/FSLC/TEST_SEL
2
475_0402_1%
2 2
SRC4 SRC4#
2
C219
CLK_PCIE_MCARD_ROB 22 CLK_PCIE_MCARD_ROB# 22
0_0402_5% 0_0402_5%
2 2
C218
CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7 0_0402_5% 0_0402_5%
2 2
41 40
SRC6 SRC6#
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4
0_0402_5% 0_0402_5%
R118 R_CLK_PCIE_MCard 1 R_CLK_PCIE_MCard# 1 R120
FSLB/TEST MODE
GND48
0_0402_5% 0_0402_5%
R438 1 1 R437
NCARD_CLKREQ_R# 2
PCIF5/ITP_EN
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
For Layout request: 1. Change MINI_CLKREQ# from pin 32 to pin 43. 2. Change CLK_PCIE_MCARD from SRC9 to SRC6.
2 2
35 34
GNDPCI
For 27_SEL, 0 = Enable DOT96 & SRC1,
R97 1 1 R100
R_CLK_PCIE_MCARD_ROB R_CLK_PCIE_MCARD_ROB#
8
52
1
1
R_MCH_BCLK R_MCH_BCLK#
2 2
47 46
SRC2/SATA SRC2#/SATA#
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
PCI2_TME
R145 10K_0402_5%
5
R_CPU_BCLK R_CPU_BCLK#
SRC8/ITP SRC8#/ITP#
SRC11/CR#_H SRC11#/CR#_G
PCI4/27_Select
1 = Overclocking of CPU and SRC NOT allowed
2
2
2
27_SEL
R144 10K_0402_5%
R140 10K_0402_5%
1
1
R139 10K_0402_5% @
ITP_EN
1
2
2
2 1
XDP@
54 53
H_STP_PCI# 20 H_STP_CPU# 20 R95 1 1 R96
CPU1_F CPU1#_F
GNDSRC
19
R138 10K_0402_5%
Q4 3 2N7002_SOT23-3
1
CLK_SMBCLK 13,14 CLK_SMBDATA 13,14
51 50
42
15
+3VS
+3VS
20,22,23 ICH_SMBCLK
CLK_SMBCLK CLK_SMBDATA
MCH_CLKSEL2 7
R129 1K_0402_5%
11
A
38 37
SRC3/CR#_C SRC3#/CR#_D
0_0402_5%
+3VS
PCI_STOP# CPU_STOP#
VDDSRC_IO
45
@ R133
+3VS
64 63
1
+1.25VS_CK505
SCLK SDATA
SRC7/CR#_F SRC7#/CR#_E
FSA
1
FSC
32 CLK_14M_DEBUG
@ 1K_0402_5%
48
PCI3
C225 18P_0402_50V8J
+VCCP
R128 10K_0402_5% 2 1
SB, MINI PCI
2 2 680P_0402_50V7K
PCI2/TME
0_0402_5% 20 CLK_48M_ICH
NC
SRC10# SRC10
CLK_XTAL_IN
1
60
2
1
5
1
2
PCI0/CR#_A
Y1 @ 1K_0402_5% FSB
2 680P_0402_50V7K
CPU0 CPU0#
VDDSRC_IO VDDCPU_IO
MCH_CLKSEL0 7
R99 1K_0402_5%
1
2
U4 2 9 16 61
1
5
+VCCP
56_0402_5% CLRP1 NO SHORT PADS
C
R98 2.2K_0402_5% FSA 2 1
2
C214
0.1U_0402_16V4Z 1 C217 C216
0308_Change R89 and R92 form 0 ohm to bead, C209, C211, C216, C218 from 0.1uF to 680pF.
+1.25VS_CK505 1
1
10U_0805_10V4Z 1 1 C215
C213
R1139
+3VS_CK505
No Stuff
0.1U_0402_16V4Z 1
2
Title
A
om
No Stuff
2
l.c
*(Default)
1
ai
R1083
S
R1135
2 G
R1107
2 G
Stuff
Stuff
CLK_SMBDATA
+1.25VS_CK505
CPU Driven
800MHz
2.2K_0402_5%
Q3 3 2N7002_SOT23-3
R93
667MHz
R92
0.1U_0402_16V4Z
D
D
0
+3VS_CK505
R90 +3VS
nf @ ho tm
CLKSEL0
Compal Electronics, Inc. Clock generator
Size
Document Number
LA-3821P Date:
R ev 0.3
ai
FSLA
CLKSEL1
1
Tuesday, July 31, 2007
he x
FSLB
2
S
FSLC CLKSEL2
3
D
5
Sheet
1
15
of
43
A
B
C
D
E
EMI
1
1 3
2
3
2
@
3
2
@
D7 @ DAN217_SC59
1
D6 DAN217_SC59
1
D5 DAN217_SC59
CRTL_B CRTL_G CRTL_R
+R_CRT_VCC , +CRTVDD (40mils) +5VS
EMI
2
+R_CRT_VCC F1 1 1
RB411D_SOT23
+CRTVDD
NZQA5V6AXV5T1_SOT533-5
+CRTVDD D8
Place close to JP6 CRT CONNECTOR
3
1
C226 0.1U_0402_16V4Z
2
2 1 JP6
4
CRT_VSYNC_R 74AHCT1G125GW_SOT353-5
2
2
16
2
17
Q6 3V_DDCCL 3 2N7002_SOT23-3
1
R153
S
D
2
CLOSE TO JP3
1
2 G 1
1 R155
2 0_0402_5%
3VDDCDA 9
2 0_0402_5%
3VDDCCL 9
R154
S
D
1
5
@ D4
SUYIN_070549FR015S208CR Q5CONN@ 3 2N7002_SOT23-3 3V_DDCDA
2 G
1
1
220P_0402_50V8J
U6 Y
1
R151 4.7K_0402_5%
C232 22P_0402_50V8J
CR T_HSYNCRFL 1 2 L5 FBM-L11-160808-800LMT_0603
R156
2 2.2K_0402_5% +3VS
C237
A
1
5 P 2
G
CR TVSYNC 2 0_0402_5%
1
@
3
CRT_VSYNC
2
C RT_VSYNCRFL 1 2 L6 FBM-L11-160808-800LMT_0603
OE#
R157 9
2
+CRTVDD 1
220P_0402_50V8J
74AHCT1G125GW_SOT353-5
2
1
C236
@ CR T_HSYNC_R
1
R150 4.7K_0402_5%
@ 4
2
CRTL_B C231 22P_0402_50V8J
U5 Y
2
1
CRTL_G
C235 10P_0402_50V8J
A
1
EMI
C234 10P_0402_50V8J
P 2
G
CRTHSYNC 2 0_0402_5%
1
2
3
CRT_HSYNC
1
0.1U_0402_16V4Z R152 9
OE#
5
C233 1 2
1
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
CRTL_R
C230 22P_0402_50V8J
EMI
+5VS
2
C229 10P_0402_50V8J
CRT_B
R149 75_0402_5% 1 2
CRT_B C228 10P_0402_50V8J
9
CRT_G
R148 75_0402_5% 1 2
CRT_G
C227 10P_0402_50V8J
9
L2 MBK2012800YZF 1 2 L3 MBK2012800YZF 1 2 L4 MBK2012800YZF 1 2
CRT_R
R147 75_0402_5% 1 2
CRT_R
4
2
1.1A_6VDC_FUSE
EMI 9
1
2.2K_0402_5%
3
3
4
4
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. CRT & TVout Connector
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet E
16
of
43
5
4
3
2
1
LVDS CONN D
D
B+
+LCDVDD
INVPWR_B+ @ L7
2 0_0805_5%
1
C238 L8 1 2 FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z
1
1
2
2
C239 0.1U_0402_16V4Z
0308_Reserve L10 and install L11. JP7
2
31 32
1
2
C241 680P_0402_50V7K
LVDSA1+ LVDSA1LVDSA0+ LVDSA0LVDSAC+ LVDSAC-
LVDSA2+ 9 LVDSA2- 9 LVDSA1+ 9 LVDSA1- 9 +3VS
LVDSA0+ 9 LVDSA0- 9 LVDSAC+ 9 LVDSAC- 9
R158 2.2K_0402_5%
GND1 GND2
LCD_CLK LCD_DATA
R159 2.2K_0402_5% C
ACES_88242-3001
LVDS connector
+3VS 2
2
C240 680P_0402_50V7K
680P_0402_50V7K
1
680P_0402_50V7K 2 1
1 2
680P_0402_50V7K
1
LVDSA2+ LVDSA2-
2
INVTPWM DISPLAYOFF# DAC_BRIG LCD_CLK LCD_DAT
INV_PWM
32 DAC_BRIG 9 LCD_CLK 9 LCD_DATA
C244
C
C243
C242
32
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
2
+3VS
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1
+LCDVDD
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
INVPWR_B+
0308_Install all cap for EMI request.
R292
1
4.7K_0402_5% 4/14 R161 1
2
@
0_0402_5% D9 32
1
BKOFF#
DISPLAYOFF#
2 CH751H-40PT_SOD323-2 D10
+LCDVDD
+3VS
Q7
+5VALW
9,32
1
ENABLT 2
+LCDVDD B
SI2301BDS-T1-E3_SOT23-3
B
R164
1
100K_0402_5% 3
2
1
D
S
1
R160
1
1
2
2 G
R162 47K_0402_5%
100_0402_5%
D Q8 2N7002_SOT23-3
2 CH751H-40PT_SOD323-2
2 G
R163 1 2 100K_0402_5% 1 C248 0.22U_0402_10V4Z
C247 S
0.047U_0402_16V7K
2
C246 C245 4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
Q9 2N7002_SOT23-3
2
2
R165 100K_0402_5%
1
D
2 G 3
ENAVDD 1
9
1
3
S
A
A
Compal Secret Data 2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. LCD CONN.
Size
Document Number
LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
Avoid Panel display garbage after power on.
Sheet
1
17
of
43
5
4
3
2
1
PCI_GNT0# 1
+3VS
D
PCI_DEVSEL#
@ R166 1K_0402_5%
PCI_STOP#
2
2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5%
PC I_TRDY#
U7B
PCI_FRAME# PCI_PLOCK# PCI_IR DY# PCI_SERR# PCI_PERR#
+3VS
2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 1 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5%
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
PCI_REQ0# PCI_REQ1#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
F9 B5 C5 A10
PIRQA# PIRQB# PIRQC# PIRQD#
PCI
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55
A4 D7 E18 C18 B19 F18 A11 C10
PCI_REQ0# PCI_GNT0# PCI_REQ1#
D
PCI_REQ2# PCI_REQ3# PCI_GNT3#
C/BE0# C/BE1# C/BE2# C/BE3#
C17 E15 F16 E17
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
C8 D9 G6 D16 A7 B7 F10 C16 C9 A17
PCI_IR DY#
PLTRST# PCICLK PME#
AG24 B10 G7
PCI_PLTRST# CLK_PCI_ICH PCI_PME#
T24
R175 PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PC I_TRDY# PCI_FRAME#
2
PCI_RST# 1 0_0402_5%
R179 2 CLK_PCI_ICH 15 PCI_PME# 32
PLT_RST# 1 0_0402_5%
Place closely pin B10
Interrupt I/F PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
PCI_RST# 31,32
F8 G11 F12 B3
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PLT_RST# 7,22,23,24
Boot BIOS Strap
C
CLK_PCI_ICH
PCI_GNT0#
R187
SPI_CS#1
Boot BIOS Location
ICH8M REV 1.0 PCI_REQ2#
@ 10_0402_5% 1
C
1 R176 1 R177 1 R178 1 R180 1 R181 1 R182 1 R183 2 R184 1 R185 1 R186 1 R188 1 R189
D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3
2
1 R167 1 R168 1 R169 1 R170 1 R171 1 R172 1 R173 1 R174
PCI_REQ3# C249
@ 8.2P_0402_50V
0
1
SPI
1
0
PCI
1
1
LPC
1
2
*
A16 swap override Strap *Low= A16 swap override Enble PCI_GNT3# High= Default
B
B
A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. ICH8(1/4)-PCI/INT
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet 1
18
of
43
5
4
+RTCVCC
2
1
ICH8M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
R192 1
1M_0402_5% 2 SM_INTRUDER#
@ R193 0_0402_5% 2
330K_0402_1% 2 ICH_INTVRMEN
+3VS R191
2
330K_0402_1% 2 LAN100_SLP
1
R190 1
R194 1
3
@ R196 0_0402_5%
ICH_INTVRMEN
GATEA20
Low = Internal VR Disabled High = Internal VR Enabled(Default)
2
1
10K_0402_5% R195 KB_RST#
ICH8M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05)
2
1
10K_0402_5% D
1
D
ICH_LAN100_SLP
Low = Internal VR Disabled High = Internal VR Enabled(Default)
+VCCP R197 H_FERR#
ICH_RTCRST#
AF23
C251 15P_0402_50V8J
C252 1U_0603_10V4Z
2
INTRUDER#
ICH_INTVRMEN AF25 LAN100_SLP AD21
INTVRMEN LAN100_SLP
1
B24
4
Y2
IN
OUT
1
D22
NC
C
+1.5VS 25 ACZ_BITCLK_MDC 27 ACZ_BITCLK 27 ACZ_SYNC 25 ACZ_SYNC_MDC 27,32 ACZ_RST# 25 ACZ_RST#_MDC 27 ACZ_SDIN0 25 ACZ_SDIN1
27 ACZ_SDOUT 25 ACZ_SDOUT_MDC
30
SATA_LED#
22 SATA_RXN0_C 22 SATA_RXP0_C 22 SATA_TXN0 22 SATA_TXP0
R203 1 R338 47_0402_5% R204 47_0402_5% R206 33_0402_5% R341 33_0402_5% R207 33_0402_5% R445 33_0402_5%
GLAN_COMP
2 24.9_0402_1% 1 2 1 2 1 2 1 2 1 2 1 2
D21 E20 C20
LAN_TXD0 LAN_TXD1 LAN_TXD2
R209 33_0402_5% 1 R446 33_0402_5% 1
HDA_BITCLK HDA_SYNC
AJ16 AJ15
HDARST#
AE14
ACZ_SDIN0 ACZ_SDIN1
AJ17 AH17 AH15 AD13
HDA_SDOUT
2 2
AE13 AE10 AG14
SATA_LED#
AF10
SATA_RXN0_C SATA_RXP0_C 3900P_0402_50V7K SATA_TXN0 C253 1 2 SATA_TXP0 C254 1 2
SATA_TXN0_C SATA_TXP0_C
3900P_0402_50V7K
B
15 CLK_PCIE_SATA# 15 CLK_PCIE_SATA
CLK_PCIE_SATA# CLK_PCIE_SATA R212 1
2
AF6 AF5 AH5 AH6
GLAN_COMPI GLAN_COMPO
FERR#
HDA_SDOUT
G9 E6
LPC_DRQ0# T25 PAD
LPC_FRAME# 22,31,32
AF13 AG26
GATEA20 H_A20M#
AF26 AE26
H_DPRSTP_R#
AD24
H_DPSLP# H_FERR#
AE24 AC20 AH14
H_INIT# H_INTR KB_RST#
NMI SMI#
AD23 AG28
H_NMI H_SMI#
H_DPRSTP# 5,7,39
within 2" from R1557 +VCCP C
H_NMI 4 H_SMI# 4
THRMTRIP_ICH#
TP8
AA23
SATARBIAS# SATARBIAS
H_DPRSTP# 1 0_0402_5%
H_INIT# 4 H_INTR 4 KB_RST# 32
H_STPCLK#
24.9_0402_1%
56_0402_5%
H_IGNNE# 4
AE27
R205 56_0402_5%
H_STPCLK# 4 1
2
R208
24_0402_1%
H_THERMTRIP# 4,7
IDE_HDD[0..15] 22
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6
IDE_HDD0 IDE_HDD1 IDE_HDD2 IDE_HDD3 IDE_HDD4 IDE_HDD5 IDE_HDD6 IDE_HDD7 IDE_HDD8 IDE_HDD9 IDE_HDD10 IDE_HDD11 IDE_HDD12 IDE_HDD13 IDE_HDD14 IDE_HDD15
DA0 DA1 DA2
AA4 AA1 AB3
IDE_HDA0 IDE_HDA1 IDE_HDA2
Y6 Y5
IDE_HDCS1# IDE_HDCS3#
W4 W3 Y2 Y3 Y1 W5
IDE_HDIOR# IDE_HDIOW# IDE_HDACK# ID E_HIRQ IDE_HIORDY IDE_HDREQ
DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ
56_0402_5% @ R201 2 1
H_PWRGOOD 5
AA24
SATA_CLKN SATA_CLKP
H_DPSLP#
H_DPSLP# 5 H_FERR# 4
H_IGNNE#
DCS1# DCS3#
56_0402_5% @ R199 2 1
GATEA20 32 H_A20M# 4
STPCLK#
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
H_DPRSTP#
LPC_DRQ#0 32
2 R202
THRMTRIP#
SATALED#
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
LPC_FRAME#
H_PWRGOOD
INIT# INTR RCIN#
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34
AF2 AF1 AE4 AE3
C4
AG29
IGNNE#
HDA_RST# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
AF27
CPUPWRGD/GPIO49
HDA_BIT_CLK HDA_SYNC
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
AB7 AC6
A20GATE A20M# DPRSTP# DPSLP#
GLAN_DOCK#/GPIO13
AG3 AG4 AJ4 AJ3
AG1 AG2
LDRQ0# LDRQ1#/GPIO23
LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2
D25 C25
FWH4/LFRAME#
GLAN_CLK
C21 B21 C22
AH21
3
2
NC
32.768KHZ_12.5P_1TJS125BJ2A251
0205_Change Crystal type.
RTCRST#
SM_INTRUDER# AD22
E5 F5 G8 F6
1
2
2
20K_0402_5%
RTC LPC
2
1
+RTCVCC 1
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
LAN / GLAN CPU
10M_0402_5% 1
RTCX1 RTCX2
IHDA
AG25 AF24
IDE
ICH_RTCX1 ICH_RTCX2 R200
C250 15P_0402_50V8J
LPC_AD[0..3] 22,31,32
U7A
ICH_RTCX2
SATA
2
1
2
ICH_RTCX1 R198 1
2
placed within 2" from ICH8M
+3VS
IDE_HDA0 22 IDE_HDA1 22 IDE_HDA2 22
IDE_HIORDY ID E_HIRQ
R210 1 R211 1
2 4.7K_0402_5% 2 8.2K_0402_5% B
IDE_HDCS1# 22 IDE_HDCS3# 22 IDE_HDIOR# 22 IDE_HDIOW# 22 IDE_HDACK# 22 IDE_HIRQ 22 IDE_HIORDY 22 IDE_HDREQ 22
ICH8M REV 1.0
Within 500 mils
All trace 20mils R214 1
+RTCVCC
2
BATT1.1
0_0603_5% RB751V_SOD323
1
R213 W=20mils 1 2 W=20mils 100_0603_1%
D14 1
2 @
+CHGRTC
2
1
C255 1U_0603_10V4Z
RB751V_SOD323
A
D11 2
Compal Secret Data 2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc.
ICH8(2/4)_LAN,HD,IDE,LPC Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
1
om
0420_Change RTC battery to power
A
CLRP3 SHORT PADS part.
2
07/23
Sheet
1
19
of
43
4
3
2
1
+3VALW
1 R230
1 R234 1 @ R237
2 8.2K_0402_5%
1
SIRQ 2 10K_0402_5% CLKSATAREQ# 2 10K_0402_5%
1
IDE_RESET# 2 8.2K_0402_5% 2 8.2K_0402_5%
23,32 CPUSB# 32 EC_SMI# 32 EC_SCI#
PAD T35
22
IDE_RESET#
27
SB_SPKR
2 @ R249
1 AG22
SMBALERT#/GPIO11
H_STP_PCI# R_STP_CPU#
AE20 AG18
CLKRUN#
AH11
VGATE
AJ20
SST_CTL
AJ22
AJ8 AJ9 CPUSB# AH9 EC_SMI# AE16 EC_SCI# AC19 AG8 AH12 GPIO20 AE11 GPIO22 AG10 GPIO27 AH25 AD16 CLKSATAREQ# AG13 GPIO38 AF9 GPIO39 AJ11 IDE_RESET# AD10 AD9
M CH_ICH_SYNC# AJ13 ICH_RSVD 1 1K_0402_5%
AJ21
STP_PCI#/GPIO15 STP_CPU#/GPIO25 CLKRUN#/GPIO32 WAKE# SERIRQ THRM#
SLP_S3# SLP_S4# SLP_S5#
S4_STATE#/GPIO26
AH27
S4_STATE#
PWROK
AE23
PM_PWROK
DPRSLPVR/GPIO16
AJ14
DPRSLPVR
AE21
ICH_LOW_BAT#
PWRBTN#
C2
PWRBTN_OUT#
VRMPWRGD
LAN_RST#
TP7
AH20
TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 SPKR MCH_SYNC# TP3
RSMRST# CK_PWRGD
AG27
@ 10_0402_5%
E1
1 @ R231
0205 Change to connect to GND.
2 100K_0402_5%
PWRBTN_OUT# 32
R235 1 2 0_0402_5% EC_RSMRST# 1 2 R236 100_0402_5% CK_PWRGD CK_PWRGD 15
CL_CLK0 CL_CLK1
F23 AE18
CL_CLK0
CL_DATA0 CL_DATA1
F22 AF19
CL_DATA0
CL_VREF0 CL_VREF1
D24 AH23
CL_VREF0_ICH CL_VREF1_ICH
EC_RSMRST# 32
M_PWROK 7,32 T34 PAD R240 3.24K_0402_1% 1 2 +3VS
CL_CLK0 7 CL_DATA0 7
AJ23
CL_RST# 7
AJ27 AJ24 AF22 AG19
D
@ 4.7P_0402_50V8C
32 32 32
DPRSLPVR 7,39
PM_SLP_M#
CL_RST#
2
C257
PM_PWROK 7,32
M_PWROK
MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14 WOL_EN/GPIO9
@ 4.7P_0402_50V8C
T32 PAD
AJ25
SLP_M#
2
SLP_S3# SLP_S4# SLP_S5#
E3
CLPWROK
2
1
C256
T31 PAD
EC_RMRST#
1
C258
2
C
R242 453_0402_1%
0.1U_0402_16V4Z 1
C259
R246 1
3.24K_0402_1% 2 +3VALW
R250 453_0402_1%
R251
low-->default
2 SB_SPKR @ 10K_0402_5%
R221
@ 10_0402_5%
2
100K_0402_5% 2
1 R252
AG23 AF21 AD18
BATLOW#
1
CLK_14M_ICH 15 CLK_48M_ICH 15
ICH_SUSCLK
SUSCLK
PAD PAD PAD PAD
CLK_14M_ICH CLK_48M_ICH
AG9 G5 D3
SLP_S3# SLP_S4# SLP_S5#
ICH8M REV 1.0
+3VS
SATA GPIO
SMB
EC_LID_OUT#
SB_SPKR
7 MCH_ICH_SYNC#
PM_BMBUSY#
BMBUSY#/GPIO0
OCP#
OCP#
15 CLKSATAREQ#
1
1
1
4
AG12
ICH_PCIE_WAKE#AE17 SIRQ AF12 THERM_SCI# AC13
PAD T33
M CH_ICH_SYNC# 2 10K_0402_5%
R245
1 0_0402_5%
GPIO20
1
R244
R248
GPIO22 2 8.2K_0402_5%
OCP# 2 10K_0402_5%
R243
2 R229
22,23,24 ICH_PCIE_WAKE# 32 SIRQ 32 THERM_SCI# 2 1 R233 100K_0402_5% 15,39 VGATE
CLKRUN# 2 8.2K_0402_5%
@ R239
H_STP_PCI# H_STP_CPU#
GPIO39 2 10K_0402_5%
1
@ R241
C
15 15
1 R238 +3VS
GPIO38 2 10K_0402_5%
SUS_STAT#/LPCPD# SYS_RESET#
PM_BMBUSY#
CLK14 CLK48
T26 T27 T28 T29
1
1 R228
EC_LID_OUT#
SUS_STAT# F4 XDP_DBRESET# AD15
RI#
AJ12 AJ10 AF11 AG11
2
+3VS
1
32
AF17
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37
1
7 PM_BMBUSY#
ICH _RI#
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1
2
@ R227 10K_0402_5%
AJ26 AD19 AG21 AC17 AE19
0.1U_0402_16V4Z
@ R226 10K_0402_5%
ICH_SMBCLK ICH_SMBDATA LINKALERT# ME_EC_CLK1 ME_EC_DATA1
1
2 1ME_EC_CLK1 10K_0402_5%
PAD T30 4 XDP_DBRESET#
2
R225
+3VS 2
2 1ME_EC_DATA1 10K_0402_5%
R220 U7C
D
R224
CLK_14M_ICH 1
1 2.2K_0402_5%
Clocks
2 XDP_DBRESET# 1K_0402_5%
2.2K_0402_5% 15,22,23 ICH_SMBCLK 15,22,23 ICH_SMBDATA
SYS GPIO
1
R218
Power MGT
2 ICH _RI# 10K_0402_5%
R217
Place closely pin AG9
CLK_48M_ICH
MISC GPIO Controller Link
2 ICH_PCIE_WAKE# 1K_0402_5%
1 R222 R223
1 ICH_LOW_BAT# 8.2K_0402_5%
1 R219
1
2 R216
2 LINKALERT# 10K_0402_5%
2
1 R215
2
+3VALW
Place closely pin G5
2
5
High -->No boot U7D PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2
PCIE_RXN1 PCIE_RXP1 1 C260 PCIE_C_TXN1 1 C261 PCIE_C_TXP1
GIGA LAN
24 24 24 24
PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2
PCIE_RXN2 M27 PCIE_RXP2 M26 1 C262 PCIE_C_TXN2 L29 1 C263 PCIE_C_TXP2 L28
New card
23 23 23 23
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2
PCIE_RXN3 PCIE_RXP3 1 C494 PCIE_C_TXN3 1 C493 PCIE_C_TXP3
K27 K26 J29 J28
22 22 22 22
PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2
PCIE_RXN4 PCIE_RXP4 1 C496 PCIE_C_TXN4 1 C495 PCIE_C_TXP4
H27 H26 G29 G28
Robeson (Mini card)
+3VALW
1 1 1 1 1 1 1
2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5%
+3VALW 2
1
@ R256 10K_0402_5% 1
USB_OC#3 R254 USB_OC#4 R255 USB_OC#5 R257 USB_OC#6 R258 USB_OC#7 R259 USB_OC#8 R260 USB_OC#9 R261 USB_OC#2 R262
29 29 29
A
USB_OC#0
1 2 R263 10K_0402_5% 1 2 USB_OC#1 R265 0_0402_5%
USB_OC#0 USB_OC#1 USB_OC#2
PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4
F27 F26 E29 E28
PERN5 PERP5 PETN5 PETP5
D27 D26 C29 C28
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
PAD T36 PAD T37 PAD T38
SPICLK C23 SPI_CS0# B23 SPI_CS1# E22
PAD T39
SPI_MOSI D23 SPI_MISO F21
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9
PERN1 PERP1 PETN1 PETP1
AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18
V27 V26 U29 U28
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
Y27 Y26 W29 W28
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
AB26 AB25 AA29 AA28
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
AD27 AD26 AC29 AC28
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
DMI_CLKN DMI_CLKP
T26 T25
CLK_PCIE_ICH# CLK_PCIE_ICH
DMI_ZCOMP DMI_IRCOMP
Y23 Y24
SPI_CLK SPI_CS0# SPI_CS1#
SPI
B
P27 P26 N29 N28
PCI-Express Direct Media Interface
22 22 22 22
WLAN (Mini card)
SPI_MOSI SPI_MISO OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9#
USB
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP
DMI_RXN0 7 DMI_RXP0 7 DMI_TXN0 7 DMI_TXP0 7 DMI_RXN1 7 DMI_RXP1 7 DMI_TXN1 7 DMI_TXP1 7 DMI_RXN2 7 DMI_RXP2 7 DMI_TXN2 7 DMI_TXP2 7
B
DMI_RXN3 7 DMI_RXP3 7 DMI_TXN3 7 DMI_TXP3 7
DMI_IRCOMP
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P
G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7
USBRBIAS# USBRBIAS
F2 F3
USBRBIAS
CLK_PCIE_ICH# 15 CLK_PCIE_ICH 15 R253 24.9_0402_1% 1 2
Within 500 mils
USB20_N0 29 USB20_P0 29 USB20_N1 29 USB20_P1 29 USB20_N2 29 USB20_P2 29 USB20_N3 23 USB20_P3 23 USB20_N4 26 USB20_P4 26 USB20_N5 29 USB20_P5 29 USB20_N6 29 USB20_P6 29 USB20_N7 29 USB20_P7 29
+1.5VS
To New Card To Card reader/B. To Bluetooth To PC Camera To Finger Printer
A
1 R264
2 22.6_0402_1%
ICH8M REV 1.0
Within 500 mils Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. ICH8(3/4)_PM,USB,GPIO
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet 1
20
of
43
5
4
3
2
1
U7E
+VCCP
1170mA
2.2U_0805_16V4Z
2
10U_0805_10V4Z
D12
R268 CH751H-40PT_SOD323-2
20 mils
1
2
100_0402_5%
ICH_V5REF_RUN 1
C274 0.1U_0402_16V4Z
2
1 2
1
0.1U_0402_16V4Z
R270
C287
10U_0805_10V4Z
C286
C288 1U_0603_10V4Z
1
2
C290 1U_0603_10V4Z
VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10]
AC10 AC9
1
VCC1_5_A[11] VCC1_5_A[12]
AA5 AA6
2
2
1
2
VCC1_5_A=1120mA +1.5VS T44 T45
+3VS
VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2
12mA 1
VCC1_5_A[20] VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24]
W23
VCC1_5_A[25]
F17 G18
VCCLAN1_05[1] VCCLAN1_05[2]
F19 G20
VCCLAN3_3[1] VCCLAN3_3[2]
+1.5VS
10U_0805_10V4Z
A
A24
VCCGLANPLL
A26 A27 B26 B27 B28
VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5]
B25
VCCGLAN3_3
GLAN POWER
CHB1608U301_0603 27mA ICH_VCCGLANPLL 2 @ R272 74mA ICH_VCCGLAN1_5 1 2 1 1 +1.5VS CHB1608U301_0603 1 C298 C299 @ C300 2 2 4.7U_0805_10V4Z 1mA 2 1 2 ICH_VCCGLAN3_3 +3VS @ R2730_0402_5%
F1 L6 L7 M6 M7
R271 1
2
2.2U_0805_16V4Z
C297 0.1U_0402_16V4Z
VCCUSBPLL
VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05] VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCCL1_05
0.1U_0402_16V4Z +3VS (SATA) 1 +3VS
VCC3_3=310mA
2
+3VS
(DMI)
C279 2
1
2
1
2
1
2
VCC3_3=310mA 0.1U_0402_16V4Z 1
C282
2
+3VS
1
2
1
0.1U_0402_16V4Z
4mA
C289 2
2 +3VALW
VCCSUS3_3=141mA 1
2
1
2
+3VALW
P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6
VCCSUS3_3=141mA 1
2
G22 VCCCL1_05_ICH
F20 G21
+3VALW
C291
AC18 AC21 AC22 AG20 AH28
VCCCL3_3[1] VCCCL3_3[2]
+3VS 1
0.1U_0402_16V4Z 1
T40 T41 AC16 VCCSUS1_5_ICH_1 T42 VCCSUS1_5_ICH_2 J7 T43 C3 0.1U_0402_16V4Z
A22
2
24mA
J6 AF20
VCCCL1_5
1
2
0.1U_0402_16V4Z
C295 0.1U_0402_16V4Z
D1
0.1U_0402_16V4Z +3VS 1
VCC3_3=310mA
C293
1
VCC1_5_A[18] VCC1_5_A[19]
USB CORE
C294 0.1U_0402_16V4Z
VCCSUSHDA
AD11
VCCSUS1_5[2]
+VCCP
VCC3_3=310mA
C292
10mA
AC12
VCCSUS3_3[01]
2
VCC3_3=310mA
VCCHDA
VCCSUS1_5[1] VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17]
AC7 AD7
VCC1_5_A=1120mA
+1.5VS
VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24]
A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11
VCCSUS1_05[1] VCCSUS1_05[2]
VCC1_5_A[13] VCC1_5_A[14]
G12 G17 H7
+1.5VS
ATX
B
VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05]
AC1 AC2 AC3 AC4 AC5
VCC1_5_A=1120mA +1.5VS
VCCSATAPLL
AE7 AF7 AG7 AH7 AJ7
AA3 U7 V7 W1 W6 W7 Y7
1
C285
2
VCC1_5_A=1120mA +1.5VS
VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]
14mA
C284
2
1
ARX
1
AJ6
AC8 AD8 AE8 AF8
40mA
C283 0.1U_0402_16V4Z
CHB1608U301_0603
1U_0603_10V4Z
ICH_VCCSATAPLL
2
VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06]
26mA
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.5VS
1
50mA
AD2
+1.25VS
C278
2
C281
VCC3_3[02]
AF29
2 10U_0805_10V4Z
0.1U_0402_16V4Z C277
20 mils 1
VCC3_3[01]
AC23 AC24
2 0.01U_0402_16V7K
C276
ICH_V5REF_SUS
VCC_DMI[1] VCC_DMI[2] V_CPU_IO[1] V_CPU_IO[2]
CHB1608U301_0603 2 +1.5VS
1 C273
0.1U_0402_16V4Z
CH751H-40PT_SOD323-2
R29 AE28 AE29
1 C272
4.7U_0805_10V4Z
D13
R269 10_0402_5%
VCCDMIPLL
R267 1
ICH_VCCDMIPLL
C275
C
VCCA3GP
+5VALW +3VALW
VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46]
0.1U_0402_16V4Z
2
10U_0805_10V4Z
2
AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25
1
C296 4.7U_0805_10V4Z
C
B
A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
ICH8M REV 1.0
T46
1U_0603_10V4Z 1
12mA
+3VS
A
2 @
ICH8M REV 1.0
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]
D
om
2
+3VS 220U_D2_2.5VM
1
C271
2
1
C267
2
l.c
+5VS
C270
2
1
1
C266
4
3
2
Title
nf @ ho tm
C269
2
1
V5REF_SUS
K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24
Compal Electronics, Inc.
ICH8(4/4)_POWER&GND Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
+
C268
40 mils
G4
VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184]
ai
V5REF[1] V5REF[2]
ICH_V5REF_SUS 10U_0805_10V4ZICH_VCC1_5 770mA
A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098]
Tuesday, July 31, 2007
he x
+1.5VS
CHB1608U301_0603 2 1
CORE
R266 1
VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28]
C280
VCCRTC
A16 T7
A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6
C301
AD25
VCCP_CORE
6mA 3mA
D
0.1U_0402_16V4Z
U7F ICH_V5REF_RUN
IDE
2
PCI
2
20 mils
VCCPSUS
1
VCCPUSB
1
C265 0.1U_0402_16V4Z
C264 0.1U_0402_16V4Z
+RTCVCC
Sheet
1
21
of
43
A
B
C
D
E
F
G
H
+5VS
Placea caps. near ODD CONN.
HDD Connector
CD-ROM Connector
C310 0.1U_0402_16V4Z
C307 10U_0805_10V4Z
C309
2 0.1U_0402_16V4Z
2 2 0.1U_0402_16V4Z
V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12
Pleace near HD CONN (JP23) +3VS_HDD
1
@ C313
1 1
@ C314
+ @ C315
2 2 2 2 1000P_0402_50V7K 1U_0603_10V4Z
@
7,18,23,24 PLT_RST#
SATA_RXN0_C 19 SATA_RXP0_C 19
Near CONN side. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+3VS_HDD 19 19 19 19 19 19
+5VS +5VS
IDE_HDIOW# IDE_HIORDY IDE_HIRQ IDE_HDA1 IDE_HDA0 IDE_HDCS1# 2 1 R278 10K_0402_5%
IDE_HDIOW# IDE_HIORDY ID E_HIRQ IDE_HDA1 IDE_HDA0 IDE_HDCS1# IDE_ACT#
+5VS SEC_CSEL
SUYIN_127043FR022G204ZL_NR
R279 470_0402_5%
IDE_HDD8 IDE_HDD9 IDE_HDD10 IDE_HDD11 IDE_HDD12 IDE_HDD13 IDE_HDD14 IDE_HDD15 IDE_HDREQ IDE_HDIOR#
2
2
1
2
C305 10U_0805_10V4Z 1
IDE_HDREQ 19 IDE_HDIOR# 19
IDE_HDACK#
IDE_HDACK# 19
PDIAG# R276 1 IDE_HDA2 IDE_HDCS3#
2
100K_0402_5%
+5VS
IDE_HDA2 19 IDE_HDCS3# 19 +5VS
SUYIN_800189MB050S105ZL CONN@
2
Pleace near HD CONN
SATA_TXP0 19 SATA_TXN0 19
1 C306 SATA_RXN0_C 1 C311 SATA_RXP0_C
1
0.1U_0402_16V4Z 1
C312 330U_V_2.5VK_R9
+3VS @ R2770_0805_5% 2 1
SATA_TXP0 SATA_TXN0 0.01U_0402_16V7K SATA_RXN0 2 SATA_RXP0 2 0.01U_0402_16V7K
2
C304
C308 2
1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
1
10U_0805_10V4Z
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
1 C303
1
20 IDE_RESET#
1
1U_0603_10V4Z
1
1 2 3 4 5 6 7
JP9
0.1U_0402_16V4Z
1
GND A+ AGND BB+ GND
@ R274 0_0402_5% 1 2 R275 33_0402_5% 1 2 IDE_HDD7 IDE_HDD6 IDE_HDD5 IDE_HDD4 IDE_HDD3 IDE_HDD2 IDE_HDD1 IDE_HDD0
C302
0213_Change Connector type.
IDE_HDD[0..15] 19 JP8 +5VS
2
2
Mini-Express Card---WLAN +3VS_MINI
NAND mini Card(Robson support) +3VS
Add in 4/27.
20 20
3
R280 R281
PCIE_RXN4 PCIE_RXP4
20 20
2 0_0402_5% 2 0_0402_5%
1 1
PCIE_C_RXN4 PCIE_C_RXP4
PCIE_TXN4 PCIE_TXP4
Add in 5/16. (Close to JP10)
C330
2
1
2
4.7U_0805_10V4Z
C329
1
0.1U_0402_16V4Z
2
0.01U_0402_16V7K
2
1 C328
C327
2
1
+1.5VS
4.7U_0805_10V4Z
C326
1
0.1U_0402_16V4Z
2
0.01U_0402_16V7K
2
1 C325
C324
2
1
+3VS
0.01U_0402_16V7K
C323
1
0.01U_0402_16V7K
+3VS
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
53
GND1
0.01U_0402_16V7K 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND2
54
2
2
C318
4.7U_0805_10V4Z 2
1
2
C320 0.1U_0402_16V4Z
1
2
ICH_PCIE_WAKE# CH_DATA CH_CLK 1 2 MINI_CLKREQ#_MC R282 0_0402_5% CLK_PCIE_MCARD# CLK_PCIE_MCARD
20,23,24 ICH_PCIE_WAKE# 29 CH_DATA 29 CH_CLK 15 MINI_CLKREQ# 15 CLK_PCIE_MCARD# 15 CLK_PCIE_MCARD
PLT_RST# 15 CLK_DEBUG_PORT_0 20 20
PCIE_RXN1 PCIE_RXP1
20 20
PCIE_TXN1 PCIE_TXP1
PCIE_RXN1 PCIE_RXP1
1 2 R288 DEBUG@ 0_0402_5% R289 0_0402_5% PCIE_C_RXN1 1 2 PCIE_C_RXP1 1 2 R290 0_0402_5%
PCIE_TXN1 PCIE_TXP1
Mini Card STANDOFF H1 HOLEA
+3VS_MINI
53
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 GND1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
1 R283 R284 R285 R286 R287
Issued Date
2
+3VS +1.5VS L9 FBMA-L11-201209-102LMA10T 1 2 2 L10 FBMA-L11-201209-102LMA10T 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5%
3
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
LPC_FRAME# 19,31,32
LPC_AD[0..3] 19,31,32
WL_ON# PLT_RST#
WL_ON#
32
+3VALW ICH_SMBCLK 15,20,23 ICH_SMBDATA 15,20,23
WL_LED#
WL_LED# 30
54
4
C
D
Compal Electronics, Inc.
Compal Secret Data 2006/02/13
2007/08/29
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
1
FOX_AS0B226-S40N-7F CONN@
Security Classification
A
2
C322 @ 0.1U_0402_16V4Z
1
1
H2 HOLEA
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
1
C321 4.7U_0805_10V4Z
+1.5VS_MINI
H4 HOLEA
1
C319 0.01U_0402_16V7K
JP11
FOX_AS0B226-S40N-7F CONN@
H3 HOLEA
1
PLT_RST#
Mini Card STANDOFF
4
1
C317 0.1U_0402_16V4Z
+3VALW
1
15 MINI_ROB_CLKREQ# 15 CLK_PCIE_MCARD_ROB# 15 CLK_PCIE_MCARD_ROB
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
C316 1
+1.5VS
JP10
+1.5VS_MINI
E
F
Title
HDD/ODD/Mini Card CONN. Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007 G
Sheet
22 H
of
43
A
B
C
D
E
Express Card Power Switch
5 6
0.1U_0402_16V4Z 2 R291
+3VALW CPUSB#
G
2
20,32
3
1
21
7 8
3.3Vaux_in
Aux_out
1
20 +1.5VS_PEC
18 19
1.5Vin1 1.5Vin2
1.5Vout1 1.5Vout2
100K_0402_5% 14 CPUSB# 15 CPPE# 4 STBY# 3 SHDN# 2 SYSRST#
SUSP# SYSON PLTRST#
GND
D
S
7,18,22,24 PLT_RST#
32,33,35,37,38 SUSP# 32,33,37 SYSON
1
3.3Vout1 3.3Vout2
+3V_PEC
C332 +3VALW 0.1U_0402_16V4Z 2 1 +1.5VS C333 2 1 +3VS
3.3Vin1 3.3Vin2
11
Q10 2N7002_SOT23-3
OC# RCLKEN PERST#
16 17
23 22 9
PERST#
NC1 NC2 NC3 NC4 NC5
1
+3VS_PEC
U8
+3VS
1 10 12 13 24
C331 0.1U_0402_16V4Z 2 1
TPS2231PWPR_PWP24
2
2
JP12
20 20
USB20_N3 USB20_P3
15,20,22 ICH_SMBCLK 15,20,22 ICH_SMBDATA +1.5VS_PEC +1.5VS_PEC 20,22,24 ICH_PCIE_WAKE# +3V_PEC
USB20_N3 USB20_P3 CPUSB# ICH_SMBCLK ICH_SMBDATA ICH_PCIE_WAKE# PERST#
+3VS_PEC 15 NCARD_CLKREQ# 15 CLK_PCIE_NCARD# 15 CLK_PCIE_NCARD 20 20 3
20 20
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
CLKREQD# CPUSB# CLK_PCIE_NC2# CLK_PCIE_NC2 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Near to Express Card slot. 15.4
GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND GND1 GND2
GND3 GND4
+3VS_PEC
+3V_PEC 4.7U_0805_10V4Z
1 C334 0.1U_0402_16V4Z
1 C335
2
2
C336 0.1U_0402_16V4Z
1
1
2
2
C337 4.7U_0805_10V4Z
+1.5VS_PEC 4.7U_0805_10V4Z 1 C338 0.1U_0402_16V4Z
1 C339 3
2
2
29 30
SANTA_131851-A_LT CONN@
4
Compal Secret Data 2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. Express Card
Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
2005/03/10
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
4
Sheet
E
23
of
43
5
4
3
2
1
+3V_LAN C340
U9
D
A0 A1 NC GND
VCC WP SCL SDA
8 7 6 5
AP2305GN
LAN_EE_CLK LAN_EE_DATA 32 LAN_POWER_OFF
CAT24C08WI-GT3 SO 8P
Turn off power when S3. 06/14
Q22
1
3
D
1 2 3 4
+3VALW R359 @ 0_1206_5% 1 2
S
10K_0402_5% GIGA_LAN_CLKREQ 1 10K_0402_5% ICH_PCIE_WAKE# 1 10K_0402_5% LAN_LOM_DIS 1
R293 1K_0402_5% 2 1
R295 2 R296 2 R297 2
+3V_LAN
0.1U_0402_16V4Z
D
2 G
+3V_LAN
1 R294 1K_0402_5% 2 1
2
+3V_LAN U10 GIGA_LAN_CLKREQ 42 0.1U_0402_16V4Z 2 1 C341 PCIE_RXP2_LAN49 0.1U_0402_16V4Z 2 1 C347 PCIE_RXN2_LAN50 54 53 ICH_PCIE_WAKE# 6 55 R298 0_0402_5% 56 1 2 5
20 PCIE_RXP2 20 PCIE_RXN2 20 PCIE_TXP2 20 PCIE_TXN2 20,22,23 ICH_PCIE_WAKE# 15 CLK_PCIE_LAN 15 CLK_PCIE_LAN# 7,18,22,23 PLT_RST# 25 25 25 25 25 25 25 25
17 18 20 21 26 27 30 31
LAN_MDI0P LAN_MDI0N LAN_MDI1P LAN_MDI1N LAN_MDI2P LAN_MDI2N LAN_MDI3P LAN_MDI3N LAN_EE_CLK LAN_EE_DATA
+3VS
LAN_X1 LAN_X2
+3V_LAN
LAN_LOM_DIS
R299
4.87K_0402_1%
CTRL18 CTRL12
LED PCI-E
TESTMODE AVDDH
POWER Media
VPD_CLK VPD_DATA
EEPROM
SPI_DO SPI_DI SPI_CLK SPI_CS
FLASH MEMORY
15 14
XTALI XTALO
CLOCK
10 12 11 47 9 16 4 3
LOM_DISABLEn VAUX_AVLBL SWITCH_VCC VMAIN_AVLBL SWITCH_VAUX RSET Analog CTRL18 CTRL12
38 41
LED_ACTn LED_LINK10/100n LED_LINK1000n LED_DUPLEXn
TEST
MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3
34 35 37 36
C
CLKREQn TX_P TX_N RX_P RX_N WAKEn REFCLKP REFCLKN PERSTn
& GROUND
AVDD AVDD AVDD AVDD VDDO_TTL VDDO_TTL VDDO_TTL VDDO_TTL VDD VDD VDD VDD VDD VDD VDD VDD VSS
C342 0.1U_0402_16V4Z
2
1 C343 0.1U_0402_16V4Z
2
1 C344 0.1U_0402_16V4Z
2
1 C345 0.1U_0402_16V4Z
2
C346 0.1U_0402_16V4Z
V1.8_LAN
19 22 23 28
V1.8_LAN
0.1U_0402_16V4Z +3V_LAN
1
1 C501
1 40 45 61
2
2
1 C500 0.1U_0402_16V4Z
2
1 C491 0.1U_0402_16V4Z
2
1 C348 0.1U_0402_16V4Z
2
1 C349 0.1U_0402_16V4Z
2
1 C350 0.1U_0402_16V4Z
2
1 C351 0.1U_0402_16V4Z
2
C352 0.1U_0402_16V4Z
V1.2_LAN
2 7 13 33 39 44 48 58 65
24 25 29 43
2
LANLINK_STATUS# 25
1
+3V_LAN
8
Reserved Reserved Reserved Reserved
LAN_ACT# 25
LANLINK_STATUS#
46
32 51 52 57 64
No Connect
LAN_ACT#
59 60 62 63
NC NC NC NC NC
1
V1.2_LAN 1
2
V1.8_LAN
1 C490 0.1U_0402_16V4Z
2
1 C353 0.1U_0402_16V4Z
2
1 C354 0.1U_0402_16V4Z
2
1 C355 0.1U_0402_16V4Z
2
1 C356 0.1U_0402_16V4Z
2
C
C357 0.1U_0402_16V4Z
V1.2_LAN 1
2
1 C414 0.1U_0402_16V4Z
2
1 C404 0.1U_0402_16V4Z
2
1 C405 0.1U_0402_16V4Z
2
C403 0.1U_0402_16V4Z
88E8055_QFN64
+3V_LAN
R435 2
4.7K_0402_5% 1
C359 27P_0402_50V8J 1 2
Q11
B
2
3
4.7U_0805_10V4Z C358 2 1
1
B
CTRL12
2SB1188T100R_SC62-3
LAN_X1 LAN_X2
4.7U_0805_10V4Z C361 2 1
1
V1.2_LAN
2
Y3 25MHZ_20P_1BG25000CK1A C360 27P_0402_50V8J 1 2
+3V_LAN
3
4.7U_0805_10V4Z C362 2 1
R436 2
2SB1188T100R_SC62-3
CTRL18
2
1
V1.8_LAN
4.7K_0402_5% 1
Q12
4.7U_0805_10V4Z C363 2 1
A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2007/08/29
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. LAN-8100CL
Size
Document Number
R ev 0.3
LA-3821P Date:
Sheet
Tuesday, July 31, 2007 1
24
of
43
5
4
3
2
1
D
D
V1.8_LAN
T47 0.1U_0402_16V4Z 1
2 C364 R3001
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
2
49.9_0402_1%
R3021
2
49.9_0402_1%
LAN_MDI0P 24
2 C367 R3031
2
49.9_0402_1%
LAN_MDI1N 24
R3051
2
49.9_0402_1%
LAN_MDI1P 24
2 C371 R3061
2
49.9_0402_1%
LAN_MDI2N 24
R3081
2
49.9_0402_1%
LAN_MDI2P 24
2 C374 R3091
2
49.9_0402_1%
LAN_MDI3N 24
R3111
2
49.9_0402_1%
LAN_MDI3P 24
LAN_MDI0N 24
2 1 C365 0.1U_0402_16V4Z
TRM_CT LAN_MDI3P LAN_MDI3N
1 2 3
TCT1 TD1+ TD1-
MCT1 MX1+ MX1-
24 23 22
2 R301 1 MDO3+ 75_0402_1% MDO3-
2 1 C368 0.1U_0402_16V4Z
TRM_CT LAN_MDI2P LAN_MDI2N
4 5 6
TCT2 TD2+ TD2-
MCT2 MX2+ MX2-
21 20 19
2 R304 1 MDO2+ 75_0402_1% MDO2-
2 1 C372 0.1U_0402_16V4Z
TRM_CT LAN_MDI1P LAN_MDI1N
7 8 9
TCT3 TD3+ TD3-
MCT3 MX3+ MX3-
18 17 16
2 R307 1 MDO1+ 75_0402_1% MDO1-
2 1 C375 0.1U_0402_16V4Z
TRM_CT LAN_MDI0P LAN_MDI0N
10 11 12
TCT4 TD4+ TD4-
MCT4 MX4+ MX4-
15 14 13
2 R310 1 MDO0+ 75_0402_1% MDO0-
C369 1 2 1000P_1808_3KV7K
0.5u_24HST1041A-2 C
C
JP40
Note: MDO[3..0]+/- signals should route to JP13 first then to JP30.
1 2 G1 G2
JP14 LAN_ACT#
LAN_ACT# R312 2
1 300_0402_5%
+3V_LAN
7
MDO1-
6
MDO2-
5
MDO2+
4
MDO1+
3
PR2+
MDO0-
2
PR1-
MDO0+
1
PR1+
1 300_0402_5%
9
7/24
PR3+
GND GND
ZZZ2
MDC 1.5 Conn.
14 13
B
Change type 4/25
Green LEDGreen LED+
ACZ_SDOUT_MDC
1 R314
ACZ_SYNC_MDC 2 ACZ_SDIN1_R ACZ_RST#_MDC 33_0402_5%
JP15 CONN@ ACES_88020-124G 1 2 1 2 3 4 3 4 5 6 5 6 7 8 7 8 9 10 9 10 11 12 11 12
+3VS
45@
ACZ_BITCLK_MDC 19 1 2 C380 @ 10P_0402_25V8K
1
2
MDC STANDOFF H5 HOLEA
1
2
C385
1
@ 4.7U_0805_10V4Z
2
1115 EMI REQUEST
C384
1
0.1U_0402_16V4Z
C383
13 14 15 16 17 18
@ C382 300p_0402_25V
MDC cable
+3VS
2 1 R315 @ 10_0402_5%
GND GND GND GND GND GND
19 ACZ_SYNC_MDC 19 ACZ_SDIN1 19 ACZ_RST#_MDC
LANLINK_STATUS#
1
FOX_305-000-1176
PR3-
1000P_0402_50V7K
1
1
GND1 GND2
PR2-
2 @ C381 300p_0402_25V
1
RJ11
Tip Ring
PR4+
19 ACZ_SDOUT_MDC
2
C506
1000P_1808_3KV7K 3 C507 4
PR4-
FOX_JM36113-L2R8-7F
LAN_ACT#
1000P_1808_3KV7K
2
Yellow LED+
MDO3+
10
2
ACES_85204-02001 CONN@
Yellow LED-
8
LANLINK_STATUS#
R313 2
11
MDO3-
B
24 LANLINK_STATUS#
12
1 2
H6 HOLEA
1
24 +3V_LAN
JP13 TIP RING
1 2 3 4
A
Compal Secret Data 2006/02/13
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Magnetic & RJ45/RJ11
Size
Document Number
LA-3821P Date:
R ev 0.3
ai
Issued Date
he x
Security Classification
nf @ ho tm
ai
l.c
om
A
Tuesday, July 31, 2007
Sheet 1
25
of
43
5
4
3
2
1
+VCC_4in1
SDPWR0_MSPWR
40mil
2 R316 1 0_0603_5% +3VS @ U12
C386
2
1
VIN VOUT VIN/CE VOUT
1 5
D
1
3 4
D
GND
1 C387
R317
@
@
2
1U_0603_10V4Z
2
RT9701CB_SOT25 0.1U_0402_16V4Z @ 2
150K_0402_5%
reserved power circuit +A3V
1 R318 C3891 0.1U_0402_16V4Z C3901 1U_0603_10V4Z
1 2 C388 0.1U_0402_16V4Z
2
SDPWR0_MSPWR 1 R319
1 3 7 9 11 33
20_0603_5%
C
2 R320 2 R321 @
+5VS +5VALW
1 0_0603_5% 1 0_0603_5%
2
C393 1
RST# MODE SEL XTLI XTLO
1 C392
USB20_N4 USB20_P4
USB20_N4 USB20_P4
VBUS RST# MODE_SEL XTLI XTLO
4 5 14
DM DP GPIO0
XTLI
2 1
5.6P_0402_50V
7/25 2
12MHZ_16P_6X12000012 Y4 C394 1
2
XTLO
5.6P_0402_50V 2 +A3V 2
12 32
R323 6.19K_0402_1%
RREF DGND DGND AGND AGND
CF_CD# CF_DMARQ CF_D10 CF_D9 CF_D2 SD_CMD
1
43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18
2 C391 1U_0603_10V4Z
XDRE#_SDD2 XDWE#_SDD3
XDD1 XDD7_SDD6_MSD3 MSINS# XDD2_SDD7_MSD2 XDD6_SDD0_MSD0 XDD3_SDD1_MSD1 XDD5_MSBS
XDD3_SDD1_MSD1 +VCC_4in1 R322 22_0402_5% 1 2
SD_MS_CLK
19 13 14 16 18 20 15 17 21 12 22 23
SD_MS_CLK MSINS# XDD6_SDD0_MSD0 XDD5_MSBS XDD7_SDD6_MSD3 XDD2_SDD7_MSD2
SDCD#
C
VCC_MS VCC_MS SCLK_MS INS_MS SDIO_MS BS_MS RESERVED_MS RESERVED_MS VSS_MS VSS_MS GND GND PROCO_MDR019-C0-1202 CONN@
SDWP
13 24 15 16 17 36
B
SDCMD
RTS5158-GR_LQFP48_7x7 R325 RST#
0_0402_5% SD_MS_CLK
1 C396
1
@
2
XD_CLE/CF_SP19 XD_CE#/CF_D11_SP18 XD_ALE/CF_D4_SP17 SD_DAT2/XD_RE#/CF_D12_SP16 SD_DAT3/XD_WE#/CF_D5_SP15 XD_RDY/CF_D13_SP14 SD_DAT4/XD_WP#/CF_D6_SP13 SD_DAT5/XD_D0/CF_D14_SP12 SD_CLK/XD_D1/MS_CLK/CF_D7_SP11 SD_DAT6/XD_D7/MS_D3/CF_D15_SP10 MS_INS#/CF_IORD#_SP9 SD_DAT7/XD_D2/MS_D2/CF_IOWR#_SP8 SD_DAT0/XD_D6/MS_D0/CF_RST#_SP7 SD_DAT1/XD_D3/MS_D1/CF_IORDY_SP6 XD_D5/MS_BS/CF_A2_SP5 CF_A1/XD_D4_SP4 CF_A0/SD_CD#_SP3 CF_D0/SM_WPM#/XD_WP_SP2 CF_D1/XD_CD#_SP1 CF_D8/SM_CD#_SP0
10 22 30
VDD_SD DAT0_SD DAT1_SD DAT2_SD CD/DAT3_SD CLK_SD WP_SD CMD_SD CD_SD VSS_SD VSS_SD
1
R326 10K_0402_5%
2
1
1
C395 0.1U_0402_16V4Z
VREG CF_DMACK# CF_CS0#
6 9 10 2 3 7 11 4 1 5 8
XDD6_SDD0_MSD0 XDD3_SDD1_MSD1 XDRE#_SDD2 XDWE#_SDD3 SD_MS_CLK SDWP SDCMD SDCD#
2
2
R324 100K_0402_5%
6 46
+VCC_4in1
1
1
MODE SEL B
JP16
AV_PLL A3V3 A3V3 CARD_3V3 D3V3 D3V3
8 44 45 47 48
0.1U_0402_16V4Z 20 20
3 in 1 Card Reader
U13
Used 9701 by 10K
2
2 0_0402_5%
R327 1U_0603_10V4Z 2
@ 10_0402_5%
1
2
C397 10P_0402_50V8J
2
@
A
A
Compal Electronics, Inc. Title
Card reader board THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet 1
26
of
43
A
B
C
D
E
F
G
H
+VDDA_ALC268 1
28.7K for Module Design (VDDA = 4.702)
+5VS
1
1
R4531U_0603_10V4Z 1
U14 4
VIN
1 1 L12 1 C399 C400 2 KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z 2 2 0.1U_0402_16V4Z
2
DELAY
7 8
10K_0402_1%
VOUT
5
SENSE or ADJ
6
CNOISE
1
ERROR SD
GND
3
40mil
1
C402
4.85V
1
2
C401 10U_0805_10V4Z 1
SI9182DH-AD_MSOP8
2
+VDDA
R329 30K_0402_1%
1
2
C502 2
(output = 250 mA)
60mil
L11 1 2 KC FBM-L11-201209-221LMAT_0805
2
10K_0402_1%
1
+5VAMP
R452
2 PCBEEP_R
R331 10K_0402_1%
0.1U_0402_16V4Z 2
1U_0603_10V4Z
1
R454
1
2
C504 20
2
SB_SPKR
1
R455
1
C
Q38
E
2SC2411K_SOT23
2 B
560_0402_5%
3
2
EC_BEEP
1
C503 32
2
D29
HD Audio Codec
RB751V_SOD323
+VDDA_ALC268
1
MIC_IN_R
2
MIC_IN_R
1
2
C413
MIC_IN_C_L 16 2.2U_0603_6.3V4Z MIC_IN_C_R 17 2.2U_0603_6.3V4Z 23 24 18 20 19
C398 1U_0603_10V4Z 1 2
PCBEEP_C @ R330 1 5.1K_0402_5% 2
28
MIC_EXT_L
28
MIC_EXT_R
MIC_EXT_L
1 C417 MIC_EXT_R 1 C418
2 2
PCBEEP
ACZ_RST#
19,32 ACZ_RST#
3
19 19
R339 1 R340 2
28 HP_DET# 28 EXTMIC_DET#
MIC_EXT_C_L 21 2.2U_0603_6.3V4Z MIC_EXT_C_R 22 2.2U_0603_6.3V4Z 12 11 10
ACZ_SYNC
5
ACZ_SDOUT
2 3 13 34
SENSE_A
2 39.2K_0402_1% 1 20K_0402_1%
47
T48
48 4 7
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-G (PIN 43, 44)
5.1K
PORT-H (PIN 45, 46)
35
LINE_OUTL
LINE_OUT_R
36
LINE_OUTR
MIC2_L
HP_OUT_L
39
HP_OUTL
MIC2_R
HP_OUT_R
41
HP_OUTR
LINE1_L
NC
LINE1_R
DMIC_CLK
CD_L
NC
CD_R
NC
CD_GND BIT_CLK
LINE_OUTL 28 LINE_OUTR 28 HP_OUTL 28 HP_OUTR 28
45 46 43 R336 2 22P_0402_50V8J1
44 C416 1 6
0_0402_5% 2 ACZ_BITCLK 19
MIC1_L MIC1_R
SDATA_IN
PCBEEP
MONO_OUT LINE1_VREFO
RESET# GPIO1 SYNC MIC1_VREFO_L SDATA_OUT MIC1_VREFO_R GPIO0 GPIO3 SENSE A SENSE B
MIC2_VREFO VREF
EAPD
JDREF
SPDIFO
NC
DVSS1 DVSS2
AVSS1 AVSS2
R337 1
8
DGND
2 33_0402_5%
ACZ_SDIN0 19
37 29 3
31
10mil
28
MIC1_VREFO_L
32
MIC1_VREFO_R
30
MIC2_VREFO CODEC_VREF
27
10mil 1
40 33 26 42
C419 10U_0805_10V4Z 2 R342 20K_0402_1%
AGND
2 0_0805_5%
1 R344
2 0_0805_5%
1 R345
2 0_0805_5%
GND
GNDA
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2006/08/18
2007/8/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
1 R343
om
20K
LINE_OUT_L
NC
l.c
SENSE B
PORT-A (PIN 39, 41)
2
ai
4
39.2K
NC
ALC268-GR_LQFP48_9X9
Codec Signals
10U_0805_10V4Z
B
C
D
E
nf @ ho tm
SENSE A
Impedance
2
F
Title
HD Audio Codec ALC268 Size B
Document Number
LA-3821P
Date:
Tuesday, July 31, 2007 G
R ev 0.3
ai
Sense Pin
2
he x
PCBEEP_R
R328 0_0402_5% 1 2
+3VS
C408
0.1U_0402_16V4Z
1
28
1 C412
1
C407
2
MIC_IN_L
2 1
U15
15 MIC_IN_L
1
C411
2 0.1U_0402_16V4Z
14
28
C406
L13 MBK1608301YZF_0603 2 1
9
2
+3VS_DVDD
0.1U_0402_16V4Z
40mil 1
DVDD
2
20mil
DVDD_IO
0.1U_0402_16V4Z 1 C410
38
C409 10U_0805_10V4Z
2
1
25
L14 1 2 FBM-L11-160808-800LMT_0603
AVDD2
+VDDA
AVDD1
2
@ R456 10K_0402_5%
2
1
1U_0603_10V4Z
1
560_0402_5%
Sheet
27 H
of
43
4
A
B
C
+5VAMP
R346 0_1206_5% 1 2
0.1U_0402_16V4Z
1 C421 10U_0805_10V4Z
1
MIC INT In-L JP35 MICIN_L
C423
2
E
@ C430 47P_0402_50V8J 2 1
1
C422
2
D
+5VS
27
2 0_0603_5%
MIC_IN_L
2
1 R351
2 0_0603_5%
1 L20
2 0_0603_5%
1
@
1 2 3 4
1 L22
C509 0.1U_0402_16V4Z
47P_0402_50V8J
10 dB
ACES_85204-02001 CONN@
2
+5VS
LINE_OUTL
LINE_OUTR_R
1 R457 1 R458
2 2
0_0603_5% C431 @
17
RIN-
0_0603_5% 0_0603_5%
1
2 0.47U_0603_10V7K
9
GAIN1
3
2 0.47U_0603_10V7K
5
27
ROUT+
18
SPKR+
ROUT-
14
SPKR-
M ICIN_R 2 1 R441 0_0603_5%
2 0_0603_5%
MIC_IN_R
LINLOUT-
@ R349 100K_0402_5%
R350 100K_0402_5%
4
2
MIC2_VREFO
1
EC_MUTE#
EC_MUTE#
19
SHUTDOWN
10
R448 1
M ICIN_R
2.2K_0402_5% 2
MICIN_L
1 2 3 4
1 L23
2
2.2K_0402_5% 2
2
Keep 10 mil width
1
R449 1
1 2 G1 G2
ACES_85204-02001 @ CONN@
1
2
1
2
@
MIC EXT In
CH751H-40PT_SOD323-2 27
2
GND5 GND1 GND2 GND3 GND4
32
BYPASS
2 0_0603_5% C510
1 2 ACES_85204-0200 CONN@
CH751H-40PT_SOD323-2
D28
12
1
@ 47P_0402_50V8J
8
NC
1 L21
D25
LOUT+
JP36 SPKR+ SPKRJP37
LIN+
R459 C492 1
2
2 2
1
1
GAIN0
1
2
RIN+
EMI C497 47P_0402_50V8J
27
LINE_OUTR
7
7/31
MIC INT In-R
@ C499 47P_0402_50V8J 2 1
2
27
2 0.47U_0603_10V7K
2
C428 1
1
SPEAKER
@ R348 100K_0402_5%
C498 47P_0402_50V8J
R347 100K_0402_5%
VDD PVDD1 PVDD2
U16
1
16 15 6
1
1
2
1 2 G1 G2
1
C433 0.47U_0603_10V7K
EXTMIC_DET#
EXTMIC_DET#
2
JP19 @
C435 47P_0402_50V8J 2 1
5
21 20 13 11 1
4 27
MIC_EXT_R
MIC_EXT_R
2R353
10_0603_5%
MICEXT_R
27
MIC_EXT_L
MIC_EXT_L
2
1
MICEXT_L
0_0603_5%
2 R389 1
2.2K_0402_5% MICEXT_R 2
MIC1_VREFO_L
R447 1
2.2K_0402_5% MICEXT_L 2
@ D15 SM05_SOT23
1
MIC1_VREFO_R
FOX_JA6333L-B3S0-7F~N CONN@
1
@ C434 47P_0402_50V8J
2
R352
10 9 8 7
3 6 2 1
3
P3017THF D0 TSSOP 20P
3
3
HeadPhone Out/Line Out 27
HP_DET#
HP_DET# JP20
@ C436 47P_0402_50V8J 2 1
HP_OUTL
2 100U_D2_6.3VM C438
HP_OUTL
1
HP_OUT_R
2 100U_D2_6.3VM HP_OUT_L
R356 2
0_0603_5% 1
2 R357
1 0_0603_5%
4 PR PL
EC_MUTE
1
S
D
3
EC_MUTE
1
32
D
3
S
2
2 1 @C439 47P_0402_50V8J Q18 EC_MUTE 2 G 2N7002_SOT23-3
10 9 8 7
3 6 2 1 FOX_JA6333L-B3S0-7F~N CONN@
Q19
2 G 2N7002_SOT23-3
D16 @ SM05_SOT23
1
27
HP_OUTR 1
+
HP_OUTR
+
C437 27
5
3
cap. high 5.7mm
0302_Change Audio Jack.
4
4
Compal Secret Data
Security Classification 2006/02/13
Issued Date
Deciphered Date
2007/08/29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. AMP & Audio Jack
Size
Document Number
R ev 0.3
LA-3821P D ate:
Tuesday, July 31, 2007
Sheet E
28
of
43
5
4
3
2
1
+5VALW
+USB_VCCB U23 1 2 3 4
C446 0.1U_0402_16V4Z 2 1 33,37 SYSON#
GND IN IN EN#
8 7 6 5
OUT OUT OUT FLG
+5VALW D
+USB_VCCA 0.1U_0402_16V4Z 1000P_0402_50V7K
USB Port
USB_OC#2 20
RT9711PS_SO8
2nd source:SA005280110
1
C447
For EMI
+USB_VCCA U17 C443 0.1U_0402_16V4Z 2 1 33,37 SYSON#
R360
GND IN IN EN#
8 7 6 5
OUT OUT OUT FLG
0_0402_5% 1
1
RT9711PS_SO8
R361 0_0402_5%
2nd source:SA005280110
L15 1 1
20 USB20_N0 20 USB20_P0
4
2
2
C441 C448
2
1
1
2
2
D
C442 1000P_0402_50V7K
2 0.1U_0402_16V4Z
4
3
2
USB20_N0_R USB20_P0_R
3
2
WCM2012F2S-900T04_0805 1
USB_OC#1 20
1
2 100U_6.3V_M
USB_OC#0 20 1
1 2 3 4
C440
+
2
R362
1
1
C444 @ 10P_0402_50V8J 2
2
C445 @10P_0402_50V8J
0_0402_5% +USB_VCCA JP17
BT Connector
USB20_N1_R USB20_P1_R
JP39 1 0_0402_5% 1 0_0402_5% 2@ 1K_0402_5% 2@ 1K_0402_5%
+3VALW
2
4
3
2
USB20_N1_R USB20_P1_R
3
1
C449 @ 10P_0402_50V8J
2
R368
1
1
2
2
C
SUYIN_020122MR008S535ZA
C450 @10P_0402_50V8J
0_0402_5%
1
2
1
1
C451
For EMI
100U_D2_6.3VM
1
R372 1
+
C452
2
1
1
2
2
C453 1000P_0402_50V7K
2 0_0402_5%
2
0.1U_0402_16V4Z
1
2
2 4.7U_0805_10V4Z
2 47K_0402_5%
2
0.1U_0402_16V4Z
C458
2
0.1U_0402_16V4Z
B
L17 4 20 20
1
2
3 2
C459 @ 10P_0402_50V8J
1
1
2
2
C460 @
0_0402_5%
1
D18 PSOT24C_SOT23-3 @
USB20_N6 USB20_P6
1 2 3 4 G1 G1
1 0_0402_5% 1 0_0402_5%
2
20 20
R373 2 R374 2 3
1 2 3 4 5 6
D19 PSOT24C_SOT23-3 @ 1
E&T_3802-E04N-01R CONN@
B
SUYIN_020173MR004S558ZL CONN@
1
2
USB20_N7_R USB20_P7_R
1 2 3 4 GND GND GND GND
+3VS
PC Camera
2
JP25
USB20_N6_R USB20_P6_R
1 2 3 4 5 6 7
1 2 3 4 5 GND1 GND2
ACES_88266-05001 CONN@ A
Compal Secret Data 2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. USB CONN.
Size
Document Number
LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
1
om
1 0_0402_5% 1 0_0402_5%
1 2 3 4 5 6 7 8
USB20_P2_R USB20_N2_R
10P_0402_50V8J
JP26 R375 2 R376 2 3
3
R370
2
A
1
JP24
4
C461 0.1U_0402_16V4Z C462 0.1U_0402_16V4Z
USB20_N7 USB20_P7
USB20_P2 USB20_N2
WCM2012F2S-900T04_0805 1 2
+3VS
Finger printer
20 20
4
CONN@
1
WCM2012F2S-900T04_0805
C457
1
07/23
USB20_N1 USB20_P1
D
R369 100K_0402_5%
R371 1
BT_OFF
20 20
+USB_VCCB
G
32
2
AP2305GN 1
S
C454
1U_0603_10V4Z
2
1
+3VAUX_BT
Q20
3
1
D17 PSOT24C_SOT23-3 @
C456
ACES_87213-0800G CONN@
0_0402_5%
L16 1
2
Change value. 5/10 Reserve R674,R677 cause BlueFlame co-existance issue. 6/14
USB20_N0_R USB20_P0_R
R365
USB20_P5 20 USB20_N5 20 CH_CLK 22 CH_DATA 22 BT_LED 30
3
2 2 1 1
C455
10
R363 R364 R367 R366
0.01U_0402_16V7K
C
For EMI
+3VAUX_BT USB20_P5_R USB20_N5_R
1
1 2 3 4 5 6 7 8
GND 1 2 3 4 5 6 7 GND 8
RV to Install. 5/10
9
1 2 3 4 5 6 7 9 8 10
Sheet
1
29
of
43
5
4
3
2
1
Power ON/OFF 2
+3VALW
R379
ON/OFFBTN#
D
2
ON/OFF
3
51ON#
1
ON/OFF 32 51ON#
2 5 6
36
T/P Board
1
DAN202U_SC70
O
Q21 DTC124EK_SC59
TP_DATA TP_CLK
1
3
4
D23
2
SW1 SMT1-05-A_4P 3 1
1
4.7K_0402_5% D
D26 PSOT24C_SOT23-3 @
2 C463 1000P_0402_50V7K
1
1
3
I 2
G
0216_Delete D19. +3VALW
R383 4.7K_0402_5%
EMI request
2
+5VS EC_ON
JP29
+3VS +3VL 1
EC_ON
1
32
2
0_0402_5%
R470 0_0402_5%
2
R469
CONN@
G2 G1 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TP_DATA TP_CLK
TP_DATA 32 TP_CLK 32
1 @ C464 2
ACES_87151-06051
0.1U_0402_16V4Z
@ C
2 32 32
I2C_INT LID_SW#
CAP_DATA
Change pin define for try ENE cap bottom
Battery Charge LED(Left 2)
@C465 100P_0402_50V8J 2
Wireless ON Amber Bluethooth ON Blue 07/23
POWER LED1 +5VS
2
2
32 AMBER_LED#
3
4
2
1
+5VALW
R386
Orange
31,32 ON/OFFBTN_LED#
ON/OFFBTN_LED# 1
2
1
820_0402_5%
R381 820_0402_5%
2
AMBER 2
1
2 470_0402_5%
+5VS LTST-C191TBKT-5A_BLUE_0603~D
29 R380 2
LTST-C191TBKT-5A_BLUE_0603~D
1
WL_LED#
2
AMBER
BT_LED
D
S
WL_LED#
06/04
WL_LED# 22
Q25 2 2N7002_SOT23-3 G
POWER LED2
2
D24 Blue
R384
1
1
BLUE 1
1
4.7K_0201_5%
LTST-C195TBKFKT_BLUE/ORG D21
19 SATA_LED#
R382 200_0402_5%
BLUE
LTST-C195TBKFKT_BLUE/ORG
D22
R232
470_0402_5% LTST-C191TBKT-5A_BLUE_0603~D
1
HDD LED(Left 3)
B
1
R377
4 2
1
+3VS
+5VALW
D20
1
200_0402_5%
R385
BLUE_LED#
32
@C466 100P_0402_50V8J
+5VS
BLUE D27 Blue
2
ACES_85203-08421-11_8P CONN@
BLUE B
TP_CLK 1
3
06/15
CAP_CLK
@ +5VS
CAP_CLK CAP_DATA
1 9 10 11 12 13 14 15 16
Orange
ESB_DATA
0_0402_5% 2 0_0402_5% 2
1 2 3 4 5 6 7 8
2 2
R465 @ ESB_CLK 1 R466 ESB_DATA 1 @
ESB_CLK
@
32 CAP_RESET
JP38
1
4,32 SMB_EC_DA2
07/23
3
4,32 SMB_EC_CK2
0_0402_5% 2 0_0402_5% 2
TP_DATA
2 1 R444 10K_0402_5%
R463 SMB_EC_CK2 1 R464 SMB_EC_DA2 1
1 R442 4.7K_0402_5% 2 1 R443 4.7K_0402_5%
C
470_0402_5%
A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
Deciphered Date
2006/07/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. LED/SW
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet 1
30
of
43
+3VALW 1
+3VALW
1 R390 100K_0402_5%
2
U18 8 7 6 5
32,40 SMB_EC_CK1 32,40 SMB_EC_DA1
2
C467 0.1U_0402_16V4Z
VCC WP SCL SDA
A0 A1 A2 GND
1 2 3 4
LPC Debug Port 1
AT24C16AN-10SI-2.7_SO8
Change from +3VL to +3VS. 6/9 Removed +3VS. 6/13
2
R391 100K_0402_5%
B+
JP30 15 CLK_DEBUG_PORT_1
SPI ROM
19,22,32 LPC_FRAME#
+3VALW U19
32
FWR#
1 R392 1 R393 FWR# 1 R394
SPI_FSEL# 2 0_0402_5% SPI_CLK_R 2 0_0402_5% SPI_FWR# 2 0_0402_5%
1
S
6 5
ON/OFFBTNLED# CAPSLED# NUMLED# VCC1PWRGD SPI_CLK_JP52 SPI_CS#_JP52 SPI_SI_JP52 SPI_SO_JP52 SPI_HOLD#_0
C SPI_SO 1 2 D Q R395 CONN@ WIESON G6179 8P SPI
2 FR D# 0_0402_5%
FRD#
32
Connect pin3 & 23 together and pin 24 to GND in 6/29.
&U19
SST25LF080B_SO8-200mil
B-Test
remove SPI ROM socket
+3VALW
DEBUG@ R396 SPI_CLK_R 1
0_0402_5% 2
SPI_CLK_JP52
FSEL#
DEBUG@ R397 1
0_0402_5% 2
SPI_CS#_JP52
FWR#
DEBUG@ R398 1
0_0402_5% 2
DEBUG@ R399 1
0_0402_5% 2
DEBUG@ R400 1
0_0402_5% 2
HOLD# FR D#
30,32 ON/OFFBTN_LED# 32 32
CAPS_LED# NUM_LED#
32 VCC1_PWRGD
ACES_87216-2404_24P CONN@
1
2
DEBUG@ R401 1
0_0402_5% 2
DEBUG@ R402 1
0_0402_5% 2
DEBUG@ R403 1
0_0402_5% 2
DEBUG@ R404
0_0402_5%
SPI_SI_JP52 SPI_HOLD#_0 SPI_SO_JP52 ON/OFFBTNLED# CAPSLED# NUMLED# VCC1PWRGD
om
SPI_CLK
HOLD
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
l.c
FSEL#
32
W
7
4
ai
32
3
VSS
Compal Secret Data
Security Classification Issued Date
2006/02/13
Deciphered Date
2006/07/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
nf @ ho tm
2
VCC
Compal Electronics, Inc. BIOS ROM
Size
Document Number
LA-3821P Date:
Tuesday, July 31, 2007
ai
C468 0.1U_0402_16V4Z
8
PCI_RST#
Ground LPC_PCI_CLK Ground LPC_FRAME# +V3S LPC_RESET# +V3S LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 VCC_3VA PWR_LED# CAPS_LED# NUM_LED# VCC1_PWRGD SPI_CLK SPI_CS# SPI_SI SPI_SO SPI_HOLD# Reserved Reserved Reserved
he x
20mils 1
18,32 19,22,32 19,22,32 19,22,32 19,22,32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Sheet
31
of
43
R ev 0.3
+3VALW_EC
C472
C473
+EC_AVCC M/B_ID
@ R408 1
GATEA20 1 KB_RST# 2 SIRQ 3 LPC_LFRAME# 4 LPC_LAD3 5 LPC_LAD2 7 LPC_LAD1 8 LPC_LAD0 10
19 GATEA20 19 KB_RST# 20 SIRQ 19,22,31 LPC_FRAME# 19,22,31 LPC_AD3 19,22,31 LPC_AD2 19,22,31 LPC_AD1 19,22,31 LPC_AD0
2
15P_0402_50V8J 33_0402_5%
CLK_PCI_EC PCI_RST# ECRST# EC_SCI#
15 CLK_PCI_EC 2 R409 1 47K_0402_5%
2
2
0.1U_0402_16V4Z
0_0402_5% 2 0_0402_5% 2
ESB_DATA
EC_SUSP# EC_PWRBTN_OUT# 31,40 31,40 4,30 4,30
20 20 20 30
EC_PIN18
1 CONN@ JP32 +5VALW 3 2
77 78 79 80
SLP_S3# SLP_S5# EC_SMI# LID_SW# EC_PIN17 EC_PIN18 PCI_PME#
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
4 30
FAN_SPEED CAP_RESET
CAP_RESET UTX URX ON/OFF CPUSB# NUM_LED#
C R Y2
2
27P_0402_50V8J C478 NC OUT 4
122 123
PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
@ 20M_0402_5% R422
NC IN 1 Y5 32.768KHZ_12.5P_1TJS125DJ2A073 C R Y1 1 2
FOR LPC SIO DEBUG PORT
27P_0402_50V8J C479
CONN@ JP33
AVCC
EC_MUTE# 28 ACZ_RST# 19,27
TP_CLK TP_DATA
100K+/-5%
Board ID
Rb
V AD_BID min
V AD_BID typ
0
0V
0V
0V
1
8.2K+/-5%
0.216V
0.250V
0.289V
2
18K+/-5%
0.436V
0.503V
0.538V
3
33K+/-5%
0.712V
0.819V
0.875V
4
56K+/-5%
1.036V
1.185V
1.264V
5
100K+/-5%
1.453V
1.650V
1.759V
6
200K+/-5%
1.935V
2.200V
2.341V
7
NC
2.500V
3.300V
3.300V +5VS
TP_CLK 30 TP_DATA 30
CLK_ENABLE R411 CLK_ENABLE 15 2 1 10K_0402_5% LAN_POWER_OFF LAN_POWER_OFF 24
TP_CLK 2 1 10K_0402_5% R410 TP_DATA 2 1 10K_0402_5% R412
FR D# FWR# SPI_CLK FSEL#
FRD# FWR# SPI_CLK FSEL#
Remove T/P dis/ena
31 31 31 31
C505 AC IN
1
2
100P_0402_50V8J 73 74 89 90 91 92 93 95 121 127
110 112 114 115 116 117 118
V18R
124
I2C_INT VCC1_PWRGD FSTCHG
04/17
I2C_INT 30 VCC1_PWRGD 31 FSTCHG 35 AMBER_LED# 30 CAPS_LED# CAPS_LED# 31 BAT_LED# BLUE_LED# 30 ON/OFFBTN_LED# ON/OFFBTN_LED# 30,31 SYSON SYSON 23,33,37 VR_ON VR_ON 39 AC IN ACIN 35 2 1 R419 10K_0402_5% EC_RSMRST# EC_RSMRST# 20 R420 1 0_0402_5% 2 EC_LID_OUT# 20 EC_ON EC_ON 30 BT_OFF 29 PM_PWROK PM_PWROK 7,20 BKOFF# BKOFF# 17 M_PWROK M_PWROK 7,20 EC_MUTE 28 WL_ON# WL_ON# 22
04/14
05/03
SLP_S4# ENABLT
SLP_S4# 20 ENABLT 9,17
THERM_SCI# EC_SUSP# EC_PWRBTN_OUT#
04/04
THERM_SCI# 20
KB926QFB0_LQFP128_14X14
05/23 EC request
For EMI KSO14 KSO11 KSO10 KSO15
JP31 KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CP1 1 2 3 4
8 7 6 5
@ 100P_1206_8P4C_50V8 CP2 1 8 2 7 3 6 4 5
KSO6 KSO3 KSO12 KSO13
@ 100P_1206_8P4C_50V8 KSO2 KSO4 KSO7 KSO8
CP3 1 2 3 4
8 7 6 5
@ 100P_1206_8P4C_50V8 CP4 1 8 2 7 3 6 4 5
KSI3 KSO5 KSO1 KSI0
@ 100P_1206_8P4C_50V8 25 26
+EC_AVCC
L18 0_0603_5%
GND1 GND2 ACES_85201-24051 CONN@
KSI4 KSI5 KSO0 KSI2
CP5 1 2 3 4
8 7 6 5
@ 100P_1206_8P4C_50V8
1 LPC_DRQ#0 19
V AD_BID max
0
SP01000FF00 85201-24051 24P P1.0 ACES_85201-24051_24P
L19
2
R421 100K_0402_5%
1 C480
2
1
2 0_0603_5%
CP6 KSI1 KSI7
0.1U_0402_16V4Z
CLK_DEBUG_PORT_1 SIRQ
ACES_85201-2005
DAC_BRIG 17 EN_FAN 4 IREF 35
3.3V+/-5%
Ra
2
06/14 119 120 126 128
PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7
1 SUSP#
CLK_14M_DEBUG 15
BATT_TEMP 40 BATT_OVP 35 ADP_I 35
VCC
R407 0_0402_5%
2
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ#0 PCI_RST#
2 ECAGND 0.01U_0402_16V7K
05/23 change to voltage control FAN
EC_MUTE# ACZ_RST#
97 98 99 109
35 1 C475
+3VALW_EC
+5VS +3VS
BATT_TEMP BATT_OVP ADP_IN M/B_ID
83 84 85 86 87 88
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 G PO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11
GPI
ACOFF
DAC_BRIG EN_FAN IR EF
100 101 102 103 104 105 106 107 108
XCLK1 XCLK0
2
ACES_85205-0400
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PCI_PME#
30 ON/OFF 20,23 CPUSB# 31 NUM_LED#
EC DEBUG port
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SLP_S3# SLP_S5# EC_SMI# LID_SW#
18
05/23 change to voltage control FAN
URX UTX
SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2
INV_PWM 17 EC_BEEP 27
ACOFF
68 70 71 72
EC_PIN17
Change pin define for try ENE cap bottom
1 2 3 4
SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2
63 64 65 66 75 76
INV_PWM EC_BEEP
AGND
R461 @ ESB_CLK 1 R462 ESB_DATA 1 @
DA Output
KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 PSCLK1/GPIO4A KSI4/GPIO34 PSDAT1/GPIO4B KSI5/GPIO35 PSCLK2/GPIO4C PS2 Interface KSI6/GPIO36 PSDAT2/GPIO4D KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 SDICS#/GPXOA00 KSO4/GPIO24 SDICLK/GPXOA01 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 KSO6/GPIO26 Matrix SDIDI/GPXID0 SPI Device Interface KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 SPIDI/RD# KSO10/GPIO2A SPIDO/WR# SPI Flash ROM SPICLK/GPIO58 KSO11/GPIO2B KSO12/GPIO2C SPICS# KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F CIR_RX/GPIO40 KSO16/GPIO48 CIR_RLC_TX/GPIO41 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 GPIO BATT_LOW_LED#/GPIO54 SCL1/GPIO44 SDA1/GPIO45 SUSP_LED#/GPIO55 S M Bus SCL2/GPIO46 SYSON/GPIO56 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59
69
0_0402_5% 2 0_0402_5% 2
WL_BTN#
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82
DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F
21 23 26 27
ECAGND
@ 1 R460 PWRBTN_OUT#1 @
AD
PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D
BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43
GND GND GND GND GND
ESB_CLK
2
2 0_0402_5% 2 0_0402_5% 2
R451
20 PWRBTN_OUT#
R414 10K_0402_5%
LID_SW#
SUSP#
23,33,35,37,38 SUSP#
1
1
2
2
2
SMB_EC_DA1 SMB_EC_CK1 SMB_EC_DA2 SMB_EC_CK2 R467 SUSP# 1 R468 PWRBTN_OUT# 1
1 2 3 4
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
+3VS
R413 10K_0402_5%
PWM Output
JOPEN
1
1
R416 4.7K_0402_5% 4.7K_0402_5%
1
1
R415
R417 R418 4.7K_0402_5% 4.7K_0402_5% 2
EC_SCI#
J1
+5VALW +3VALW
06/15
PCI_RST#
20
0.1U_0402_16V4Z
INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13
1
+3VS
18,31
GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC
11 24 35 94 113
1
1
+3VALW C477
12 13 37 20 38
Rb
1
@ C474
VCC VCC VCC VCC VCC VCC
U20
@ C476 1 2
100K_0402_5%
R406 2 1 0_0805_5%
2
2
+3VALW_EC
1
C471
2 2 1000P_0402_50V7K
R405
+3VALW
2
C470
1000P_0402_50V7K 1
67
C469 2 2 0.1U_0402_16V4Z
0.1U_0402_16V4Z 1
9 22 33 96 111 125
0.1U_0402_16V4Z 1 1
1
Ra
1
+3VALW_EC
@ R423 10K_0402_5% 2 1
1 2 3 4
8 7 6 5
@ 100P_1206_8P4C_50V8
CLK_DEBUG_PORT_2 15
Compal Secret Data
Security Classification Issued Date
2006/02/13
Deciphered Date
2006/07/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Compal Electronics, Inc. EC KB926/KB conn
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet
32
of
43
A
B
C
D
E
C488
+5VALW to +5VS Transfer
1
+3VALW to +3VS Transfer
1
+VCC_CORE
2
+VCCP
1
0.1U_0402_16V4Z +5VALW
+5VS
+3VALW
+3VS
B+ U21
C481
S S S G
1 2 3 4
8 7 6 5
1
D D D D
R424 1
AO4466_SO8 2 10U_0805_10V4Z
1
C483
2
2
C484
1
C482
D D D D
330K_0402_5%
C489
10U_0805_10V4Z
10U_0805_10V4Z
1 2 3 4
S S S G
1
AO4466_SO8 2 10U_0805_10V4Z
2
1
8 7 6 5
U22
C485
2
1
1
+VCCP
2
+1.5VS
0.1U_0402_16V4Z C486
2
RU NON 1
RU NON 0.1U_0402_16V4Z
0.1U_0402_16V4Z
D
S
470_0402_5% 2
1 SUSP
3
R425
Q28 2N7002_SOT23-3
2 G
1
2
C487 0.01U_0402_16V7K
2
2
1
+5VALW
1
+5VALW
100K_0402_5%
S
Q30 2N7002_SOT23-3
470_0402_5% 2
H29 HOLEA
1
3
1
H22 HOLEA
H31 HOLEA
1
1
H28 HOLEA
1
H27 HOLEA
H21 HOLEA
1
1
1
1
1
1
1
1
H26 HOLEA
H20 HOLEA
H14 HOLEA
D
S
Q36 SUSP 2 2N7002_SOT23-3 G
Q37 2N7002_SOT23-3
1
S
Q35 SUSP 2 2N7002_SOT23-3 G
H25 HOLEA
H19 HOLEA
H13 HOLEA
H32 HOLEA
1
D
3
S
Q34 SUSP 2 2N7002_SOT23-3 G
1
D
3
S
Q33 SUSP 2 2N7002_SOT23-3 G
1
D
3
S
SYSON# 2 Q32 2N7002_SOT23-3 G
1
1
D
H18 HOLEA
H12 HOLEA
1
1
1 R434
470_0402_5% 2
R433
470_0402_5% 2
R432
470_0402_5% 2
R431
470_0402_5% 2
R430
H24 HOLEA
H17 HOLEA
H11 HOLEA
1
H23 HOLEA
+0.9V
1
1
+VCCP
470_0402_5%
3
S
Q31 SUSP 2 2N7002_SOT23-3 G
2 G
+1.25VS
R429
2 1
S
D
3
2 1 3
SUSP
D
+1.5VS
3
R428 470_0402_5%
+1.8V
1
1
+3VS
1
+5VS
1
Discharge circuit
H16 HOLEA
H10 HOLEA
1
1
H15 HOLEA
H9 HOLEA
1
3
H8 HOLEA
1
H7 HOLEA
1
S
1
3
D
SUSP# 2 G
23,32,35,37,38 SUSP#
1
Q29 2N7002_SOT23-3
2 G
1
SYSON
23,32,37 SYSON
SUSP
SUSP
1
37 D
3
SYSON#
SYSON#
1
29,37
2
R427
100K_0402_5% 2
R426
1
FM1 1
FM2
FM3 1
FM4 1 4
Compal Secret Data 2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. DC/DC Interface
Size
Document Number
LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
T u es day , J u l y 3 1 , 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
4
Sheet
E
33
of
43
A
B
C
D
1
1
2
2
VIN PL1 SMB3025500YA_2P 1
1
2
PC3 100P_0402_50V8J 2 1
1 PC2 1000P_0402_50V7K
2
3
SINGA_2DC-S756B200
1
2
2
G G
A DPIN
PC4 1000P_0402_50V7K 2 1
PCN1
PC1 100P_0402_50V8J
3
3
4
4
Compal Secret Data
Security Classification Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title Size Document Number C ustom D ate:
DC CONN
R ev
LA-3821P Sheet
Tuesday, July 31, 2007 D
34
of
43
A
B
C
D
P2 V IN PQ1 FDS4435BZ_SO8
4 1
4
PACIN
ACIN XACOK
18
8
-INE1
RT
17
9
+INE1
-INE3
16
10
OUTC1 FB123
15
11
SEL
14
1
P R27 33K_0402_1% M B39A126 1
CTL
-INC1
+INC1
13
2 1 1 3
1
PQ7 RHU002N06_SOT323-3
3
1 P D2 EC31QS04
1
1
2
BATT
2
0.02_2512_1%
F STCHG
RB751V-40_SOD323-2 P D4 1 2
SUSP#
23,32,33,37,38
RB751V-40_SOD323-2
3
2
2
CV=12.6V (6/12 CELLS LI-ION) CC=3.08A (6/12 CELLS LI-ION)
P R36 100K_0402_5% 1
1
PU4A LM358ADT_SO8
+5VALW
BATT_DET 40
2 G 3
S
P U4B LM358ADT_SO8
4
P
+
5
G
8 7
3
D PQ12 RHU002N06_SOT323-3
PQ13 RHU002N06_SOT323-3
2
+3VALW
P R34 100K_0402_5%
1
2
D
S PQ14 DTC115EUA_SC70-3
+3VALW
2 3
-
2
1
2
16UH_SIL104R-160PF_3.6A_30%
P C24 1500P_0402_50V7K 21 2
P C25 10P_0402_50V8J 1 2
1
2 8 P
+
0 4
1
G
P R37 10K_0402_5% 1 2
CS
2 G
1
P C27 47P_0402_50V8J 1 2
2
1
P C10 4.7U_1206_25V6K
P R19 47K_0402_1% 1 2
P D3
P C30 0.01U_0402_25V7K
NC
P C9 4.7U_1206_25V6K 2 1
1 2 3
1 P R13
2
P R17
PL3
P C21 10U_1206_25V6M 2 1
7
P C16 0.1U_0603_25V7K 1 2
P C20 10U_1206_25V6M 2 1
VH
32
FDS4435BZ_SO8
1
VREF
A COFF
2
P C19 10U_1206_25V6M 2 1
20 19
3
OUT
DTC115EUA_SC70-3
5 6 7 8
ACOK
6
1 2 1 P R35 P R33 499K_0402_1% 340K_0402_1%
2
1 P R39 105K_0402_1%
NC
1
3
ANODE
P R38 47K_0402_1%
-
6
4
0
4
A
B
C
Compal Electronics, Inc. Charger
Dat e:
Tu esday, July 31, 2007 D
Rev
l.c
Size D ocument Number Cus t om
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
nf @ ho tm
Deciphered Date
ai
Issued Date
om
Compal Secret Data
Security Classification
he x
1 2
5
2
+5VALW
1 .24VREF
CATHODE
P C29 0.01U_0402_25V7K
REF
32 BATT_OVP
1
21
BATT P U3
3
VCC
PQ11
4
P C13 0.22U_0603_16V7K 1 2 P C14 0.1U_0603_25V7K 1 2
2 G PQ10 S RHU002N06_SOT323-3
S
PQ8
P R31 10K_0402_5% 2
P C28 22P_0402_25V8K 2 1
-INE2
D
D
RLZ4.3B_LL34
P R32 1 2 49.9K_0402_1%
+3VALW
F STCHG
4
CS
36
LMV431ACM5X_SOT23-5
32
22
+3VLP
P R9 100K_0402_5% 2 1 2 G
1
G
P A C IN
P D5
5
23
CS
2
3.2V
1
LM393DG_SO8
4
GND
+INE2
12
P2
3
OUTC2
3
A CO FF#
2 2
32
2
1
1
ACIN
P R26 10K_0402_1% 2 1
P C23 1U_0603_6.3V6M
P R25 100K_0402_1%
2
P U2A O
1
P R18 P C18 1K_0402_1% 2200P_0402_50V7K M B39A1261 2 1 2
P R21 150K_0402_1% 2
2
P R29 100K_0402_1%
32
1K_0402_5%
1
-
1
2
2
1
2 8 +
2
P R23 10K_0402_1%
P C22 0.1U_0603_25V7K
1
V IN
P R6 10K_0402_5%
P A C IN
1
1
1
P R24
P
3
4
1
133K_0603_1%
P R22 2 1 P R30 2
P R28 2.15K_0402_1% 1 2 10K_0603_0.1%
P C26 0.047U_0402_16V7K 2 1
IRE F
P R20 47_1206_5%
ADP_I_A
P C8 2200P_0402_50V7K 2 1
1 2 2
1
P R16 1 2 1M_0402_5% V IN
V IN
P C12 P R12 4700P_0402_25V7K 100K_0402_1% 1 2 2 1
VREF
P C17 0.22U_0603_16V7K
2
1 P R14 10K_0402_1% 2 1
M B39A126
P R15 30K_0603_1%
P R11 10K_0402_1% 1 2
S
2
P2
P U1 MB39A126PFV-ER_SSOP24 1 -INC2 +INC2 24
2
P D1 RLS4148_LLDS2 2
1
1
2 G
P C15 0.01U_0402_25V7K
A CO FF#
CHG_B+
D PQ9 RHU002N06_SOT323-3
3
1 2 3K_0402_5%
1
P R8 10K_0402_5%
2
2
0_0402_5%
A DP_I
2
32
1 1 P R10
CHG_B+ P C7 0.1U_0603_25V7K 2 1
P R7 150K_0402_5%
P C11 0.22U_0603_16V7K P A C IN
2
0.02_2512_1%
3
PQ6 S RHU002N06_SOT323-3
PL2 SMB3025500YA_2P 1 2
P R5
3
2 G
P R3 1 2 47K_0402_5%
2
P C6 1 2
0.22U_0603_16V7K
P4
8 7 6 5
P R2 200K_0402_5%
1
PQ5 DTC115EUA_SC70-3
BATT
1 2 3
1
D
PQ3 FDS6675BZ_SO8
B+
DTA144EUA_SC70-3
2 1
4 PQ4
8 7 6 5
2
P R4 47K_0402_1% 1 2
3 2 1
2
1
1
PQ2 FDS4435BZ_SO8 3 2 1
3
P C5 47P_0402_50V8J 1 2
P R1 47K_0402_5% 2 1
8 7 6 5
Sheet
35
of
43
B
PC46 0.047U_0603_16V7K
5 6 7 8
1
2
2
2
1
2
3 2 1 5 6 7 8
2 P R48 0_0402_5%
1
1 2 1 P R47 499K_0402_1%
1
2
3 2 1
1 2 1 PR46 @499K_0402_1%
2
17 VCC
TON
13
20 V+
1
10U_LF919AS-100M-P3_4.5A_20%
7 2
FB3 PGOOD
+3VALWP 2
RT8203PA_SSOP_28P
+3VLP
1
PR58 0_0402_5%
2
1 +
2
VL 1
2
1
1
PR56 2 1 499K_0603_1%
BST_3.3V DH _3.3V DL_3.3V LX_3.3V
P C44 150U_D2_6.3VM
MAINPW ON 40
2
MAINPW ON
P C43 0.22U_0603_10V7K
2VREF_1999 VL
2
PL6
1
REF
28 26 24 27 22
4
P R55 @3.57K_0402_1%
SKIP#
BST3 DH3 DL3 LX3 OUT3
PQ18 AO4466_SO8
2
12
ILIM5
11
100K_0402_1% PR45
1
SHDN# ON5 ON3
8
1
2
6 4 3
5
PR44 0_0402_5%
P R59 0_0402_5%
PR52 1 2 @0_0402_5% 1 2 PR53 @10K_0402_5%
ILIM3
DH_3.3V_B
PRO#
2VREF_1999
PR43 0_0402_5%
10
2 0_0402_5%
4
2
PR50
PQ16 AO4466_SO8
1
LX5 DL5 OUT5 FB5 N.C.
LDO3
15 19 21 9 1
GND
LX_5V DL_5V
25
DH5
23
1
16
P R57 300K_0402_5% 2 1
P R54 0_0402_5%
2
2VREF_1999
BST5
D H_5V
P C45 4.7U_0805_10V4Z
B++ P R51 47K_0402_5% 2 1 2 1 P C42 0.1U_0603_25V7K
1 2
+
1
P C41 220U_6.3VM_R15
2
P R49 @10.2K_0402_1%
+5VALWP
18
1 2 3 2
PC121 @0.1U_0402_16V7K 2 1
PC37 0.1U_0603_16V7K
2VREF_1999
2
PU5 BST_5V 14
1
1
LD05
P C38 4.7U_0805_10V4Z
1
4
PL5 4.7U_LF919AS-4R7M-P3_5.2A_20%
VL
1
P C39 2 1 0.1U_0603_50V4Z
1
8 7 6 5
1 2 3
PR42 0_0402_5%
P C40 1U_0805_16V7K
B++
2
2
1
PR40 0_0402_5% 2
2
1
P R41 47_0402_5%
4DH_5V_B
1
P C36 4.7U_1206_25V6K
3
VL
PQ17 AO4466_SO8
2
B++
PD6 CHP202UPT_SOT323-3 PQ15 AO4466_SO8
E
PC32 0.1U_0603_50V4Z 1 2
BST_3.3V_B
8 7 6 5
1
2 1 P C34 10U_1206_25V6M
2
2 1 P C33 2200P_0402_50V7K
B+ 1
BST_5V_B
P C35 2200P_0402_50V7K
PC31 0.1U_0603_50V4Z 1 2
B++
HCB2012KF-121T50_0805
D
1
PL4
C
2
A
3
RTC Charger Circuit 2007/04/20
PQ19
2
1
D
3
PR60 100K_0402_5%
2 G S RHU002N06_SOT323-3 D
1
35 S
2 G PQ21 RHU002N06_SOT323-3
1
3
+3VLP 2
+CHGRTC
2 P ACIN G PQ20 RHU002N06_SOT323-3
2
3
S
PQ22 TP0610K-T1-E3_SOT23
D
3
PR157 PR158 560_0603_5% 560_0603_5% 1 2 1 2
1
3
+3VL
PR62 100K_0402_5%
2 1
1
PR61 100K_0402_5%
BATT1.1
W=20mils
+
BATT1
1
2
30
51ON#
@ML1220T13RE 45@
4
4
Compal Secret Data
Security Classification
Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. 3.3VALWP / 5VALWP
Size D ate:
Document Number Tuesday, July 31, 2007
R ev Sheet E
36
of
43
5
3
1
1
1
2
1
P R66 73.2K_0402_1%
2
2
P R65 75K_0402_1%
P R64 10.2K_0603_0.1% 1 2
P C51 4.7U_1206_25V6K D
2
P R63 14.3K_0603_0.1% 1 2
P C50 @2200P_0402_50V7K 2 1
2 1 P C49 10U_1206_25V6M
D
P C48 2200P_0402_50V7K 2 1
2
P C47 680P_0402_50V7K
2
B+++
PL7 HCB2012KF-121T50_0805 1 2
1
B+
4
DR VH1
21
DR VL1
+1.5VSP
PL16
2
1
0.1U_0603_25V7K
2
3.3UH_SIQB74-3R3RF_4.8A_30%
LX_1.5V
1
LG_1.5V P C54 4.7U_0805_6.3V6K
PGND1
TRIP1
20 19
1
+ 2
TPS51124RGER_QFN24_4x4
C
18
17
13
LL1
BS T_1.5V UG_1.5V
SP8K10S FD5 2N SOP8
P C52
P C55 220U_6.3VM_R15
2
1 VO1
VFB1
4
3 GND
TONSEL
5
DR VL2 PGND2
8 7 6 5
22
P R72 0_0402_5% 1 2
1
LL2
LG_1.8V
P R74 18.2K_0402_1% 1 2
1 2 3
VBST1
P R71 0_0402_5% 1 2 UG1_1.5V
1 2 3 4
P R 75 15.4K_0402_1%
1
2
2
P C76 680P_0603_50V7K
6
DR VH2
11 12
4
PQ25 FDS6690AS_NL_SO8
EN1
VBST2
1 2
P R 88 4.7_1206_5%
1
P C58 0.1U_0402_16V7K
1 2
+ 2
P C57 0.1U_0402_16V7K 2 1
220U_6.3VM_R15 P C56
C
1
24 23
G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A
1
LX_1.8V
9 10
V5IN
0.1U_0603_25V7K
PL9 3.3UH_PCMC063T-3R3MN_6A_20% 2 1
BS T_1.8V UG_1.8V
PGOOD1
EN2
V5FILT
2
1 2 3
+1.8VP
PGOOD2
8
PQ24 8 7 6 5
2
7
16
P R73 0_0402_5% 1 1 2
P C53
15
UG1_1.8V
TRIP2
P R68 0_0402_5% 1 2
P PAD
14
4
25
VO2
P U6
PQ23 AO4466_SO8
VFB2
8 7 6 5
1
P R67 0_0402_5%
P C59 1U_0603_10V6K
P R76 3.3_0402_5% 2
1
P R77 0_0402_5% 2
2
1
+5VALWP 1
1
23,32,33 SYSON
P C60 4.7U_0805_10V6K
1
2
SUSP# 23,32,33,35,38
0_0402_5% P R78
2
1
2
PR160 100K_0402_5%
2
P C61 @1000P_0402_50V7K
B
B
+1.8V
1 P R82 0_0402_5%
6
NC
5
3
VREF
NC
7
4
VOUT
NC
8
TP
9
+5VALW
2
1
1
P C64 1U_0603_16V6K
D
S
2 G
+0.9VP 1
1 2
P R81 1K_0402_1% 2
SUSP
1
33
1
PQ26 RHU002N06_SOT323-3
VCNTL
GND
G2992F1U_SO8
2
P R80 @0_0402_5%
2
1
3
29,33 SYSON#
P R79 1K_0402_1%
2 1 P C65 0.1U_0402_16V7K
7,13,14 V_DDR_MCH_REF
VIN
2
2
1 2
2
P C62 10U_0805_10V4Z
P C63 @10U_0805_10V4Z
1
P U7 1
P C66 10U_1206_6.3V7K
2
P C67 @0.1U_0402_16V7K
A
A
Compal Secret Data
5
4
3
2
Title
Compal Electronics, Inc.
Size
om
1.8VP/0.9VP/1.5VSP D ocument Number
L A-3821P Dat e:
T uesday, July 31, 2007
Sheet
1
Rev 0.2
l.c
2007/11/23
ai
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
nf @ ho tm
2006/11/23
ai
Issued Date
he x
Security Classification
37
of
43
5
4
3
2
1
PL10 HCB1608KF-121T30_0603 B+
2
1
1.05V_B+
5 6 7 8 1
2
2
3 2 1
2
+1.05V_VCCP
5 6 7 8
1
12
LX
11
ILIM
10
2 4
9
P C75 4.7U_0805_6.3V6K
DL
1
VDDP
+
PQ28 FDS6690AS_NL_SO8
LX_1.05V P R89 1 2 21K_0402_1%
2
13
14
15
1
BST DH
SC411MLTRT_MLPQ16_4X4
8
PGND
VSSA
7
6
17
C
NC
PGD TP
FB
4
5
P R90 2 1 0_0402_5%
3
PL11 2.2UH_PCMC063T-2R2MN_8A_20%
2
1
VCCA
1
P C71 0.1U_0402_16V7K
3 2 1
VOUT
2
UG_1.05V BOOT1_1.05V
2 0_0402_5%
2
1
NC
EN/PSV
16 TON
2
P U8
1
P C73 220U_V_4VM_R25M
BOOT_1.05V 1
2 P R87 10K_0402_1%
2
1
VCCP_POK
P R86
1 1 P C72 @2200P_0402_25V7K
P C74 1U_0603_10V6K
4
1SS355_SOD323-2
2
P R85 0_0402_5%
2
1
P D7
1
1
P C70 1000P_0402_50V7K
23,32,33,35,37 SUSP#
D
PQ27 AO4466_SO8
P R84 1M_0402_5%
2
D
P R83 10_0402_5%
2 1 P C69 10U_1206_25V6M
+5VALWP
P C77 1U_0603_10V6K
C
LG_1.05V
P R91 1 2 11K_0402_1% 2 +5VALWP
2
(4.5A,180mils ,Via NO.= 9)
+1.25VSP
1
+3VALWP
1
2
P R94 0_0402_5%
2
+3VALW
(3A,120mils ,Via NO.= 6) 2
1
+3VL
(7A,280mils ,Via NO.= 14)
+ VCCP
(6A,240mils ,Via NO.=12)
+1.5VS
(6A,240mils ,Via NO.=12)
+0.9V
(2A,80mils ,Via NO.= 4)
FB
2
2
VCNTL
VOUT
(100mA,20mils ,Via NO.= 1)
P R95 33.2K_0402_1%
PAD-OPEN 4x4m
1
2
P C82 22U_1206_6.3V6M
P C83 47P_0402_50V8J
P R96 59K_0402_1% 2
PJP6 +1.05V_VCCP
B
+1.25VSP
APL5913-KAC-TRL_SO8
PAD-OPEN 2x2m +1.8V
EN
P C80 10U_1206_6.3V6M
1
2
23,32,33,35,37 SUSP#
,Via NO.= 1)
4
PJP4 +3VLP
1
+1.25VS(500mA,40mils
P C81 @0.01U_0402_16V7K
PAD-OPEN 4x4m PJP5 +1.8VP
2 PAD-OPEN 3x3m
PAD-OPEN 4x4m PJP3
VOUT
3
1
+5VALW
8
9
1
2
2
5
VIN
1
1
1
VIN
2
+5VALWP
PJP2
POK
1
PJP1
1
B
7
GND
2 P R93 @0_0402_5%
1
P U9 1
+1.5VS
P C79 1U_0603_6.3V6M
6
2
1
P R92 10K_0402_1%
2
1
P C78 33P_0402_50V8J
2
1
PAD-OPEN 4x4m PJP7 +1.5VSP
1
2 PAD-OPEN 4x4m PJP8
+0.9VP A
1
2 PAD-OPEN 3x3m
A
Compal Secret Data
Security Classification Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. 1.05V_VCCP/2.5VSP
Size
D ocument Number
Rev 0.2
L A-3821P Dat e:
T uesday, July 31, 2007
Sheet 1
38
of
43
5
4
3
2
1
+5VS
G S S S
220P_0402_50V7K
255_0402_1% 1
2
PC115 0.22U_0603_10V7K
1
1 2
PC90 1000P_0402_50V7K
1
1
2
1 2
PC127 1000P_0402_50V7K
PC89 2200P_0402_50V7K 2 1
PC128 1000P_0402_50V7K
PC126 4700P_0402_25V7K 2 1
1 2
PC125 4700P_0402_25V7K 2 1
PC98 2200P_0402_50V7K 2 1
1 2
D D D D G S S S 4 3 2 1
CPU_B+
B
1
PR144 4.42K_0402_1% PC114 0.1U_0402_16V7K 1 2
2
10KB_0603_5%_ERTJ1VR103J PH2
1
11K_0402_1%
1 PR142 2
2
2
PR139
1
1
2
ISEN2
VSUM
2 PR143 1K_0402_1% VCC_PRM
PC106 1 2
PC109 0.1U_0603_25V7K
PC112 0.01U_0603_50V7K
PC113 180P_0402_50V8J 1 2 2
@0_0603_5% 2
0.22U_0603_10V7K
1 2
PC111 @0.022U_0603_50V7K
1
24
23
22
21
1 PC110 820P_0603_50V7K 1 2
VSSSENSE
VSUM
1_0402_5%
PR129 1
2
PR136 1K_0402_1%
5
+5VS
PR128
VCC_PRM
2
VCCSENSE
PC103 680P_0603_50V8J
PR132 1_0603_5% PC105 1U_0402_6.3V4Z
PR135 10_0603_5% 1 2
B
5
20
19
1
PC108 1000P_0402_50V7K 1 2
PR1341
ISEN1 ISEN2 2
PR127 10K_0402_1% 2 1
ISEN2
VDD
GND
VIN
VSUM
VO 18
17
16
15
D D D D 470P_0402_50V7K 2
PU10
C
2.61K_0402_1%
1 PC107
1
2
PR130 97.6K_0402_1% PC104 1 2 2
1 PR131 2 @0_0402_5%
PC102 1000P_0402_50V7K
14
13
2 2 PR133 1 1K_0402_1%
1
PR125 6.8_1206_5%
1
25
2
NC
CPU_B+
0.36UH_PCMC104T-R36MN1R17_30A_20% 2 1 PL14 3.65K_0805_1%
FB2
PC96 10U_1206_25V6M 2 1
12
UGATE_CPU2-2
PR126
26
PC95 10U_1206_25V6M 2 1
BOOT2
1
FB
PR118 @0_0603_5% 1 2 PC94 1 2 VCC_PRM ISEN1 0.22U_0603_10V7K
VSUM
1 2
11
PHASE_CPU2 PR122 UGATE_CPU2-1 1 2 2.2_0603_5% BOOT_CPU2 1 2 1 2 PR123 0_0603_5% PC101 0.22U_0603_10V7K
2
27
PQ34 FDS6676AS_SO8
UGATE2
G S S S
COMP
4 3 2 1
10
PQ33 FDS6676AS_SO8 4 5 G D 3 6 S D 2 7 S D 1 8 S D
28
LGATE_CPU2
PQ32 SI4684DY-T1-E3_SO8
+VCC_CORE
PR117 1_0402_5%
LGATE_CPU1
5 6 7 8
PHASE2
ISEN1
29
VW
DFB
1 2 1000P_0402_50V7K PC100 PR124 6.81K_0402_1% 1 2
PGND2
9
ISL6262ACRZ-T_QFN48_7X7
DROOP
13K_0402_1% 1 2
OCSET
RTN
PR121
SOFT
8
VSEN
0.022U_0603_25V7K PC99 1 2
7
VDIFF
C
PL13
D
2
1 PR115 2
PR114
5 6 7 8 D D D D
PR116 10K_0402_1% 2 1
LGATE2
30
3.65K_0805_1%
31
5 6 7 8
1 32
PVCC
0.36UH_PCMC104T-R36MN1R17_30A_20% 2 1
6.8_1206_5% 680P_0603_50V8J
LGATE1
1 2
PHASE_CPU1
33
PC93
34
PGND1
2
PHASE1
RBIAS
PQ31 FDS6676AS_SO8
PMON
PC88 10U_1206_25V6M 2 1
PC86 47U 25V M 6.3X6 ESR0.44 CE-LX PC87 10U_1206_25V6M 2 1
PC123 4700P_0402_25V7K
1 2 D D D D
5 6 7 8
2
4 3 2 1 UGATE_CPU1-1
G S S S
35
4 3 2 1
36 G S S S
BOOT1 UGATE1
D D D D
37 VID0
38 VID1
PC124 4700P_0402_25V7K 2 1
1 1
1 2
PR105
PR109
PR108 39 VID2
40 VID3
42
44
43
46
45
47
41 VID4
NTC
VID5
VR_TT#
6
VID6
5
DPRSLPVR
4
DPRSTP#
48 3V3
3
+ 2
1 PC122 4700P_0402_25V7K
5
5
5
5 CPU_VID2 5 CPU_VID1 5 CPU_VID0 5
32 CPU_VID3
CPU_VID4
PR104
1 PSI#
1
5 6 7 8
VR_TT#
PGOOD
2
1 2 2.2_0603_5% PR113
PQ30 FDS6676AS_SO8
2 PR119 147K_0402_1% 1 2
PQ29 SI4684DY-T1-E3_SO8
0.22U_0603_10V7KUGATE_CPU1-2 PC92 2 1 2
0_0603_5% PR110 1
4 3 2 1
1 PR159 @0_0402_5%
1
CLK_EN#
H_PSI#
CPU_VID5
2 PGD_IN
VGATE
PC85 2.2U_0603_6.3V6K
2 49
PC91 1U_0603_6.3V6M
1 15,20 5
PC84 0.022U_0402_16V7K
BOOT_CPU1
1
2
499_0402_1%
1.91K_0402_1%
PR112
2
PR111
0_0402_5% 2
GND
PR106 1
+3VS +3VS
0_0402_5% 2
PL12 SMB3025500YA_2P 2
2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5%
PR100 1
CLK_ENABLE#
VR_ON
5,7,19 H_DPRSTP#
PR103
0_0402_5% 2
PR102
PR99 1
CPU_VID6
VR_ON 499_0402_1% 2
PR101
1
7,20 DPRSLPVR
PR107
PR98
D
B+
CPU_B+ PR97 1_0603_5%
PC116 0.22U_0402_6.3V6K 2 1
1
A
nf @ ho tm
ai
l.c
om
A
Compal Electronics, Inc. Title
5
4
3
2
Date:
Tuesday, July 31, 2007
he x
Size Document Number Custom
ai
+CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sheet
1
R ev 0.2 39
of
43
A
B
C
D
BATT PCN2
2
PR145
1 1
@1K_0402_5%
PD8 1
3
1
2
SUYIN_200275MR007G113ZL
1
BATT_DET 35
2 PR156 1 1K_0402_5%
@SM05_SOT23
PC117 @1000P_0402_50V7K
2
EC_SMD EC_SMC
2
9 8
7 6 5 4 3 2 1
3
1
BATT+ SMD SMC ID B/I G TS G GND
PC118 @0.01U_0402_50V4Z
PD9 @SM24.TC_SOT23-3
+3VL
1
1
1
PR146 6.49K_0402_1% 1 2
1
2
PR147 1K_0402_5%
2
PR148 100_0402_5%
BATT_TEMP 32
2
2
PR149 100_0402_5%
PCN2 battery connector
2
SMB_EC_DA1
SMB_EC_DA1 31,32
SMB_EC_CK1
S M A RT Batte ry: 7 . BATT+ 6. SMD 5.SMC 4. ID 3.B/I 2.TS 1. GND
SMB_EC_CK1 31,32
2
PH3 under CPU botten side : CPU thermal protection at 90 +-3 degree C Recovery at 47 +-3 degree C PR150 47K_0402_1% 1 2
+5VS
2
CPU
1
+5VS
3
PR151 10K_0402_5%
PH3 10K_TH11-3H103FT_0603_1%
1
2
3
-
2
4 1
7
S
PQ35 RHU002N06_SOT323-3
2 G
LM393DG_SO8
1 2
PR155 150K_0402_1%
D
P O
PC120 1000P_0402_50V7K
2
2
PC119 0.22U_0603_10V7K
PR154 2.55K_0603_1%
2
1
1
PR153 150K_0402_1%
1
+
6
8 5
1
G
+5VS
PU2B
3
MAINPWON 36 PR152 15K_0603_1% 1 2
4
4
Compal Secret Data
Security Classification Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title
Compal Electronics, Inc. BATTERY CONN
Size Document Number C ustom LA-3821P D ate:
R ev Sheet
Tuesday, July 31, 2007 D
40
of
43
5
4
3
Version change list (P.I.R. List) Item D
Reason for change
2
Power section PG#
1
Page 1 of 1
Modify List
Date
Phase
1
RT8203 crosstalk issue
37
add PC121 and 0.1uF
2007/05/24
SI
2
PU6 pin8 add a resistor to GND
38
add PR160
2007/05/24
SI
3
remove PL15
36
remove PL15
2007/06/12
SI
39
add PC122,PC123,PC124,PC125,PC126,PC127,PC128
2007/07/23
PV
4
EMI request
100K_ohm
D
C
C
5
6
7
B
8
B
9
10 11 12 13
14
nf @ ho tm
ai
l.c
om
A
Compal Electronics, Inc. Title
PWR PIR
5
4
3
2
Size Document Number Custom Date:
Tuesday, July 31, 2007
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sheet 1
he x
A
41
of
43
Rev 0.2
5
4
3
Version change list (P.I.R. List) Item
Reason for change
2
Power section PG#
1
Page 1 of 1
Modify List
Date
Phase
1
EC team request
32
ACIN add 100P (C505) to GND
2007/05/30
SI
2
Change Board ID
32
R407 from 0 Ohm to 8.2K,R405 install 100K
2007/05/30
SI
3
USB power switch fail
29
U23 & U17 change pin 4 from SLP_S5# to SYSON#
2007/05/30
SI
4
FAN use voltage control
4
del U2,Q1;add U24,C13 for 3 pin FAN
2007/05/30
SI
5
USB JP24 fail
29
Change pin define
2007/05/30
SI
6
Speaker output fail
28
Add R457,R458,R459 for Line_out
2007/05/30
SI
7
MS Pro fail
26
Add MS_D1,MS_D2,MS_D3 net
2007/06/06
SI
8
WLAN LED fail when disable WLAN
30
Add R232 pull high +5VS
2007/06/06
SI
9
+3VALW leakage
30
Del R387
2007/06/06
SI
10
Capacitor board fail
32
Add net CAP_RESET for Capacitor board reset
2007/06/06
SI
11
XDP fail
15
XDP clock share in robeson card
2007/06/06
SI
12
LAN power consumption is too large when S3
24
Add Q22
2007/06/14
SI
13
RJ11' cap is duplicate MDC module.
25
Delete C378,C379
2007/06/14
SI
14
Reverse some resister for tring ENE cap board
Add R460~R468,R451
2007/06/14
SI
15
+LCDVDD over current when diplay.
Change R163 from 47K to 100K Change C248 from 0.1U to 0.22U
2007/06/21
SI
D
D
C
C
30 32 17
B
B
16 17 18 19 20
LAN fail
24
WLAN LED (Amber led) issue
30
030 project Bluetooth module issue
29
change Cap board LED supply voltage
Change JP14 pin define WLAN LED need change from +5VS to +3VS Swap pin5 & pin7
30
CMOS timing can't reset
19
20
EMI issue (CPU core)
5
21
EMI/ESD
4
issue (XDO connector)
2007/06/06
from +3VS to +5VS
add
2007/07/23
PV
2007/07/23
PV
2007/07/23
SHORT PAD (CLRP3) connect between +RTCVCC and GND
SI
2007/07/23
PV PV
C43 & C44 (330U)
2007/07/23
PV
delete XDP connector
2007/07/23
PV
2007/07/23
PV
A
A
22
EMI/ESD
issue (RJ11 connector)
25
add 1000P at RJ11 RING & TIP
Compal Electronics, Inc. Title
PWR PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size Document Number Custom Date:
Tuesday, July 31, 2007
Rev 0.3 Sheet 1
42
of
43
5
4
3
Version change list (P.I.R. List) Item 23
Reason for change
2
Power section PG#
card reader RTL5158 chip issue
26
1
Page 1 of 1
Modify List
Date
change C393, C394 from 27p to 5.6p
Phase
2007/07/25
PV
D
D
24 25
monitor wave riple issue
10
MIC issue for EMI solution
28
add C508
2007/07/25
PV
add L20, L21, L22, L23, C509, C510
2007/07/31
PV
C
B
B
A
A
nf @ ho tm
ai
l.c
om
C
Compal Electronics, Inc. Title
PWR PIR
5
4
3
2
Date:
Tuesday, July 31, 2007
ai
Size Document Number Custom Sheet 1
he x
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
43
of
43
Rev 0.3
B
C
D
E
1
1
Compal confidential
2
2
Schematics Document Mobile Merom uFCPGA with Satna Rosa Platform 3
3
2007-07-24 REV:0.3
4
Compal Secret Data 2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. Cover Sheet
Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
4
Sheet
E
1
of
43
A
B
Compal confidential File Name : LA-3821P ZZZ1
C
D
E
Supra 1.0 (Merom +Crestline+ICH8) 12"
PCB 1
1
Mobile Yonah/Merom uFCPGA-478 CPU Socket P
Fan Control page 4
Thermal Sensor ADM1032AR
page 4,5,6
Clock Generator ICS9LPRS355
page 4
page 15
FSB H_A#(3..31)
LVDS Conn
H_D#(0..63)
533/667/800MHz
LED
USB2.0
page 7,8,9,10,11,12
page 28 USB2.0
2
RTC CKT.
USB2.0
page 19
DDR2-SO-DIMM X2 BANK 0, 1, 2, 3
page 13,14
Dual Channel
NB Crestline
page 17
DDR2 -400/533/667
DMI USB2.0
Bluetooth Ver:2.0 page 29 Conn FingerPrinter page 29 Conn PC Camera page 29 Conn Card Reader RTS5158 page 26 USB Conn X 3
2
RJ11CONN page 26
page 29
MDC V1.5
PCI-E BUS
page 26 AC-LINK/Azalia
SB ICH8 Marvall Giga LAN 8055 page 26
AMON Agere CSP1040 page
Audio Realtek ALC268
page 24
Mini-Card WLAN
3
page 22
Mini-Card Robeson page 22
New card
page 18,19,20,21
AMP & Audio Jack TPA6017A2 page 26
SATA
SATA HDD Connector page 23
28
3
page 22 PATA Master
IDE ODD Connector
RJ45CONN
page 22
page 27
LPC BUS
ENE KB926
Power On/Off CKT.
page 30
page 28
4
SPI
page 29
Int.KBD
Touch Pad CONN.
DC/DC Interface CKT.
SPI ROM 25LF080A
page 28
4
page 30
page 31
2006/02/13
Issued Date
Page 32,33,34,35,36,37,38
A
Compal Secret Data
Security Classification
Power Circuit DC/DC
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
C
D
Title
Compal Electronics, Inc. Block Diagram
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet E
2
of
43
5
4
3
2
1
Voltage Rails +5VS +3VS
power plane +B D
+5VALW +3VALW
+1.5VS +1.25VS
+1.8V
+0.9V
State
D
+VCCP +CPU_CORE
S0
O
O
O
O
S1
O
O
O
O
O
O
O
X
S3 S5 S4/AC
O
O
X
X
S5 S4/ Battery only
O
X
X
X
S5 S4/AC & Battery don't exist
X
X
X
X
Symbol Note : : means Digital Ground
: means Analog Ground @ : means just reserve , no build DEBUG@ : means just reserve for debug.
C
C
SMBUS Control Table
B
I2C / SMBUS ADDRESSING
SOURCE
DEVICE
HEX
ADDRESS
DDR SO-DIMM 0
A0
10100000
DDR SO-DIMM 1
A4
10100100
CL OCK GENERATOR (EXT.)
D2
11010010
INVERTER
BATT
SODIMM
CLK CHIP
MINI CARD
LCD
X X
V X
V X
X V
X X
X X
X X
X X
ICH8
X
X
X
X
V
V
V
X
Crestline
X
X
X
X
X
X
X
V
SMB_EC_CK1 SMB_EC_DA1
KB925
SMB_EC_CK2 SMB_EC_DA2
KB925
SMB_CK_CLK1 SMB_CK_DAT1 LCD_CLK LCD_DAT
BOM: 43XXXXXX
om l.c Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Notes List
Size
Document Number
LA-3821P Date:
nf @ ho tm
ai
PJP?
R ev 0.3
ai
Jump-Short:
A
Tuesday, July 31, 2007
he x
A
B
THERMAL SERIAL SENSOR EEPROM (CPU) ADM1032
Sheet
1
3
of
43
5
4
3
2
1
D
D
7/23
+VCCP
H_STPCLK# H_INTR H_NMI H_SMI#
H_STPCLK# H_INTR H_NMI H_SMI#
D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6
B
A20M# FERR# IGNNE#
G6 E4
H_HIT# H_HITM#
BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
H_BR0# H_INIT#
R10 56_0402_5% 2 1
7
+VCCP
19 C2
H_LOCK# 7
PROCHOT# THERMDA THERMDC THERMTRIP#
D21 A24 B25
54.9_0402_1%
2
54.9_0402_1%
XDP_TRST#
R7
1
2
51_0402_1%
XDP_TCK
R8
1
2
1
54.9_0402_1%
0.1U_0402_16V4Z 2
H_RESET# 7 H_RS#0 7 H_RS#1 7 H_RS#2 7 H_TRDY# 7 H_HIT# 7 H_HITM# 7
EMI request 4/18
C
Thermal Sensor ADM1032ARMZ +3VS XDP_TCK XDP_TDI 0.1U_0402_16V4Z XDP_DBRESET# 20
U1 1
+VCCP
H_THERMDA_R1 R14 H_THERMDC_R1 R15
2 0_0402_5% 2 0_0402_5%
H_THERMDA H_THERMDC
1
2
H_THERMTRIP# 7,19 1
+3VS CLK_CPU_BCLK CLK_CPU_BCLK#
THERM#
4
SDATA
D-
ALERT#
THERM#
GND
8
SMB_EC_CK2
7
SMB_EC_DA2
6 5
ADM1032ARMZ-2REEL_MSOP8
2
Address:100_1100
SMB_EC_DA2 SMB_EC_CK2
30,32 SMB_EC_DA2 30,32 SMB_EC_CK2
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
B
For Merom, R14 and R15 are 0ohm For Penryn, R14 and R15 are 100ohm.
+5VS
Voltage Fan Control circuit +5VS 1
2 1
+VCC_FAN
E
1
C
20 2
A
C13
EN_FAN
1000P_0402_50V7K
32
1 2 3 4
VEN VIN VO VSET
GND GND GND GND
8 7 6 5
G993P1UF_SOP8
D2
1
2
C5
1
C6
2
+VCC_FAN FAN_SPEED
1 2 3 4 5
1 2 3 GND GND
ACES_85205-03001
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
JP3
U24
1
FAN_SPEED
2 4.7U_0805_10V4Z
B
2 2
32 FAN_SPEED
D1 1SS355_SOD323-2
C12
+3VS
@ 56_0402_5%
5
SCLK
D+
CLK_CPU_BCLK 15 CLK_CPU_BCLK# 15
R17 10K_0402_5%
OCP#
3
10K_0402_5% A22 A21
SP07000FP00 S SOCKET TYCO 2-1871873-2 478P H3 CPU SP07000FD00 S SOCKET FOXCONN PZ4782A-274M-41 478P H3
3 1 OCP# @ Q2 MMBT3904_SOT23
H_THERMDC
VDD
R16
R18
H_PROCHOT#
2
C4
Merom Ball-out Rev 1a CONN@ +VCCP
H_THERMDA
2200P_0402_50V7K
H CLK BCLK[0] BCLK[1]
1
H_PROCHOT#
2 1 68_0402_5%
H_THERMTRIP#
C7
2
C3 XDP_TMS XDP_TRST# XDP_DBRESET# H_PROCHOT#
THERMAL
2
1
H_DEFER# 7 H_DRDY# 7 H_DBSY# 7
R13
STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]
RESET# RS[0]# RS[1]# RS[2]# TRDY#
H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY#
1
R3
1000P_0402_50V7K
A6 A5 C4
H_LOCK#
C1 F3 F4 G3 G2
R2
XDP_TMS
4.7U_0805_10V4Z
19 19 19 19
H_A20M# H_FERR# H_IGNNE#
H_IERR# H_INIT#
XDP_TDI
1
H_A20M# H_FERR# H_IGNNE#
H_BR0#
D20 B3
H_ADS# 7 H_BNR# 7 H_BPRI# 7
2
19 19 19
F1
H4
HIT# HITM#
A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
H5 F21 E1
H_DEFER# H_DRD Y# H_DBSY#
LOCK#
ICH
H_ADSTB#1
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#
ADDR GROUP 1
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1
C
7
K3 H2 K2 J3 L1
BR0# IERR# INIT#
H_ADS# H_BNR# H_BPRI#
1
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
DEFER# DRDY# DBSY#
H1 E2 G5
2
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17..35]
ADS# BNR# BPRI#
CONTROL
7 7 7 7 7 7
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
XDP/ITP SIGNALS
H_ADSTB#0
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
ADDR GROUP 0
7
JP2A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0
BAS16_SOT23-3
H_A#[3..16]
RESERVED
7
3
2
Title
Compal Electronics, Inc. Merom(1/3)-AGTL+/XDP
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet 1
4
of
43
4
3
2
1
+VCC_CORE
R21 R22
AD26 C23 D25 C24 AF26 AF1 A26
C8
H_DSTBN#1 H_DSTBP#1 H_DINV#1 2 @ 1K_0402_5% 2 @ 1K_0402_5%
1 1 1
15 15 15
2
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
B22 B23 C21
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3
COMP[0] COMP[1] COMP[2] COMP[3]
R26 U26 AA1 Y1
COMP0 COMP1 COMP2 COMP3
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
E5 B5 D24 D6 D7 AE6
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI#
MISC
BSEL[0] BSEL[1] BSEL[2]
Merom Ball-out Rev 1a CONN@
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
B
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
166
0
1
1
200
0
1
0
H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7
H_DPRSTP# 7,19,39 H_DPSLP# 19 H_DPWR# 7 H_PWRGOOD 19 H_CPUSLP# 7 H_PSI# 39
Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
D
+VCCP R19 2 2 R20
0_0402_5% 1 1 0_0402_5% 1 + 2
330U_D2E_2.5VM_R7
B26 C26
VCCA[01] VCCA[02]
AD6 AF5 AE5 AF4 AE3 AF3 AE2
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
VCCSENSE
AF7
VCCSENSE
VSSSENSE
AE7
VSSSENSE
Merom Ball-out Rev 1a CONN@
C
C7
39 39 39 39 39 39 39
1
2
VCCSENSE 39
1
2
+1.5VS
0.01U_0402_16V7K
7 7 7
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
C9
V_CPU_GTLREF TEST1 TEST2 TEST3 T1 TEST4 @ 0.1U_0402_16V4Z TEST5 T2 TEST6 T3
C
D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#
H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7 H_D#[48..63] 7
R26 27.4_0402_1% 2 1
D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
JP2C
R25 54.9_0402_1% 2 1
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2
DATA GRP 2
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16..31]
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
R24 27.4_0402_1% 2 1
7 7 7 7
DATA GRP 1
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#
DATA GRP 0
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
D
+VCC_CORE
H_D#[32..47] 7
JP2B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0
R23 54.9_0402_1% 2 1
H_D#[0..15]
DATA GRP 3
7
10U_0805_6.3V6M C10
5
Near pin B26
VSSSENSE 39 B
.
Length match within 25 mils. The trace width/space/other is 20/7/25.
1
+VCCP
R28 1K_0402_1% 2
+VCC_CORE R29 100_0402_1% 2
VCCSENSE
R31 100_0402_1% 1 2
VSSSENSE
1
1
V_CPU_GTLREF
2
R30 2K_0402_1%
Close to CPU pin AD26 within 500mils.
Close to CPU pin within 500mils. A
Compal Secret Data 2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Merom(2/3)-AGTL+/PWR
Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
A
Sheet
1
5
of
43
5
4
3
2
1
D
D
JP2D
C
B
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
Near CPU CORE regulator
Proadlizer
+VCC_CORE
+VCC_CORE
1 2 C43 @ 330U_D2E_2.5VM_R7
1
1
+
+
2
2
07/23
C
+ C44 @ 330U_D2E_2.5VM_R7
C11 1200P_PFAF250E128MNTTE_2.5VM
3 4
EMI solution
B
Place these inside socket cavity on L8 (North side Secondary) +VCCP
Merom Ball-out Rev 1a .
1
2
1
C48 0.1U_0402_16V4Z
2
C49 0.1U_0402_16V4Z
1
2
C50 0.1U_0402_16V4Z
1
2
1
C51 0.1U_0402_16V4Z
2
1
C52 0.1U_0402_16V4Z
2
C53 0.1U_0402_16V4Z
A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Merom(3/3)-GND&Bypass
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet 1
6
of
43
5 5 5 5
H_RS#0 H_RS#1 H_RS#2
4 4 4
BL15 BK14
SM_RCOMP_VOH SM_RCOMP_VOL
BK31 BL31
SMRCOMP_VOH SMRCOMP_VOL
SM_VREF_0 SM_VREF_1
AR49 AW4
1
10K_0402_5%
1
MUXING DDR
2 1 2
C57
2
CLK
PM_EXTTS#1
R39 CLKREQ#_B
2
T4 T5 T6 T7 T8 T9 T10 T11 T12
C FG5 C FG6 C FG7 C FG8 C FG9 CFG10 CFG11 CFG12 CFG13
T13
CFG16
T14 T15 T16
CFG18 CFG19 CFG20
20 PM_BMBUSY# 5,19,39 H_DPRSTP# 13 PM_EXTTS#0 14 PM_EXTTS#1 20,32 PM_PWROK 18,22,23,24 PLT_RST# 4,19 H_THERMTRIP# 20,39 DPRSLPVR
P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35
PM_BMBUSY# G41 H_DPRSTP# L39 PM_EXTTS#0 L36 PM_EXTTS#1 J36 PM_PWROK AW49 PLT_RST# AV20 H_THERMTRIP# N20 DPRSLPVR G36
BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2
1
+1.8V
2
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16
R35
+1.8V 20_0402_1% 1 1 20_0402_1%
2 2
R36
V_DDR_MCH_REF
CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK#
K44 K45
CLK_MCH_3GPLL CLK_MCH_3GPLL#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
AN47 AJ38 AN42 AN46
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
AM47 AJ39 AN41 AN45
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
AJ46 AJ41 AM40 AM44
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
AJ47 AJ42 AM39 AM43
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN
CLK_MCH_DREFCLK 15 CLK_MCH_DREFCLK# 15 MCH_SSCDREFCLK 15 MCH_SSCDREFCLK# 15 CLK_MCH_3GPLL 15 CLK_MCH_3GPLL# 15
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
20 20 20 20
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
20 20 20 20
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
20 20 20 20
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
20 20 20 20
T17 T18 T19 T20 T21
E35 A39 C38 B39 E36
B
+1.25VM_AXD
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
CL_CLK0 CL_DATA0 M_PWROK CL_RST# CL_VREF
AM49 AK50 AT43 AN49 AM50
CL_CLK0 20 CL_DATA0 20 M_PWROK 20,32 CL_RST# 20 CL_VREF 0.1U_0402_16V4Z 1
SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2
2
H35 K36 G39 G40
CLKREQ#_B M CH_ICH_SYNC#
R48
CLKREQ#_B 15 MCH_ICH_SYNC# 20
R49 0_0402_5%
A
ai
l.c
2
2
1K_0402_1%
A37 R32
CRESTLINE_1p0
@ R47 1K_0402_1%
R42
R43 392_0402_1%
C58
20K_0402_5% 2
13 13 14 14
C
10K_0402_5%
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
13 13 14 14
M_ODT0 M_ODT1 M_ODT2 M_ODT3
B42 C42 H48 H47
PEG_CLK PEG_CLK#
1
1
V_DDR_MCH_REF C59 0.1U_0402_16V4Z
0.1U_0402_16V4Z C61
1 R46
221_0603_1%
2 1 R52 2
100_0402_1%
R51 24.9_0402_1% 2 1
C60
1 R45
1K_0402_1%
2 1 R50 2
2K_0402_1%
13,14,37 V_DDR_MCH_REF
2
SM_RCOMP SM_RCOMP#
SMRCOMP SMRCOMP#
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
NC
5
C56
R38
@ R44 1K_0402_1%
1
M_ODT0 M_ODT1 M_ODT2 M_ODT3
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
D
om
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.
H_SWNG
BH18 BJ15 BJ14 BE16
SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3
13 13 14 14
1
5 5 5 5
4 4 4 4 4
1
10K_0402_5%
15 MCH_CLKSEL0 15 MCH_CLKSEL1 15 MCH_CLKSEL2
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
2
PM
within 100 mils from NB
1K_0402_1%
R37 PM_EXTTS#0
5 5 5 5
+VCCP
2
2
R34
RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45
SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3
DMI
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
+VCCP
1
2
1
+3VS
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
H_RCOMP
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
1 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 15 CLK_MCH_BCLK# 15 H_DPWR# 5 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4
CRESTLINE_1p0
0.1U_0402_16V4Z H_VREF
H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34
13 DDR_A_MA14 14 DDR_B_MA14
layout note:
A
1
0.01U_0402_16V7K
SMRCOMP_VOL
H_AVREF H_DVREF
Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20
BG20 BK16 BG16 BE13
R33 3.01K_0402_1% NA lead free
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
2
H_RS#0 H_RS#1 H_RS#2
1
E12 D7 D8
2
H_RS#_0 H_RS#_1 H_RS#_2
C55
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
2.2U_0805_16V4Z C54
M14 E13 A11 H13 B12
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
13 13 14 14
1
H_VREF
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
BE29 AY32 BD39 BG37
SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
2
H_SWING H_RCOMP
B
B9 A9
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Near B3 pin 4
3
2
Title
nf @ ho tm
H_CPURST# H_CPUSLP#
L7 K2 AC2 AJ10
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
AW30 BA23 AW25 AW23
13 13 14 14
Compal Electronics, Inc.
CRESTLINE(1/6)-AGTL+/DMI/DDR2 Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
B6 E5
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
Tuesday, July 31, 2007
he x
H_RESET# H_CPUSLP#
M7 K3 AD2 AH11
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
1K_0402_1%
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
1
H_SCOMP H_SCOMP#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
SMRCOMP_VOH
R32
AV29 BB23 BA25 AV23
2
W1 W2
K5 L2 AD13 AE13
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
1
+1.8V
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4
1
B3 C2
H_SCOMP H_SCOMP#
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRD Y# H_HIT# H_HITM# H_LOCK# H_TRDY#
1
2
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14
GRAPHICS VID
R41 54.9_0402_1% 2 1 H_RESET# H_CPUSLP#
H_SWNG H_RCOMP
G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
2
P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20
CFG
R40 54.9_0402_1% 2 1
+VCCP
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
ME
C
J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
1
For Crestline: 20ohm For Calero: 80.6ohm
RSVD
D
E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13
2.2U_0805_16V4Z
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
2
U3B
0.01U_0402_16V7K
U3A
H_D#[0..63]
4 5
3
H_A#[3..35] 4
HOST
5
4
MISC
5
Sheet
1
7
of
43
5
4
3
2
1
D
D
14 DDR_B_D[0..63]
B
DDR_A_BS0 DDR_A_BS1 DDR_A_BS2
SA_CAS#
BL17
DDR_A_CAS#
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13
BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13
SA_RAS# SA_RCVEN#
BE18 AY20
DDR_A_RAS# SA_RCVEN#
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
SA_WE#
BA19
DDR_A_WE#
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_A_BS0 13 DDR_A_BS1 13 DDR_A_BS2 13 DDR_A_CAS# 13 DDR_A_DM[0..7] 13
DDR_A_DQS[0..7] 13
DDR_A_DQS#[0..7] 13
DDR_A_MA[0..13] 13
DDR_A_RAS# 13 T23 DDR_A_WE# 13
AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2
CRESTLINE_1p0
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
B
BB19 BK19 BF29
MEMORY
SA_BS_0 SA_BS_1 SA_BS_2
U3E
SYSTEM
MEMORY
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SYSTEM
C
AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11
DDR
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
A
U3D
DDR
13 DDR_A_D[0..63]
SB_BS_0 SB_BS_1 SB_BS_2
AY17 BG18 BG36
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
SB_CAS#
BE17
DDR_B_CAS#
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_RAS# SB_RCVEN# SB_WE#
AV16 AY18
DDR_B_RAS# SB_RCVEN#
BC17
DDR_B_WE#
DDR_B_BS0 14 DDR_B_BS1 14 DDR_B_BS2 14 DDR_B_CAS# 14 DDR_B_DM[0..7] 14
DDR_B_DQS[0..7] 14
DDR_B_DQS#[0..7] 14
C
DDR_B_MA[0..13] 14
DDR_B_RAS# 14 T22 DDR_B_WE# 14
B
CRESTLINE_1p0
A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. CRESTLINE((2/6)-DDR2 A/B CH
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet 1
8
of
43
5
4
3
2
1
Strap Pin Table 010 = FSB 800MHz CFG[2:0] FSB Freq select
011 = FSB 667MHz Others = Reserved
17,32
For Crestline:2.4kohm For Calero: 1.5Kohm
BKLT_CTRL
T49 ENABLT R54 1 R55 1 LCD_CLK LCD_DATA ENAVDD
ENABLT +3VS
17 LCD_CLK 17 LCD_DATA 17 ENAVDD
1 2.4K_0402_1%
17 17
LVDSACLVDSAC+
17 17 17
LVDSA0LVDSA1LVDSA2-
17 17 17
LVDSA0+ LVDSA1+ LVDSA2+
J40 H39 E39 E40 C37 D35 K40 L41 L43 N41 N40 D46 C45 D44 E42
LVDSACLVDSAC+
LVDSA0LVDSA1LVDSA2-
G51 E51 F49
LVDSA0+ LVDSA1+ LVDSA2+
G50 E50 F48 G44 B47 B45
C
E44 A47 A45
5/03
1 1 1
150_0402_5% E27 150_0402_5% G27 150_0402_5% K27 F27 J27 L27
R57
+3VS
CRT_B
16
CRT_G
16
CRT_R
16 16 16
3VDDCCL 3VDDCDA CRT_HSYNC
16
CRT_VSYNC
CRT_B
H32 G32 K29 J29 F29 E29
CRT_G CRT_R
3VDDCCL 3VDDCDA CR T_HSYNC
K33 G35 F33 C32 E33
CRT_VSYNC
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2
TVA_DAC TVB_DAC TVC_DAC TVA_RTN TVB_RTN TVC_RTN TV_DCONSEL_0 TV_DCONSEL_1
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
1
16
M35 P33
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2
2
1.3K_0402_1%
R58
VGA
B
2.2K_0402_5% 1 2
LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
PEG_COMPI PEG_COMPO
TV
R247 2 R355 2 R358 2
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN
LVDS
2 R56
2 10K_0402_5% 2 10K_0402_5%
0 = DMI x 2
CFG5 (DMI select)
U3C
GRAPHICS
0312_Add test point.
PCI-EXPRESS
D
N43 M43
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
PEGCOMP
R53 24.9_0402_1% 1 2
D
1 = DMI x 4
*
+VCCP
CFG6
PEGCOMP trace width and spacing is 20/25 mils.
Reserved 0 = Reserved
CFG7 (CPU Strap)
1 = Mobile CPU CFG8 (Low power PCIE) CFG9
*
0 = Normal mode 1 = Low Power mode
*
0 = Reverse Lane
(PCIE Graphics Lane Reversal) CFG[11:10]
1 = Normal Operation
*
Reserved 00 01 10 11
CFG[13:12] (XOR/ALLZ)
CFG[15:14]
= Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation (Default)
* C
Reserved
CFG16 (FSB Dynamic ODT)
0 = Disabled 1 = Enabled
CFG[18:17]
*
Reserved 0 = No SDVO Device Present
SDVO_CTRLDATA
1 = SDVO Device Present
CFG19 (DMI Lane Reversal)
0 = Normal Operation (Lane number in Order)
*
*
1 = Reverse Lane CFG20 (PCIE/SDVO concurrent)
0 = Only PCIE or SDVO is operational.
*
1 = PCIE/SDVO are operating simu.
CFG[17:3] have internal pull up CFG[19:18] have internal pull down
B
CRESTLINE_1p0
For Crestline:1.3kohm For Calero: 255ohm
A
Compal Secret Data 2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc.
CRESTLINE((3/6)-VGA/LVDS/TV Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
A
Sheet
1
9
of
43
5
4
VCC SYNC
+3VS
2
2
2 1U_0603_10V4Z
N28
+1.5VS_QDAC
250mA 100mA
VCC_TX_LVDS
A PEG
C70
+3VS_HV
VCC_HV_1 VCC_HV_2
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
VCC_RXR_DMI_1 VCC_RXR_DMI_2
AD51 1200mA W50 W51 V49 V50
1450mA +VCC_PEG
AH50 250mA AH51
1
2
+
2
@
1
2
2
2
2 1 MBK2012121YZF_0805
+1.25VS
10U_FLC-453232-100K_0.25A_10% C95 0.1U_0402_16V4Z
1
1
2
2
+VCCP
+1.25VM_MPLL
+VCC_PEG
20mils
R74
1 +
2
1
2
2
2 1 MBK2012121YZF_0805
10U_0805_10V4Z
2
1
C103
2
1
+1.25VS
R73
2 1 0_0805_5%
1
C96 10U_0805_10V4Z
0.1U_0402_16V4Z
A7 F2 AH1
CRESTLINE_1p0
1
C92
1
+1.25VS
R71
R 70
1
C102 220U_6.3V_M
VTTLF1 VTTLF2 VTTLF3
100mA
C40 B40
0.47U_0603_10V7K C108
C110
2
+1.25VM_HPLL
+1.8V_TXLVDS
0.47U_0603_10V7K C107
+3VS BLM18PG181SN1D_0603 2 1 R 75
VCCD_LVDS_1 VCCD_LVDS_2
2
C
+1.25VS_DPLLA
A43
0.1U_0402_16V4Z
C109 0.022U_0402_16V7K
2
VCCD_PEG_PLL
J41 H42
2
1
+1.8V_SM_CK
0.47U_0603_10V7K C106
150mA
1
VCCD_HPLL
U48
+1.8V_LVDS
1
VCCD_QDAC
AN2
+1.25VS_PEGPLL
+3VS_TVDACC
VCCD_CRT VCCD_TVDAC
1
+1.5VS R68 1 2 0_0805_5%
120mA
100mA
D TV/CRT
75mA 50mAM32 25mAL29 5mA
2
+1.5VS_TVDAC
2
10U_0805_10V4Z
40mA
+3VS_TVDACC
VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2
2
1
C94
40mA
+3VS_TVDACB
+1.25VM_HPLL
VCCA_SM_CK_1 VCCA_SM_CK_2
C25 B25 C27 B27 B28 A28
BK24 BK23 BJ24 BJ23
1
C93
40mA +3VS_TVDACA
+1.5VS_TVDAC_R
4/20
BC29 BB29
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
C101
2
2 1 0_0603_5%
Reserv resister
B
VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2
+1.25VS_DMI
0.1U_0402_16V4Z
C100
2
1
0.1U_0402_16V4Z
C99
2
1
1U_0603_10V4Z
1
R450 +1.5VS_TVDAC
AT22 AT21 AT19 AT18 AT17 AR17 AR16
C 91
100mA 10U_0805_10V4Z
2
C98
C97
1
1U_0603_10V4Z
2 1 0_0603_5%
1
VTTLF
10U_0805_10V4Z 4.7U_0805_10V4Z 2 2 +1.25VM_A_SM_CK
1
+1.25VS L1 BLM18PG121SN1D_0603 2 1
150U_B_6.3VM_R40M
R72
C90
LVDS
220U_6.3V_M
C 89
SM CK
1
+1.25VS_PEGPLL
100mA
AJ50
1
+1.25VS
+V1.25VS_AXF
VCC_DMI
HV
1 2 0_0805_5%
POWER
B23 B21 A21
R65 1 2 0_0805_5%
0.1U_0402_16V4Z
1 C88 +
350mA VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
+1.8V
2
C86
+1.25VS
2
2
1
C87 0.022U_0402_16V7K
C
VCC_AXD_NCTF
2
1
C85
950mA
VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5
1
R64 0_0603_5%
C84
+1.25VM_A_SM R69
VCCA_PEG_PLL
AW18 AV19 AU19 AU18 AU17
AR29
R66 1 2 0_0805_5%
1
2
10U_0805_10V4Z
2
U51
AT23 AU28 AU24 AT29 AT25 AT30
0.1U_0402_16V4Z
+1.25VS_PEGPLL 20 mils
VSSA_PEG_BG
1
10U_0805_10V4Z
C83
K49
1
200mA VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6
C82
0.1U_0402_16V4Z
VCCA_PEG_BG
2
2
C81
K50
2
+1.8V_SM_CK
+1.25VS
1
+1.25VM_AXD
1U_0603_10V4Z
5mA
AXD
+3VS_PEG_BG R67 2 1 0_0603_5%
+3VS
AXF
VSSA_LVDS
2
C75
VTT PLL
VCCA_LVDS
B41
PEG
A41
1
C80
DMI
1000P_0402_50V7K
A LVDS
+1.8V_TXLVDS
A SM
10mA
2
C74
VCCA_MPLL
C73
CRT
VCCA_HPLL
AM2
150mA
R62 0_0603_5%
C78
AL2
+1.25VM_MPLL
1
0.1U_0402_16V4Z
+1.25VM_HPLL
2
C77
2
1
C76
VCCA_DPLLB
50mA
+1.25VS_DMI
1
10U_0805_10V4Z
VCCA_DPLLA
H49
80mA
10U_0805_10V4Z
B49
+1.25VS_DPLLB
2
1
2
D
0.1U_0402_16V4Z C79
+1.25VS_DPLLA
2
2.2U_0805_16V4Z
VSSA_DAC_BG
2 2
4.7U_0805_10V4Z
B32
1
+
0.47U_0603_10V7K
2
VCCA_DAC_BG
80mA
0.1U_0402_16V4Z
1 C72
C71 0.022U_0402_16V7K
1
A30
+3VS_DAC_BG
+3VS BLM18PG181SN1D_0603 2 1 R 63
1
1
1
C68
+3VS_DAC_CRT
C 69
10U_FLC-453232-100K_0.25A_10%
1
C67
VCCA_CRT_DAC_1 VCCA_CRT_DAC_2
1
+1.25VS
C66
+3VS_DAC_CRT
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1
C65
7/25
A33 B33
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22
4.7U_0805_10V4Z
C64
80mA
330U_D2E_2.5VM_R7
VCCSYNC
2
1U_0603_10V4Z
U 3H
J32
+1.25VS
+V1.25VS_AXF
R61
1
10U_0805_10V4Z
2
+1.25VS_DPLLB
5mA D
1
+VCCP
850mA
10U_0805_10V4Z
2
1 C62
0.1U_0402_16V4Z
2
2
R 59 2 1 0_0603_5%
A CK
1
3
10mA 0.1U_0402_16V4Z
1
1U_0603_10V4Z
2
0.1U_0402_16V4Z
C63 0.022U_0402_16V7K
1
+3VS BLM18PG181SN1D_0603 2 1 R 60 C508
TV
+3VS_DAC_BG
C104 0.1U_0402_16V4Z
1
1
2
2
C105 10U_0805_10V4Z
B
+VCCP_D
D3
+VCCP
2
R 76 2 1 10_0402_5% CH751H-40PT_SOD323-2
1
R77 2 1 0_0402_5%
+3VS_HV
+3VS +1.5VS_QDAC +3VS_TVDACA
2 1 100_0603_1% 1 C112
2
1
2
0.1U_0402_16V4Z
2
+1.5VS R78
C111 0.022U_0402_16V7K
C114
2
1
0.1U_0402_16V4Z
C113 0.022U_0402_16V7K
1
+3VS BLM18PG181SN1D_0603 2 1 R 79
+1.8V_TXLVDS R 80
2 1 0_0603_5% C115 1000P_0402_50V7K
1
1
2
2
+1.8V
C116 10U_0805_10V4Z
0208_Change C117 value from 220uF to 10uF. +1.8V_LVDS A
+3VS_TVDACB
2 1 0_0603_5% 1
2
C118 1U_0603_10V4Z
2
A
R 82 C117 10U_0805_10V4Z
C120
2
1
0.1U_0402_16V4Z
C119 0.022U_0402_16V7K
1
+3VS BLM18PG181SN1D_0603 2 1 R 81
+1.8V
1
2
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. CRESTLINE(4/6)-PWR
Size Document Number C ustom LA-38 21P D ate:
Rev 0.3
T u es d ay , J u l y 3 1 , 2 0 07
Sheet 1
10
of
43
5
4
3
2
1
+VCCP +VCCP
U3G
VCC_AXG=7700mA
VCC=1260mA
U3F
2
2
1
VCC AXM VCC AXM NCTF
VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19
A3 B2 C1 BL1 BL51 A51
VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7
AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
+VCCP
VCC_AXG=7700mA +VCCP 0.1U_0402_16V4Z
10U_0805_10V4Z 1 C136
1
C135
+
C137
1
1 C138
1U_0603_10V4Z
2
2
2
330U_D2E_2.5VM_R7
1 C139
2 10U_0805_10V4Z
CRESTLINE_1p0
2
0.1U_0402_16V4Z 1 C121
1
2
2
C122
1
C123 D
2 4.7U_0805_10V4Z
0.22U_0603_10V7K
C
B
1
1
2
1
2
1
2
1
2
A
om
2
C151 1U_0603_10V4Z
2
C150 1U_0603_10V4Z
A
1
C149 0.47U_0603_10V7K
2
C148 0.22U_0603_10V7K
AW45VCCSM_LF1 BC39 VCCSM_LF2 BE39 VCCSM_LF3 BD17 VCCSM_LF4 BD4 VCCSM_LF5 AW8 VCCSM_LF6 AT6 VCCSM_LF7 1
C147 0.22U_0603_10V7K
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
C146 0.1U_0402_16V4Z
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83
C145 0.1U_0402_16V4Z
R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14
VCC GFX NCTF
2
1
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36
VCC SM
1
C132
+
0.01U_0402_16V7K C131
AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33
1 C129 330U_4V_M
10U_0805_10V4Z C130
2
C144 0.1U_0402_16V4Z
2
1
2
C134
2
1
C143 0.1U_0402_16V4Z
Compal Secret Data 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc.
CRESTLINE((5/6)-PWR/GND Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
Security Classification
nf @ ho tm
ai
l.c
CRESTLINE_1p0
Tuesday, July 31, 2007
he x
2
1
C142 0.1U_0402_16V4Z
1
C141 0.22U_0402_10V4Z
2
C140 0.22U_0402_10V4Z
1
2
10U_0805_10V4Z C133
10U_0805_10V4Z
B
1
+1.8V
VCC_AXM=970mA
VCC_AXM=970mA
VCC_13
POWER
POWER VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6
R30
AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30
3720mA
2
+VCCP
1
R83 1 2 0_0603_5%
10U_0805_10V4Z
C
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
VCC GFX
2
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
VSS SCB
2
1
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50
VCC NCTF
2
1
C128
2
1
0.1U_0402_16V4Z C127
2
1
0.22U_0603_10V7K C126
C124
0.22U_0402_10V4Z C125
+
10U_0805_10V4Z
220U_D2_2.5VM
1
AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37
VSS NCTF
VCC=1260mA
VCC CORE
+VCCP D
VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12
VCC SM LF
AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32
Sheet
1
11
of
43
5
4
3
2
1
U3I A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16
D
C
B
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99
VSS
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
U3J C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39
VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243
K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3
VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286
VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305
W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28
VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
D
C
VSS
B
CRESTLINE_1p0
CRESTLINE_1p0 A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. CRESTLINE((6/6)-PWR/GND
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet 1
12
of
43
5
4
3
2
1
+1.8V
+1.8V V_DDR_MCH_REF
8 DDR_A_DQS#[0..7]
DDR_A_D2 DDR_A_D3
D
DDR_A_D8 DDR_A_D14
Layout Note: Place near JP34
DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D9 DDR_A_D15
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
V_DDR_MCH_REF 7,14,37
DDR_A_D6 DDR_A_D0 DDR_A_DM0 DDR_A_D5 DDR_A_D7
1
2
1
C153
DDR_A_DQS#0 DDR_A_DQS0
7,8 DDR_A_MA[0..14]
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
0.1U_0402_16V4Z
DDR_A_D4 DDR_A_D1
8 DDR_A_DQS[0..7]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
C152
8 DDR_A_DM[0..7]
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2.2U_0805_16V4Z
JP4
8 DDR_A_D[0..63]
2
D
DDR_A_D13 DDR_A_D12 DDR_A_DM1 M_CLK_DDR0 M_CLK_DDR#0
M_CLK_DDR0 7 M_CLK_DDR#0 7
DDR_A_D11 DDR_A_D10
+1.8V
DDR_A_DM3 DDR_A_D26 DDR_A_D27 DDR_CKE0_DIMMA
8
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
8 8
+0.9V
DDR_A_MA10 DDR_A_BS0 DDR_A_WE#
DDR_A_BS0 DDR_A_WE#
DDR_A_CAS# DDR_CS1_DIMMA#
8 DDR_A_CAS# 7 DDR_CS1_DIMMA#
2
1
2
M_ODT1
M_ODT1
1
DDR_A_D37 DDR_A_D36
2
DDR_A_DQS#4 DDR_A_DQS4
C176
C175
C174
C173
C172
C171
C170
C169
C168
C167
C166
C165
C164
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
7
DDR_A_D35 DDR_A_D32 DDR_A_D40 DDR_A_D44
B
DDR_A_DM5 DDR_A_D41 DDR_A_D46 DDR_A_D49 DDR_A_D48 +0.9V
1 2 RP3
4 3
4 3
56_0404_4P2R_5% RP4 1 4 4 2 3 3
56_0404_4P2R_5% 1 DDR_A_MA7 2 DDR_A_MA6
56_0404_4P2R_5% RP6 DDR_A_RAS# 1 4 4 DDR_CS0_DIMMA# 2 3 3
56_0404_4P2R_5% 1 DDR_A_MA12 2 DDR_A_MA9
DDR_A_MA8 DDR_A_MA5 RP5
RP7 DDR_A_MA1 DDR_A_BS0
1 2
56_0404_4P2R_5% RP8 4 4 3 3
1 2
56_0404_4P2R_5% RP10 56_0404_4P2R_5% 4 4 1 DDR_A_MA0 3 3 2 DDR_A_BS1
RP9 DDR_A_WE# DDR_A_CAS# A
Layout Note: Place t hes e resistor closely JP34,all trace length Max=1.5"
56_0404_4P2R_5% 1 DDR_CKE0_DIMMA 2 DDR_A_BS2
DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D54 DDR_A_D50 DDR_A_D61 DDR_A_D60 DDR_A_DM7 DDR_A_D59 DDR_A_D58
56_0404_4P2R_5% 1 DDR_A_MA4 2 DDR_A_MA2
+3VS
RP11 56_0404_4P2R_5% RP12 56_0404_4P2R_5% DDR_CS1_DIMMA# 2 3 4 1 M_ODT0 M_ODT1 1 4 3 2 DDR_A_MA13 56_0404_4P2R_5% RP13 56_0404_4P2R_5% 4 1 DDR_CKE1_DIMMA 1 2 3 2 DDR_A_MA14
DDR_A_MA11 R86
CLK_SMBDATA CLK_SMBCLK
14,15 CLK_SMBDATA 14,15 CLK_SMBCLK
1
C178
2
2006/02/13
Issued Date
2
FOX_ASOA426-M4R-TR CONN@
SO-DIMM A
DDR_A_D31 DDR_A_D30 DDR_CKE1_DIMMA
DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 DDR_A_MA13
4
3
DDR_A_BS1 8 DDR_A_RAS# 8 DDR_CS0_DIMMA# 7 M_ODT0
7
DDR_A_D39 DDR_A_D38 DDR_A_DM4 DDR_A_D34 DDR_A_D33 DDR_A_D45 DDR_A_D43 B
DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D47 DDR_A_D42 DDR_A_D52 DDR_A_D53 M_CLK_DDR1 M_CLK_DDR#1
M_CLK_DDR1 7 M_CLK_DDR#1 7
DDR_A_DM6 DDR_A_D51 DDR_A_D55 DDR_A_D57 DDR_A_D56 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63
A
SP07F001720 S SOCKET FOXCONN AS0A426-N4RN-7F DR2R H4 FOX_AS0A426-M4R-TR_200P
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
C
DDR_CKE1_DIMMA 7
DDR_A_MA14
Compal Secret Data
Security Classification
56_0402_5%
1
C177
0.1U_0402_16V4Z
DDR_A_MA3 DDR_A_MA10
RP2
2.2U_0805_16V4Z
RP1
DDR_A_DQS#3 DDR_A_DQS3
ai
7 DDR_CKE0_DIMMA
DDR_A_D28 DDR_A_D25
2
Title
nf @ ho tm
C
DDR_A_D23 DDR_A_D22
om
DDR_A_D29 DDR_A_D24
PM_EXTTS#0 7
DDR_A_DM2
l.c
DDR_A_D18 DDR_A_D19
DDR_A_D20 DDR_A_D21
Compal Electronics, Inc. DDRII-SODIMM SLOT1
Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
C154 330U_4V_M 2
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204
Tuesday, July 31, 2007
he x
+
2
DDR_A_DQS#2 DDR_A_DQS2
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND
R85 10K_0402_5% 2 1
2
1
C163
C162
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C161
0.1U_0402_16V4Z
2
1
C160
C159
2
1
0.1U_0402_16V4Z
C158
2
1
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
C157
2
2.2U_0805_16V4Z
2
1
C156
2.2U_0805_16V4Z
C155
2.2U_0805_16V4Z
1
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
R84 10K_0402_5% 2 1
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203
DDR_A_D16 DDR_A_D17 1
Sheet
1
13
of
43
5
4
3
2
1
+1.8V
8 DDR_B_DQS#[0..7]
+1.8V
8 DDR_B_D[0..63]
V_DDR_MCH_REF
8 DDR_B_DM[0..7]
DDR_B_D10 DDR_B_D11
+1.8V
2
DDR_B_D17 DDR_B_D20
1
C189
C188
2
1
0.1U_0402_16V4Z
C187
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
1
C186
0.1U_0402_16V4Z
2
1
C185
C184
2
1
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
C183
2
2.2U_0805_16V4Z
C182
C181
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2
1
DDR_B_DQS#2 DDR_B_DQS2
2
DDR_B_D18 DDR_B_D19 DDR_B_D28 DDR_B_D25 DDR_B_DM3 DDR_B_D30 DDR_B_D31
C
DDR_CKE2_DIMMB
7 DDR_CKE2_DIMMB
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
8
DDR_B_BS2
DDR_B_BS2
DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
+0.9V
2
1
2
DDR_B_MA10 DDR_B_BS0 DDR_B_WE#
DDR_B_BS0 DDR_B_WE#
DDR_B_CAS# DDR_CS3_DIMMB#
8 DDR_B_CAS# 7 DDR_CS3_DIMMB# 1
7
M_ODT3
M_ODT3
DDR_B_D32 DDR_B_D33
2 C202
C201
C200
C199
C198
C197
C196
C195
C194
C193
C192
C191
C190
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
8 8
DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35
B
DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43
RP14 1 2
DDR_B_BS0 DDR_B_MA10
RP16 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_B_MA14 1 4 4 1 DDR_B_MA11 2 3 3 2
DDR_B_MA0 DDR_B_BS1
RP18 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DDR_B_MA5 1 4 4 1 DDR_B_MA8 2 3 3 2
4 3
4 3
RP15 56_0404_4P2R_5% DDR_B_MA9 1 DDR_B_MA12 2
Layout Note: Place t hes e resistor closely JP10,all trace length Max=1.5"
DDR_B_D51 DDR_B_D50 DDR_B_D56 DDR_B_D61 DDR_B_DM7 DDR_B_D59 DDR_B_D58
RP20 56_0404_4P2R_5% RP21 56_0404_4P2R_5% DDR_B_RAS# DDR_B_MA7 1 4 4 1 DDR_CS2_DIMMB# 2 DDR_B_MA6 3 3 2
56_0402_5%
2.2U_0805_16V4Z
1 2
C204 C203
2
2006/02/13
Issued Date
2
M_CLK_DDR3 M_CLK_DDR#3
DDR_B_D21 DDR_B_D16
4
3
PM_EXTTS#1 7
DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D26 DDR_B_D24 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D29 DDR_B_D27
C
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB 7
DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB#
DDR_B_BS1 8 DDR_B_RAS# 8 DDR_CS2_DIMMB# 7
M_ODT2 DDR_B_MA13
M_ODT2
DDR_B_DM4 DDR_B_D39 DDR_B_D38 DDR_B_D44 DDR_B_D45
B
DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 M_CLK_DDR2 M_CLK_DDR#2
M_CLK_DDR2 7 M_CLK_DDR#2 7
DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63
FOX_AS0A426-N8RN-7F CONN@
SO-DIMM B
SP07000BZ00 S SOCKET FOXCON AS0A426-N8RN-7F H8 DDR2R FOX_AS0A426-N8RN-7F_200P
2006/03/10
Deciphered Date
2
7
DDR_B_D36 DDR_B_D37
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
M_CLK_DDR3 7 M_CLK_DDR#3 7
DDR_B_D14 DDR_B_D15
R87 1
2
+3VS
10K_0402_5%
Compal Secret Data
Security Classification
56_0404_4P2R_5%
1
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 GND
DDR_B_DM1
R88
DDR_CKE3_DIMMB R89
DDR_B_BS2 DDR_CKE2_DIMMB
1
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
2
D
10K_0402_5%
RP22 56_0404_4P2R_5% RP23 56_0404_4P2R_5% DDR_B_MA4 1 4 4 1 DDR_B_MA2 2 3 3 2 RP24 56_0404_4P2R_5% RP25 56_0404_4P2R_5% DDR_CS3_DIMMB# 2 M_ODT2 3 4 1 M_ODT3 DDR_B_MA13 1 4 3 2 56_0404_4P2R_5% RP26 4 1 2 3
CLK_SMBDATA CLK_SMBCLK
13,15 CLK_SMBDATA 13,15 CLK_SMBCLK +3VS
DDR_B_CAS# DDR_B_WE# A
DDR_B_DQS#6 DDR_B_DQS6
0.1U_0402_16V4Z
+0.9V
DDR_B_MA1 DDR_B_MA3
DDR_B_D48 DDR_B_D49
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201
2
1
DDR_B_D12 DDR_B_D13
1
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D6 DDR_B_D7
1
A
2
DDR_B_D8 DDR_B_D9
DDR_B_DM0
C180
DDR_B_D2 DDR_B_D3
Layout Note: Place near JP10
DDR_B_D5 DDR_B_D4
C179
DDR_B_DQS#0 DDR_B_DQS0 D
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
0.1U_0402_16V4Z
DDR_B_D0 DDR_B_D1
7,8 DDR_B_MA[0..14]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
2.2U_0805_16V4Z
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
8 DDR_B_DQS[0..7]
1
V_DDR_MCH_REF 7,13,37
JP5
Title
Compal Electronics, Inc. DDRII-SODIMM SLOT2
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet 1
14
of
43
4
CPU MHz
SRC MHz
PCI MHz
0
1
133
100
33.3
0
1
0
200
100
33.3
0
1
1
166
100
33.3
1
+3VS
2 1
FBMA-L11-201209-221LMA30T_0805
1
C205 10U_0805_10V4Z
2
2
1
C206 0.1U_0402_16V4Z
1 C207 680P_0402_50V7K
2
2
1
C208 0.1U_0402_16V4Z
+1.25VS
1 C209 680P_0402_50V7K
2
1
C210
C211 R91
2
0.1U_0402_16V4Z
2
2.2K_0402_5%
Place close to U4
FSB Frequency Selet:
1
20,22,23 ICH_SMBDATA
R1074
R1086
R1098
1
FBMA-L11-201209-221LMA30T_0805
Stuff
R1086
R1139
R1135
No Stuff
R1083
R1107
R1128
R1113
R1098
R1135
R1139
R1113 R1074
R1128 R1139
R1083
R1086
R1098
R1074
R1107
R1113
C212
2 10U_0805_10V4Z
R1135
D
R1128
R94
1 2
CPU_BSEL0
2 1
2
CLRP2 NO SHORT PADS
VDD_PCI VDD48 VDDPLL3 VDDREF
39 55
VDDSRC VDDCPU
12 20 26
VDD96_IO VDDPLL3_IO VDDSRC_IO
36 49
CLRP4,CLRP5 for 667/800 FSB select SHORT CLRP5, NO SHORT CLRP4 -- CPU option SHORT CLRP4, NO SHORT CLRP5 -- FSB 667
0301_Change R105 from 22 ohm to 0 ohm. 0312_Change R106, 107, 109 from 22 to 33 ohm.
R103
475_0402_1%1
2 R104
475_0402_1%1
2 R105
PCI_CLK1
3
22_0402_5% 1 22_0402_5% 1 0_0402_5% 1
2 R106 2 R354 2 R107
PCI2_TME
4
32 CLK_PCI_EC
33_0402_5% 1
2 R108
27_SEL
18 CLK_PCI_ICH
33_0402_5% 1
20 CLKSATAREQ#
@ 1K_0402_5%
CLKREQ#_B
2
7
2
22 CLK_DEBUG_PORT_0 Remove PCI LAN,Change to Debug clock31 CLK_DEBUG_PORT_1 +VCCP 32 CLK_DEBUG_PORT_2
R110
1
CPU_BSEL1
1
2
1 2 R114 0_0402_5%
2
MCH_CLKSEL1 7
Routing the trace at least 10mil
R113 1K_0402_5%
PCI3
ITP_EN
2 R109
5 6 7
PCI1/CR#_B
C224 18P_0402_50V8J @ R117
B
14.31818MHZ_16P CLK_XTAL_OUT
1
59
2
1
2
33_0402_1% 1
2
R119
33_0402_1% 1
2
R123
2
20 CLK_14M_ICH R124
33_0402_1% 1
2 @ R125
5
CPU_BSEL2
1 2 R130 0_0402_5%
10
FSB
57
FSC
62
1
2
2
23
1= Enable SRC0 & 27MHz For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed
29 58
R_CLK_PCIE_NCARD# R_CLK_PCIE_NCARD
33 32
R335
SRC9 SRC9#
30 R_CLK_PCIE_LAN 31 R_CLK_PCIE_LAN#
X1 X2
USB_48MHZ/FSLA
44 43
R111 1 1 R112
R_MINI_ROB_CLKREQ# R_CLKREQ#_G
R146 10K_0402_5% @
R440 1 1 R439 1 R334 1
CLK_SMBCLK
2
0_0402_5% 0_0402_5%
2 2
475_0402_1% R115 2 1 2 1 R333 475_0402_1%
1
2
C222
2
C223
2
C376
2
C
New card WLAN clock REQ
NCARD_CLKREQ# 23
CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24 +3VS
R332 10K_0402_5%
1
R116 10K_0402_5% 2 +3VS
R121 1 1 R122
2 2
0_0402_5% 0_0402_5%
24 25
R _PCIE_ICH R_PCIE_ICH#
R126 1 1 R127
2 2
0_0402_5% 0_0402_5%
21 22
R_PCIE_SATA R_PCIE_SATA#
R131 1 1 R132
2 2
0_0402_5% 0_0402_5%
17 18
SSCDREFCLK R134 SSCDREFCLK# R135
1 1
2 2
0_0402_5% 0_0402_5%
13 14
R_MCH_DREFCLK R_MCH_DREFCLK#
R136 1 1 R137
2 2
0_0402_5% 0_0402_5%
56
1 @ R141
2
ICS9LPRS355_TSSOP64
1 @ R142 1 R143
2
0_0402_5% 0_0402_5%
MINI_ROB_CLKREQ# 22 MINI_CLKREQ# 22
Mini card Robeson clock REQ Mini card WLAN clock REQ B
CLK_PCIE_MCARD 22 CLK_PCIE_MCARD# 22
CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7
CLK_PCIE_ICH 20 CLK_PCIE_ICH# 20
CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19
MCH_SSCDREFCLK 7 MCH_SSCDREFCLK# 7
GND GND SRC0/DOT96 SRC0/DOT96#
GNDCPU
CLK_MCH_DREFCLK 7 CLK_MCH_DREFCLK# 7
GNDSRC GNDSRC CK_PWRGD/PD# GNDREF
VGATE
0_0402_5%
CLK_ENABLE 32
0_0402_5%
CK_PWRGD 20
2
2006/02/13
3
20,39
Compal Secret Data
Security Classification Issued Date
0_0402_5%
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
2
C221
CLK_PCIE_NCARD# 23 CLK_PCIE_NCARD 23
2
R_MCH_3GPLL R_MCH_3GPLL#
SRC1/SE1/27MHz_NonSS SRC1#/SE2/27MHz_SS
C220
1 CLK_48M_ICH @ 5P_0402_50V8C 1 CLK_14M_ICH @ 4.7P_0402_50V8C 1 CLK_PCI_ICH @ 4.7P_0402_50V8C 1 CLK_PCI_EC @ 4.7P_0402_50V8C 1 CLK_DEBUG_PORT_0 @ 4.7P_0402_50V8C 1 CLK_DEBUG_PORT_1 @ 5P_0402_50V8C 1 CLK_DEBUG_PORT_2 @ 5P_0402_50V8C
+3VS
10K_0402_5%
27 28
REF0/FSLC/TEST_SEL
2
475_0402_1%
2 2
SRC4 SRC4#
2
C219
CLK_PCIE_MCARD_ROB 22 CLK_PCIE_MCARD_ROB# 22
0_0402_5% 0_0402_5%
2 2
C218
CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7 0_0402_5% 0_0402_5%
2 2
41 40
SRC6 SRC6#
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4
0_0402_5% 0_0402_5%
R118 R_CLK_PCIE_MCard 1 R_CLK_PCIE_MCard# 1 R120
FSLB/TEST MODE
GND48
0_0402_5% 0_0402_5%
R438 1 1 R437
NCARD_CLKREQ_R# 2
PCIF5/ITP_EN
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
For Layout request: 1. Change MINI_CLKREQ# from pin 32 to pin 43. 2. Change CLK_PCIE_MCARD from SRC9 to SRC6.
2 2
35 34
GNDPCI
For 27_SEL, 0 = Enable DOT96 & SRC1,
R97 1 1 R100
R_CLK_PCIE_MCARD_ROB R_CLK_PCIE_MCARD_ROB#
8
52
1
1
R_MCH_BCLK R_MCH_BCLK#
2 2
47 46
SRC2/SATA SRC2#/SATA#
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
PCI2_TME
R145 10K_0402_5%
5
R_CPU_BCLK R_CPU_BCLK#
SRC8/ITP SRC8#/ITP#
SRC11/CR#_H SRC11#/CR#_G
PCI4/27_Select
1 = Overclocking of CPU and SRC NOT allowed
2
2
2
27_SEL
R144 10K_0402_5%
R140 10K_0402_5%
1
1
R139 10K_0402_5% @
ITP_EN
1
2
2
2 1
XDP@
54 53
H_STP_PCI# 20 H_STP_CPU# 20 R95 1 1 R96
CPU1_F CPU1#_F
GNDSRC
19
R138 10K_0402_5%
Q4 3 2N7002_SOT23-3
1
CLK_SMBCLK 13,14 CLK_SMBDATA 13,14
51 50
42
15
+3VS
+3VS
20,22,23 ICH_SMBCLK
CLK_SMBCLK CLK_SMBDATA
MCH_CLKSEL2 7
R129 1K_0402_5%
11
A
38 37
SRC3/CR#_C SRC3#/CR#_D
0_0402_5%
+3VS
PCI_STOP# CPU_STOP#
VDDSRC_IO
45
@ R133
+3VS
64 63
1
+1.25VS_CK505
SCLK SDATA
SRC7/CR#_F SRC7#/CR#_E
FSA
1
FSC
32 CLK_14M_DEBUG
@ 1K_0402_5%
48
PCI3
C225 18P_0402_50V8J
+VCCP
R128 10K_0402_5% 2 1
SB, MINI PCI
2 2 680P_0402_50V7K
PCI2/TME
0_0402_5% 20 CLK_48M_ICH
NC
SRC10# SRC10
CLK_XTAL_IN
1
60
2
1
5
1
2
PCI0/CR#_A
Y1 @ 1K_0402_5% FSB
2 680P_0402_50V7K
CPU0 CPU0#
VDDSRC_IO VDDCPU_IO
MCH_CLKSEL0 7
R99 1K_0402_5%
1
2
U4 2 9 16 61
1
5
+VCCP
56_0402_5% CLRP1 NO SHORT PADS
C
R98 2.2K_0402_5% FSA 2 1
2
C214
0.1U_0402_16V4Z 1 C217 C216
0308_Change R89 and R92 form 0 ohm to bead, C209, C211, C216, C218 from 0.1uF to 680pF.
+1.25VS_CK505 1
1
10U_0805_10V4Z 1 1 C215
C213
R1139
+3VS_CK505
No Stuff
0.1U_0402_16V4Z 1
2
Title
A
om
No Stuff
2
l.c
*(Default)
1
ai
R1083
S
R1135
2 G
R1107
2 G
Stuff
Stuff
CLK_SMBDATA
+1.25VS_CK505
CPU Driven
800MHz
2.2K_0402_5%
Q3 3 2N7002_SOT23-3
R93
667MHz
R92
0.1U_0402_16V4Z
D
D
0
+3VS_CK505
R90 +3VS
nf @ ho tm
CLKSEL0
Compal Electronics, Inc. Clock generator
Size
Document Number
LA-3821P Date:
R ev 0.3
ai
FSLA
CLKSEL1
1
Tuesday, July 31, 2007
he x
FSLB
2
S
FSLC CLKSEL2
3
D
5
Sheet
1
15
of
43
A
B
C
D
E
EMI
1
1 3
2
3
2
@
3
2
@
D7 @ DAN217_SC59
1
D6 DAN217_SC59
1
D5 DAN217_SC59
CRTL_B CRTL_G CRTL_R
+R_CRT_VCC , +CRTVDD (40mils) +5VS
EMI
2
+R_CRT_VCC F1 1 1
RB411D_SOT23
+CRTVDD
NZQA5V6AXV5T1_SOT533-5
+CRTVDD D8
Place close to JP6 CRT CONNECTOR
3
1
C226 0.1U_0402_16V4Z
2
2 1 JP6
4
CRT_VSYNC_R 74AHCT1G125GW_SOT353-5
2
2
16
2
17
Q6 3V_DDCCL 3 2N7002_SOT23-3
1
R153
S
D
2
CLOSE TO JP3
1
2 G 1
1 R155
2 0_0402_5%
3VDDCDA 9
2 0_0402_5%
3VDDCCL 9
R154
S
D
1
5
@ D4
SUYIN_070549FR015S208CR Q5CONN@ 3 2N7002_SOT23-3 3V_DDCDA
2 G
1
1
220P_0402_50V8J
U6 Y
1
R151 4.7K_0402_5%
C232 22P_0402_50V8J
CR T_HSYNCRFL 1 2 L5 FBM-L11-160808-800LMT_0603
R156
2 2.2K_0402_5% +3VS
C237
A
1
5 P 2
G
CR TVSYNC 2 0_0402_5%
1
@
3
CRT_VSYNC
2
C RT_VSYNCRFL 1 2 L6 FBM-L11-160808-800LMT_0603
OE#
R157 9
2
+CRTVDD 1
220P_0402_50V8J
74AHCT1G125GW_SOT353-5
2
1
C236
@ CR T_HSYNC_R
1
R150 4.7K_0402_5%
@ 4
2
CRTL_B C231 22P_0402_50V8J
U5 Y
2
1
CRTL_G
C235 10P_0402_50V8J
A
1
EMI
C234 10P_0402_50V8J
P 2
G
CRTHSYNC 2 0_0402_5%
1
2
3
CRT_HSYNC
1
0.1U_0402_16V4Z R152 9
OE#
5
C233 1 2
1
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
CRTL_R
C230 22P_0402_50V8J
EMI
+5VS
2
C229 10P_0402_50V8J
CRT_B
R149 75_0402_5% 1 2
CRT_B C228 10P_0402_50V8J
9
CRT_G
R148 75_0402_5% 1 2
CRT_G
C227 10P_0402_50V8J
9
L2 MBK2012800YZF 1 2 L3 MBK2012800YZF 1 2 L4 MBK2012800YZF 1 2
CRT_R
R147 75_0402_5% 1 2
CRT_R
4
2
1.1A_6VDC_FUSE
EMI 9
1
2.2K_0402_5%
3
3
4
4
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. CRT & TVout Connector
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet E
16
of
43
5
4
3
2
1
LVDS CONN D
D
B+
+LCDVDD
INVPWR_B+ @ L7
2 0_0805_5%
1
C238 L8 1 2 FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z
1
1
2
2
C239 0.1U_0402_16V4Z
0308_Reserve L10 and install L11. JP7
2
31 32
1
2
C241 680P_0402_50V7K
LVDSA1+ LVDSA1LVDSA0+ LVDSA0LVDSAC+ LVDSAC-
LVDSA2+ 9 LVDSA2- 9 LVDSA1+ 9 LVDSA1- 9 +3VS
LVDSA0+ 9 LVDSA0- 9 LVDSAC+ 9 LVDSAC- 9
R158 2.2K_0402_5%
GND1 GND2
LCD_CLK LCD_DATA
R159 2.2K_0402_5% C
ACES_88242-3001
LVDS connector
+3VS 2
2
C240 680P_0402_50V7K
680P_0402_50V7K
1
680P_0402_50V7K 2 1
1 2
680P_0402_50V7K
1
LVDSA2+ LVDSA2-
2
INVTPWM DISPLAYOFF# DAC_BRIG LCD_CLK LCD_DAT
INV_PWM
32 DAC_BRIG 9 LCD_CLK 9 LCD_DATA
C244
C
C243
C242
32
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
2
+3VS
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1
+LCDVDD
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
INVPWR_B+
0308_Install all cap for EMI request.
R292
1
4.7K_0402_5% 4/14 R161 1
2
@
0_0402_5% D9 32
1
BKOFF#
DISPLAYOFF#
2 CH751H-40PT_SOD323-2 D10
+LCDVDD
+3VS
Q7
+5VALW
9,32
1
ENABLT 2
+LCDVDD B
SI2301BDS-T1-E3_SOT23-3
B
R164
1
100K_0402_5% 3
2
1
D
S
1
R160
1
1
2
2 G
R162 47K_0402_5%
100_0402_5%
D Q8 2N7002_SOT23-3
2 CH751H-40PT_SOD323-2
2 G
R163 1 2 100K_0402_5% 1 C248 0.22U_0402_10V4Z
C247 S
0.047U_0402_16V7K
2
C246 C245 4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
Q9 2N7002_SOT23-3
2
2
R165 100K_0402_5%
1
D
2 G 3
ENAVDD 1
9
1
3
S
A
A
Compal Secret Data 2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. LCD CONN.
Size
Document Number
LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
Avoid Panel display garbage after power on.
Sheet
1
17
of
43
5
4
3
2
1
PCI_GNT0# 1
+3VS
D
PCI_DEVSEL#
@ R166 1K_0402_5%
PCI_STOP#
2
2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5%
PC I_TRDY#
U7B
PCI_FRAME# PCI_PLOCK# PCI_IR DY# PCI_SERR# PCI_PERR#
+3VS
2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 1 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5%
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
PCI_REQ0# PCI_REQ1#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
F9 B5 C5 A10
PIRQA# PIRQB# PIRQC# PIRQD#
PCI
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55
A4 D7 E18 C18 B19 F18 A11 C10
PCI_REQ0# PCI_GNT0# PCI_REQ1#
D
PCI_REQ2# PCI_REQ3# PCI_GNT3#
C/BE0# C/BE1# C/BE2# C/BE3#
C17 E15 F16 E17
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
C8 D9 G6 D16 A7 B7 F10 C16 C9 A17
PCI_IR DY#
PLTRST# PCICLK PME#
AG24 B10 G7
PCI_PLTRST# CLK_PCI_ICH PCI_PME#
T24
R175 PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PC I_TRDY# PCI_FRAME#
2
PCI_RST# 1 0_0402_5%
R179 2 CLK_PCI_ICH 15 PCI_PME# 32
PLT_RST# 1 0_0402_5%
Place closely pin B10
Interrupt I/F PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
PCI_RST# 31,32
F8 G11 F12 B3
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PLT_RST# 7,22,23,24
Boot BIOS Strap
C
CLK_PCI_ICH
PCI_GNT0#
R187
SPI_CS#1
Boot BIOS Location
ICH8M REV 1.0 PCI_REQ2#
@ 10_0402_5% 1
C
1 R176 1 R177 1 R178 1 R180 1 R181 1 R182 1 R183 2 R184 1 R185 1 R186 1 R188 1 R189
D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3
2
1 R167 1 R168 1 R169 1 R170 1 R171 1 R172 1 R173 1 R174
PCI_REQ3# C249
@ 8.2P_0402_50V
0
1
SPI
1
0
PCI
1
1
LPC
1
2
*
A16 swap override Strap *Low= A16 swap override Enble PCI_GNT3# High= Default
B
B
A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. ICH8(1/4)-PCI/INT
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet 1
18
of
43
5
4
+RTCVCC
2
1
ICH8M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
R192 1
1M_0402_5% 2 SM_INTRUDER#
@ R193 0_0402_5% 2
330K_0402_1% 2 ICH_INTVRMEN
+3VS R191
2
330K_0402_1% 2 LAN100_SLP
1
R190 1
R194 1
3
@ R196 0_0402_5%
ICH_INTVRMEN
GATEA20
Low = Internal VR Disabled High = Internal VR Enabled(Default)
2
1
10K_0402_5% R195 KB_RST#
ICH8M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05)
2
1
10K_0402_5% D
1
D
ICH_LAN100_SLP
Low = Internal VR Disabled High = Internal VR Enabled(Default)
+VCCP R197 H_FERR#
ICH_RTCRST#
AF23
C251 15P_0402_50V8J
C252 1U_0603_10V4Z
2
INTRUDER#
ICH_INTVRMEN AF25 LAN100_SLP AD21
INTVRMEN LAN100_SLP
1
B24
4
Y2
IN
OUT
1
D22
NC
C
+1.5VS 25 ACZ_BITCLK_MDC 27 ACZ_BITCLK 27 ACZ_SYNC 25 ACZ_SYNC_MDC 27,32 ACZ_RST# 25 ACZ_RST#_MDC 27 ACZ_SDIN0 25 ACZ_SDIN1
27 ACZ_SDOUT 25 ACZ_SDOUT_MDC
30
SATA_LED#
22 SATA_RXN0_C 22 SATA_RXP0_C 22 SATA_TXN0 22 SATA_TXP0
R203 1 R338 47_0402_5% R204 47_0402_5% R206 33_0402_5% R341 33_0402_5% R207 33_0402_5% R445 33_0402_5%
GLAN_COMP
2 24.9_0402_1% 1 2 1 2 1 2 1 2 1 2 1 2
D21 E20 C20
LAN_TXD0 LAN_TXD1 LAN_TXD2
R209 33_0402_5% 1 R446 33_0402_5% 1
HDA_BITCLK HDA_SYNC
AJ16 AJ15
HDARST#
AE14
ACZ_SDIN0 ACZ_SDIN1
AJ17 AH17 AH15 AD13
HDA_SDOUT
2 2
AE13 AE10 AG14
SATA_LED#
AF10
SATA_RXN0_C SATA_RXP0_C 3900P_0402_50V7K SATA_TXN0 C253 1 2 SATA_TXP0 C254 1 2
SATA_TXN0_C SATA_TXP0_C
3900P_0402_50V7K
B
15 CLK_PCIE_SATA# 15 CLK_PCIE_SATA
CLK_PCIE_SATA# CLK_PCIE_SATA R212 1
2
AF6 AF5 AH5 AH6
GLAN_COMPI GLAN_COMPO
FERR#
HDA_SDOUT
G9 E6
LPC_DRQ0# T25 PAD
LPC_FRAME# 22,31,32
AF13 AG26
GATEA20 H_A20M#
AF26 AE26
H_DPRSTP_R#
AD24
H_DPSLP# H_FERR#
AE24 AC20 AH14
H_INIT# H_INTR KB_RST#
NMI SMI#
AD23 AG28
H_NMI H_SMI#
H_DPRSTP# 5,7,39
within 2" from R1557 +VCCP C
H_NMI 4 H_SMI# 4
THRMTRIP_ICH#
TP8
AA23
SATARBIAS# SATARBIAS
H_DPRSTP# 1 0_0402_5%
H_INIT# 4 H_INTR 4 KB_RST# 32
H_STPCLK#
24.9_0402_1%
56_0402_5%
H_IGNNE# 4
AE27
R205 56_0402_5%
H_STPCLK# 4 1
2
R208
24_0402_1%
H_THERMTRIP# 4,7
IDE_HDD[0..15] 22
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6
IDE_HDD0 IDE_HDD1 IDE_HDD2 IDE_HDD3 IDE_HDD4 IDE_HDD5 IDE_HDD6 IDE_HDD7 IDE_HDD8 IDE_HDD9 IDE_HDD10 IDE_HDD11 IDE_HDD12 IDE_HDD13 IDE_HDD14 IDE_HDD15
DA0 DA1 DA2
AA4 AA1 AB3
IDE_HDA0 IDE_HDA1 IDE_HDA2
Y6 Y5
IDE_HDCS1# IDE_HDCS3#
W4 W3 Y2 Y3 Y1 W5
IDE_HDIOR# IDE_HDIOW# IDE_HDACK# ID E_HIRQ IDE_HIORDY IDE_HDREQ
DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ
56_0402_5% @ R201 2 1
H_PWRGOOD 5
AA24
SATA_CLKN SATA_CLKP
H_DPSLP#
H_DPSLP# 5 H_FERR# 4
H_IGNNE#
DCS1# DCS3#
56_0402_5% @ R199 2 1
GATEA20 32 H_A20M# 4
STPCLK#
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
H_DPRSTP#
LPC_DRQ#0 32
2 R202
THRMTRIP#
SATALED#
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
LPC_FRAME#
H_PWRGOOD
INIT# INTR RCIN#
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34
AF2 AF1 AE4 AE3
C4
AG29
IGNNE#
HDA_RST# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
AF27
CPUPWRGD/GPIO49
HDA_BIT_CLK HDA_SYNC
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
AB7 AC6
A20GATE A20M# DPRSTP# DPSLP#
GLAN_DOCK#/GPIO13
AG3 AG4 AJ4 AJ3
AG1 AG2
LDRQ0# LDRQ1#/GPIO23
LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2
D25 C25
FWH4/LFRAME#
GLAN_CLK
C21 B21 C22
AH21
3
2
NC
32.768KHZ_12.5P_1TJS125BJ2A251
0205_Change Crystal type.
RTCRST#
SM_INTRUDER# AD22
E5 F5 G8 F6
1
2
2
20K_0402_5%
RTC LPC
2
1
+RTCVCC 1
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
LAN / GLAN CPU
10M_0402_5% 1
RTCX1 RTCX2
IHDA
AG25 AF24
IDE
ICH_RTCX1 ICH_RTCX2 R200
C250 15P_0402_50V8J
LPC_AD[0..3] 22,31,32
U7A
ICH_RTCX2
SATA
2
1
2
ICH_RTCX1 R198 1
2
placed within 2" from ICH8M
+3VS
IDE_HDA0 22 IDE_HDA1 22 IDE_HDA2 22
IDE_HIORDY ID E_HIRQ
R210 1 R211 1
2 4.7K_0402_5% 2 8.2K_0402_5% B
IDE_HDCS1# 22 IDE_HDCS3# 22 IDE_HDIOR# 22 IDE_HDIOW# 22 IDE_HDACK# 22 IDE_HIRQ 22 IDE_HIORDY 22 IDE_HDREQ 22
ICH8M REV 1.0
Within 500 mils
All trace 20mils R214 1
+RTCVCC
2
BATT1.1
0_0603_5% RB751V_SOD323
1
R213 W=20mils 1 2 W=20mils 100_0603_1%
D14 1
2 @
+CHGRTC
2
1
C255 1U_0603_10V4Z
RB751V_SOD323
A
D11 2
Compal Secret Data 2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc.
ICH8(2/4)_LAN,HD,IDE,LPC Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
1
om
0420_Change RTC battery to power
A
CLRP3 SHORT PADS part.
2
07/23
Sheet
1
19
of
43
4
3
2
1
+3VALW
1 R230
1 R234 1 @ R237
2 8.2K_0402_5%
1
SIRQ 2 10K_0402_5% CLKSATAREQ# 2 10K_0402_5%
1
IDE_RESET# 2 8.2K_0402_5% 2 8.2K_0402_5%
23,32 CPUSB# 32 EC_SMI# 32 EC_SCI#
PAD T35
22
IDE_RESET#
27
SB_SPKR
2 @ R249
1 AG22
SMBALERT#/GPIO11
H_STP_PCI# R_STP_CPU#
AE20 AG18
CLKRUN#
AH11
VGATE
AJ20
SST_CTL
AJ22
AJ8 AJ9 CPUSB# AH9 EC_SMI# AE16 EC_SCI# AC19 AG8 AH12 GPIO20 AE11 GPIO22 AG10 GPIO27 AH25 AD16 CLKSATAREQ# AG13 GPIO38 AF9 GPIO39 AJ11 IDE_RESET# AD10 AD9
M CH_ICH_SYNC# AJ13 ICH_RSVD 1 1K_0402_5%
AJ21
STP_PCI#/GPIO15 STP_CPU#/GPIO25 CLKRUN#/GPIO32 WAKE# SERIRQ THRM#
SLP_S3# SLP_S4# SLP_S5#
S4_STATE#/GPIO26
AH27
S4_STATE#
PWROK
AE23
PM_PWROK
DPRSLPVR/GPIO16
AJ14
DPRSLPVR
AE21
ICH_LOW_BAT#
PWRBTN#
C2
PWRBTN_OUT#
VRMPWRGD
LAN_RST#
TP7
AH20
TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 SPKR MCH_SYNC# TP3
RSMRST# CK_PWRGD
AG27
@ 10_0402_5%
E1
1 @ R231
0205 Change to connect to GND.
2 100K_0402_5%
PWRBTN_OUT# 32
R235 1 2 0_0402_5% EC_RSMRST# 1 2 R236 100_0402_5% CK_PWRGD CK_PWRGD 15
CL_CLK0 CL_CLK1
F23 AE18
CL_CLK0
CL_DATA0 CL_DATA1
F22 AF19
CL_DATA0
CL_VREF0 CL_VREF1
D24 AH23
CL_VREF0_ICH CL_VREF1_ICH
EC_RSMRST# 32
M_PWROK 7,32 T34 PAD R240 3.24K_0402_1% 1 2 +3VS
CL_CLK0 7 CL_DATA0 7
AJ23
CL_RST# 7
AJ27 AJ24 AF22 AG19
D
@ 4.7P_0402_50V8C
32 32 32
DPRSLPVR 7,39
PM_SLP_M#
CL_RST#
2
C257
PM_PWROK 7,32
M_PWROK
MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14 WOL_EN/GPIO9
@ 4.7P_0402_50V8C
T32 PAD
AJ25
SLP_M#
2
SLP_S3# SLP_S4# SLP_S5#
E3
CLPWROK
2
1
C256
T31 PAD
EC_RMRST#
1
C258
2
C
R242 453_0402_1%
0.1U_0402_16V4Z 1
C259
R246 1
3.24K_0402_1% 2 +3VALW
R250 453_0402_1%
R251
low-->default
2 SB_SPKR @ 10K_0402_5%
R221
@ 10_0402_5%
2
100K_0402_5% 2
1 R252
AG23 AF21 AD18
BATLOW#
1
CLK_14M_ICH 15 CLK_48M_ICH 15
ICH_SUSCLK
SUSCLK
PAD PAD PAD PAD
CLK_14M_ICH CLK_48M_ICH
AG9 G5 D3
SLP_S3# SLP_S4# SLP_S5#
ICH8M REV 1.0
+3VS
SATA GPIO
SMB
EC_LID_OUT#
SB_SPKR
7 MCH_ICH_SYNC#
PM_BMBUSY#
BMBUSY#/GPIO0
OCP#
OCP#
15 CLKSATAREQ#
1
1
1
4
AG12
ICH_PCIE_WAKE#AE17 SIRQ AF12 THERM_SCI# AC13
PAD T33
M CH_ICH_SYNC# 2 10K_0402_5%
R245
1 0_0402_5%
GPIO20
1
R244
R248
GPIO22 2 8.2K_0402_5%
OCP# 2 10K_0402_5%
R243
2 R229
22,23,24 ICH_PCIE_WAKE# 32 SIRQ 32 THERM_SCI# 2 1 R233 100K_0402_5% 15,39 VGATE
CLKRUN# 2 8.2K_0402_5%
@ R239
H_STP_PCI# H_STP_CPU#
GPIO39 2 10K_0402_5%
1
@ R241
C
15 15
1 R238 +3VS
GPIO38 2 10K_0402_5%
SUS_STAT#/LPCPD# SYS_RESET#
PM_BMBUSY#
CLK14 CLK48
T26 T27 T28 T29
1
1 R228
EC_LID_OUT#
SUS_STAT# F4 XDP_DBRESET# AD15
RI#
AJ12 AJ10 AF11 AG11
2
+3VS
1
32
AF17
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37
1
7 PM_BMBUSY#
ICH _RI#
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1
2
@ R227 10K_0402_5%
AJ26 AD19 AG21 AC17 AE19
0.1U_0402_16V4Z
@ R226 10K_0402_5%
ICH_SMBCLK ICH_SMBDATA LINKALERT# ME_EC_CLK1 ME_EC_DATA1
1
2 1ME_EC_CLK1 10K_0402_5%
PAD T30 4 XDP_DBRESET#
2
R225
+3VS 2
2 1ME_EC_DATA1 10K_0402_5%
R220 U7C
D
R224
CLK_14M_ICH 1
1 2.2K_0402_5%
Clocks
2 XDP_DBRESET# 1K_0402_5%
2.2K_0402_5% 15,22,23 ICH_SMBCLK 15,22,23 ICH_SMBDATA
SYS GPIO
1
R218
Power MGT
2 ICH _RI# 10K_0402_5%
R217
Place closely pin AG9
CLK_48M_ICH
MISC GPIO Controller Link
2 ICH_PCIE_WAKE# 1K_0402_5%
1 R222 R223
1 ICH_LOW_BAT# 8.2K_0402_5%
1 R219
1
2 R216
2 LINKALERT# 10K_0402_5%
2
1 R215
2
+3VALW
Place closely pin G5
2
5
High -->No boot U7D PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2
PCIE_RXN1 PCIE_RXP1 1 C260 PCIE_C_TXN1 1 C261 PCIE_C_TXP1
GIGA LAN
24 24 24 24
PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2
PCIE_RXN2 M27 PCIE_RXP2 M26 1 C262 PCIE_C_TXN2 L29 1 C263 PCIE_C_TXP2 L28
New card
23 23 23 23
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2
PCIE_RXN3 PCIE_RXP3 1 C494 PCIE_C_TXN3 1 C493 PCIE_C_TXP3
K27 K26 J29 J28
22 22 22 22
PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2
PCIE_RXN4 PCIE_RXP4 1 C496 PCIE_C_TXN4 1 C495 PCIE_C_TXP4
H27 H26 G29 G28
Robeson (Mini card)
+3VALW
1 1 1 1 1 1 1
2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5%
+3VALW 2
1
@ R256 10K_0402_5% 1
USB_OC#3 R254 USB_OC#4 R255 USB_OC#5 R257 USB_OC#6 R258 USB_OC#7 R259 USB_OC#8 R260 USB_OC#9 R261 USB_OC#2 R262
29 29 29
A
USB_OC#0
1 2 R263 10K_0402_5% 1 2 USB_OC#1 R265 0_0402_5%
USB_OC#0 USB_OC#1 USB_OC#2
PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4
F27 F26 E29 E28
PERN5 PERP5 PETN5 PETP5
D27 D26 C29 C28
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
PAD T36 PAD T37 PAD T38
SPICLK C23 SPI_CS0# B23 SPI_CS1# E22
PAD T39
SPI_MOSI D23 SPI_MISO F21
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9
PERN1 PERP1 PETN1 PETP1
AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18
V27 V26 U29 U28
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
Y27 Y26 W29 W28
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
AB26 AB25 AA29 AA28
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
AD27 AD26 AC29 AC28
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
DMI_CLKN DMI_CLKP
T26 T25
CLK_PCIE_ICH# CLK_PCIE_ICH
DMI_ZCOMP DMI_IRCOMP
Y23 Y24
SPI_CLK SPI_CS0# SPI_CS1#
SPI
B
P27 P26 N29 N28
PCI-Express Direct Media Interface
22 22 22 22
WLAN (Mini card)
SPI_MOSI SPI_MISO OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9#
USB
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP
DMI_RXN0 7 DMI_RXP0 7 DMI_TXN0 7 DMI_TXP0 7 DMI_RXN1 7 DMI_RXP1 7 DMI_TXN1 7 DMI_TXP1 7 DMI_RXN2 7 DMI_RXP2 7 DMI_TXN2 7 DMI_TXP2 7
B
DMI_RXN3 7 DMI_RXP3 7 DMI_TXN3 7 DMI_TXP3 7
DMI_IRCOMP
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P
G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7
USBRBIAS# USBRBIAS
F2 F3
USBRBIAS
CLK_PCIE_ICH# 15 CLK_PCIE_ICH 15 R253 24.9_0402_1% 1 2
Within 500 mils
USB20_N0 29 USB20_P0 29 USB20_N1 29 USB20_P1 29 USB20_N2 29 USB20_P2 29 USB20_N3 23 USB20_P3 23 USB20_N4 26 USB20_P4 26 USB20_N5 29 USB20_P5 29 USB20_N6 29 USB20_P6 29 USB20_N7 29 USB20_P7 29
+1.5VS
To New Card To Card reader/B. To Bluetooth To PC Camera To Finger Printer
A
1 R264
2 22.6_0402_1%
ICH8M REV 1.0
Within 500 mils Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. ICH8(3/4)_PM,USB,GPIO
Size Document Number Custom LA-3821P Date:
R ev 0.3
Tuesday, July 31, 2007
Sheet 1
20
of
43
5
4
3
2
1
U7E
+VCCP
1170mA
2.2U_0805_16V4Z
2
10U_0805_10V4Z
D12
R268 CH751H-40PT_SOD323-2
20 mils
1
2
100_0402_5%
ICH_V5REF_RUN 1
C274 0.1U_0402_16V4Z
2
1 2
1
0.1U_0402_16V4Z
R270
C287
10U_0805_10V4Z
C286
C288 1U_0603_10V4Z
1
2
C290 1U_0603_10V4Z
VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10]
AC10 AC9
1
VCC1_5_A[11] VCC1_5_A[12]
AA5 AA6
2
2
1
2
VCC1_5_A=1120mA +1.5VS T44 T45
+3VS
VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2
12mA 1
VCC1_5_A[20] VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24]
W23
VCC1_5_A[25]
F17 G18
VCCLAN1_05[1] VCCLAN1_05[2]
F19 G20
VCCLAN3_3[1] VCCLAN3_3[2]
+1.5VS
10U_0805_10V4Z
A
A24
VCCGLANPLL
A26 A27 B26 B27 B28
VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5]
B25
VCCGLAN3_3
GLAN POWER
CHB1608U301_0603 27mA ICH_VCCGLANPLL 2 @ R272 74mA ICH_VCCGLAN1_5 1 2 1 1 +1.5VS CHB1608U301_0603 1 C298 C299 @ C300 2 2 4.7U_0805_10V4Z 1mA 2 1 2 ICH_VCCGLAN3_3 +3VS @ R2730_0402_5%
F1 L6 L7 M6 M7
R271 1
2
2.2U_0805_16V4Z
C297 0.1U_0402_16V4Z
VCCUSBPLL
VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05] VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCCL1_05
0.1U_0402_16V4Z +3VS (SATA) 1 +3VS
VCC3_3=310mA
2
+3VS
(DMI)
C279 2
1
2
1
2
1
2
VCC3_3=310mA 0.1U_0402_16V4Z 1
C282
2
+3VS
1
2
1
0.1U_0402_16V4Z
4mA
C289 2
2 +3VALW
VCCSUS3_3=141mA 1
2
1
2
+3VALW
P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6
VCCSUS3_3=141mA 1
2
G22 VCCCL1_05_ICH
F20 G21
+3VALW
C291
AC18 AC21 AC22 AG20 AH28
VCCCL3_3[1] VCCCL3_3[2]
+3VS 1
0.1U_0402_16V4Z 1
T40 T41 AC16 VCCSUS1_5_ICH_1 T42 VCCSUS1_5_ICH_2 J7 T43 C3 0.1U_0402_16V4Z
A22
2
24mA
J6 AF20
VCCCL1_5
1
2
0.1U_0402_16V4Z
C295 0.1U_0402_16V4Z
D1
0.1U_0402_16V4Z +3VS 1
VCC3_3=310mA
C293
1
VCC1_5_A[18] VCC1_5_A[19]
USB CORE
C294 0.1U_0402_16V4Z
VCCSUSHDA
AD11
VCCSUS1_5[2]
+VCCP
VCC3_3=310mA
C292
10mA
AC12
VCCSUS3_3[01]
2
VCC3_3=310mA
VCCHDA
VCCSUS1_5[1] VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17]
AC7 AD7
VCC1_5_A=1120mA
+1.5VS
VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24]
A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11
VCCSUS1_05[1] VCCSUS1_05[2]
VCC1_5_A[13] VCC1_5_A[14]
G12 G17 H7
+1.5VS
ATX
B
VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05]
AC1 AC2 AC3 AC4 AC5
VCC1_5_A=1120mA +1.5VS
VCCSATAPLL
AE7 AF7 AG7 AH7 AJ7
AA3 U7 V7 W1 W6 W7 Y7
1
C285
2
VCC1_5_A=1120mA +1.5VS
VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]
14mA
C284
2
1
ARX
1
AJ6
AC8 AD8 AE8 AF8
40mA
C283 0.1U_0402_16V4Z
CHB1608U301_0603
1U_0603_10V4Z
ICH_VCCSATAPLL
2
VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06]
26mA
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.5VS
1
50mA
AD2
+1.25VS
C278
2
C281
VCC3_3[02]
AF29
2 10U_0805_10V4Z
0.1U_0402_16V4Z C277
20 mils 1
VCC3_3[01]
AC23 AC24
2 0.01U_0402_16V7K
C276
ICH_V5REF_SUS
VCC_DMI[1] VCC_DMI[2] V_CPU_IO[1] V_CPU_IO[2]
CHB1608U301_0603 2 +1.5VS
1 C273
0.1U_0402_16V4Z
CH751H-40PT_SOD323-2
R29 AE28 AE29
1 C272
4.7U_0805_10V4Z
D13
R269 10_0402_5%
VCCDMIPLL
R267 1
ICH_VCCDMIPLL
C275
C
VCCA3GP
+5VALW +3VALW
VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46]
0.1U_0402_16V4Z
2
10U_0805_10V4Z
2
AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25
1
C296 4.7U_0805_10V4Z
C
B
A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
ICH8M REV 1.0
T46
1U_0603_10V4Z 1
12mA
+3VS
A
2 @
ICH8M REV 1.0
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]
D
om
2
+3VS 220U_D2_2.5VM
1
C271
2
1
C267
2
l.c
+5VS
C270
2
1
1
C266
4
3
2
Title
nf @ ho tm
C269
2
1
V5REF_SUS
K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24
Compal Electronics, Inc.
ICH8(4/4)_POWER&GND Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
+
C268
40 mils
G4
VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184]
ai
V5REF[1] V5REF[2]
ICH_V5REF_SUS 10U_0805_10V4ZICH_VCC1_5 770mA
A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098]
Tuesday, July 31, 2007
he x
+1.5VS
CHB1608U301_0603 2 1
CORE
R266 1
VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28]
C280
VCCRTC
A16 T7
A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6
C301
AD25
VCCP_CORE
6mA 3mA
D
0.1U_0402_16V4Z
U7F ICH_V5REF_RUN
IDE
2
PCI
2
20 mils
VCCPSUS
1
VCCPUSB
1
C265 0.1U_0402_16V4Z
C264 0.1U_0402_16V4Z
+RTCVCC
Sheet
1
21
of
43
A
B
C
D
E
F
G
H
+5VS
Placea caps. near ODD CONN.
HDD Connector
CD-ROM Connector
C310 0.1U_0402_16V4Z
C307 10U_0805_10V4Z
C309
2 0.1U_0402_16V4Z
2 2 0.1U_0402_16V4Z
V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12
Pleace near HD CONN (JP23) +3VS_HDD
1
@ C313
1 1
@ C314
+ @ C315
2 2 2 2 1000P_0402_50V7K 1U_0603_10V4Z
@
7,18,23,24 PLT_RST#
SATA_RXN0_C 19 SATA_RXP0_C 19
Near CONN side. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+3VS_HDD 19 19 19 19 19 19
+5VS +5VS
IDE_HDIOW# IDE_HIORDY IDE_HIRQ IDE_HDA1 IDE_HDA0 IDE_HDCS1# 2 1 R278 10K_0402_5%
IDE_HDIOW# IDE_HIORDY ID E_HIRQ IDE_HDA1 IDE_HDA0 IDE_HDCS1# IDE_ACT#
+5VS SEC_CSEL
SUYIN_127043FR022G204ZL_NR
R279 470_0402_5%
IDE_HDD8 IDE_HDD9 IDE_HDD10 IDE_HDD11 IDE_HDD12 IDE_HDD13 IDE_HDD14 IDE_HDD15 IDE_HDREQ IDE_HDIOR#
2
2
1
2
C305 10U_0805_10V4Z 1
IDE_HDREQ 19 IDE_HDIOR# 19
IDE_HDACK#
IDE_HDACK# 19
PDIAG# R276 1 IDE_HDA2 IDE_HDCS3#
2
100K_0402_5%
+5VS
IDE_HDA2 19 IDE_HDCS3# 19 +5VS
SUYIN_800189MB050S105ZL CONN@
2
Pleace near HD CONN
SATA_TXP0 19 SATA_TXN0 19
1 C306 SATA_RXN0_C 1 C311 SATA_RXP0_C
1
0.1U_0402_16V4Z 1
C312 330U_V_2.5VK_R9
+3VS @ R2770_0805_5% 2 1
SATA_TXP0 SATA_TXN0 0.01U_0402_16V7K SATA_RXN0 2 SATA_RXP0 2 0.01U_0402_16V7K
2
C304
C308 2
1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
1
10U_0805_10V4Z
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
1 C303
1
20 IDE_RESET#
1
1U_0603_10V4Z
1
1 2 3 4 5 6 7
JP9
0.1U_0402_16V4Z
1
GND A+ AGND BB+ GND
@ R274 0_0402_5% 1 2 R275 33_0402_5% 1 2 IDE_HDD7 IDE_HDD6 IDE_HDD5 IDE_HDD4 IDE_HDD3 IDE_HDD2 IDE_HDD1 IDE_HDD0
C302
0213_Change Connector type.
IDE_HDD[0..15] 19 JP8 +5VS
2
2
Mini-Express Card---WLAN +3VS_MINI
NAND mini Card(Robson support) +3VS
Add in 4/27.
20 20
3
R280 R281
PCIE_RXN4 PCIE_RXP4
20 20
2 0_0402_5% 2 0_0402_5%
1 1
PCIE_C_RXN4 PCIE_C_RXP4
PCIE_TXN4 PCIE_TXP4
Add in 5/16. (Close to JP10)
C330
2
1
2
4.7U_0805_10V4Z
C329
1
0.1U_0402_16V4Z
2
0.01U_0402_16V7K
2
1 C328
C327
2
1
+1.5VS
4.7U_0805_10V4Z
C326
1
0.1U_0402_16V4Z
2
0.01U_0402_16V7K
2
1 C325
C324
2
1
+3VS
0.01U_0402_16V7K
C323
1
0.01U_0402_16V7K
+3VS
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
53
GND1
0.01U_0402_16V7K 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND2
54
2
2
C318
4.7U_0805_10V4Z 2
1
2
C320 0.1U_0402_16V4Z
1
2
ICH_PCIE_WAKE# CH_DATA CH_CLK 1 2 MINI_CLKREQ#_MC R282 0_0402_5% CLK_PCIE_MCARD# CLK_PCIE_MCARD
20,23,24 ICH_PCIE_WAKE# 29 CH_DATA 29 CH_CLK 15 MINI_CLKREQ# 15 CLK_PCIE_MCARD# 15 CLK_PCIE_MCARD
PLT_RST# 15 CLK_DEBUG_PORT_0 20 20
PCIE_RXN1 PCIE_RXP1
20 20
PCIE_TXN1 PCIE_TXP1
PCIE_RXN1 PCIE_RXP1
1 2 R288 DEBUG@ 0_0402_5% R289 0_0402_5% PCIE_C_RXN1 1 2 PCIE_C_RXP1 1 2 R290 0_0402_5%
PCIE_TXN1 PCIE_TXP1
Mini Card STANDOFF H1 HOLEA
+3VS_MINI
53
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 GND1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
1 R283 R284 R285 R286 R287
Issued Date
2
+3VS +1.5VS L9 FBMA-L11-201209-102LMA10T 1 2 2 L10 FBMA-L11-201209-102LMA10T 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5%
3
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
LPC_FRAME# 19,31,32
LPC_AD[0..3] 19,31,32
WL_ON# PLT_RST#
WL_ON#
32
+3VALW ICH_SMBCLK 15,20,23 ICH_SMBDATA 15,20,23
WL_LED#
WL_LED# 30
54
4
C
D
Compal Electronics, Inc.
Compal Secret Data 2006/02/13
2007/08/29
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
1
FOX_AS0B226-S40N-7F CONN@
Security Classification
A
2
C322 @ 0.1U_0402_16V4Z
1
1
H2 HOLEA
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
1
C321 4.7U_0805_10V4Z
+1.5VS_MINI
H4 HOLEA
1
C319 0.01U_0402_16V7K
JP11
FOX_AS0B226-S40N-7F CONN@
H3 HOLEA
1
PLT_RST#
Mini Card STANDOFF
4
1
C317 0.1U_0402_16V4Z
+3VALW
1
15 MINI_ROB_CLKREQ# 15 CLK_PCIE_MCARD_ROB# 15 CLK_PCIE_MCARD_ROB
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
C316 1
+1.5VS
JP10
+1.5VS_MINI
E
F
Title
HDD/ODD/Mini Card CONN. Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007 G
Sheet
22 H
of
43
A
B
C
D
E
Express Card Power Switch
5 6
0.1U_0402_16V4Z 2 R291
+3VALW CPUSB#
G
2
20,32
3
1
21
7 8
3.3Vaux_in
Aux_out
1
20 +1.5VS_PEC
18 19
1.5Vin1 1.5Vin2
1.5Vout1 1.5Vout2
100K_0402_5% 14 CPUSB# 15 CPPE# 4 STBY# 3 SHDN# 2 SYSRST#
SUSP# SYSON PLTRST#
GND
D
S
7,18,22,24 PLT_RST#
32,33,35,37,38 SUSP# 32,33,37 SYSON
1
3.3Vout1 3.3Vout2
+3V_PEC
C332 +3VALW 0.1U_0402_16V4Z 2 1 +1.5VS C333 2 1 +3VS
3.3Vin1 3.3Vin2
11
Q10 2N7002_SOT23-3
OC# RCLKEN PERST#
16 17
23 22 9
PERST#
NC1 NC2 NC3 NC4 NC5
1
+3VS_PEC
U8
+3VS
1 10 12 13 24
C331 0.1U_0402_16V4Z 2 1
TPS2231PWPR_PWP24
2
2
JP12
20 20
USB20_N3 USB20_P3
15,20,22 ICH_SMBCLK 15,20,22 ICH_SMBDATA +1.5VS_PEC +1.5VS_PEC 20,22,24 ICH_PCIE_WAKE# +3V_PEC
USB20_N3 USB20_P3 CPUSB# ICH_SMBCLK ICH_SMBDATA ICH_PCIE_WAKE# PERST#
+3VS_PEC 15 NCARD_CLKREQ# 15 CLK_PCIE_NCARD# 15 CLK_PCIE_NCARD 20 20 3
20 20
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
CLKREQD# CPUSB# CLK_PCIE_NC2# CLK_PCIE_NC2 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Near to Express Card slot. 15.4
GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND GND1 GND2
GND3 GND4
+3VS_PEC
+3V_PEC 4.7U_0805_10V4Z
1 C334 0.1U_0402_16V4Z
1 C335
2
2
C336 0.1U_0402_16V4Z
1
1
2
2
C337 4.7U_0805_10V4Z
+1.5VS_PEC 4.7U_0805_10V4Z 1 C338 0.1U_0402_16V4Z
1 C339 3
2
2
29 30
SANTA_131851-A_LT CONN@
4
Compal Secret Data 2006/03/10
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. Express Card
Size Document Number Custom LA-3821P Date:
R ev 0.3
ai
2005/03/10
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
4
Sheet
E
23
of
43
5
4
3
2
1
+3V_LAN C340
U9
D
A0 A1 NC GND
VCC WP SCL SDA
8 7 6 5
AP2305GN
LAN_EE_CLK LAN_EE_DATA 32 LAN_POWER_OFF
CAT24C08WI-GT3 SO 8P
Turn off power when S3. 06/14
Q22
1
3
D
1 2 3 4
+3VALW R359 @ 0_1206_5% 1 2
S
10K_0402_5% GIGA_LAN_CLKREQ 1 10K_0402_5% ICH_PCIE_WAKE# 1 10K_0402_5% LAN_LOM_DIS 1
R293 1K_0402_5% 2 1
R295 2 R296 2 R297 2
+3V_LAN
0.1U_0402_16V4Z
D
2 G
+3V_LAN
1 R294 1K_0402_5% 2 1
2
+3V_LAN U10 GIGA_LAN_CLKREQ 42 0.1U_0402_16V4Z 2 1 C341 PCIE_RXP2_LAN49 0.1U_0402_16V4Z 2 1 C347 PCIE_RXN2_LAN50 54 53 ICH_PCIE_WAKE# 6 55 R298 0_0402_5% 56 1 2 5
20 PCIE_RXP2 20 PCIE_RXN2 20 PCIE_TXP2 20 PCIE_TXN2 20,22,23 ICH_PCIE_WAKE# 15 CLK_PCIE_LAN 15 CLK_PCIE_LAN# 7,18,22,23 PLT_RST# 25 25 25 25 25 25 25 25
17 18 20 21 26 27 30 31
LAN_MDI0P LAN_MDI0N LAN_MDI1P LAN_MDI1N LAN_MDI2P LAN_MDI2N LAN_MDI3P LAN_MDI3N LAN_EE_CLK LAN_EE_DATA
+3VS
LAN_X1 LAN_X2
+3V_LAN
LAN_LOM_DIS
R299
4.87K_0402_1%
CTRL18 CTRL12
LED PCI-E
TESTMODE AVDDH
POWER Media
VPD_CLK VPD_DATA
EEPROM
SPI_DO SPI_DI SPI_CLK SPI_CS
FLASH MEMORY
15 14
XTALI XTALO
CLOCK
10 12 11 47 9 16 4 3
LOM_DISABLEn VAUX_AVLBL SWITCH_VCC VMAIN_AVLBL SWITCH_VAUX RSET Analog CTRL18 CTRL12
38 41
LED_ACTn LED_LINK10/100n LED_LINK1000n LED_DUPLEXn
TEST
MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3
34 35 37 36
C
CLKREQn TX_P TX_N RX_P RX_N WAKEn REFCLKP REFCLKN PERSTn
& GROUND
AVDD AVDD AVDD AVDD VDDO_TTL VDDO_TTL VDDO_TTL VDDO_TTL VDD VDD VDD VDD VDD VDD VDD VDD VSS
C342 0.1U_0402_16V4Z
2
1 C343 0.1U_0402_16V4Z
2
1 C344 0.1U_0402_16V4Z
2
1 C345 0.1U_0402_16V4Z
2
C346 0.1U_0402_16V4Z
V1.8_LAN
19 22 23 28
V1.8_LAN
0.1U_0402_16V4Z +3V_LAN
1
1 C501
1 40 45 61
2
2
1 C500 0.1U_0402_16V4Z
2
1 C491 0.1U_0402_16V4Z
2
1 C348 0.1U_0402_16V4Z
2
1 C349 0.1U_0402_16V4Z
2
1 C350 0.1U_0402_16V4Z
2
1 C351 0.1U_0402_16V4Z
2
C352 0.1U_0402_16V4Z
V1.2_LAN
2 7 13 33 39 44 48 58 65
24 25 29 43
2
LANLINK_STATUS# 25
1
+3V_LAN
8
Reserved Reserved Reserved Reserved
LAN_ACT# 25
LANLINK_STATUS#
46
32 51 52 57 64
No Connect
LAN_ACT#
59 60 62 63
NC NC NC NC NC
1
V1.2_LAN 1
2
V1.8_LAN
1 C490 0.1U_0402_16V4Z
2
1 C353 0.1U_0402_16V4Z
2
1 C354 0.1U_0402_16V4Z
2
1 C355 0.1U_0402_16V4Z
2
1 C356 0.1U_0402_16V4Z
2
C
C357 0.1U_0402_16V4Z
V1.2_LAN 1
2
1 C414 0.1U_0402_16V4Z
2
1 C404 0.1U_0402_16V4Z
2
1 C405 0.1U_0402_16V4Z
2
C403 0.1U_0402_16V4Z
88E8055_QFN64
+3V_LAN
R435 2
4.7K_0402_5% 1
C359 27P_0402_50V8J 1 2
Q11
B
2
3
4.7U_0805_10V4Z C358 2 1
1
B
CTRL12
2SB1188T100R_SC62-3
LAN_X1 LAN_X2
4.7U_0805_10V4Z C361 2 1
1
V1.2_LAN
2
Y3 25MHZ_20P_1BG25000CK1A C360 27P_0402_50V8J 1 2
+3V_LAN
3
4.7U_0805_10V4Z C362 2 1
R436 2
2SB1188T100R_SC62-3
CTRL18
2
1
V1.8_LAN
4.7K_0402_5% 1
Q12
4.7U_0805_10V4Z C363 2 1
A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
2007/08/29
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. LAN-8100CL
Size
Document Number
R ev 0.3
LA-3821P Date:
Sheet
Tuesday, July 31, 2007 1
24
of
43
5
4
3
2
1
D
D
V1.8_LAN
T47 0.1U_0402_16V4Z 1
2 C364 R3001
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
2
49.9_0402_1%
R3021
2
49.9_0402_1%
LAN_MDI0P 24
2 C367 R3031
2
49.9_0402_1%
LAN_MDI1N 24
R3051
2
49.9_0402_1%
LAN_MDI1P 24
2 C371 R3061
2
49.9_0402_1%
LAN_MDI2N 24
R3081
2
49.9_0402_1%
LAN_MDI2P 24
2 C374 R3091
2
49.9_0402_1%
LAN_MDI3N 24
R3111
2
49.9_0402_1%
LAN_MDI3P 24
LAN_MDI0N 24
2 1 C365 0.1U_0402_16V4Z
TRM_CT LAN_MDI3P LAN_MDI3N
1 2 3
TCT1 TD1+ TD1-
MCT1 MX1+ MX1-
24 23 22
2 R301 1 MDO3+ 75_0402_1% MDO3-
2 1 C368 0.1U_0402_16V4Z
TRM_CT LAN_MDI2P LAN_MDI2N
4 5 6
TCT2 TD2+ TD2-
MCT2 MX2+ MX2-
21 20 19
2 R304 1 MDO2+ 75_0402_1% MDO2-
2 1 C372 0.1U_0402_16V4Z
TRM_CT LAN_MDI1P LAN_MDI1N
7 8 9
TCT3 TD3+ TD3-
MCT3 MX3+ MX3-
18 17 16
2 R307 1 MDO1+ 75_0402_1% MDO1-
2 1 C375 0.1U_0402_16V4Z
TRM_CT LAN_MDI0P LAN_MDI0N
10 11 12
TCT4 TD4+ TD4-
MCT4 MX4+ MX4-
15 14 13
2 R310 1 MDO0+ 75_0402_1% MDO0-
C369 1 2 1000P_1808_3KV7K
0.5u_24HST1041A-2 C
C
JP40
Note: MDO[3..0]+/- signals should route to JP13 first then to JP30.
1 2 G1 G2
JP14 LAN_ACT#
LAN_ACT# R312 2
1 300_0402_5%
+3V_LAN
7
MDO1-
6
MDO2-
5
MDO2+
4
MDO1+
3
PR2+
MDO0-
2
PR1-
MDO0+
1
PR1+
1 300_0402_5%
9
7/24
PR3+
GND GND
ZZZ2
MDC 1.5 Conn.
14 13
B
Change type 4/25
Green LEDGreen LED+
ACZ_SDOUT_MDC
1 R314
ACZ_SYNC_MDC 2 ACZ_SDIN1_R ACZ_RST#_MDC 33_0402_5%
JP15 CONN@ ACES_88020-124G 1 2 1 2 3 4 3 4 5 6 5 6 7 8 7 8 9 10 9 10 11 12 11 12
+3VS
45@
ACZ_BITCLK_MDC 19 1 2 C380 @ 10P_0402_25V8K
1
2
MDC STANDOFF H5 HOLEA
1
2
C385
1
@ 4.7U_0805_10V4Z
2
1115 EMI REQUEST
C384
1
0.1U_0402_16V4Z
C383
13 14 15 16 17 18
@ C382 300p_0402_25V
MDC cable
+3VS
2 1 R315 @ 10_0402_5%
GND GND GND GND GND GND
19 ACZ_SYNC_MDC 19 ACZ_SDIN1 19 ACZ_RST#_MDC
LANLINK_STATUS#
1
FOX_305-000-1176
PR3-
1000P_0402_50V7K
1
1
GND1 GND2
PR2-
2 @ C381 300p_0402_25V
1
RJ11
Tip Ring
PR4+
19 ACZ_SDOUT_MDC
2
C506
1000P_1808_3KV7K 3 C507 4
PR4-
FOX_JM36113-L2R8-7F
LAN_ACT#
1000P_1808_3KV7K
2
Yellow LED+
MDO3+
10
2
ACES_85204-02001 CONN@
Yellow LED-
8
LANLINK_STATUS#
R313 2
11
MDO3-
B
24 LANLINK_STATUS#
12
1 2
H6 HOLEA
1
24 +3V_LAN
JP13 TIP RING
1 2 3 4
A
Compal Secret Data 2006/02/13
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Magnetic & RJ45/RJ11
Size
Document Number
LA-3821P Date:
R ev 0.3
ai
Issued Date
he x
Security Classification
nf @ ho tm
ai
l.c
om
A
Tuesday, July 31, 2007
Sheet 1
25
of
43
5
4
3
2
1
+VCC_4in1
SDPWR0_MSPWR
40mil
2 R316 1 0_0603_5% +3VS @ U12
C386
2
1
VIN VOUT VIN/CE VOUT
1 5
D
1
3 4
D
GND
1 C387
R317
@
@
2
1U_0603_10V4Z
2
RT9701CB_SOT25 0.1U_0402_16V4Z @ 2
150K_0402_5%
reserved power circuit +A3V
1 R318 C3891 0.1U_0402_16V4Z C3901 1U_0603_10V4Z
1 2 C388 0.1U_0402_16V4Z
2
SDPWR0_MSPWR 1 R319
1 3 7 9 11 33
20_0603_5%
C
2 R320 2 R321 @
+5VS +5VALW
1 0_0603_5% 1 0_0603_5%
2
C393 1
RST# MODE SEL XTLI XTLO
1 C392
USB20_N4 USB20_P4
USB20_N4 USB20_P4
VBUS RST# MODE_SEL XTLI XTLO
4 5 14
DM DP GPIO0
XTLI
2 1
5.6P_0402_50V
7/25 2
12MHZ_16P_6X12000012 Y4 C394 1
2
XTLO
5.6P_0402_50V 2 +A3V 2
12 32
R323 6.19K_0402_1%
RREF DGND DGND AGND AGND
CF_CD# CF_DMARQ CF_D10 CF_D9 CF_D2 SD_CMD
1
43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18
2 C391 1U_0603_10V4Z
XDRE#_SDD2 XDWE#_SDD3
XDD1 XDD7_SDD6_MSD3 MSINS# XDD2_SDD7_MSD2 XDD6_SDD0_MSD0 XDD3_SDD1_MSD1 XDD5_MSBS
XDD3_SDD1_MSD1 +VCC_4in1 R322 22_0402_5% 1 2
SD_MS_CLK
19 13 14 16 18 20 15 17 21 12 22 23
SD_MS_CLK MSINS# XDD6_SDD0_MSD0 XDD5_MSBS XDD7_SDD6_MSD3 XDD2_SDD7_MSD2
SDCD#
C
VCC_MS VCC_MS SCLK_MS INS_MS SDIO_MS BS_MS RESERVED_MS RESERVED_MS VSS_MS VSS_MS GND GND PROCO_MDR019-C0-1202 CONN@
SDWP
13 24 15 16 17 36
B
SDCMD
RTS5158-GR_LQFP48_7x7 R325 RST#
0_0402_5% SD_MS_CLK
1 C396
1
@
2
XD_CLE/CF_SP19 XD_CE#/CF_D11_SP18 XD_ALE/CF_D4_SP17 SD_DAT2/XD_RE#/CF_D12_SP16 SD_DAT3/XD_WE#/CF_D5_SP15 XD_RDY/CF_D13_SP14 SD_DAT4/XD_WP#/CF_D6_SP13 SD_DAT5/XD_D0/CF_D14_SP12 SD_CLK/XD_D1/MS_CLK/CF_D7_SP11 SD_DAT6/XD_D7/MS_D3/CF_D15_SP10 MS_INS#/CF_IORD#_SP9 SD_DAT7/XD_D2/MS_D2/CF_IOWR#_SP8 SD_DAT0/XD_D6/MS_D0/CF_RST#_SP7 SD_DAT1/XD_D3/MS_D1/CF_IORDY_SP6 XD_D5/MS_BS/CF_A2_SP5 CF_A1/XD_D4_SP4 CF_A0/SD_CD#_SP3 CF_D0/SM_WPM#/XD_WP_SP2 CF_D1/XD_CD#_SP1 CF_D8/SM_CD#_SP0
10 22 30
VDD_SD DAT0_SD DAT1_SD DAT2_SD CD/DAT3_SD CLK_SD WP_SD CMD_SD CD_SD VSS_SD VSS_SD
1
R326 10K_0402_5%
2
1
1
C395 0.1U_0402_16V4Z
VREG CF_DMACK# CF_CS0#
6 9 10 2 3 7 11 4 1 5 8
XDD6_SDD0_MSD0 XDD3_SDD1_MSD1 XDRE#_SDD2 XDWE#_SDD3 SD_MS_CLK SDWP SDCMD SDCD#
2
2
R324 100K_0402_5%
6 46
+VCC_4in1
1
1
MODE SEL B
JP16
AV_PLL A3V3 A3V3 CARD_3V3 D3V3 D3V3
8 44 45 47 48
0.1U_0402_16V4Z 20 20
3 in 1 Card Reader
U13
Used 9701 by 10K
2
2 0_0402_5%
R327 1U_0603_10V4Z 2
@ 10_0402_5%
1
2
C397 10P_0402_50V8J
2
@
A
A
Compal Electronics, Inc. Title
Card reader board THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet 1
26
of
43
A
B
C
D
E
F
G
H
+VDDA_ALC268 1
28.7K for Module Design (VDDA = 4.702)
+5VS
1
1
R4531U_0603_10V4Z 1
U14 4
VIN
1 1 L12 1 C399 C400 2 KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z 2 2 0.1U_0402_16V4Z
2
DELAY
7 8
10K_0402_1%
VOUT
5
SENSE or ADJ
6
CNOISE
1
ERROR SD
GND
3
40mil
1
C402
4.85V
1
2
C401 10U_0805_10V4Z 1
SI9182DH-AD_MSOP8
2
+VDDA
R329 30K_0402_1%
1
2
C502 2
(output = 250 mA)
60mil
L11 1 2 KC FBM-L11-201209-221LMAT_0805
2
10K_0402_1%
1
+5VAMP
R452
2 PCBEEP_R
R331 10K_0402_1%
0.1U_0402_16V4Z 2
1U_0603_10V4Z
1
R454
1
2
C504 20
2
SB_SPKR
1
R455
1
C
Q38
E
2SC2411K_SOT23
2 B
560_0402_5%
3
2
EC_BEEP
1
C503 32
2
D29
HD Audio Codec
RB751V_SOD323
+VDDA_ALC268
1
MIC_IN_R
2
MIC_IN_R
1
2
C413
MIC_IN_C_L 16 2.2U_0603_6.3V4Z MIC_IN_C_R 17 2.2U_0603_6.3V4Z 23 24 18 20 19
C398 1U_0603_10V4Z 1 2
PCBEEP_C @ R330 1 5.1K_0402_5% 2
28
MIC_EXT_L
28
MIC_EXT_R
MIC_EXT_L
1 C417 MIC_EXT_R 1 C418
2 2
PCBEEP
ACZ_RST#
19,32 ACZ_RST#
3
19 19
R339 1 R340 2
28 HP_DET# 28 EXTMIC_DET#
MIC_EXT_C_L 21 2.2U_0603_6.3V4Z MIC_EXT_C_R 22 2.2U_0603_6.3V4Z 12 11 10
ACZ_SYNC
5
ACZ_SDOUT
2 3 13 34
SENSE_A
2 39.2K_0402_1% 1 20K_0402_1%
47
T48
48 4 7
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-G (PIN 43, 44)
5.1K
PORT-H (PIN 45, 46)
35
LINE_OUTL
LINE_OUT_R
36
LINE_OUTR
MIC2_L
HP_OUT_L
39
HP_OUTL
MIC2_R
HP_OUT_R
41
HP_OUTR
LINE1_L
NC
LINE1_R
DMIC_CLK
CD_L
NC
CD_R
NC
CD_GND BIT_CLK
LINE_OUTL 28 LINE_OUTR 28 HP_OUTL 28 HP_OUTR 28
45 46 43 R336 2 22P_0402_50V8J1
44 C416 1 6
0_0402_5% 2 ACZ_BITCLK 19
MIC1_L MIC1_R
SDATA_IN
PCBEEP
MONO_OUT LINE1_VREFO
RESET# GPIO1 SYNC MIC1_VREFO_L SDATA_OUT MIC1_VREFO_R GPIO0 GPIO3 SENSE A SENSE B
MIC2_VREFO VREF
EAPD
JDREF
SPDIFO
NC
DVSS1 DVSS2
AVSS1 AVSS2
R337 1
8
DGND
2 33_0402_5%
ACZ_SDIN0 19
37 29 3
31
10mil
28
MIC1_VREFO_L
32
MIC1_VREFO_R
30
MIC2_VREFO CODEC_VREF
27
10mil 1
40 33 26 42
C419 10U_0805_10V4Z 2 R342 20K_0402_1%
AGND
2 0_0805_5%
1 R344
2 0_0805_5%
1 R345
2 0_0805_5%
GND
GNDA
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2006/08/18
2007/8/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
1 R343
om
20K
LINE_OUT_L
NC
l.c
SENSE B
PORT-A (PIN 39, 41)
2
ai
4
39.2K
NC
ALC268-GR_LQFP48_9X9
Codec Signals
10U_0805_10V4Z
B
C
D
E
nf @ ho tm
SENSE A
Impedance
2
F
Title
HD Audio Codec ALC268 Size B
Document Number
LA-3821P
Date:
Tuesday, July 31, 2007 G
R ev 0.3
ai
Sense Pin
2
he x
PCBEEP_R
R328 0_0402_5% 1 2
+3VS
C408
0.1U_0402_16V4Z
1
28
1 C412
1
C407
2
MIC_IN_L
2 1
U15
15 MIC_IN_L
1
C411
2 0.1U_0402_16V4Z
14
28
C406
L13 MBK1608301YZF_0603 2 1
9
2
+3VS_DVDD
0.1U_0402_16V4Z
40mil 1
DVDD
2
20mil
DVDD_IO
0.1U_0402_16V4Z 1 C410
38
C409 10U_0805_10V4Z
2
1
25
L14 1 2 FBM-L11-160808-800LMT_0603
AVDD2
+VDDA
AVDD1
2
@ R456 10K_0402_5%
2
1
1U_0603_10V4Z
1
560_0402_5%
Sheet
27 H
of
43
4
A
B
C
+5VAMP
R346 0_1206_5% 1 2
0.1U_0402_16V4Z
1 C421 10U_0805_10V4Z
1
MIC INT In-L JP35 MICIN_L
C423
2
E
@ C430 47P_0402_50V8J 2 1
1
C422
2
D
+5VS
27
2 0_0603_5%
MIC_IN_L
2
1 R351
2 0_0603_5%
1 L20
2 0_0603_5%
1
@
1 2 3 4
1 L22
C509 0.1U_0402_16V4Z
47P_0402_50V8J
10 dB
ACES_85204-02001 CONN@
2
+5VS
LINE_OUTL
LINE_OUTR_R
1 R457 1 R458
2 2
0_0603_5% C431 @
17
RIN-
0_0603_5% 0_0603_5%
1
2 0.47U_0603_10V7K
9
GAIN1
3
2 0.47U_0603_10V7K
5
27
ROUT+
18
SPKR+
ROUT-
14
SPKR-
M ICIN_R 2 1 R441 0_0603_5%
2 0_0603_5%
MIC_IN_R
LINLOUT-
@ R349 100K_0402_5%
R350 100K_0402_5%
4
2
MIC2_VREFO
1
EC_MUTE#
EC_MUTE#
19
SHUTDOWN
10
R448 1
M ICIN_R
2.2K_0402_5% 2
MICIN_L
1 2 3 4
1 L23
2
2.2K_0402_5% 2
2
Keep 10 mil width
1
R449 1
1 2 G1 G2
ACES_85204-02001 @ CONN@
1
2
1
2
@
MIC EXT In
CH751H-40PT_SOD323-2 27
2
GND5 GND1 GND2 GND3 GND4
32
BYPASS
2 0_0603_5% C510
1 2 ACES_85204-0200 CONN@
CH751H-40PT_SOD323-2
D28
12
1
@ 47P_0402_50V8J
8
NC
1 L21
D25
LOUT+
JP36 SPKR+ SPKRJP37
LIN+
R459 C492 1
2
2 2
1
1
GAIN0
1
2
RIN+
EMI C497 47P_0402_50V8J
27
LINE_OUTR
7
7/31
MIC INT In-R
@ C499 47P_0402_50V8J 2 1
2
27
2 0.47U_0603_10V7K
2
C428 1
1
SPEAKER
@ R348 100K_0402_5%
C498 47P_0402_50V8J
R347 100K_0402_5%
VDD PVDD1 PVDD2
U16
1
16 15 6
1
1
2
1 2 G1 G2
1
C433 0.47U_0603_10V7K
EXTMIC_DET#
EXTMIC_DET#
2
JP19 @
C435 47P_0402_50V8J 2 1
5
21 20 13 11 1
4 27
MIC_EXT_R
MIC_EXT_R
2R353
10_0603_5%
MICEXT_R
27
MIC_EXT_L
MIC_EXT_L
2
1
MICEXT_L
0_0603_5%
2 R389 1
2.2K_0402_5% MICEXT_R 2
MIC1_VREFO_L
R447 1
2.2K_0402_5% MICEXT_L 2
@ D15 SM05_SOT23
1
MIC1_VREFO_R
FOX_JA6333L-B3S0-7F~N CONN@
1
@ C434 47P_0402_50V8J
2
R352
10 9 8 7
3 6 2 1
3
P3017THF D0 TSSOP 20P
3
3
HeadPhone Out/Line Out 27
HP_DET#
HP_DET# JP20
@ C436 47P_0402_50V8J 2 1
HP_OUTL
2 100U_D2_6.3VM C438
HP_OUTL
1
HP_OUT_R
2 100U_D2_6.3VM HP_OUT_L
R356 2
0_0603_5% 1
2 R357
1 0_0603_5%
4 PR PL
EC_MUTE
1
S
D
3
EC_MUTE
1
32
D
3
S
2
2 1 @C439 47P_0402_50V8J Q18 EC_MUTE 2 G 2N7002_SOT23-3
10 9 8 7
3 6 2 1 FOX_JA6333L-B3S0-7F~N CONN@
Q19
2 G 2N7002_SOT23-3
D16 @ SM05_SOT23
1
27
HP_OUTR 1
+
HP_OUTR
+
C437 27
5
3
cap. high 5.7mm
0302_Change Audio Jack.
4
4
Compal Secret Data
Security Classification 2006/02/13
Issued Date
Deciphered Date
2007/08/29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. AMP & Audio Jack
Size
Document Number
R ev 0.3
LA-3821P D ate:
Tuesday, July 31, 2007
Sheet E
28
of
43
5
4
3
2
1
+5VALW
+USB_VCCB U23 1 2 3 4
C446 0.1U_0402_16V4Z 2 1 33,37 SYSON#
GND IN IN EN#
8 7 6 5
OUT OUT OUT FLG
+5VALW D
+USB_VCCA 0.1U_0402_16V4Z 1000P_0402_50V7K
USB Port
USB_OC#2 20
RT9711PS_SO8
2nd source:SA005280110
1
C447
For EMI
+USB_VCCA U17 C443 0.1U_0402_16V4Z 2 1 33,37 SYSON#
R360
GND IN IN EN#
8 7 6 5
OUT OUT OUT FLG
0_0402_5% 1
1
RT9711PS_SO8
R361 0_0402_5%
2nd source:SA005280110
L15 1 1
20 USB20_N0 20 USB20_P0
4
2
2
C441 C448
2
1
1
2
2
D
C442 1000P_0402_50V7K
2 0.1U_0402_16V4Z
4
3
2
USB20_N0_R USB20_P0_R
3
2
WCM2012F2S-900T04_0805 1
USB_OC#1 20
1
2 100U_6.3V_M
USB_OC#0 20 1
1 2 3 4
C440
+
2
R362
1
1
C444 @ 10P_0402_50V8J 2
2
C445 @10P_0402_50V8J
0_0402_5% +USB_VCCA JP17
BT Connector
USB20_N1_R USB20_P1_R
JP39 1 0_0402_5% 1 0_0402_5% 2@ 1K_0402_5% 2@ 1K_0402_5%
+3VALW
2
4
3
2
USB20_N1_R USB20_P1_R
3
1
C449 @ 10P_0402_50V8J
2
R368
1
1
2
2
C
SUYIN_020122MR008S535ZA
C450 @10P_0402_50V8J
0_0402_5%
1
2
1
1
C451
For EMI
100U_D2_6.3VM
1
R372 1
+
C452
2
1
1
2
2
C453 1000P_0402_50V7K
2 0_0402_5%
2
0.1U_0402_16V4Z
1
2
2 4.7U_0805_10V4Z
2 47K_0402_5%
2
0.1U_0402_16V4Z
C458
2
0.1U_0402_16V4Z
B
L17 4 20 20
1
2
3 2
C459 @ 10P_0402_50V8J
1
1
2
2
C460 @
0_0402_5%
1
D18 PSOT24C_SOT23-3 @
USB20_N6 USB20_P6
1 2 3 4 G1 G1
1 0_0402_5% 1 0_0402_5%
2
20 20
R373 2 R374 2 3
1 2 3 4 5 6
D19 PSOT24C_SOT23-3 @ 1
E&T_3802-E04N-01R CONN@
B
SUYIN_020173MR004S558ZL CONN@
1
2
USB20_N7_R USB20_P7_R
1 2 3 4 GND GND GND GND
+3VS
PC Camera
2
JP25
USB20_N6_R USB20_P6_R
1 2 3 4 5 6 7
1 2 3 4 5 GND1 GND2
ACES_88266-05001 CONN@ A
Compal Secret Data 2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. USB CONN.
Size
Document Number
LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
Tuesday, July 31, 2007
he x
Security Classification
nf @ ho tm
ai
l.c
1
om
1 0_0402_5% 1 0_0402_5%
1 2 3 4 5 6 7 8
USB20_P2_R USB20_N2_R
10P_0402_50V8J
JP26 R375 2 R376 2 3
3
R370
2
A
1
JP24
4
C461 0.1U_0402_16V4Z C462 0.1U_0402_16V4Z
USB20_N7 USB20_P7
USB20_P2 USB20_N2
WCM2012F2S-900T04_0805 1 2
+3VS
Finger printer
20 20
4
CONN@
1
WCM2012F2S-900T04_0805
C457
1
07/23
USB20_N1 USB20_P1
D
R369 100K_0402_5%
R371 1
BT_OFF
20 20
+USB_VCCB
G
32
2
AP2305GN 1
S
C454
1U_0603_10V4Z
2
1
+3VAUX_BT
Q20
3
1
D17 PSOT24C_SOT23-3 @
C456
ACES_87213-0800G CONN@
0_0402_5%
L16 1
2
Change value. 5/10 Reserve R674,R677 cause BlueFlame co-existance issue. 6/14
USB20_N0_R USB20_P0_R
R365
USB20_P5 20 USB20_N5 20 CH_CLK 22 CH_DATA 22 BT_LED 30
3
2 2 1 1
C455
10
R363 R364 R367 R366
0.01U_0402_16V7K
C
For EMI
+3VAUX_BT USB20_P5_R USB20_N5_R
1
1 2 3 4 5 6 7 8
GND 1 2 3 4 5 6 7 GND 8
RV to Install. 5/10
9
1 2 3 4 5 6 7 9 8 10
Sheet
1
29
of
43
5
4
3
2
1
Power ON/OFF 2
+3VALW
R379
ON/OFFBTN#
D
2
ON/OFF
3
51ON#
1
ON/OFF 32 51ON#
2 5 6
36
T/P Board
1
DAN202U_SC70
O
Q21 DTC124EK_SC59
TP_DATA TP_CLK
1
3
4
D23
2
SW1 SMT1-05-A_4P 3 1
1
4.7K_0402_5% D
D26 PSOT24C_SOT23-3 @
2 C463 1000P_0402_50V7K
1
1
3
I 2
G
0216_Delete D19. +3VALW
R383 4.7K_0402_5%
EMI request
2
+5VS EC_ON
JP29
+3VS +3VL 1
EC_ON
1
32
2
0_0402_5%
R470 0_0402_5%
2
R469
CONN@
G2 G1 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TP_DATA TP_CLK
TP_DATA 32 TP_CLK 32
1 @ C464 2
ACES_87151-06051
0.1U_0402_16V4Z
@ C
2 32 32
I2C_INT LID_SW#
CAP_DATA
Change pin define for try ENE cap bottom
Battery Charge LED(Left 2)
@C465 100P_0402_50V8J 2
Wireless ON Amber Bluethooth ON Blue 07/23
POWER LED1 +5VS
2
2
32 AMBER_LED#
3
4
2
1
+5VALW
R386
Orange
31,32 ON/OFFBTN_LED#
ON/OFFBTN_LED# 1
2
1
820_0402_5%
R381 820_0402_5%
2
AMBER 2
1
2 470_0402_5%
+5VS LTST-C191TBKT-5A_BLUE_0603~D
29 R380 2
LTST-C191TBKT-5A_BLUE_0603~D
1
WL_LED#
2
AMBER
BT_LED
D
S
WL_LED#
06/04
WL_LED# 22
Q25 2 2N7002_SOT23-3 G
POWER LED2
2
D24 Blue
R384
1
1
BLUE 1
1
4.7K_0201_5%
LTST-C195TBKFKT_BLUE/ORG D21
19 SATA_LED#
R382 200_0402_5%
BLUE
LTST-C195TBKFKT_BLUE/ORG
D22
R232
470_0402_5% LTST-C191TBKT-5A_BLUE_0603~D
1
HDD LED(Left 3)
B
1
R377
4 2
1
+3VS
+5VALW
D20
1
200_0402_5%
R385
BLUE_LED#
32
@C466 100P_0402_50V8J
+5VS
BLUE D27 Blue
2
ACES_85203-08421-11_8P CONN@
BLUE B
TP_CLK 1
3
06/15
CAP_CLK
@ +5VS
CAP_CLK CAP_DATA
1 9 10 11 12 13 14 15 16
Orange
ESB_DATA
0_0402_5% 2 0_0402_5% 2
1 2 3 4 5 6 7 8
2 2
R465 @ ESB_CLK 1 R466 ESB_DATA 1 @
ESB_CLK
@
32 CAP_RESET
JP38
1
4,32 SMB_EC_DA2
07/23
3
4,32 SMB_EC_CK2
0_0402_5% 2 0_0402_5% 2
TP_DATA
2 1 R444 10K_0402_5%
R463 SMB_EC_CK2 1 R464 SMB_EC_DA2 1
1 R442 4.7K_0402_5% 2 1 R443 4.7K_0402_5%
C
470_0402_5%
A
A
Compal Secret Data
Security Classification 2006/02/13
Issued Date
Deciphered Date
2006/07/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. LED/SW
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet 1
30
of
43
+3VALW 1
+3VALW
1 R390 100K_0402_5%
2
U18 8 7 6 5
32,40 SMB_EC_CK1 32,40 SMB_EC_DA1
2
C467 0.1U_0402_16V4Z
VCC WP SCL SDA
A0 A1 A2 GND
1 2 3 4
LPC Debug Port 1
AT24C16AN-10SI-2.7_SO8
Change from +3VL to +3VS. 6/9 Removed +3VS. 6/13
2
R391 100K_0402_5%
B+
JP30 15 CLK_DEBUG_PORT_1
SPI ROM
19,22,32 LPC_FRAME#
+3VALW U19
32
FWR#
1 R392 1 R393 FWR# 1 R394
SPI_FSEL# 2 0_0402_5% SPI_CLK_R 2 0_0402_5% SPI_FWR# 2 0_0402_5%
1
S
6 5
ON/OFFBTNLED# CAPSLED# NUMLED# VCC1PWRGD SPI_CLK_JP52 SPI_CS#_JP52 SPI_SI_JP52 SPI_SO_JP52 SPI_HOLD#_0
C SPI_SO 1 2 D Q R395 CONN@ WIESON G6179 8P SPI
2 FR D# 0_0402_5%
FRD#
32
Connect pin3 & 23 together and pin 24 to GND in 6/29.
&U19
SST25LF080B_SO8-200mil
B-Test
remove SPI ROM socket
+3VALW
DEBUG@ R396 SPI_CLK_R 1
0_0402_5% 2
SPI_CLK_JP52
FSEL#
DEBUG@ R397 1
0_0402_5% 2
SPI_CS#_JP52
FWR#
DEBUG@ R398 1
0_0402_5% 2
DEBUG@ R399 1
0_0402_5% 2
DEBUG@ R400 1
0_0402_5% 2
HOLD# FR D#
30,32 ON/OFFBTN_LED# 32 32
CAPS_LED# NUM_LED#
32 VCC1_PWRGD
ACES_87216-2404_24P CONN@
1
2
DEBUG@ R401 1
0_0402_5% 2
DEBUG@ R402 1
0_0402_5% 2
DEBUG@ R403 1
0_0402_5% 2
DEBUG@ R404
0_0402_5%
SPI_SI_JP52 SPI_HOLD#_0 SPI_SO_JP52 ON/OFFBTNLED# CAPSLED# NUMLED# VCC1PWRGD
om
SPI_CLK
HOLD
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
l.c
FSEL#
32
W
7
4
ai
32
3
VSS
Compal Secret Data
Security Classification Issued Date
2006/02/13
Deciphered Date
2006/07/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
nf @ ho tm
2
VCC
Compal Electronics, Inc. BIOS ROM
Size
Document Number
LA-3821P Date:
Tuesday, July 31, 2007
ai
C468 0.1U_0402_16V4Z
8
PCI_RST#
Ground LPC_PCI_CLK Ground LPC_FRAME# +V3S LPC_RESET# +V3S LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 VCC_3VA PWR_LED# CAPS_LED# NUM_LED# VCC1_PWRGD SPI_CLK SPI_CS# SPI_SI SPI_SO SPI_HOLD# Reserved Reserved Reserved
he x
20mils 1
18,32 19,22,32 19,22,32 19,22,32 19,22,32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Sheet
31
of
43
R ev 0.3
+3VALW_EC
C472
C473
+EC_AVCC M/B_ID
@ R408 1
GATEA20 1 KB_RST# 2 SIRQ 3 LPC_LFRAME# 4 LPC_LAD3 5 LPC_LAD2 7 LPC_LAD1 8 LPC_LAD0 10
19 GATEA20 19 KB_RST# 20 SIRQ 19,22,31 LPC_FRAME# 19,22,31 LPC_AD3 19,22,31 LPC_AD2 19,22,31 LPC_AD1 19,22,31 LPC_AD0
2
15P_0402_50V8J 33_0402_5%
CLK_PCI_EC PCI_RST# ECRST# EC_SCI#
15 CLK_PCI_EC 2 R409 1 47K_0402_5%
2
2
0.1U_0402_16V4Z
0_0402_5% 2 0_0402_5% 2
ESB_DATA
EC_SUSP# EC_PWRBTN_OUT# 31,40 31,40 4,30 4,30
20 20 20 30
EC_PIN18
1 CONN@ JP32 +5VALW 3 2
77 78 79 80
SLP_S3# SLP_S5# EC_SMI# LID_SW# EC_PIN17 EC_PIN18 PCI_PME#
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
4 30
FAN_SPEED CAP_RESET
CAP_RESET UTX URX ON/OFF CPUSB# NUM_LED#
C R Y2
2
27P_0402_50V8J C478 NC OUT 4
122 123
PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
@ 20M_0402_5% R422
NC IN 1 Y5 32.768KHZ_12.5P_1TJS125DJ2A073 C R Y1 1 2
FOR LPC SIO DEBUG PORT
27P_0402_50V8J C479
CONN@ JP33
AVCC
EC_MUTE# 28 ACZ_RST# 19,27
TP_CLK TP_DATA
100K+/-5%
Board ID
Rb
V AD_BID min
V AD_BID typ
0
0V
0V
0V
1
8.2K+/-5%
0.216V
0.250V
0.289V
2
18K+/-5%
0.436V
0.503V
0.538V
3
33K+/-5%
0.712V
0.819V
0.875V
4
56K+/-5%
1.036V
1.185V
1.264V
5
100K+/-5%
1.453V
1.650V
1.759V
6
200K+/-5%
1.935V
2.200V
2.341V
7
NC
2.500V
3.300V
3.300V +5VS
TP_CLK 30 TP_DATA 30
CLK_ENABLE R411 CLK_ENABLE 15 2 1 10K_0402_5% LAN_POWER_OFF LAN_POWER_OFF 24
TP_CLK 2 1 10K_0402_5% R410 TP_DATA 2 1 10K_0402_5% R412
FR D# FWR# SPI_CLK FSEL#
FRD# FWR# SPI_CLK FSEL#
Remove T/P dis/ena
31 31 31 31
C505 AC IN
1
2
100P_0402_50V8J 73 74 89 90 91 92 93 95 121 127
110 112 114 115 116 117 118
V18R
124
I2C_INT VCC1_PWRGD FSTCHG
04/17
I2C_INT 30 VCC1_PWRGD 31 FSTCHG 35 AMBER_LED# 30 CAPS_LED# CAPS_LED# 31 BAT_LED# BLUE_LED# 30 ON/OFFBTN_LED# ON/OFFBTN_LED# 30,31 SYSON SYSON 23,33,37 VR_ON VR_ON 39 AC IN ACIN 35 2 1 R419 10K_0402_5% EC_RSMRST# EC_RSMRST# 20 R420 1 0_0402_5% 2 EC_LID_OUT# 20 EC_ON EC_ON 30 BT_OFF 29 PM_PWROK PM_PWROK 7,20 BKOFF# BKOFF# 17 M_PWROK M_PWROK 7,20 EC_MUTE 28 WL_ON# WL_ON# 22
04/14
05/03
SLP_S4# ENABLT
SLP_S4# 20 ENABLT 9,17
THERM_SCI# EC_SUSP# EC_PWRBTN_OUT#
04/04
THERM_SCI# 20
KB926QFB0_LQFP128_14X14
05/23 EC request
For EMI KSO14 KSO11 KSO10 KSO15
JP31 KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CP1 1 2 3 4
8 7 6 5
@ 100P_1206_8P4C_50V8 CP2 1 8 2 7 3 6 4 5
KSO6 KSO3 KSO12 KSO13
@ 100P_1206_8P4C_50V8 KSO2 KSO4 KSO7 KSO8
CP3 1 2 3 4
8 7 6 5
@ 100P_1206_8P4C_50V8 CP4 1 8 2 7 3 6 4 5
KSI3 KSO5 KSO1 KSI0
@ 100P_1206_8P4C_50V8 25 26
+EC_AVCC
L18 0_0603_5%
GND1 GND2 ACES_85201-24051 CONN@
KSI4 KSI5 KSO0 KSI2
CP5 1 2 3 4
8 7 6 5
@ 100P_1206_8P4C_50V8
1 LPC_DRQ#0 19
V AD_BID max
0
SP01000FF00 85201-24051 24P P1.0 ACES_85201-24051_24P
L19
2
R421 100K_0402_5%
1 C480
2
1
2 0_0603_5%
CP6 KSI1 KSI7
0.1U_0402_16V4Z
CLK_DEBUG_PORT_1 SIRQ
ACES_85201-2005
DAC_BRIG 17 EN_FAN 4 IREF 35
3.3V+/-5%
Ra
2
06/14 119 120 126 128
PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7
1 SUSP#
CLK_14M_DEBUG 15
BATT_TEMP 40 BATT_OVP 35 ADP_I 35
VCC
R407 0_0402_5%
2
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ#0 PCI_RST#
2 ECAGND 0.01U_0402_16V7K
05/23 change to voltage control FAN
EC_MUTE# ACZ_RST#
97 98 99 109
35 1 C475
+3VALW_EC
+5VS +3VS
BATT_TEMP BATT_OVP ADP_IN M/B_ID
83 84 85 86 87 88
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 G PO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11
GPI
ACOFF
DAC_BRIG EN_FAN IR EF
100 101 102 103 104 105 106 107 108
XCLK1 XCLK0
2
ACES_85205-0400
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PCI_PME#
30 ON/OFF 20,23 CPUSB# 31 NUM_LED#
EC DEBUG port
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SLP_S3# SLP_S5# EC_SMI# LID_SW#
18
05/23 change to voltage control FAN
URX UTX
SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2
INV_PWM 17 EC_BEEP 27
ACOFF
68 70 71 72
EC_PIN17
Change pin define for try ENE cap bottom
1 2 3 4
SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2
63 64 65 66 75 76
INV_PWM EC_BEEP
AGND
R461 @ ESB_CLK 1 R462 ESB_DATA 1 @
DA Output
KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 PSCLK1/GPIO4A KSI4/GPIO34 PSDAT1/GPIO4B KSI5/GPIO35 PSCLK2/GPIO4C PS2 Interface KSI6/GPIO36 PSDAT2/GPIO4D KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 SDICS#/GPXOA00 KSO4/GPIO24 SDICLK/GPXOA01 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 KSO6/GPIO26 Matrix SDIDI/GPXID0 SPI Device Interface KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 SPIDI/RD# KSO10/GPIO2A SPIDO/WR# SPI Flash ROM SPICLK/GPIO58 KSO11/GPIO2B KSO12/GPIO2C SPICS# KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F CIR_RX/GPIO40 KSO16/GPIO48 CIR_RLC_TX/GPIO41 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 GPIO BATT_LOW_LED#/GPIO54 SCL1/GPIO44 SDA1/GPIO45 SUSP_LED#/GPIO55 S M Bus SCL2/GPIO46 SYSON/GPIO56 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59
69
0_0402_5% 2 0_0402_5% 2
WL_BTN#
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82
DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F
21 23 26 27
ECAGND
@ 1 R460 PWRBTN_OUT#1 @
AD
PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D
BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43
GND GND GND GND GND
ESB_CLK
2
2 0_0402_5% 2 0_0402_5% 2
R451
20 PWRBTN_OUT#
R414 10K_0402_5%
LID_SW#
SUSP#
23,33,35,37,38 SUSP#
1
1
2
2
2
SMB_EC_DA1 SMB_EC_CK1 SMB_EC_DA2 SMB_EC_CK2 R467 SUSP# 1 R468 PWRBTN_OUT# 1
1 2 3 4
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
+3VS
R413 10K_0402_5%
PWM Output
JOPEN
1
1
R416 4.7K_0402_5% 4.7K_0402_5%
1
1
R415
R417 R418 4.7K_0402_5% 4.7K_0402_5% 2
EC_SCI#
J1
+5VALW +3VALW
06/15
PCI_RST#
20
0.1U_0402_16V4Z
INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13
1
+3VS
18,31
GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC
11 24 35 94 113
1
1
+3VALW C477
12 13 37 20 38
Rb
1
@ C474
VCC VCC VCC VCC VCC VCC
U20
@ C476 1 2
100K_0402_5%
R406 2 1 0_0805_5%
2
2
+3VALW_EC
1
C471
2 2 1000P_0402_50V7K
R405
+3VALW
2
C470
1000P_0402_50V7K 1
67
C469 2 2 0.1U_0402_16V4Z
0.1U_0402_16V4Z 1
9 22 33 96 111 125
0.1U_0402_16V4Z 1 1
1
Ra
1
+3VALW_EC
@ R423 10K_0402_5% 2 1
1 2 3 4
8 7 6 5
@ 100P_1206_8P4C_50V8
CLK_DEBUG_PORT_2 15
Compal Secret Data
Security Classification Issued Date
2006/02/13
Deciphered Date
2006/07/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Compal Electronics, Inc. EC KB926/KB conn
Size
Document Number
R ev 0.3
LA-3821P Date:
Tuesday, July 31, 2007
Sheet
32
of
43
A
B
C
D
E
C488
+5VALW to +5VS Transfer
1
+3VALW to +3VS Transfer
1
+VCC_CORE
2
+VCCP
1
0.1U_0402_16V4Z +5VALW
+5VS
+3VALW
+3VS
B+ U21
C481
S S S G
1 2 3 4
8 7 6 5
1
D D D D
R424 1
AO4466_SO8 2 10U_0805_10V4Z
1
C483
2
2
C484
1
C482
D D D D
330K_0402_5%
C489
10U_0805_10V4Z
10U_0805_10V4Z
1 2 3 4
S S S G
1
AO4466_SO8 2 10U_0805_10V4Z
2
1
8 7 6 5
U22
C485
2
1
1
+VCCP
2
+1.5VS
0.1U_0402_16V4Z C486
2
RU NON 1
RU NON 0.1U_0402_16V4Z
0.1U_0402_16V4Z
D
S
470_0402_5% 2
1 SUSP
3
R425
Q28 2N7002_SOT23-3
2 G
1
2
C487 0.01U_0402_16V7K
2
2
1
+5VALW
1
+5VALW
100K_0402_5%
S
Q30 2N7002_SOT23-3
470_0402_5% 2
H29 HOLEA
1
3
1
H22 HOLEA
H31 HOLEA
1
1
H28 HOLEA
1
H27 HOLEA
H21 HOLEA
1
1
1
1
1
1
1
1
H26 HOLEA
H20 HOLEA
H14 HOLEA
D
S
Q36 SUSP 2 2N7002_SOT23-3 G
Q37 2N7002_SOT23-3
1
S
Q35 SUSP 2 2N7002_SOT23-3 G
H25 HOLEA
H19 HOLEA
H13 HOLEA
H32 HOLEA
1
D
3
S
Q34 SUSP 2 2N7002_SOT23-3 G
1
D
3
S
Q33 SUSP 2 2N7002_SOT23-3 G
1
D
3
S
SYSON# 2 Q32 2N7002_SOT23-3 G
1
1
D
H18 HOLEA
H12 HOLEA
1
1
1 R434
470_0402_5% 2
R433
470_0402_5% 2
R432
470_0402_5% 2
R431
470_0402_5% 2
R430
H24 HOLEA
H17 HOLEA
H11 HOLEA
1
H23 HOLEA
+0.9V
1
1
+VCCP
470_0402_5%
3
S
Q31 SUSP 2 2N7002_SOT23-3 G
2 G
+1.25VS
R429
2 1
S
D
3
2 1 3
SUSP
D
+1.5VS
3
R428 470_0402_5%
+1.8V
1
1
+3VS
1
+5VS
1
Discharge circuit
H16 HOLEA
H10 HOLEA
1
1
H15 HOLEA
H9 HOLEA
1
3
H8 HOLEA
1
H7 HOLEA
1
S
1
3
D
SUSP# 2 G
23,32,35,37,38 SUSP#
1
Q29 2N7002_SOT23-3
2 G
1
SYSON
23,32,37 SYSON
SUSP
SUSP
1
37 D
3
SYSON#
SYSON#
1
29,37
2
R427
100K_0402_5% 2
R426
1
FM1 1
FM2
FM3 1
FM4 1 4
Compal Secret Data 2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. DC/DC Interface
Size
Document Number
LA-3821P Date:
R ev 0.3
ai
2006/02/13
Issued Date
T u es day , J u l y 3 1 , 2007
he x
Security Classification
nf @ ho tm
ai
l.c
om
4
Sheet
E
33
of
43
A
B
C
D
1
1
2
2
VIN PL1 SMB3025500YA_2P 1
1
2
PC3 100P_0402_50V8J 2 1
1 PC2 1000P_0402_50V7K
2
3
SINGA_2DC-S756B200
1
2
2
G G
A DPIN
PC4 1000P_0402_50V7K 2 1
PCN1
PC1 100P_0402_50V8J
3
3
4
4
Compal Secret Data
Security Classification Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title Size Document Number C ustom D ate:
DC CONN
R ev
LA-3821P Sheet
Tuesday, July 31, 2007 D
34
of
43
A
B
C
D
P2 V IN PQ1 FDS4435BZ_SO8
4 1
4
PACIN
ACIN XACOK
18
8
-INE1
RT
17
9
+INE1
-INE3
16
10
OUTC1 FB123
15
11
SEL
14
1
P R27 33K_0402_1% M B39A126 1
CTL
-INC1
+INC1
13
2 1 1 3
1
PQ7 RHU002N06_SOT323-3
3
1 P D2 EC31QS04
1
1
2
BATT
2
0.02_2512_1%
F STCHG
RB751V-40_SOD323-2 P D4 1 2
SUSP#
23,32,33,37,38
RB751V-40_SOD323-2
3
2
2
CV=12.6V (6/12 CELLS LI-ION) CC=3.08A (6/12 CELLS LI-ION)
P R36 100K_0402_5% 1
1
PU4A LM358ADT_SO8
+5VALW
BATT_DET 40
2 G 3
S
P U4B LM358ADT_SO8
4
P
+
5
G
8 7
3
D PQ12 RHU002N06_SOT323-3
PQ13 RHU002N06_SOT323-3
2
+3VALW
P R34 100K_0402_5%
1
2
D
S PQ14 DTC115EUA_SC70-3
+3VALW
2 3
-
2
1
2
16UH_SIL104R-160PF_3.6A_30%
P C24 1500P_0402_50V7K 21 2
P C25 10P_0402_50V8J 1 2
1
2 8 P
+
0 4
1
G
P R37 10K_0402_5% 1 2
CS
2 G
1
P C27 47P_0402_50V8J 1 2
2
1
P C10 4.7U_1206_25V6K
P R19 47K_0402_1% 1 2
P D3
P C30 0.01U_0402_25V7K
NC
P C9 4.7U_1206_25V6K 2 1
1 2 3
1 P R13
2
P R17
PL3
P C21 10U_1206_25V6M 2 1
7
P C16 0.1U_0603_25V7K 1 2
P C20 10U_1206_25V6M 2 1
VH
32
FDS4435BZ_SO8
1
VREF
A COFF
2
P C19 10U_1206_25V6M 2 1
20 19
3
OUT
DTC115EUA_SC70-3
5 6 7 8
ACOK
6
1 2 1 P R35 P R33 499K_0402_1% 340K_0402_1%
2
1 P R39 105K_0402_1%
NC
1
3
ANODE
P R38 47K_0402_1%
-
6
4
0
4
A
B
C
Compal Electronics, Inc. Charger
Dat e:
Tu esday, July 31, 2007 D
Rev
l.c
Size D ocument Number Cus t om
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
nf @ ho tm
Deciphered Date
ai
Issued Date
om
Compal Secret Data
Security Classification
he x
1 2
5
2
+5VALW
1 .24VREF
CATHODE
P C29 0.01U_0402_25V7K
REF
32 BATT_OVP
1
21
BATT P U3
3
VCC
PQ11
4
P C13 0.22U_0603_16V7K 1 2 P C14 0.1U_0603_25V7K 1 2
2 G PQ10 S RHU002N06_SOT323-3
S
PQ8
P R31 10K_0402_5% 2
P C28 22P_0402_25V8K 2 1
-INE2
D
D
RLZ4.3B_LL34
P R32 1 2 49.9K_0402_1%
+3VALW
F STCHG
4
CS
36
LMV431ACM5X_SOT23-5
32
22
+3VLP
P R9 100K_0402_5% 2 1 2 G
1
G
P A C IN
P D5
5
23
CS
2
3.2V
1
LM393DG_SO8
4
GND
+INE2
12
P2
3
OUTC2
3
A CO FF#
2 2
32
2
1
1
ACIN
P R26 10K_0402_1% 2 1
P C23 1U_0603_6.3V6M
P R25 100K_0402_1%
2
P U2A O
1
P R18 P C18 1K_0402_1% 2200P_0402_50V7K M B39A1261 2 1 2
P R21 150K_0402_1% 2
2
P R29 100K_0402_1%
32
1K_0402_5%
1
-
1
2
2
1
2 8 +
2
P R23 10K_0402_1%
P C22 0.1U_0603_25V7K
1
V IN
P R6 10K_0402_5%
P A C IN
1
1
1
P R24
P
3
4
1
133K_0603_1%
P R22 2 1 P R30 2
P R28 2.15K_0402_1% 1 2 10K_0603_0.1%
P C26 0.047U_0402_16V7K 2 1
IRE F
P R20 47_1206_5%
ADP_I_A
P C8 2200P_0402_50V7K 2 1
1 2 2
1
P R16 1 2 1M_0402_5% V IN
V IN
P C12 P R12 4700P_0402_25V7K 100K_0402_1% 1 2 2 1
VREF
P C17 0.22U_0603_16V7K
2
1 P R14 10K_0402_1% 2 1
M B39A126
P R15 30K_0603_1%
P R11 10K_0402_1% 1 2
S
2
P2
P U1 MB39A126PFV-ER_SSOP24 1 -INC2 +INC2 24
2
P D1 RLS4148_LLDS2 2
1
1
2 G
P C15 0.01U_0402_25V7K
A CO FF#
CHG_B+
D PQ9 RHU002N06_SOT323-3
3
1 2 3K_0402_5%
1
P R8 10K_0402_5%
2
2
0_0402_5%
A DP_I
2
32
1 1 P R10
CHG_B+ P C7 0.1U_0603_25V7K 2 1
P R7 150K_0402_5%
P C11 0.22U_0603_16V7K P A C IN
2
0.02_2512_1%
3
PQ6 S RHU002N06_SOT323-3
PL2 SMB3025500YA_2P 1 2
P R5
3
2 G
P R3 1 2 47K_0402_5%
2
P C6 1 2
0.22U_0603_16V7K
P4
8 7 6 5
P R2 200K_0402_5%
1
PQ5 DTC115EUA_SC70-3
BATT
1 2 3
1
D
PQ3 FDS6675BZ_SO8
B+
DTA144EUA_SC70-3
2 1
4 PQ4
8 7 6 5
2
P R4 47K_0402_1% 1 2
3 2 1
2
1
1
PQ2 FDS4435BZ_SO8 3 2 1
3
P C5 47P_0402_50V8J 1 2
P R1 47K_0402_5% 2 1
8 7 6 5
Sheet
35
of
43
B
PC46 0.047U_0603_16V7K
5 6 7 8
1
2
2
2
1
2
3 2 1 5 6 7 8
2 P R48 0_0402_5%
1
1 2 1 P R47 499K_0402_1%
1
2
3 2 1
1 2 1 PR46 @499K_0402_1%
2
17 VCC
TON
13
20 V+
1
10U_LF919AS-100M-P3_4.5A_20%
7 2
FB3 PGOOD
+3VALWP 2
RT8203PA_SSOP_28P
+3VLP
1
PR58 0_0402_5%
2
1 +
2
VL 1
2
1
1
PR56 2 1 499K_0603_1%
BST_3.3V DH _3.3V DL_3.3V LX_3.3V
P C44 150U_D2_6.3VM
MAINPW ON 40
2
MAINPW ON
P C43 0.22U_0603_10V7K
2VREF_1999 VL
2
PL6
1
REF
28 26 24 27 22
4
P R55 @3.57K_0402_1%
SKIP#
BST3 DH3 DL3 LX3 OUT3
PQ18 AO4466_SO8
2
12
ILIM5
11
100K_0402_1% PR45
1
SHDN# ON5 ON3
8
1
2
6 4 3
5
PR44 0_0402_5%
P R59 0_0402_5%
PR52 1 2 @0_0402_5% 1 2 PR53 @10K_0402_5%
ILIM3
DH_3.3V_B
PRO#
2VREF_1999
PR43 0_0402_5%
10
2 0_0402_5%
4
2
PR50
PQ16 AO4466_SO8
1
LX5 DL5 OUT5 FB5 N.C.
LDO3
15 19 21 9 1
GND
LX_5V DL_5V
25
DH5
23
1
16
P R57 300K_0402_5% 2 1
P R54 0_0402_5%
2
2VREF_1999
BST5
D H_5V
P C45 4.7U_0805_10V4Z
B++ P R51 47K_0402_5% 2 1 2 1 P C42 0.1U_0603_25V7K
1 2
+
1
P C41 220U_6.3VM_R15
2
P R49 @10.2K_0402_1%
+5VALWP
18
1 2 3 2
PC121 @0.1U_0402_16V7K 2 1
PC37 0.1U_0603_16V7K
2VREF_1999
2
PU5 BST_5V 14
1
1
LD05
P C38 4.7U_0805_10V4Z
1
4
PL5 4.7U_LF919AS-4R7M-P3_5.2A_20%
VL
1
P C39 2 1 0.1U_0603_50V4Z
1
8 7 6 5
1 2 3
PR42 0_0402_5%
P C40 1U_0805_16V7K
B++
2
2
1
PR40 0_0402_5% 2
2
1
P R41 47_0402_5%
4DH_5V_B
1
P C36 4.7U_1206_25V6K
3
VL
PQ17 AO4466_SO8
2
B++
PD6 CHP202UPT_SOT323-3 PQ15 AO4466_SO8
E
PC32 0.1U_0603_50V4Z 1 2
BST_3.3V_B
8 7 6 5
1
2 1 P C34 10U_1206_25V6M
2
2 1 P C33 2200P_0402_50V7K
B+ 1
BST_5V_B
P C35 2200P_0402_50V7K
PC31 0.1U_0603_50V4Z 1 2
B++
HCB2012KF-121T50_0805
D
1
PL4
C
2
A
3
RTC Charger Circuit 2007/04/20
PQ19
2
1
D
3
PR60 100K_0402_5%
2 G S RHU002N06_SOT323-3 D
1
35 S
2 G PQ21 RHU002N06_SOT323-3
1
3
+3VLP 2
+CHGRTC
2 P ACIN G PQ20 RHU002N06_SOT323-3
2
3
S
PQ22 TP0610K-T1-E3_SOT23
D
3
PR157 PR158 560_0603_5% 560_0603_5% 1 2 1 2
1
3
+3VL
PR62 100K_0402_5%
2 1
1
PR61 100K_0402_5%
BATT1.1
W=20mils
+
BATT1
1
2
30
51ON#
@ML1220T13RE 45@
4
4
Compal Secret Data
Security Classification
Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. 3.3VALWP / 5VALWP
Size D ate:
Document Number Tuesday, July 31, 2007
R ev Sheet E
36
of
43
5
3
1
1
1
2
1
P R66 73.2K_0402_1%
2
2
P R65 75K_0402_1%
P R64 10.2K_0603_0.1% 1 2
P C51 4.7U_1206_25V6K D
2
P R63 14.3K_0603_0.1% 1 2
P C50 @2200P_0402_50V7K 2 1
2 1 P C49 10U_1206_25V6M
D
P C48 2200P_0402_50V7K 2 1
2
P C47 680P_0402_50V7K
2
B+++
PL7 HCB2012KF-121T50_0805 1 2
1
B+
4
DR VH1
21
DR VL1
+1.5VSP
PL16
2
1
0.1U_0603_25V7K
2
3.3UH_SIQB74-3R3RF_4.8A_30%
LX_1.5V
1
LG_1.5V P C54 4.7U_0805_6.3V6K
PGND1
TRIP1
20 19
1
+ 2
TPS51124RGER_QFN24_4x4
C
18
17
13
LL1
BS T_1.5V UG_1.5V
SP8K10S FD5 2N SOP8
P C52
P C55 220U_6.3VM_R15
2
1 VO1
VFB1
4
3 GND
TONSEL
5
DR VL2 PGND2
8 7 6 5
22
P R72 0_0402_5% 1 2
1
LL2
LG_1.8V
P R74 18.2K_0402_1% 1 2
1 2 3
VBST1
P R71 0_0402_5% 1 2 UG1_1.5V
1 2 3 4
P R 75 15.4K_0402_1%
1
2
2
P C76 680P_0603_50V7K
6
DR VH2
11 12
4
PQ25 FDS6690AS_NL_SO8
EN1
VBST2
1 2
P R 88 4.7_1206_5%
1
P C58 0.1U_0402_16V7K
1 2
+ 2
P C57 0.1U_0402_16V7K 2 1
220U_6.3VM_R15 P C56
C
1
24 23
G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A
1
LX_1.8V
9 10
V5IN
0.1U_0603_25V7K
PL9 3.3UH_PCMC063T-3R3MN_6A_20% 2 1
BS T_1.8V UG_1.8V
PGOOD1
EN2
V5FILT
2
1 2 3
+1.8VP
PGOOD2
8
PQ24 8 7 6 5
2
7
16
P R73 0_0402_5% 1 1 2
P C53
15
UG1_1.8V
TRIP2
P R68 0_0402_5% 1 2
P PAD
14
4
25
VO2
P U6
PQ23 AO4466_SO8
VFB2
8 7 6 5
1
P R67 0_0402_5%
P C59 1U_0603_10V6K
P R76 3.3_0402_5% 2
1
P R77 0_0402_5% 2
2
1
+5VALWP 1
1
23,32,33 SYSON
P C60 4.7U_0805_10V6K
1
2
SUSP# 23,32,33,35,38
0_0402_5% P R78
2
1
2
PR160 100K_0402_5%
2
P C61 @1000P_0402_50V7K
B
B
+1.8V
1 P R82 0_0402_5%
6
NC
5
3
VREF
NC
7
4
VOUT
NC
8
TP
9
+5VALW
2
1
1
P C64 1U_0603_16V6K
D
S
2 G
+0.9VP 1
1 2
P R81 1K_0402_1% 2
SUSP
1
33
1
PQ26 RHU002N06_SOT323-3
VCNTL
GND
G2992F1U_SO8
2
P R80 @0_0402_5%
2
1
3
29,33 SYSON#
P R79 1K_0402_1%
2 1 P C65 0.1U_0402_16V7K
7,13,14 V_DDR_MCH_REF
VIN
2
2
1 2
2
P C62 10U_0805_10V4Z
P C63 @10U_0805_10V4Z
1
P U7 1
P C66 10U_1206_6.3V7K
2
P C67 @0.1U_0402_16V7K
A
A
Compal Secret Data
5
4
3
2
Title
Compal Electronics, Inc.
Size
om
1.8VP/0.9VP/1.5VSP D ocument Number
L A-3821P Dat e:
T uesday, July 31, 2007
Sheet
1
Rev 0.2
l.c
2007/11/23
ai
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
nf @ ho tm
2006/11/23
ai
Issued Date
he x
Security Classification
37
of
43
5
4
3
2
1
PL10 HCB1608KF-121T30_0603 B+
2
1
1.05V_B+
5 6 7 8 1
2
2
3 2 1
2
+1.05V_VCCP
5 6 7 8
1
12
LX
11
ILIM
10
2 4
9
P C75 4.7U_0805_6.3V6K
DL
1
VDDP
+
PQ28 FDS6690AS_NL_SO8
LX_1.05V P R89 1 2 21K_0402_1%
2
13
14
15
1
BST DH
SC411MLTRT_MLPQ16_4X4
8
PGND
VSSA
7
6
17
C
NC
PGD TP
FB
4
5
P R90 2 1 0_0402_5%
3
PL11 2.2UH_PCMC063T-2R2MN_8A_20%
2
1
VCCA
1
P C71 0.1U_0402_16V7K
3 2 1
VOUT
2
UG_1.05V BOOT1_1.05V
2 0_0402_5%
2
1
NC
EN/PSV
16 TON
2
P U8
1
P C73 220U_V_4VM_R25M
BOOT_1.05V 1
2 P R87 10K_0402_1%
2
1
VCCP_POK
P R86
1 1 P C72 @2200P_0402_25V7K
P C74 1U_0603_10V6K
4
1SS355_SOD323-2
2
P R85 0_0402_5%
2
1
P D7
1
1
P C70 1000P_0402_50V7K
23,32,33,35,37 SUSP#
D
PQ27 AO4466_SO8
P R84 1M_0402_5%
2
D
P R83 10_0402_5%
2 1 P C69 10U_1206_25V6M
+5VALWP
P C77 1U_0603_10V6K
C
LG_1.05V
P R91 1 2 11K_0402_1% 2 +5VALWP
2
(4.5A,180mils ,Via NO.= 9)
+1.25VSP
1
+3VALWP
1
2
P R94 0_0402_5%
2
+3VALW
(3A,120mils ,Via NO.= 6) 2
1
+3VL
(7A,280mils ,Via NO.= 14)
+ VCCP
(6A,240mils ,Via NO.=12)
+1.5VS
(6A,240mils ,Via NO.=12)
+0.9V
(2A,80mils ,Via NO.= 4)
FB
2
2
VCNTL
VOUT
(100mA,20mils ,Via NO.= 1)
P R95 33.2K_0402_1%
PAD-OPEN 4x4m
1
2
P C82 22U_1206_6.3V6M
P C83 47P_0402_50V8J
P R96 59K_0402_1% 2
PJP6 +1.05V_VCCP
B
+1.25VSP
APL5913-KAC-TRL_SO8
PAD-OPEN 2x2m +1.8V
EN
P C80 10U_1206_6.3V6M
1
2
23,32,33,35,37 SUSP#
,Via NO.= 1)
4
PJP4 +3VLP
1
+1.25VS(500mA,40mils
P C81 @0.01U_0402_16V7K
PAD-OPEN 4x4m PJP5 +1.8VP
2 PAD-OPEN 3x3m
PAD-OPEN 4x4m PJP3
VOUT
3
1
+5VALW
8
9
1
2
2
5
VIN
1
1
1
VIN
2
+5VALWP
PJP2
POK
1
PJP1
1
B
7
GND
2 P R93 @0_0402_5%
1
P U9 1
+1.5VS
P C79 1U_0603_6.3V6M
6
2
1
P R92 10K_0402_1%
2
1
P C78 33P_0402_50V8J
2
1
PAD-OPEN 4x4m PJP7 +1.5VSP
1
2 PAD-OPEN 4x4m PJP8
+0.9VP A
1
2 PAD-OPEN 3x3m
A
Compal Secret Data
Security Classification Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. 1.05V_VCCP/2.5VSP
Size
D ocument Number
Rev 0.2
L A-3821P Dat e:
T uesday, July 31, 2007
Sheet 1
38
of
43
5
4
3
2
1
+5VS
G S S S
220P_0402_50V7K
255_0402_1% 1
2
PC115 0.22U_0603_10V7K
1
1 2
PC90 1000P_0402_50V7K
1
1
2
1 2
PC127 1000P_0402_50V7K
PC89 2200P_0402_50V7K 2 1
PC128 1000P_0402_50V7K
PC126 4700P_0402_25V7K 2 1
1 2
PC125 4700P_0402_25V7K 2 1
PC98 2200P_0402_50V7K 2 1
1 2
D D D D G S S S 4 3 2 1
CPU_B+
B
1
PR144 4.42K_0402_1% PC114 0.1U_0402_16V7K 1 2
2
10KB_0603_5%_ERTJ1VR103J PH2
1
11K_0402_1%
1 PR142 2
2
2
PR139
1
1
2
ISEN2
VSUM
2 PR143 1K_0402_1% VCC_PRM
PC106 1 2
PC109 0.1U_0603_25V7K
PC112 0.01U_0603_50V7K
PC113 180P_0402_50V8J 1 2 2
@0_0603_5% 2
0.22U_0603_10V7K
1 2
PC111 @0.022U_0603_50V7K
1
24
23
22
21
1 PC110 820P_0603_50V7K 1 2
VSSSENSE
VSUM
1_0402_5%
PR129 1
2
PR136 1K_0402_1%
5
+5VS
PR128
VCC_PRM
2
VCCSENSE
PC103 680P_0603_50V8J
PR132 1_0603_5% PC105 1U_0402_6.3V4Z
PR135 10_0603_5% 1 2
B
5
20
19
1
PC108 1000P_0402_50V7K 1 2
PR1341
ISEN1 ISEN2 2
PR127 10K_0402_1% 2 1
ISEN2
VDD
GND
VIN
VSUM
VO 18
17
16
15
D D D D 470P_0402_50V7K 2
PU10
C
2.61K_0402_1%
1 PC107
1
2
PR130 97.6K_0402_1% PC104 1 2 2
1 PR131 2 @0_0402_5%
PC102 1000P_0402_50V7K
14
13
2 2 PR133 1 1K_0402_1%
1
PR125 6.8_1206_5%
1
25
2
NC
CPU_B+
0.36UH_PCMC104T-R36MN1R17_30A_20% 2 1 PL14 3.65K_0805_1%
FB2
PC96 10U_1206_25V6M 2 1
12
UGATE_CPU2-2
PR126
26
PC95 10U_1206_25V6M 2 1
BOOT2
1
FB
PR118 @0_0603_5% 1 2 PC94 1 2 VCC_PRM ISEN1 0.22U_0603_10V7K
VSUM
1 2
11
PHASE_CPU2 PR122 UGATE_CPU2-1 1 2 2.2_0603_5% BOOT_CPU2 1 2 1 2 PR123 0_0603_5% PC101 0.22U_0603_10V7K
2
27
PQ34 FDS6676AS_SO8
UGATE2
G S S S
COMP
4 3 2 1
10
PQ33 FDS6676AS_SO8 4 5 G D 3 6 S D 2 7 S D 1 8 S D
28
LGATE_CPU2
PQ32 SI4684DY-T1-E3_SO8
+VCC_CORE
PR117 1_0402_5%
LGATE_CPU1
5 6 7 8
PHASE2
ISEN1
29
VW
DFB
1 2 1000P_0402_50V7K PC100 PR124 6.81K_0402_1% 1 2
PGND2
9
ISL6262ACRZ-T_QFN48_7X7
DROOP
13K_0402_1% 1 2
OCSET
RTN
PR121
SOFT
8
VSEN
0.022U_0603_25V7K PC99 1 2
7
VDIFF
C
PL13
D
2
1 PR115 2
PR114
5 6 7 8 D D D D
PR116 10K_0402_1% 2 1
LGATE2
30
3.65K_0805_1%
31
5 6 7 8
1 32
PVCC
0.36UH_PCMC104T-R36MN1R17_30A_20% 2 1
6.8_1206_5% 680P_0603_50V8J
LGATE1
1 2
PHASE_CPU1
33
PC93
34
PGND1
2
PHASE1
RBIAS
PQ31 FDS6676AS_SO8
PMON
PC88 10U_1206_25V6M 2 1
PC86 47U 25V M 6.3X6 ESR0.44 CE-LX PC87 10U_1206_25V6M 2 1
PC123 4700P_0402_25V7K
1 2 D D D D
5 6 7 8
2
4 3 2 1 UGATE_CPU1-1
G S S S
35
4 3 2 1
36 G S S S
BOOT1 UGATE1
D D D D
37 VID0
38 VID1
PC124 4700P_0402_25V7K 2 1
1 1
1 2
PR105
PR109
PR108 39 VID2
40 VID3
42
44
43
46
45
47
41 VID4
NTC
VID5
VR_TT#
6
VID6
5
DPRSLPVR
4
DPRSTP#
48 3V3
3
+ 2
1 PC122 4700P_0402_25V7K
5
5
5
5 CPU_VID2 5 CPU_VID1 5 CPU_VID0 5
32 CPU_VID3
CPU_VID4
PR104
1 PSI#
1
5 6 7 8
VR_TT#
PGOOD
2
1 2 2.2_0603_5% PR113
PQ30 FDS6676AS_SO8
2 PR119 147K_0402_1% 1 2
PQ29 SI4684DY-T1-E3_SO8
0.22U_0603_10V7KUGATE_CPU1-2 PC92 2 1 2
0_0603_5% PR110 1
4 3 2 1
1 PR159 @0_0402_5%
1
CLK_EN#
H_PSI#
CPU_VID5
2 PGD_IN
VGATE
PC85 2.2U_0603_6.3V6K
2 49
PC91 1U_0603_6.3V6M
1 15,20 5
PC84 0.022U_0402_16V7K
BOOT_CPU1
1
2
499_0402_1%
1.91K_0402_1%
PR112
2
PR111
0_0402_5% 2
GND
PR106 1
+3VS +3VS
0_0402_5% 2
PL12 SMB3025500YA_2P 2
2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5% 2 1 0_0402_5%
PR100 1
CLK_ENABLE#
VR_ON
5,7,19 H_DPRSTP#
PR103
0_0402_5% 2
PR102
PR99 1
CPU_VID6
VR_ON 499_0402_1% 2
PR101
1
7,20 DPRSLPVR
PR107
PR98
D
B+
CPU_B+ PR97 1_0603_5%
PC116 0.22U_0402_6.3V6K 2 1
1
A
nf @ ho tm
ai
l.c
om
A
Compal Electronics, Inc. Title
5
4
3
2
Date:
Tuesday, July 31, 2007
he x
Size Document Number Custom
ai
+CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sheet
1
R ev 0.2 39
of
43
A
B
C
D
BATT PCN2
2
PR145
1 1
@1K_0402_5%
PD8 1
3
1
2
SUYIN_200275MR007G113ZL
1
BATT_DET 35
2 PR156 1 1K_0402_5%
@SM05_SOT23
PC117 @1000P_0402_50V7K
2
EC_SMD EC_SMC
2
9 8
7 6 5 4 3 2 1
3
1
BATT+ SMD SMC ID B/I G TS G GND
PC118 @0.01U_0402_50V4Z
PD9 @SM24.TC_SOT23-3
+3VL
1
1
1
PR146 6.49K_0402_1% 1 2
1
2
PR147 1K_0402_5%
2
PR148 100_0402_5%
BATT_TEMP 32
2
2
PR149 100_0402_5%
PCN2 battery connector
2
SMB_EC_DA1
SMB_EC_DA1 31,32
SMB_EC_CK1
S M A RT Batte ry: 7 . BATT+ 6. SMD 5.SMC 4. ID 3.B/I 2.TS 1. GND
SMB_EC_CK1 31,32
2
PH3 under CPU botten side : CPU thermal protection at 90 +-3 degree C Recovery at 47 +-3 degree C PR150 47K_0402_1% 1 2
+5VS
2
CPU
1
+5VS
3
PR151 10K_0402_5%
PH3 10K_TH11-3H103FT_0603_1%
1
2
3
-
2
4 1
7
S
PQ35 RHU002N06_SOT323-3
2 G
LM393DG_SO8
1 2
PR155 150K_0402_1%
D
P O
PC120 1000P_0402_50V7K
2
2
PC119 0.22U_0603_10V7K
PR154 2.55K_0603_1%
2
1
1
PR153 150K_0402_1%
1
+
6
8 5
1
G
+5VS
PU2B
3
MAINPWON 36 PR152 15K_0603_1% 1 2
4
4
Compal Secret Data
Security Classification Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title
Compal Electronics, Inc. BATTERY CONN
Size Document Number C ustom LA-3821P D ate:
R ev Sheet
Tuesday, July 31, 2007 D
40
of
43
5
4
3
Version change list (P.I.R. List) Item D
Reason for change
2
Power section PG#
1
Page 1 of 1
Modify List
Date
Phase
1
RT8203 crosstalk issue
37
add PC121 and 0.1uF
2007/05/24
SI
2
PU6 pin8 add a resistor to GND
38
add PR160
2007/05/24
SI
3
remove PL15
36
remove PL15
2007/06/12
SI
39
add PC122,PC123,PC124,PC125,PC126,PC127,PC128
2007/07/23
PV
4
EMI request
100K_ohm
D
C
C
5
6
7
B
8
B
9
10 11 12 13
14
nf @ ho tm
ai
l.c
om
A
Compal Electronics, Inc. Title
PWR PIR
5
4
3
2
Size Document Number Custom Date:
Tuesday, July 31, 2007
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sheet 1
he x
A
41
of
43
Rev 0.2
5
4
3
Version change list (P.I.R. List) Item
Reason for change
2
Power section PG#
1
Page 1 of 1
Modify List
Date
Phase
1
EC team request
32
ACIN add 100P (C505) to GND
2007/05/30
SI
2
Change Board ID
32
R407 from 0 Ohm to 8.2K,R405 install 100K
2007/05/30
SI
3
USB power switch fail
29
U23 & U17 change pin 4 from SLP_S5# to SYSON#
2007/05/30
SI
4
FAN use voltage control
4
del U2,Q1;add U24,C13 for 3 pin FAN
2007/05/30
SI
5
USB JP24 fail
29
Change pin define
2007/05/30
SI
6
Speaker output fail
28
Add R457,R458,R459 for Line_out
2007/05/30
SI
7
MS Pro fail
26
Add MS_D1,MS_D2,MS_D3 net
2007/06/06
SI
8
WLAN LED fail when disable WLAN
30
Add R232 pull high +5VS
2007/06/06
SI
9
+3VALW leakage
30
Del R387
2007/06/06
SI
10
Capacitor board fail
32
Add net CAP_RESET for Capacitor board reset
2007/06/06
SI
11
XDP fail
15
XDP clock share in robeson card
2007/06/06
SI
12
LAN power consumption is too large when S3
24
Add Q22
2007/06/14
SI
13
RJ11' cap is duplicate MDC module.
25
Delete C378,C379
2007/06/14
SI
14
Reverse some resister for tring ENE cap board
Add R460~R468,R451
2007/06/14
SI
15
+LCDVDD over current when diplay.
Change R163 from 47K to 100K Change C248 from 0.1U to 0.22U
2007/06/21
SI
D
D
C
C
30 32 17
B
B
16 17 18 19 20
LAN fail
24
WLAN LED (Amber led) issue
30
030 project Bluetooth module issue
29
change Cap board LED supply voltage
Change JP14 pin define WLAN LED need change from +5VS to +3VS Swap pin5 & pin7
30
CMOS timing can't reset
19
20
EMI issue (CPU core)
5
21
EMI/ESD
4
issue (XDO connector)
2007/06/06
from +3VS to +5VS
add
2007/07/23
PV
2007/07/23
PV
2007/07/23
SHORT PAD (CLRP3) connect between +RTCVCC and GND
SI
2007/07/23
PV PV
C43 & C44 (330U)
2007/07/23
PV
delete XDP connector
2007/07/23
PV
2007/07/23
PV
A
A
22
EMI/ESD
issue (RJ11 connector)
25
add 1000P at RJ11 RING & TIP
Compal Electronics, Inc. Title
PWR PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size Document Number Custom Date:
Tuesday, July 31, 2007
Rev 0.3 Sheet 1
42
of
43
5
4
3
Version change list (P.I.R. List) Item 23
Reason for change
2
Power section PG#
card reader RTL5158 chip issue
26
1
Page 1 of 1
Modify List
Date
change C393, C394 from 27p to 5.6p
Phase
2007/07/25
PV
D
D
24 25
monitor wave riple issue
10
MIC issue for EMI solution
28
add C508
2007/07/25
PV
add L20, L21, L22, L23, C509, C510
2007/07/31
PV
C
B
B
A
A
nf @ ho tm
ai
l.c
om
C
Compal Electronics, Inc. Title
PWR PIR
5
4
3
2
Date:
Tuesday, July 31, 2007
ai
Size Document Number Custom Sheet 1
he x
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
43
of
43
Rev 0.3
Related documents
INTELBRAS N6000W - COMPAL LA-3821P JFT00 - REV 0.3
43 Pages • 26,622 Words • PDF • 1.1 MB
HP COMPAL LA-4732P UMA - REV 1.0
46 Pages • 27,925 Words • PDF • 1.4 MB
POP A-03-01 Registro rev.8
6 Pages • 1,380 Words • PDF • 233.5 KB
Genética aula 03 (03)
3 Pages • 1,187 Words • PDF • 463.2 KB
Memorial Descritivo - Paradiso REV.02
15 Pages • 4,029 Words • PDF • 777.2 KB
MSI MS-1035 - REV 02S
47 Pages • 25,826 Words • PDF • 1.1 MB
INFOS DO ENVIO rev.
13 Pages • 598 Words • PDF • 3.1 MB
Aula Digitada 03 Parte 03
3 Pages • 2,057 Words • PDF • 123 KB
Olivia River - Tone Deaf (rev)
255 Pages • 74,079 Words • PDF • 2.1 MB
ECS 845GV-M2 - REV 1.2A
30 Pages • 16,223 Words • PDF • 1004.7 KB
ECS 761GX-M754 - REV 1.0
35 Pages • 20,079 Words • PDF • 890.6 KB
Nestor Marquez Flores - Rev A
1 Pages • 245 Words • PDF • 124.3 KB